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URL https://opencores.org/ocsvn/jart/jart/trunk

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  • This comparison shows the changes necessary to convert path 
    /jart/trunk/BLRT
    from Rev 21 to Rev 22
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  •

Rev 21 → Rev 22

/powerGrid.vhd
28,6 → 28,31
 
package powerGrid is
 
--A one stage pipe a+b+c with w width bits in input as well as output.
component p1ax
generic ( W : integer := 36 );
port ( clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
dataa : in std_logic_vector(W-1 downto 0);
datab : in std_logic_vector(W-1 downto 0);
datac : in std_logic_vector(W-1 downto 0);
result : out std_logic_vector(W-1 downto 0)
);
end component;
-- A 1 stage pipe 18x18 multiplier. On Cycle III devices is a M-R (Multiplier, Register). (Should be generated using a synthesis tool....).
component p1m18
port (
aclr : in std_logic ;
clken : in std_logic ;
clock : in std_logic ;
dataa : in std_logic_vector (17 downto 0);
datab : in std_logic_vector (17 downto 0);
result : out std_logic_vector (35 downto 0)
);
end component;
 
-- Signed "less than"
component sl32
port (
57,14 → 82,17
rst : in std_logic;
cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the sphere identification output.
refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell.
colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! .
cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the result column identification output.
refvd : in std_logic_vector (W - 1 downto 0); -- This is the reference projection incoming from the previous cell.
colvd : in std_logic_vector (W - 1 downto 0); -- This is the sphere position over the ray traced vector projection.
selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd.
)
);
end component;
-- Dot Product Calculation.
-- Dot Product Calculation Cell.
-- A 4 side cell along with an upper side.
-- V input flows through V output using a data flipflop, so turning V output in the next cell on the next row V Input. V input also flows upwards into the dotproduct 3 stage pipeline.
-- D input flows through D output using a data flipflop, so turning D output in the next column cell. D input also flows upwards into the dotproduct 3 stage.
component dotCell
generic ( levelW : integer := 18; -- Actual Level Width
nLevelW : integer := 32); -- Next Level Width
74,6 → 102,8
-- Object control.
nxtSphere : in std_logic; -- This bit controls when the sphere center goes to the next row.
nxtRay : in std_logic; -- This bit controls when the ray goes to the next column.
-- First Side.
vxInput : in std_logic_vector(levelW-1 downto 0);
vyInput : in std_logic_vector(levelW-1 downto 0);
95,15 → 125,14
dzOutput : in std_logic_vector(levelW-1 downto 0);
--Fifth Side (Going to the floor right upstairs!)
vdOutput : out std_logic_vector(nLevelW-1 downto 0); -- Dot product.
vdOutput : out std_logic_vector(nLevelW-1 downto 0) -- Dot product.
);
);
end component;
-- K discriminant comparison.
component kComparisonCell
generic ( W : integer := 32;
idW : integer := 12
);
port (
clk : in std_logic;
110,13 → 139,13
rst : in std_logic;
nxtRow : in std_logic; -- Controls when the sphere goes to the next Row.
vdinput : in std_logic_vector (W-1 downto 0);
kinput : in std_logic_vector (W-1 downto 0);
koutput : out std_logic_vector (W-1 downto 0);
sDP : out std_logic_vector (W-1 downto 0) -- Selected dot product.
sDP : out std_logic_vector (W-1 downto 0) -- Selected dot product.
);
end component;
end component;
end powerGrid;

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