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    from Rev 13 to Rev 14
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Rev 13 → Rev 14

/BLRT/kComparisonCell.vhd
0,0 → 1,93
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
 
entity kComparisonCell is
generic ( W : integer := 32;
idW : integer := 12
);
port (
clk : in std_logic;
rst : in std_logic;
vdinput : in std_logic_vector (W-1 downto 0);
kinput : in std_logic_vector (W-1 downto 0);
koutput : out std_logic_vector (W-1 downto 0);
sDP : out std_logic_vector (W-1 downto 0); -- Selected dot product.
);
end port;
end entity;
 
 
architecture rtl of kComparisonCell is
 
signal sge32 : std_logic; -- Greater or equal signal
 
begin
 
-- Instantiation of the compare.
discriminantCompare : ge32 port map (
dataa => vdinput,
datab => kinput,
AgeB => sge32
);
 
 
-- When sge32 (greater or equal signal) is set then V.D > kte, thus intersection is confirmed and shifting V.D to the distance comparison grid.
intersectionSelector : for i in 0 to W-1 generate
 
selector : process (rst,clk)
begin
if rst='0' then
-- At the beginning set the Maximum over Maximum distance.
if i = W-1 then
sDP (i) <= '0';
else
sDP (i) <= '1';
end if;
elsif rising_edge(clk) then
if i = W-1 then
sDP (i) <= sge32 and vdinput(i);
else
sDP (i) <= (sge32 and vdinput(i)) or not(sge32);
end if;
end if;
end process;
end generate;
 
kPipeStage : process (clk,rst)
begin
if rst='0' then
koutput <= (others => '0');
elsif rising_edge(clk) then
koutput <= kinput;
end if;
end process;
 
 
 
end rtl;
 
 
 
/BLRT/dotCell.vhd
0,0 → 1,124
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
entity dotCell is
generic ( levelW : integer := 18; -- Actual Level Width
nLevelW : integer := 32); -- Next Level Width
port ( clk : in std_logic;
rst : in std_logic;
-- Object control.
nxtSphere : in std_logic; -- This bit controls when the sphere center goes to the next row.
-- First Side.
vxInput : in std_logic_vector(levelW-1 downto 0);
vyInput : in std_logic_vector(levelW-1 downto 0);
vzInput : in std_logic_vector(levelW-1 downto 0);
 
-- Second Side (Opposite to the first one)
vxOutput : out std_logic_vector(levelW-1 downto 0);
vyOutput : out std_logic_vector(levelW-1 downto 0);
vzOutput : out std_logic_vector(levelW-1 downto 0);
 
-- Third Side (Perpendicular to the first and second ones)
dxInput : in std_logic_vector(levelW-1 downto 0);
dyInput : in std_logic_vector(levelW-1 downto 0);
dzInput : in std_logic_vector(levelW-1 downto 0);
--Fourth Side (Opposite to the third one)
dxOutput : in std_logic_vector(levelW-1 downto 0);
dyOutput : in std_logic_vector(levelW-1 downto 0);
dzOutput : in std_logic_vector(levelW-1 downto 0);
--Fifth Side (Going to the floor right upstairs!)
vdOutput : out std_logic_vector(nLevelW-1 downto 0); -- Dot product.
)
end port;
end entity;
 
 
architecture rtl of rtCell is
 
 
signal svd : std_logic_vector (nLevelW - 1 downto 0);
begin
 
-- The Dotprod Machine
vd : dp18 port map (
clock0 => clk,
dataa_0 => dxInput,
dataa_1 => dyInput,
dataa_2 => dzInput,
datab_0 => vxInput,
datab_1 => vyInput,
datab_2 => vzInput,
result => svd
);
-- Ray PipeLine
rayPipeStage : process (clk,rst)
begin
if rst = '0' then
-- There is no ray load yet.
dxOutput <= (others => '0');
dyOutput <= (others => '0');
dzOutput <= (others => '0');
elsif rising_edge (clk) then
-- Set
dxOutput <= dxInput;
dyOutput <= dyInput;
dzOutput <= dzInput;
end if;
end process;
 
-- Sphere Pipe Line
spherePipeStage : process (clk,rts)
begin
if rst = '0' then
 
-- There is no object center yet.
vxOutput <= (others => '0');
vyOutput <= (others => '0');
vzOutput <= (others => '0');
elsif rising_edge (clk) and nxtSphere ='1' then
-- Shift sphere to the next row.
vxOutput <= vxInput;
vyOutput <= vyInput;
vzOutput <= vzInput;
end if;
end process;
-- Upper Level
vdPipeStage : process (clk,rst)
begin
if rst='0' then
vdOutput <= (others => '0');
elsif rising_edge(clk) then
vdOutput <= svd;
end if;
end process;
end rtl;
 
 
 
 
/BLRT/dComparisonCell.vhd
0,0 → 1,86
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
use work.powerGrid.all;
 
 
entity dComparisonCell is
generic ( W : integer := 32; -- V.D, minDistance and selectD Width
idColW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
idCol : integer := 0 -- Column Id
);
port (
clk : in std_logic;
rst : in std_logic;
cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the sphere identification output.
refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell.
colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! .
selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd.
)
end port;
end entity;
 
 
architecture rtl of dComparisonCell is
 
signal sl32 : std_logic; -- This signal indicates if refvd is less than colvd
 
begin
 
-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual max V.D
cl32 : l32 port map ( dataa => colvd,
datab => refvd,
AlB => sl32
);
-- A flip flop with 2 to 1 mux.
selector : scanFF generic map ( W = 32 )
port map ( clk => clk,
rst => rst,
scLoad => sl32,
extData => colvd,
dStage => refvd,
qStage => selvd);
colIdSelector : process (clk,rst)
begin
if rst = '0' then
--Set max Distance on reset and column identifier
cIdq <= CONV_STD_LOGIC_VECTOR(idCol,idColW);
selvd(W-1) <= '0';
selvd(W-2 downto 0) <= (others => '1');
elsif rising_edge(clk) then
if sl32 ='0' then
-- If reference V.D. is less than column V.D then shift the reference id.
cIdq <= cIdd;
else
--If column V.D. is less than
cIdq <= CONV_STD_LOGIC(idCol,idColW);
end if;
end process;
 
end rtl;

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