URL
https://opencores.org/ocsvn/jart/jart/trunk
Subversion Repositories jart
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- This comparison shows the changes necessary to convert path
/jart/trunk
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/BLRT/dComparisonCell.vhd
32,9 → 32,9
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entity dComparisonCell is |
generic ( W : integer := 32; -- V.D, minDistance and selectD Width |
generic ( W : integer := 32; -- operands Width ( reference V.D and column V.D) |
idColW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on. |
idCol : integer := 0 -- Column Id |
idCol : integer := 0 -- Column Id |
); |
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47,28 → 47,26
refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell. |
colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! . |
selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd. |
) |
end port; |
); |
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end entity; |
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architecture rtl of dComparisonCell is |
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signal ssl32 : std_logic; -- This signal indicates if refvd is less than colvd |
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signal ssl32 : std_logic; -- This signal indicates if refvd is less than colvd |
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begin |
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-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual max V.D |
-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual min V.D |
cl32 : sl32 port map ( dataa => colvd, |
datab => refvd, |
AlB => sl32 |
AlB => ssl32 |
); |
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-- A flip flop with 2 to 1 mux. |
selector : scanFF generic map ( W = 32 ) |
selectorVD : scanFF generic map ( W = W ) |
port map ( clk => clk, |
rst => rst, |
scLoad => ssl32, |
75,36 → 73,14
extData => colvd, |
dStage => refvd, |
qStage => selvd); |
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colIdSelector : process (clk,rst) |
begin |
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if rst = '0' then |
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--Set max Distance on reset and column identifier |
cIdq <= CONV_STD_LOGIC_VECTOR(idCol,idColW); |
selvd(W-1) <= '0'; |
selvd(W-2 downto 0) <= (others => '1'); |
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elsif rising_edge(clk) then |
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if ssl32 ='0' then |
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-- If reference V.D. is less than column V.D then shift the reference id. |
cIdq <= cIdd; |
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else |
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--If column V.D. is less than |
cIdq <= CONV_STD_LOGIC(idCol,idColW); |
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end if; |
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end process; |
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-- Another flip flip with 2 to 1 mux. |
selectorID : scanFF generic map ( W = idColW ) |
port map ( clk => clk, |
rst => rst, |
scLoad => ssl32, |
extData => CONV_STD_LOGIC(idCol,idColW), |
dStage => cIdd, |
qStage => cIdq |
); |
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end rtl; |