URL
https://opencores.org/ocsvn/jart/jart/trunk
Subversion Repositories jart
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- from Rev 13 to Rev 14
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Rev 13 → Rev 14
/trunk/BLRT/kComparisonCell.vhd
0,0 → 1,93
library ieee; |
use ieee.std_logic_1164.all; |
use work.powerGrid.all; |
|
|
entity kComparisonCell is |
generic ( W : integer := 32; |
idW : integer := 12 |
); |
port ( |
clk : in std_logic; |
rst : in std_logic; |
|
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vdinput : in std_logic_vector (W-1 downto 0); |
kinput : in std_logic_vector (W-1 downto 0); |
koutput : out std_logic_vector (W-1 downto 0); |
|
sDP : out std_logic_vector (W-1 downto 0); -- Selected dot product. |
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); |
end port; |
end entity; |
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architecture rtl of kComparisonCell is |
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signal sge32 : std_logic; -- Greater or equal signal |
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begin |
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-- Instantiation of the compare. |
discriminantCompare : ge32 port map ( |
dataa => vdinput, |
datab => kinput, |
AgeB => sge32 |
); |
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-- When sge32 (greater or equal signal) is set then V.D > kte, thus intersection is confirmed and shifting V.D to the distance comparison grid. |
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intersectionSelector : for i in 0 to W-1 generate |
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selector : process (rst,clk) |
begin |
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if rst='0' then |
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-- At the beginning set the Maximum over Maximum distance. |
if i = W-1 then |
sDP (i) <= '0'; |
else |
sDP (i) <= '1'; |
end if; |
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elsif rising_edge(clk) then |
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if i = W-1 then |
sDP (i) <= sge32 and vdinput(i); |
else |
sDP (i) <= (sge32 and vdinput(i)) or not(sge32); |
end if; |
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end if; |
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end process; |
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end generate; |
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kPipeStage : process (clk,rst) |
begin |
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if rst='0' then |
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koutput <= (others => '0'); |
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elsif rising_edge(clk) then |
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koutput <= kinput; |
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end if; |
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end process; |
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end rtl; |
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/trunk/BLRT/dotCell.vhd
0,0 → 1,124
library ieee; |
use ieee.std_logic_1164.all; |
use work.powerGrid.all; |
|
entity dotCell is |
generic ( levelW : integer := 18; -- Actual Level Width |
nLevelW : integer := 32); -- Next Level Width |
port ( clk : in std_logic; |
rst : in std_logic; |
|
-- Object control. |
nxtSphere : in std_logic; -- This bit controls when the sphere center goes to the next row. |
-- First Side. |
vxInput : in std_logic_vector(levelW-1 downto 0); |
vyInput : in std_logic_vector(levelW-1 downto 0); |
vzInput : in std_logic_vector(levelW-1 downto 0); |
|
-- Second Side (Opposite to the first one) |
vxOutput : out std_logic_vector(levelW-1 downto 0); |
vyOutput : out std_logic_vector(levelW-1 downto 0); |
vzOutput : out std_logic_vector(levelW-1 downto 0); |
|
-- Third Side (Perpendicular to the first and second ones) |
dxInput : in std_logic_vector(levelW-1 downto 0); |
dyInput : in std_logic_vector(levelW-1 downto 0); |
dzInput : in std_logic_vector(levelW-1 downto 0); |
|
--Fourth Side (Opposite to the third one) |
dxOutput : in std_logic_vector(levelW-1 downto 0); |
dyOutput : in std_logic_vector(levelW-1 downto 0); |
dzOutput : in std_logic_vector(levelW-1 downto 0); |
|
--Fifth Side (Going to the floor right upstairs!) |
vdOutput : out std_logic_vector(nLevelW-1 downto 0); -- Dot product. |
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) |
end port; |
end entity; |
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architecture rtl of rtCell is |
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signal svd : std_logic_vector (nLevelW - 1 downto 0); |
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begin |
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-- The Dotprod Machine |
vd : dp18 port map ( |
clock0 => clk, |
dataa_0 => dxInput, |
dataa_1 => dyInput, |
dataa_2 => dzInput, |
datab_0 => vxInput, |
datab_1 => vyInput, |
datab_2 => vzInput, |
result => svd |
); |
|
-- Ray PipeLine |
rayPipeStage : process (clk,rst) |
begin |
if rst = '0' then |
-- There is no ray load yet. |
dxOutput <= (others => '0'); |
dyOutput <= (others => '0'); |
dzOutput <= (others => '0'); |
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elsif rising_edge (clk) then |
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-- Set |
dxOutput <= dxInput; |
dyOutput <= dyInput; |
dzOutput <= dzInput; |
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end if; |
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end process; |
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-- Sphere Pipe Line |
spherePipeStage : process (clk,rts) |
begin |
if rst = '0' then |
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-- There is no object center yet. |
vxOutput <= (others => '0'); |
vyOutput <= (others => '0'); |
vzOutput <= (others => '0'); |
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elsif rising_edge (clk) and nxtSphere ='1' then |
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-- Shift sphere to the next row. |
vxOutput <= vxInput; |
vyOutput <= vyInput; |
vzOutput <= vzInput; |
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end if; |
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end process; |
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-- Upper Level |
vdPipeStage : process (clk,rst) |
begin |
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if rst='0' then |
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vdOutput <= (others => '0'); |
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elsif rising_edge(clk) then |
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vdOutput <= svd; |
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end if; |
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end process; |
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end rtl; |
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/trunk/BLRT/dComparisonCell.vhd
0,0 → 1,86
library ieee; |
|
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
use work.powerGrid.all; |
|
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entity dComparisonCell is |
generic ( W : integer := 32; -- V.D, minDistance and selectD Width |
idColW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on. |
idCol : integer := 0 -- Column Id |
); |
|
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port ( |
clk : in std_logic; |
rst : in std_logic; |
|
cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input. |
cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the sphere identification output. |
refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell. |
colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! . |
selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd. |
) |
end port; |
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end entity; |
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architecture rtl of dComparisonCell is |
|
signal sl32 : std_logic; -- This signal indicates if refvd is less than colvd |
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begin |
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-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual max V.D |
cl32 : l32 port map ( dataa => colvd, |
datab => refvd, |
AlB => sl32 |
); |
|
-- A flip flop with 2 to 1 mux. |
selector : scanFF generic map ( W = 32 ) |
port map ( clk => clk, |
rst => rst, |
scLoad => sl32, |
extData => colvd, |
dStage => refvd, |
qStage => selvd); |
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colIdSelector : process (clk,rst) |
begin |
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if rst = '0' then |
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--Set max Distance on reset and column identifier |
cIdq <= CONV_STD_LOGIC_VECTOR(idCol,idColW); |
selvd(W-1) <= '0'; |
selvd(W-2 downto 0) <= (others => '1'); |
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elsif rising_edge(clk) then |
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if sl32 ='0' then |
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-- If reference V.D. is less than column V.D then shift the reference id. |
cIdq <= cIdd; |
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else |
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--If column V.D. is less than |
cIdq <= CONV_STD_LOGIC(idCol,idColW); |
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end if; |
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end process; |
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end rtl; |