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- from Rev 57 to Rev 58
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Rev 57 → Rev 58
/branches/ver0branch/powerGrid.vhd
27,7 → 27,18
use ieee.std_logic_1164.all; |
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package powerGrid is |
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-- A scan flip flop, aka selectable input ff. |
component scanFF |
generic ( |
W : integer := 8); |
port ( |
clk,rst,ena,sel : std_logic; -- The usual control signals |
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d0,d1 : std_logic_vector (W-1 downto 0); -- The two operands. |
q : std_logic_vector (W-1 downto 0) -- The selected data. |
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); |
end component; |
--A one stage pipe (1 Clk) a+b+c with w width bits in input as well as output. |
--As a fixed signed addtion we have: |
-- A(B,C) ====> B+C SIGNED BITS FORMAT : 1 bit for sign, B bits for integer part, C bits for decimal part. (FORMAT) |