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https://opencores.org/ocsvn/jart/jart/trunk
Subversion Repositories jart
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Rev 59 → Rev 60
/branches/ver0branch/scanFF.vhd
29,31 → 29,33
entity scanFF is |
generic ( W : integer := 8); |
port ( |
clk,rst,ena,sel : std_logic; -- The usual control signals |
clk,rst,ena,sel : in std_logic; -- The usual control signals |
|
d0,d1 : std_logic_vector (W-1 downto 0); -- The two operands. |
q : std_logic_vector (W-1 downto 0) -- The selected data. |
d0,d1 : in std_logic_vector (W-1 downto 0); -- The two operands. |
q : out std_logic_vector (W-1 downto 0) -- The selected data. |
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); |
end entity; |
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architecture rtl of scanFF is |
signal mux: std_logic_vector (W-1 downto 0); |
begin |
|
dff_ena_sel : process (clk,rst,ena) |
dff_ena_sel :for i in 0 to W-1 generate |
mux(i) <= (d1(i) and sel) or (d0(i) and not(sel)); |
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process (clk,rst,ena) |
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begin |
begin |
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if rst = '0' then |
q <= '0' & (others => '1'); |
elsif rising_edge (clk) and ena = '1' then |
if sel='1' then |
q <= d1; |
else |
q <= d0; |
if rst = '0' then |
q(i) <= '1'; |
elsif rising_edge (clk) and ena = '1' then |
q(i) <= mux(i); |
end if; |
end if; |
end process; |
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end process; |
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end generate; |
end rtl; |
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