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    /jart
    from Rev 64 to Rev 65
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Rev 64 → Rev 65

/branches/ver0branch/sphereRegisterBlock.vhd
0,0 → 1,104
 
-- The Spheres Register Bank.
 
library ieee;
use ieee.std_logic_1164.all;
 
 
entity sphereRegisterBlock is
generic (
OPMODE : integer := OP4; -- By default push out 4 spheres at same time.
SZMODE : integer := SZBETA; -- By default the max sphere numbers is 2048, but could be .
);
port (
-- The usual control signals.
clk, ena: in std_logic;
-- Write enable signals, address bus.
wen : in std_logic_vector (CIDSZADD(OPMODE(SZINDEX))*4-1 downto 0);
add : in std_logic_vector (REGSZADD(OPMODE)-SZMODE downto 0);
-- incoming data from 32 bits width bus.
datain : in std_logic_vector (BUSW-1 downto 0);
-- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vx : out std_logic_vector (OPMODE*HBUSW-1 downto 0);
Vy : out std_logic_vector (OPMODE*HBUSW-1 downto 0);
Vz : out std_logic_vector (OPMODE*HBUSW-1 downto 0);
K : out std_logic_vector (OPMODE*BUSW-1 downto 0)
);
end entity;
 
 
architecture rtl of sphereRegisterBlock is
 
begin
 
-- OP1 : output to 1 column
rb1x : if OPMODE=OP1 generate
rop1_inst : rop1
generic map(
SZMODE => SZMODE
)
port map (
clk => clk,
ena => ena,
wen => wen,
add => add,
datain => datain,
Vx => Vx,
Vy => Vy,
Vz => Vz,
K => K
);
end generate;
-- OP2 : output to 2 columns
rb2x : if OPMODE=OP2 generate
rop2_inst : rop2
generic map(
SZMODE => SZMODE
)
port map (
clk => clk,
ena => ena,
wen => wen,
add => add,
datain => datain,
Vx => Vx,
Vy => Vy,
Vz => Vz,
K => K
);
end generate;
-- OP24
rb4x : if OPMODE=OP4 generate
rop4_inst : rop4
generic map(
SZMODE => SZMODE
)
port map (
clk => clk,
ena => ena,
wen => wen,
add => add,
datain => datain,
Vx => Vx,
Vy => Vy,
Vz => Vz,
K => K
);
end generate;
end rtl;
/branches/ver0branch/rop1.vhd
0,0 → 1,63
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
entity rop1 is
generic (
SZMODE : integer := SZBETA -- By default use the 50% of the max memory for sphere register block.
);
port (
clk, ena: in std_logic; -- The usual control signals.
wen : in std_logic_vector (3 downto 0);
add : in std_logic_vector (REGSZADD(OP1)-SZMODE downto 0);
datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
K : out std_logic_vector (BUSW-1 downto 0)
);
end entity;
 
 
architecture rtl of rop1 is
 
begin
 
if SZMODE = SZALFA generate
r8_inst : r8
port map (
clk => clk,
ena => ena,
wen => wen,
add => add,
datain => datain,
Vx => Vx,
Vy => Vy,
Vz => Vz,
K => K
);
end generate
if SZMODE = SZBETA generate
r4_inst : r4
port map (
clk => clk,
ena => ena,
wen => wen,
add => add,
datain => datain,
Vx => Vx,
Vy => Vy,
Vz => Vz,
K => K
);
end generate
 
end rtl;
/branches/ver0branch/rop2.vhd
0,0 → 1,69
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
entity rop2 is
generic (
SZMODE : integer := SZBETA -- By default use the 50% of the max memory for sphere register block.
);
port (
clk, ena: in std_logic; -- The usual control signals.
wen : in std_logic_vector (7 downto 0);
add : in std_logic_vector (REGSZADD(OP2)-SZMODE downto 0);
datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
Vx : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vy : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vz : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
K : out std_logic_vector (2*BUSW-1 downto 0)
);
end entity;
 
 
architecture rtl of rop1 is
 
begin
 
if SZMODE = SZALFA generate
for i in generate 0 to 1 generate
r4_inst : r4
port map (
clk => clk,
ena => ena,
wen => wen((i+1)*4-1 downto i*4),
add => add,
datain => datain,
Vx => Vx((i+1)*HBUSW-1 downto i*HBUSW),
Vy => Vy((i+1)*HBUSW-1 downto i*HBUSW),
Vz => Vz((i+1)*HBUSW-1 downto i*HBUSW),
K => K((i+1)*HBUSW-1 downto i*HBUSW)
);
end generate
 
end generate;
if SZMODE = SZBETA generate
for i in generate 0 to 1 generate
r2_inst : r2
port map (
clk => clk,
ena => ena,
wen => wen((i+1)*4-1 downto i*4),
add => add,
datain => datain,
Vx => Vx((i+1)*HBUSW-1 downto i*HBUSW),
Vy => Vy((i+1)*HBUSW-1 downto i*HBUSW),
Vz => Vz((i+1)*HBUSW-1 downto i*HBUSW),
K => K((i+1)*HBUSW-1 downto i*HBUSW)
);
end generate
end generate
 
end rtl;
/branches/ver0branch/r1.vhd
0,0 → 1,68
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
entity r1 is
port (
clk, ena: in std_logic; -- The usual control signals.
wen : in std_logic_vector (3 downto 0);
add : in std_logic_vector (8 downto 0);
datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
K : out std_logic_vector (BUSW-1 downto 0)
);
end entity;
 
 
 
architecture rtl of r8 is
 
begin
-- K Register
bt11_inst : bt11
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(0),
q => K
);
-- Vx, Vy, VZ registers
bt14x : bt14
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(3),
q => Vx
);
bt14y : bt14
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(2),
q => Vy
);
bt14z : bt14
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(1),
q => Vz
);
 
end;
/branches/ver0branch/r2.vhd
0,0 → 1,68
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
entity r2 is
port (
clk, ena: in std_logic; -- The usual control signals.
wen : in std_logic_vector (3 downto 0);
add : in std_logic_vector (9 downto 0);
datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
K : out std_logic_vector (BUSW-1 downto 0)
);
end entity;
 
 
 
architecture rtl of r8 is
 
begin
-- K Register
bt21_inst : bt21
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(0),
q => K
);
-- Vx, Vy, VZ registers
bt24x : bt24
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(3),
q => Vx
);
bt24y : bt24
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(2),
q => Vy
);
bt24z : bt24
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(1),
q => Vz
);
 
end;
/branches/ver0branch/rop4.vhd
0,0 → 1,70
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
entity rop4 is
generic (
SZMODE : integer := SZBETA -- By default use the 50% of the max memory for sphere register block.
);
port (
clk, ena: in std_logic; -- The usual control signals.
wen : in std_logic_vector (15 downto 0);
add : in std_logic_vector (REGSZADD(OP4)-SZMODE downto 0);
datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
Vx : out std_logic_vector (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vy : out std_logic_vector (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vz : out std_logic_vector (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
K : out std_logic_vector (4*BUSW-1 downto 0)
);
end entity;
 
 
architecture rtl of rop1 is
 
begin
 
if SZMODE = SZALFA generate
for i in generate 0 to 3 generate
r2_inst : r2
port map (
clk => clk,
ena => ena,
wen => wen((i+1)*4-1 downto i*4),
add => add,
datain => datain,
Vx => Vx((i+1)*HBUSW-1 downto i*HBUSW),
Vy => Vy((i+1)*HBUSW-1 downto i*HBUSW),
Vz => Vz((i+1)*HBUSW-1 downto i*HBUSW),
K => K((i+1)*HBUSW-1 downto i*HBUSW)
);
end generate
 
end generate;
if SZMODE = SZBETA generate
for i in generate 0 to 3 generate
r1_inst : r1
port map (
clk => clk,
ena => ena,
wen => wen((i+1)*4-1 downto i*4),
add => add,
datain => datain,
Vx => Vx((i+1)*HBUSW-1 downto i*HBUSW),
Vy => Vy((i+1)*HBUSW-1 downto i*HBUSW),
Vz => Vz((i+1)*HBUSW-1 downto i*HBUSW),
K => K((i+1)*HBUSW-1 downto i*HBUSW)
);
end generate
end generate
 
end rtl;
/branches/ver0branch/r4.vhd
0,0 → 1,68
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
entity r4 is
port (
clk, ena: in std_logic; -- The usual control signals.
wen : in std_logic_vector (3 downto 0);
add : in std_logic_vector (10 downto 0);
datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
K : out std_logic_vector (BUSW-1 downto 0)
);
end entity;
 
 
 
architecture rtl of r8 is
 
begin
-- K Register
bt41_inst : bt41
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(0),
q => K
);
-- Vx, Vy, VZ registers
bt44x : bt44
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(3),
q => Vx
);
bt44y : bt44
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(2),
q => Vy
);
bt44z : bt44
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(1),
q => Vz
);
 
end;
/branches/ver0branch/r8.vhd
0,0 → 1,68
library ieee;
use ieee.std_logic_1164.all;
use work.powerGrid.all;
 
entity r8 is
port (
clk, ena: in std_logic; -- The usual control signals.
wen : in std_logic_vector (3 downto 0);
add : in std_logic_vector (11 downto 0);
datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
K : out std_logic_vector (BUSW-1 downto 0)
);
end entity;
 
 
 
architecture rtl of r8 is
 
begin
-- K Register
bt81_inst : bt81
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(0),
q => K
);
-- Vx, Vy, VZ registers
bt84x : bt84
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(3),
q => Vx
);
bt84y : bt84
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(2),
q => Vy
);
bt84z : bt84
port map (
address => add,
clken => ena,
clock => clk,
data => datain,
wren => wen(1),
q => Vz
);
 
end;

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