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Rev 7 → Rev 8

/trunk/BLSQRT/gLeftShift.vhd
0,0 → 1,56
-- Author : Julian Andres Guarin Reyes.
-- Project : JART, Just Another Ray Tracer.
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
 
-- This code was entirely written by Julian Andres Guarin Reyes.
-- The following code is licensed under GNU Public License
-- http://www.gnu.org/licenses/gpl-3.0.txt.
 
-- This file is part of JART (Just Another Ray Tracer).
 
-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
 
-- The following code is a 1 Clock Fixed Square Root. Where's the catch? , well I simulate it through a lot of values (not really a simulation, just an openoffice electronic sheet), and found the maximum error is 6%. This error could be huge in terms of precision, but reasonable in terms of 1 CLOCK (maybe 2 CLOCKS) of fxd sq root latency.library ieee;
use ieee.std_logic_1164.all;
 
-- Left Shifting : The most significant one must be shifted one place to the left, the hole it leaves must be filled with most significant bit (0 or 1) of the most significant bit pair with at least a one in it.
 
entity gLeftShift is
port ( Sn : in std_logic_vector (1 downto 0); -- Sn(1) is the pair under test selector, Sn (0) is the next to the right pair selector.
Din : in std_logic_vector (2 downto 0); -- Dn(2 downto 1) is the pair under test, Dn(0) is the most significant bit of the next to the right pair selector.
Dout : out std_logic_vector (1 downto 0) -- Dout (1 downto 0 ) is the new result of the pair under test.
);
end entity gLeftShift;
 
architecture rtl of gLeftShift is
begin
 
shift:
process (Sn,Din) is
begin
 
if Sn(1)='1' then
Dout <= '1' & (Din(2) and Din(1));
else
case Sn(0) is
when '1' =>
Dout <= Din(2) & Din(0); --The n-1 n-pair was selected.
when others =>
Dout <= Din(2 downto 1) ; --Nor this n-pair or the n-1 n-pair was selected......
end case;
end if;
end process;
end rtl;
 
/trunk/BLSQRT/gMux.vhd
0,0 → 1,154
-- Author : Julian Andres Guarin Reyes.
-- Project : JART, Just Another Ray Tracer.
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
 
-- This code was entirely written by Julian Andres Guarin Reyes.
-- The following code is licensed under GNU Public License
-- http://www.gnu.org/licenses/gpl-3.0.txt.
 
-- This file is part of JART (Just Another Ray Tracer).
 
-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
 
-- The following code is a 1 Clock Fixed Square Root. Where's the catch? , well I simulate it through a lot of values (not really a simulation, just an openoffice electronic sheet), and found the maximum error is 6%. This error could be huge in terms of precision, but reasonable in terms of 1 CLOCK (maybe 2 CLOCKS) of fxd sq root latency.
library ieee;
use ieee.std_logic_1164.all;
 
 
 
entity gMux is
port (
rawSq : in std_logic_vector(31 downto 1); -- Square Root Raw Value
ohSel : in std_logic_vector(15 downto 0); -- One Hot Selector
sQ : out std_logic_vector (15 downto 0) -- Properly Selected Bits Square Root
);
end entity gMux;
 
 
architecture rtl of gMux is
 
begin
gMux:
process (rawSq,ohSel)
begin
sQ <= X"0000" ;
case ohSel is
when X"8000" =>
sQ <= rawSq(31 downto 16);
when X"4000" =>
if rawSq(30)='1' then
sQ (14 downto 0) <= rawSq (30 downto 16);
else
sQ (14 downto 0) <= rawSq (29 downto 15);
end if;
when X"2000" =>
if rawSq(28)='1' then
sQ (13 downto 0) <= rawSq( 28 downto 15);
else
sQ (13 downto 0) <= rawSq (27 downto 14);
end if;
when X"1000" =>
if rawSq(26)='1' then
sQ (12 downto 0) <= rawSq (26 downto 14);
else
sQ (12 downto 0) <= rawSq (25 downto 13);
end if;
when X"0800" =>
if rawSq(24)='1' then
sQ (11 downto 0) <= rawSq (24 downto 13);
else
sQ (11 downto 0) <= rawSq (23 downto 12);
end if;
when X"0400" =>
if rawSq(22)='1' then
sQ (10 downto 0) <= rawSq (22 downto 12);
else
sQ (10 downto 0) <= rawSq (21 downto 11);
end if;
when X"0200" =>
if rawSq(20)='1' then
sQ (9 downto 0) <= rawSq (20 downto 11);
else
sQ (9 downto 0) <= rawSq (19 downto 10);
end if;
when X"0100" =>
if rawSq(18)='1' then
sQ (8 downto 0) <= rawSq (18 downto 10);
else
sQ (8 downto 0) <= rawSq (17 downto 9);
end if;
when X"0080" =>
if rawSq(16)='1' then
sQ (7 downto 0) <= rawSq (16 downto 9);
else
sQ (7 downto 0) <= rawSq (15 downto 8);
end if;
when X"0040" =>
if rawSq(14)='1' then
sQ (6 downto 0) <= rawSq (14 downto 8);
else
sQ (6 downto 0) <= rawSq (13 downto 7);
end if;
when X"0020" =>
if rawSq(12)='1' then
sQ (5 downto 0) <= rawSq (12 downto 7);
else
sQ (5 downto 0) <= rawSq (11 downto 6);
end if;
when X"0010" =>
if rawSq(10)='1' then
sQ (4 downto 0) <= rawSq (10 downto 6);
else
sQ (4 downto 0) <= rawSq (9 downto 5);
end if;
when X"0008" =>
if rawSq(8)='1' then
sQ (3 downto 0) <= rawSq (8 downto 5);
else
sQ (3 downto 0) <= rawSq (7 downto 4);
end if;
when X"0004" =>
if rawSq(6)='1' then
sQ (2 downto 0) <= rawSq (6 downto 4);
else
sQ (2 downto 0) <= rawSq (5 downto 3);
end if;
when X"0002" =>
if rawSq(4)='1' then
sQ (1 downto 0) <= rawSq (4 downto 3);
else
sQ (1 downto 0) <= rawSq (3 downto 2);
end if;
when X"0001" =>
if rawSq(2)='1' then
sQ (0) <= rawSq (2);
else
sQ (0) <= rawSq (1);
end if;
when others =>
null;
end case;
end process;
 
 
 
end rtl;
 
 
 
 
/trunk/BLSQRT/gsqrt.vhd
0,0 → 1,66
-- Author : Julian Andres Guarin Reyes.
-- Project : JART, Just Another Ray Tracer.
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
 
-- This code was entirely written by Julian Andres Guarin Reyes.
-- The following code is licensed under GNU Public License
-- http://www.gnu.org/licenses/gpl-3.0.txt.
 
-- This file is part of JART (Just Another Ray Tracer).
 
-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
 
-- The following code is a 1 Clock Fixed Square Root. Where's the catch? , well I simulate it through a lot of values (not really a simulation, just an openoffice electronic sheet), and found the maximum error is 6%. This error could be huge in terms of precision, but reasonable in terms of 1 CLOCK (maybe 2 CLOCKS) of fxd sq root latency.
 
library ieee;
use ieee.std_logic_1164.all;
 
-- This is package file in order to mantain smaller code files.
package gsqrt is
-- Indicador ONE HOT del bit mas significativo
component gMsb
generic ( W : integer:=16);
port ( DataIn : in std_logic_vector (2*W-1 downto 0);
Sel : out std_logic_vector (W-1 downto 0)
);
end component;
 
-- Indica la presencia de algun 1 en un par de bits.
component gPar
generic ( W : integer:=32);
port ( radical : in std_logic_vector (W-1 downto 0);
rad_2 : out std_logic_vector ((W/2)-1 downto 0)
);
end component;
 
-- Calcula el corrimiento del 1 mas significativo a la izquierda y rellena el espacio que se deja.
component gLeftShift
port ( Sn : in std_logic_vector ( 1 downto 0 );
Din : in std_logic_vector ( 2 downto 0 );
Dout : out std_logic_vector ( 1 downto 0 )
);
end component;
-- El codificador de prioridad indica cuantas lugares se debe correr las comas.
component gMux
port ( rawSq : in std_logic_vector (31 downto 1);
ohSel : in std_logic_vector (15 downto 0); --One Hot Selector
sQ : out std_logic_vector (15 downto 0)
);
end component;
 
end package;
/trunk/BLSQRT/blsqrt.vhd
0,0 → 1,94
-- Author : Julian Andres Guarin Reyes.
-- Project : JART, Just Another Ray Tracer.
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
 
-- This code was entirely written by Julian Andres Guarin Reyes.
-- The following code is licensed under GNU Public License
-- http://www.gnu.org/licenses/gpl-3.0.txt.
 
-- This file is part of JART (Just Another Ray Tracer).
 
-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
 
-- The following code is a 1 Clock Fixed Square Root. Where's the catch? , well I simulate it through a lot of values (not really a simulation, just an openoffice electronic sheet), and found the maximum error is 6%. This error could be huge in terms of precision, but reasonable in terms of 1 CLOCK (maybe 2 CLOCKS) of fxd sq root latency.
library ieee;
use ieee.std_logic_1164.all;
use work.gsqrt.all;
 
entity blsqrt is
port (
radicando_U22_10 : in std_logic_vector (31 downto 0);
raizCuadrada_U11_5 : out std_logic_vector (15 downto 0)
);
end entity;
 
architecture rtl of blsqrt is
 
signal sOhSelector : std_logic_vector (15 downto 0);
signal sRawSq : std_logic_vector (31 downto 0);
 
begin
 
-- Seleccionar el bit mas significativo
priorityEncoder : giraldoMsb port map ( DataIn => radicando_U22_10,
Sel => sOhSelector);
 
-- Calcular el valor crudo de los pares
msbPairShifting :
for index in 1 to 15 generate
leftShifting : giraldoLeftShift port map ( Sn => sOhSelector(index downto index-1),
Din => radicando_U22_10 (index*2+1 downto index*2-1),
Dout => sRawSq(index*2+1 downto index*2));
end generate;
lsbPairShifting : giraldoLeftShift port map ( Sn => sOhSelector (1) & '0',
Din => radicando_U22_10 (1 downto 0) & '0',
Dout => sRawSq (1 downto 0));
-- Realizar el corrimento y multiplexacion para obtener el resultado final.
fixation : giraldoMux port map ( rawSq => sRawSq(31 downto 1),
ohSel => sOhSelector,
sQ => raizCuadrada_U11_5);
 
 
end rtl;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/trunk/BLSQRT/gMsb.vhd
0,0 → 1,60
-- Author : Julian Andres Guarin Reyes.
-- Project : JART, Just Another Ray Tracer.
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
 
-- This code was entirely written by Julian Andres Guarin Reyes.
-- The following code is licensed under GNU Public License
-- http://www.gnu.org/licenses/gpl-3.0.txt.
 
-- This file is part of JART (Just Another Ray Tracer).
 
-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
 
-- The following code is a 1 Clock Fixed Square Root. Where's the catch? , well I simulate it through a lot of values (not really a simulation, just an openoffice electronic sheet), and found the maximum error is 6%. This error could be huge in terms of precision, but reasonable in terms of 1 CLOCK (maybe 2 CLOCKS) of fxd sq root latency.library ieee;
use ieee.std_logic_1164.all;
 
 
 
entity gMsb is
generic ( W : integer:=16);
port ( DataIn : in std_logic_vector (2*W-1 downto 0);
Sel : out std_logic_vector (W-1 downto 0)
);
end entity gMsb;
 
architecture rtl of gMsb is
signal carry : std_logic_vector (W-1 downto 0);
signal DataPar : std_logic_vector (W-1 downto 0);
begin
 
-- Generar los Or's
ors :
for index in 0 to W-1 generate
DataPar(index) <= DataIn(index*2) or DataIn(index*2+1);
end generate;
-- Generar los selectores
selector :
for index in 0 to W-1 generate
Sel(index) <= carry(index) and DataPar(index);
end generate;
 
-- Carry Chain
carry(W-1) <= '1';
cChain :
for index in 0 to W-2 generate
carry(index) <= not(DataPar(index+1)) and carry(index+1);
end generate;
end rtl;
/trunk/BLSQRT/gPar.vhd
0,0 → 1,43
-- Author : Julian Andres Guarin Reyes.
-- Project : JART, Just Another Ray Tracer.
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
 
-- This code was entirely written by Julian Andres Guarin Reyes.
-- The following code is licensed under GNU Public License
-- http://www.gnu.org/licenses/gpl-3.0.txt.
 
-- This file is part of JART (Just Another Ray Tracer).
 
-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
 
-- The following code is a 1 Clock Fixed Square Root. Where's the catch? , well I simulate it through a lot of values (not really a simulation, just an openoffice electronic sheet), and found the maximum error is 6%. This error could be huge in terms of precision, but reasonable in terms of 1 CLOCK (maybe 2 CLOCKS) of fxd sq root latency.
 
library ieee;
use ieee.std_logic_1164.all;
 
entity gPar is
generic ( W : integer:=32);
port ( radical : in std_logic_vector (W-1 downto 0);
rad_2 : out std_logic_vector ((W/2)-1 downto 0)
);
end entity gPar;
 
architecture rtl of gPar is
begin
orArray :
for index in 0 to (W/2)-1 generate
rad_2(index) <= radical(index*2) or radical(index*2+1);
end generate;
end rtl;
/trunk/BLSQRT
trunk/BLSQRT Property changes : Added: svn:ignore ## -0,0 +1 ## +gsqrt.txt

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