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URL https://opencores.org/ocsvn/jpegencode/jpegencode/trunk

Subversion Repositories jpegencode

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  • This comparison shows the changes necessary to convert path 
    /jpegencode
    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/trunk/fifo_out.v
46,14 → 46,16
output data_ready;
output [4:0] orc_reg;
 
 
 
wire [31:0] cb_JPEG_bitstream, cr_JPEG_bitstream, y_JPEG_bitstream;
wire [4:0] cr_orc, cb_orc, y_orc;
wire [31:0] cr_bits_out, cb_bits_out, y_bits_out;
wire cr_out_enable, cb_out_enable, y_out_enable;
wire [31:0] y_bits_out;
wire y_out_enable;
wire cb_data_ready, cr_data_ready, y_data_ready;
wire end_of_block_output, y_eob_empty;
wire cb_eob_empty, cr_eob_empty;
wire cb_fifo_empty, cr_fifo_empty, y_fifo_empty;
wire y_fifo_empty;
reg [4:0] orc, orc_reg, orc_cb, orc_cr, old_orc_reg, sorc_reg, roll_orc_reg;
reg [4:0] orc_1, orc_2, orc_3, orc_4, orc_5, orc_reg_delay;
reg [4:0] static_orc_1, static_orc_2, static_orc_3, static_orc_4, static_orc_5;
76,34 → 78,75
reg rollover, rollover_1, rollover_2, rollover_3, rollover_eob;
reg rollover_4, rollover_5, rollover_6, rollover_7;
reg data_ready, eobe_1, cb_read_req, cr_read_req, y_read_req;
reg eob_early_out_enable;
reg eob_early_out_enable, fifo_mux;
wire [31:0] cr_bits_out1, cr_bits_out2, cb_bits_out1, cb_bits_out2;
wire cr_fifo_empty1, cr_fifo_empty2, cb_fifo_empty1, cb_fifo_empty2;
wire cr_out_enable1, cr_out_enable2, cb_out_enable1, cb_out_enable2;
wire cb_write_enable = cb_data_ready && !cb_eob_empty;
wire cr_write_enable = cr_data_ready && !cr_eob_empty;
wire y_write_enable = y_data_ready && !y_eob_empty;
wire cr_read_req1 = fifo_mux ? 0 : cr_read_req;
wire cr_read_req2 = fifo_mux ? cr_read_req : 0;
wire [31:0] cr_JPEG_bitstream1 = fifo_mux ? cr_JPEG_bitstream : 0;
wire [31:0] cr_JPEG_bitstream2 = fifo_mux ? 0 : cr_JPEG_bitstream;
wire cr_write_enable1 = fifo_mux && cr_write_enable;
wire cr_write_enable2 = !fifo_mux && cr_write_enable;
wire [31:0] cr_bits_out = fifo_mux ? cr_bits_out2 : cr_bits_out1;
wire cr_fifo_empty = fifo_mux ? cr_fifo_empty2 : cr_fifo_empty1;
wire cr_out_enable = fifo_mux ? cr_out_enable2 : cr_out_enable1;
wire cb_read_req1 = fifo_mux ? 0 : cb_read_req;
wire cb_read_req2 = fifo_mux ? cb_read_req : 0;
wire [31:0] cb_JPEG_bitstream1 = fifo_mux ? cb_JPEG_bitstream : 0;
wire [31:0] cb_JPEG_bitstream2 = fifo_mux ? 0 : cb_JPEG_bitstream;
wire cb_write_enable1 = fifo_mux && cb_write_enable;
wire cb_write_enable2 = !fifo_mux && cb_write_enable;
wire [31:0] cb_bits_out = fifo_mux ? cb_bits_out2 : cb_bits_out1;
wire cb_fifo_empty = fifo_mux ? cb_fifo_empty2 : cb_fifo_empty1;
wire cb_out_enable = fifo_mux ? cb_out_enable2 : cb_out_enable1;
 
 
pre_fifo u14(.clk(clk), .rst(rst), .enable(enable), .data_in(data_in),
.cr_JPEG_bitstream(cr_JPEG_bitstream), .cr_data_ready(cr_data_ready),
.cr_orc(cr_orc), .cb_JPEG_bitstream(cb_JPEG_bitstream),
.cb_data_ready(cb_data_ready), .cb_orc(cb_orc),
.y_JPEG_bitstream(y_JPEG_bitstream), .y_data_ready(y_data_ready), .y_orc(y_orc),
.y_JPEG_bitstream(y_JPEG_bitstream),
.y_data_ready(y_data_ready), .y_orc(y_orc),
.y_eob_output(end_of_block_output), .y_eob_empty(y_eob_empty),
.cb_eob_empty(cb_eob_empty), .cr_eob_empty(cr_eob_empty));
 
sync_fifo_32 u15(.clk(clk), .rst(rst), .read_req(cb_read_req),
.write_data(cb_JPEG_bitstream), .write_enable(cb_write_enable),
.read_data(cb_bits_out),
.fifo_empty(cb_fifo_empty), .rdata_valid(cb_out_enable));
sync_fifo_32 u15(.clk(clk), .rst(rst), .read_req(cb_read_req1),
.write_data(cb_JPEG_bitstream1), .write_enable(cb_write_enable1),
.read_data(cb_bits_out1),
.fifo_empty(cb_fifo_empty1), .rdata_valid(cb_out_enable1));
sync_fifo_32 u16(.clk(clk), .rst(rst), .read_req(cr_read_req),
.write_data(cr_JPEG_bitstream), .write_enable(cr_write_enable),
.read_data(cr_bits_out),
.fifo_empty(cr_fifo_empty), .rdata_valid(cr_out_enable));
sync_fifo_32 u25(.clk(clk), .rst(rst), .read_req(cb_read_req2),
.write_data(cb_JPEG_bitstream2), .write_enable(cb_write_enable2),
.read_data(cb_bits_out2),
.fifo_empty(cb_fifo_empty2), .rdata_valid(cb_out_enable2));
sync_fifo_32 u16(.clk(clk), .rst(rst), .read_req(cr_read_req1),
.write_data(cr_JPEG_bitstream1), .write_enable(cr_write_enable1),
.read_data(cr_bits_out1),
.fifo_empty(cr_fifo_empty1), .rdata_valid(cr_out_enable1));
sync_fifo_32 u24(.clk(clk), .rst(rst), .read_req(cr_read_req2),
.write_data(cr_JPEG_bitstream2), .write_enable(cr_write_enable2),
.read_data(cr_bits_out2),
.fifo_empty(cr_fifo_empty2), .rdata_valid(cr_out_enable2));
sync_fifo_32 u17(.clk(clk), .rst(rst), .read_req(y_read_req),
.write_data(y_JPEG_bitstream), .write_enable(y_write_enable),
.read_data(y_bits_out),
.fifo_empty(y_fifo_empty), .rdata_valid(y_out_enable));
 
always @(posedge clk)
begin
if (rst)
fifo_mux <= 0;
else if (end_of_block_output)
fifo_mux <= fifo_mux + 1;
end
always @(posedge clk)
begin
if (y_fifo_empty || read_mux != 3'b001)

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