OpenCores
URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /klc32/trunk
    from Rev 6 to Rev 7
    Reverse comparison

Rev 6 → Rev 7

/rtl/verilog/REGFETCHA.v
26,10 → 26,11
a <= rfo;
b <= 32'd0;
Rn <= ir[20:16];
if (opcode==`RR || opcode==`RRR) begin
if (opcode==`RR || opcode==`RRR || opcode==`SW || opcode==`SH || opcode==`SB) begin
state <= REGFETCHB;
end
else begin
// RIX format ?
if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
state <= FETCH_IMM32;
else begin
88,6 → 89,10
state <= IFETCH;
end
endcase
`R:
case(func)
`UNLK: state <= UNLK;
endcase
`NOP: state <= IFETCH;
`JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
`JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
130,7 → 135,6
`SETcc: Rn <= ir[15:11];
`PUSH: state <= PUSH1;
`POP: state <= POP1;
`UNLK: state <= UNLK;
endcase
if (isIllegalOpcode) begin
vector <= `ILLEGAL_INSN;
/rtl/verilog/REGFETCHB.v
27,6 → 27,13
Rn <= ir[15:11];
if (opcode==`RRR || (opcode==`RR && (func==`SWX||func==`SHX||func==`SBX)))
state <= REGFETCHC;
else
state <= EXECUTE;
else begin
// RIX format ?
if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
state <= FETCH_IMM32;
else begin
imm <= {{16{ir[15]}},ir[15:0]};
state <= EXECUTE;
end
end
end
/rtl/verilog/MEMORY.v
174,6 → 174,7
adr_o <= ea;
end
else if (ack_i) begin
cyc_o <= ~dat_i[31];
stb_o <= 1'b0;
sel_o <= 4'b0000;
res <= dat_i;

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