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/trunk/rtl/verilog/carry.v
0,0 → 1,49
/* ============================================================================ |
(C) 2005-2007 Robert T Finch |
All rights reserved. |
rob@birdcomputer.ca |
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carry.v |
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Verilog 1995 |
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You may use this source code for non-commercial or evaluation purposes, |
provided this copyright statement and disclaimer remains present in the |
file. |
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NO WARRANTY. |
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER |
EXPRESS OR IMPLIED. The user must assume the entire risk of using the |
Work. |
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY |
INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO |
THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR. |
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK |
IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN |
REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN |
LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU |
AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR |
LOSSES RELATING TO SUCH UNAUTHORIZED USE. |
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This module computes carry for add/subtract given two operands and the |
result. Assuming we don't know what the carry input is and there may |
have been one. |
============================================================================ */ |
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module carry(op, a, b, s, c); |
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input op; // 0=add,1=sub |
input a; |
input b; |
input s; // sum |
output c; |
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assign c = op? (~a&b)|(s&~a)|(s&b) : (a&b)|(a&~s)|(b&~s); |
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endmodule |
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