URL
https://opencores.org/ocsvn/lattice6502/lattice6502/trunk
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Rev 2 → Rev 3
/65C02.vhd
12,7 → 12,7
-- |
-- ************************************************************* |
-- Distributed under the GNU Lesser General Public License. * |
-- This can be obtained from “www.gnu.org”. * |
-- This can be obtained from www.gnu.org. * |
-- ************************************************************* |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
64,6 → 64,20
-- 7 Add the 65C02 stuff. I think the most needed is phx, phy, plx |
-- and ply are the most useful. |
------------------------------------------------------------------------------------ |
-- Revision history |
-- Nov 4, 2010 |
-- Rationalized all flavours of cmp, cpy and cpx. |
-- Changed jsr to combine out_dat1 and out_dat2 into out_dat. |
-- Changed wr_ctr to wr_fg. |
-- This saved 43 slices, 69% of slices are used. |
-- Removed many redundant comment lines. |
-- ****************************************************************** |
-- Nov 1, 2010 |
-- Double quotes inside a comment line rejected by ghdl |
-- cmp carry not set when equal |
-- php not saving flags, had to add a cycle for flags to prop in cycle 0 |
-- |
-- ****************************************************************************** |
|
library IEEE; --Use standard IEEE libs as recommended by Tristan. |
use IEEE.STD_LOGIC_1164.ALL; |
79,8 → 93,6
proc_write: inout std_logic; |
irq: in std_logic; --Active 0 |
nmi: in std_logic; --Neg transition. |
-- cycle_mark : out std_logic; |
-- add_hold : inout unsigned(15 downto 14); |
address: inout unsigned(15 downto 0) |
); |
end P65C02; |
93,10 → 105,10
signal add_hold : unsigned(15 downto 0); |
signal reg_a : unsigned(8 downto 0); |
signal reg_x, reg_y, reg_s, reg_sp : unsigned(7 downto 0); |
signal Instruction_in, dat_in1, dat_in2, dat_out1, dat_out2 : unsigned(7 downto 0); |
signal n_fg, v_fg, b_fg, d_fg, i_fg, z_fg, v_ff : std_logic; |
signal Instruction_in, dat_in1, dat_in2, dat_out : unsigned(7 downto 0); |
signal n_fg, v_fg, b_fg, d_fg, i_fg, z_fg, v_ff, wr_fg : std_logic; |
signal cycle_ctr, add_fg : unsigned(3 downto 0); |
signal wr_ctr, flags_fg : unsigned(1 downto 0); |
signal flags_fg : unsigned(1 downto 0); |
|
|
signal reset_fg, irq_fg, nmi_fg, start_fg, pc_inc_fg, branch_fg: std_logic; |
116,7 → 128,6
dat_in2 <= dat_in1; |
dat_in1 <= data_rd; |
|
-- if cycle_ctr = x"0" and start_fg = '0' then |
if cycle_ctr = x"0" then |
if irq = '0' or nmi = '0' or (reset = '1' and reset_fg = '0') then |
Instruction_in <= x"00"; |
156,9 → 167,7
begin |
if reset = '0' then |
address <= reg_pc; |
-- elsif rising_edge(clock) then |
else |
|
Case add_fg is |
when x"0" => |
address <= reg_pc; |
222,7 → 231,6
address(7 downto 0) <= dat_in1 + reg_x + "1"; |
address(15 downto 8) <= x"00"; |
when x"F" => --Hold address steady for INC etc |
-- address <= address; |
address <= add_hold; |
when others => |
address <= reg_pc; |
239,19 → 247,15
end if; |
end process hold_address; |
|
memory_proc_write:process(clock, reset, wr_ctr) |
memory_proc_write:process(clock, reset, wr_fg) |
begin |
if reset = '0' then |
data_wr <= (others => '0'); |
proc_write <= '0'; |
elsif rising_edge(clock) then |
proc_write <= wr_ctr(0) or wr_ctr(1); |
if wr_ctr = "01" then |
data_wr <= dat_out1; |
elsif wr_ctr = "10" then |
data_wr <= dat_out2; |
else |
data_wr <= x"22"; |
proc_write <= wr_fg; |
if wr_fg = '1' then |
data_wr <= dat_out; |
end if; |
end if; |
end process memory_proc_write; |
260,7 → 264,6
begin |
if reset = '0' then |
cycle_ctr <= (others => '0'); |
-- cycle_mark <= '0'; |
pc_inc_fg <= '0'; |
pc_dec_fg <= '0'; |
dat2pc_fg <= '0'; |
267,7 → 270,7
add_fg <= (others => '0'); |
branch_fg <= '0'; |
flags_fg <= (others => '0'); |
wr_ctr <= "00"; |
wr_fg <= '0'; |
reg_a <= (others => '0'); |
reg_x <= (others => '0'); |
reg_y <= (others => '0'); |
284,18 → 287,15
v_ff <= '0'; |
nmi_fg <= '0'; |
irq_fg <= '0'; |
dat_out1 <= (others => '0'); |
dat_out2<= (others => '0'); |
dat_out <= (others => '0'); |
|
--elsif rising_edge(clock) and run_fg = '1' then |
elsif rising_edge(clock) then |
-- v_ff <= dat_out2(7); --Used to track the v_fg |
reset_fg <= reset; |
|
-- This section is to get started |
if reset = '1' and reset_fg = '0' then |
start_fg <= '1'; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
add_fg <= x"8"; --get start up vectors FFFC FFFD |
cycle_ctr <= x"5"; --Jump into cycle 5 add_fg <= x'8' |
-- end if; |
305,12 → 305,11
case cycle_ctr is --cycle counter case |
when x"0" => |
|
-- cycle_mark <= '1'; |
if reset_fg = '1' and reset = '1' then |
|
if flags_fg /= "00" then |
n_fg <= dat_out2(7); |
if dat_out2 = x"00" then |
n_fg <= dat_out(7); |
if dat_out = x"00" then |
z_fg <= '1'; |
else |
z_fg <= '0'; |
340,14 → 339,12
|
-- =========================================================================================== |
when x"48" => --PHA 1st part accumulator onto stack |
wr_ctr <= "01"; |
dat_out1 <= reg_a(7 downto 0); |
wr_fg <= '1'; |
dat_out <= reg_a(7 downto 0); |
pc_dec_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"08" => --PHP 1st part status onto stack |
wr_ctr <= "01"; |
dat_out1 <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8); |
pc_dec_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
379,17 → 376,17
when x"88" => --DEY Decrement y reg |
reg_y <= reg_y - "1"; |
flags_fg <= "01"; |
dat_out2 <= reg_y - "1"; |
dat_out <= reg_y - "1"; |
cycle_ctr <= x"0"; |
when x"98" => --TYA transfer Y to A |
reg_a(7 downto 0) <= reg_y; |
flags_fg <= "01"; |
dat_out2 <= reg_y; |
dat_out <= reg_y; |
cycle_ctr <= x"0"; |
when x"A8" => --TAY transfer A to Y |
reg_y <= reg_a(7 downto 0); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0); |
dat_out <= reg_a(7 downto 0); |
cycle_ctr <= x"0"; |
when x"B8" => --CLV clear overflow flag |
v_fg <= '0'; |
398,7 → 395,7
when x"C8" => --INY increment Y reg |
reg_y <= reg_y + x"1"; |
flags_fg <= "01"; |
dat_out2 <= reg_y + x"1"; |
dat_out <= reg_y + x"1"; |
cycle_ctr <= x"0"; |
when x"D8" => --CLD Clear decimnal flag |
d_fg <= '0'; |
406,7 → 403,7
when x"E8" => --INX increment X reg |
reg_x <= reg_x + x"1"; |
flags_fg <= "01"; |
dat_out2 <= reg_x + x"1"; |
dat_out <= reg_x + x"1"; |
cycle_ctr <= x"0"; |
when x"F8" => --SLD Set decimnal flag |
d_fg <= '1'; |
414,25 → 411,25
when x"2A" => --ROL A Rotate Left one bit 1st part. |
reg_a(8 downto 1) <= reg_a(7 downto 0); |
reg_a(0) <= reg_a(8); |
dat_out2(7 downto 1) <= reg_a(6 downto 0); |
dat_out2(0) <= reg_a(8); |
dat_out(7 downto 1) <= reg_a(6 downto 0); |
dat_out(0) <= reg_a(8); |
flags_fg <= "01"; |
cycle_ctr <= x"0"; |
when x"6A" => --ROR A Rotateft right one bit 1st part. |
reg_a(7 downto 0) <= reg_a(8 downto 1); |
reg_a(8) <= reg_a(0); |
dat_out2 <= reg_a(8 downto 1); |
dat_out <= reg_a(8 downto 1); |
flags_fg <= "01"; |
cycle_ctr <= x"0"; |
when x"0A" => --ASL A Shift Left one bit 1st part. |
reg_a <= reg_a(7 downto 0) & '0'; |
dat_out2 <= reg_a(6 downto 0) & '0'; |
dat_out <= reg_a(6 downto 0) & '0'; |
flags_fg <= "01"; |
cycle_ctr <= x"0"; |
when x"4A" => --LSR A Logical Shift Right one bit 1st part. |
reg_a(7 downto 0) <= '0' & reg_a(7 downto 1); |
reg_a(8) <= reg_a(0); |
dat_out2 <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & reg_a(7 downto 1); |
flags_fg <= "01"; |
cycle_ctr <= x"0"; |
when x"9A" => --TXS |
441,22 → 438,22
when x"AA" => --TAX |
reg_x <= reg_a(7 downto 0); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0); |
dat_out <= reg_a(7 downto 0); |
cycle_ctr <= x"0"; |
when x"8A" => --TXA |
reg_a(7 downto 0) <= reg_x; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0); |
dat_out <= reg_a(7 downto 0); |
cycle_ctr <= x"0"; |
when x"BA" => --TSX |
reg_x <= reg_sp; |
flags_fg <= "01"; |
dat_out2 <= reg_sp; |
dat_out <= reg_sp; |
cycle_ctr <= x"0"; |
when x"CA" => --DEX |
reg_x <= reg_X - X"01"; |
flags_fg <= "01"; |
dat_out2 <= reg_x - X"01"; |
dat_out <= reg_x - X"01"; |
cycle_ctr <= x"0"; |
-- ============================================================================================= |
when x"F0" => --BEQ branch true 1st part. |
513,29 → 510,29
|
-- ============================================================================================= |
when x"84" => --STY zero 1st part proto |
dat_out1 <= reg_y; |
wr_ctr <= "01"; |
dat_out <= reg_y; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"85" => --STA zero 1st part proto |
dat_out1 <= reg_a(7 downto 0); |
wr_ctr <= "01"; |
dat_out <= reg_a(7 downto 0); |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"86" => --STX zero 1st part proto |
dat_out1 <= reg_x; |
wr_ctr <= "01"; |
dat_out <= reg_x; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"94" => --STY zero, X 1st part proto |
dat_out1 <= reg_y; |
dat_out <= reg_y; |
add_fg <= x"2"; |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"95" => --STA zero, X 1st part proto |
dat_out1 <= reg_a(7 downto 0); |
wr_ctr <= "01"; |
dat_out <= reg_a(7 downto 0); |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"96" => --STX zero, Y 1st part proto |
dat_out1 <= reg_x; |
wr_ctr <= "01"; |
dat_out <= reg_x; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
|
-- =============================================================================================== |
765,19 → 762,19
cycle_ctr <= cycle_ctr + x"1"; |
--......................................................................................... |
when x"8D" => --STA abs 1st part. |
dat_out1 <= reg_a(7 downto 0); |
dat_out <= reg_a(7 downto 0); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"9D" => --STA,x abs 1st part. |
dat_out1 <= reg_a(7 downto 0); |
dat_out <= reg_a(7 downto 0); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"99" => --STA, y abs 1st part. |
dat_out1 <= reg_a(7 downto 0); |
dat_out <= reg_a(7 downto 0); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"8E" => --STX abs 1st part. |
dat_out1 <= reg_x; |
dat_out <= reg_x; |
cycle_ctr <= cycle_ctr + x"1";-- |
when x"8C" => --STY abs 1st part. |
dat_out1 <= reg_y; |
dat_out <= reg_y; |
cycle_ctr <= cycle_ctr + x"1"; |
--......................................................................................... |
|
816,7 → 813,6
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"20" => --JSR abs first part |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"60" => --RTS first part |
reg_sp <= reg_sp - "1"; |
847,8 → 843,6
|
|
when x"1" => |
-- cycle_mark <= '0'; |
|
case Instruction_in is |
-- ================================================================================================ |
|
855,12 → 849,12
when x"48" => --PHA 2nd part accumulator onto stack |
pc_dec_fg <= '0'; |
add_fg <= x"7"; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"08" => --PHP 2nd part Status reg onto stack |
wr_fg <= '1'; |
pc_dec_fg <= '0'; |
add_fg <= x"7"; |
wr_ctr <= "00"; |
dat_out <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8); |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"68" => --PLA 2nd part Pull Accumulator from Stack |
933,43 → 927,37
when x"A2" => --LDX #. 2nd part Proto imediate instruction |
pc_inc_fg <= '0'; |
reg_x <= data_rd; |
-- flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"A9" => --LDA #. 2nd part Proto imediate instruction |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
flags_fg <= "01"; |
reg_a(7 downto 0) <= data_rd; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"A0" => --LDY # |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
flags_fg <= "01"; |
reg_y <= data_rd; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"09" => --ORA # |
pc_inc_fg <= '0'; |
add_fg <= x"0"; |
-- flags_fg <= "01"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
dat_out <= reg_a(7 downto 0) and data_rd; |
cycle_ctr <= x"0"; |
when x"29" => --AND # 2nd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
flags_fg <= "01"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
dat_out <= reg_a(7 downto 0) and data_rd; |
cycle_ctr <= x"0"; |
when x"49" => --EOR # |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
flags_fg <= "01"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; |
dat_out2 <= reg_a(7 downto 0) xor data_rd; |
dat_out <= reg_a(7 downto 0) xor data_rd; |
cycle_ctr <= x"0"; |
when x"69" => --ADC # |
pc_inc_fg <= '0'; |
976,7 → 964,7
v_ff <= not reg_a(7) and not data_rd(7); --Pos+Pos=Overflow possible |
flags_fg <= "10"; |
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); |
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
cycle_ctr <= x"0"; |
when x"E9" => --SBC # 2nd part |
pc_inc_fg <= '0'; |
983,14 → 971,14
v_ff <= reg_a(7) and data_rd(7); --Neg-Neg=Underflow possible |
flags_fg <= "10"; |
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); |
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
cycle_ctr <= x"0"; |
|
when x"C9" => --CMP # 2nd part. |
pc_inc_fg <= '0'; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) > data_rd then |
dat_out <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
999,8 → 987,8
when x"E0" => --CPX #. |
pc_inc_fg <= '0'; |
flags_fg <= "01"; |
dat_out2 <= reg_x - data_rd; |
if reg_x > data_rd then |
dat_out <= reg_x - data_rd; |
if reg_x >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
1009,8 → 997,8
when x"C0" => --CPY #. |
pc_inc_fg <= '0'; |
flags_fg <= "01"; |
dat_out2 <= reg_y - data_rd; |
if reg_y > data_rd then |
dat_out <= reg_y - data_rd; |
if reg_y >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
1020,27 → 1008,27
-- =================================================================================================== |
when x"84" => --STY zero 2nd part proto |
add_fg <= x"1"; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"85" => --STA zero 2nd part proto |
add_fg <= x"1"; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"86" => --STX zero 2nd part proto |
add_fg <= x"1"; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"94" => --STY zero, X 2nd part proto |
add_fg <= x"2"; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"95" => --STA zero, X 2nd part proto |
add_fg <= x"2"; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"96" => --STX zero, Y 2nd part proto |
add_fg <= x"3"; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
|
-- ================================================================================= |
1120,7 → 1108,7
|
when x"C5" => --CMP zero 2nd part |
pc_inc_fg <= '1'; |
add_fg <= x"f"; |
add_fg <= x"0"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"C6" => --DEC zero 2nd part |
add_fg <= x"f"; |
1252,6 → 1240,7
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"3D" => --AND, x abs 2nd part. |
|
add_fg <= x"5"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"39" => --AND, Y abs 2nd part. |
1332,19 → 1321,19
cycle_ctr <= cycle_ctr + x"1"; |
-- ............................................................................... |
when x"8D" => --STA abs 2nd part. |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"9D" => --STA,x abs 2nd part. |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"99" => --STA, y abs 2nd part. |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"8E" => --STX abs 2nd part. |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"8C" => --STY abs 2nd part. |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
-- ........................................................................ |
|
1396,11 → 1385,8
cycle_ctr <= cycle_ctr + "1"; |
when x"20" => --JSR abs 2nd part |
dat2pc_fg <= '1'; |
pc_inc_fg <= '0'; |
wr_ctr <= "10"; |
-- add_fg <= x"7"; |
dat_out1 <= reg_pc(7 downto 0); |
dat_out2 <= reg_pc(15 downto 8); |
wr_fg <= '1'; |
dat_out <= reg_pc(15 downto 8); |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"60" => --RTS second part |
1411,10 → 1397,10
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break second part cyc 1 |
wr_ctr <= "01"; --put dat_out2 onto stack |
dat_out1 <= reg_pc(15 downto 8); |
dat2pc_fg <= '0'; |
wr_fg <= '1'; --put dat_out onto stack |
dat_out <= reg_pc(15 downto 8); |
add_fg <= x"7"; |
dat2pc_fg <= '0'; |
pc_dec_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
1436,18 → 1422,17
reg_sp <= reg_sp + "1"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"08" => --PHP 3rd part Status reg onto stack |
pc_inc_fg <= '1'; |
add_fg <= x"0"; |
reg_sp <= reg_sp + "1"; |
wr_fg <= '0'; |
add_fg <= x"7"; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"68" => --PLA 3rd part Pull Accumulator from Stack |
pc_dec_fg <= '0'; |
-- pc_dec_fg <= '0'; |
add_fg <= x"0"; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"28" => --PLP 3rd part Pull Status from Stack |
pc_dec_fg <= '0'; |
-- pc_dec_fg <= '0'; |
add_fg <= x"0"; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
1516,6 → 1501,7
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
end if; |
|
-- ==================================================================================== |
when x"84" => --STY zero 3rd part proto |
pc_inc_fg <= '1'; |
1545,128 → 1531,116
-- ======================================================================================== |
when x"A5" => --LDA zero 3rd part proto |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"A4" => --LDY zero 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_y <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"A6" => --LDX zero 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_x <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"B5" => --LDA zero,X 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"B4" => --LDY zero,X 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_y <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"B6" => --LDX zero,Y 3rd part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_x <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= x"0"; |
when x"05" => --ORA zero 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) or data_rd; |
dat_out <= reg_a(7 downto 0) or data_rd; |
cycle_ctr <= x"0"; |
when x"15" => --ORA zero,X 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) or data_rd; |
dat_out <= reg_a(7 downto 0) or data_rd; |
cycle_ctr <= x"0"; |
when x"24" => --BIT zero 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
n_fg <= data_rd(7); |
v_fg <= data_rd(6); |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
dat_out <= reg_a(7 downto 0) and data_rd; |
flags_fg <= "01"; |
cycle_ctr <= x"0"; |
when x"25" => --AND zero 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
dat_out <= reg_a(7 downto 0) and data_rd; |
cycle_ctr <= x"0"; |
|
when x"35" => --AND zero,X 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
dat_out <= reg_a(7 downto 0) and data_rd; |
cycle_ctr <= x"0"; |
|
when x"45" => --EOR zero 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) xor data_rd; |
dat_out <= reg_a(7 downto 0) xor data_rd; |
cycle_ctr <= x"0"; |
|
when x"55" => --EOR zero,X 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) xor data_rd; |
dat_out <= reg_a(7 downto 0) xor data_rd; |
cycle_ctr <= x"0"; |
|
when x"65" => --ADC zero 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
cycle_ctr <= x"0"; |
|
when x"75" => --ADC zero,X 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
cycle_ctr <= x"0"; |
|
when x"C4" => --CPY zero 3rd part |
flags_fg <= "01"; |
dat_out <= reg_y - data_rd; |
if reg_y >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
end if; |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
cycle_ctr <= x"0"; |
when x"C5" => --CMP zero 3rd part |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) > data_rd then |
dat_out <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
1674,15 → 1648,15
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
when x"C6" => --DEC zero 3rd part |
dat_out1 <= data_rd - x"01"; |
dat_out2 <= data_rd - x"01"; |
wr_ctr <= "01"; |
dat_out <= data_rd - x"01"; |
dat_out <= data_rd - x"01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"D5" => --CMP zero,X 3rd part |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) > data_rd then |
dat_out <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
1694,20 → 1668,22
add_fg <= x"0"; |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= cycle_ctr + "1"; |
when x"E4" => --CPX zero 3rd part |
flags_fg <= "01"; |
dat_out <= reg_x - data_rd; |
if reg_X >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
end if; |
pc_inc_fg <= '0'; |
add_fg <= x"0"; |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
cycle_ctr <= x"0"; |
when x"E5" => --SBC zero 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); |
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
flags_fg <= "01"; |
cycle_ctr <= x"0"; |
|
1714,83 → 1690,71
|
when x"F5" => --SBC zero,X 3rd part |
pc_inc_fg <= '0'; |
-- add_fg <= x"0"; |
reg_a <= reg_a - ('0' & data_rd) - ("00000000" & reg_a(8)); |
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
flags_fg <= "01"; |
cycle_ctr <= x"0"; |
|
when x"E6" => --INC zero 3rd part |
dat_out1 <= data_rd + x"01"; |
dat_out2 <= data_rd + x"01"; |
wr_ctr <= "01"; |
dat_out <= data_rd + x"01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"F6" => --INC zero,X 3rd part |
dat_out1 <= data_rd + x"01"; |
dat_out2 <= data_rd + x"01"; |
wr_ctr <= "01"; |
dat_out <= data_rd + x"01"; |
|
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
|
when x"66" => --ROR zero 3rd part |
reg_a(8) <= data_rd(0); |
dat_out1 <= reg_a(8) & data_rd(7 downto 1); |
dat_out2 <= reg_a(8) & data_rd(7 downto 1); |
wr_ctr <= "01"; |
dat_out <= reg_a(8) & data_rd(7 downto 1); |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
|
when x"76" => --ROR zero,X 3rd part |
reg_a(8) <= data_rd(0); |
dat_out1 <= reg_a(8) & data_rd(7 downto 1); |
dat_out2 <= reg_a(8) & data_rd(7 downto 1); |
wr_ctr <= "01"; |
dat_out <= reg_a(8) & data_rd(7 downto 1); |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
|
when x"26" => --ROL zero 3rd part |
dat_out1(7 downto 1) <= data_rd(6 downto 0); |
dat_out1(0) <= reg_a(8); |
dat_out2(7 downto 1) <= data_rd(6 downto 0); |
dat_out2(0) <= reg_a(8); |
dat_out(7 downto 1) <= data_rd(6 downto 0); |
dat_out(0) <= reg_a(8); |
flags_fg <= "01"; |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"36" => --ROL zero,X 3rd part |
dat_out1(7 downto 1) <= data_rd(6 downto 0); |
dat_out1(0) <= reg_a(8); |
dat_out2(7 downto 1) <= data_rd(6 downto 0); |
dat_out2(0) <= reg_a(8); |
dat_out(7 downto 1) <= data_rd(6 downto 0); |
dat_out(0) <= reg_a(8); |
flags_fg <= "01"; |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"46" => --LSR zero 3rd part |
dat_out1 <= '0' & reg_a(7 downto 1); |
dat_out2 <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & reg_a(7 downto 1); |
reg_a(8) <= data_rd(0); |
wr_ctr <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"56" => --LSR zero,X 3rd part |
dat_out1 <= '0' & reg_a(7 downto 1); |
dat_out2 <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & reg_a(7 downto 1); |
reg_a(8) <= data_rd(0); |
wr_ctr <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"06" => --ASL zero 3rd part |
reg_a(8) <= data_rd(7); |
dat_out1 <= data_rd(6 downto 0) & '0'; |
dat_out2 <= data_rd(6 downto 0) & '0'; |
wr_ctr <= "01"; |
dat_out <= data_rd(6 downto 0) & '0'; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"16" => --ASL zero,X 3rd part |
reg_a(8) <= data_rd(7); |
dat_out1 <= data_rd(6 downto 0) & data_rd(0); |
dat_out2 <= data_rd(6 downto 0) & data_rd(0); |
wr_ctr <= "01"; |
dat_out <= data_rd(6 downto 0) & data_rd(0); |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
|
1846,13 → 1810,13
|
when x"81" => --STA (zero,x) 3rd part proto |
add_fg <= x"4"; |
wr_ctr <= "01"; |
dat_out1 <= reg_a(7 downto 0); |
wr_fg <= '1'; |
dat_out <= reg_a(7 downto 0); |
cycle_ctr <= cycle_ctr + "1"; |
when x"91" => --STA (zero),y 3rd part proto |
add_fg <= x"6"; |
wr_ctr <= "01"; |
dat_out1 <= reg_a(7 downto 0); |
wr_fg <= '1'; |
dat_out <= reg_a(7 downto 0); |
cycle_ctr <= cycle_ctr + "1"; |
-- ============================================================================== |
when x"AD" => --LDA abs 3rd part. |
1982,27 → 1946,27
|
-- ................................................................................ |
when x"8D" => --STA abs 3rd part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
add_fg <= x"4"; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"9D" => --STA,x abs 3rd part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
add_fg <= x"5"; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"99" => --STA, y abs 3rd part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
add_fg <= x"6"; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"8E" => --STX abs 3rd part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
add_fg <= x"4"; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"8C" => --STY abs 3rd part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
add_fg <= x"4"; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
2055,8 → 2019,8
when x"20" => --JSR abs 3rd part |
dat2pc_fg <= '0'; |
add_fg <= x"7"; |
wr_ctr <= "01"; |
-- reg_sp <= reg_sp + "1"; |
wr_fg <= '1'; |
dat_out <= reg_pc(7 downto 0); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"60" => --RTS third part |
dat2pc_fg <= '1'; |
2076,7 → 2040,7
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break third part cyc 2 |
dat_out1 <= reg_pc(7 downto 0); --put dat_out1 onto stack set up dat_out2 |
dat_out <= reg_pc(7 downto 0); --put dat_out onto stack set up dat_out |
reg_sp <= reg_sp + "1"; |
cycle_ctr <= cycle_ctr + x"1"; |
|
2125,8 → 2089,10
|
|
when x"08" => --PHP 4th part accumulator onto stack |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
pc_inc_fg <= '1'; |
add_fg <= x"0"; |
reg_sp <= reg_sp + "1"; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"48" => --PHA 4th part accumulator onto stack |
pc_inc_fg <= '0'; |
2184,42 → 2150,42
-- ====================================================================================== |
|
when x"E6" => --INC zero fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"F6" => --INC zero,X fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= x"0"; |
when x"C6" => --DEC zero fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"D6" => --DEC zero,X fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= x"0"; |
|
when x"26" => --ROL zero fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"36" => --ROL zero,X fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"66" => --ROR zero fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"76" => --ROR zero,X fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"06" => --ASL zero fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"16" => --ASL zero,X fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"46" => --LSR zero fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"56" => --LSR zero,X fourth part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
-- |
-- ============================================================================== |
2226,216 → 2192,168
when x"AD" => --LDA abs 4th part. |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
pc_inc_fg <= '1'; |
dat_out <= data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"BD" => --LDA, x abs 4th part. |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
pc_inc_fg <= '1'; |
dat_out <= data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"B9" => --LDA, Y abs 4th part |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
pc_inc_fg <= '1'; |
dat_out <= data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
|
|
when x"2D" => --AND abs 4th part. |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) and data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"3D" => --AND, x abs 4th part. |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) and data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"39" => --AND, Y abs 4th part. |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) and data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"0D" => --ORA abs 4th part. |
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) or data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) or data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"1D" => --ORA, x abs 4th part. |
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) or data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) or data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"19" => --ORA, Y abs 4th part. |
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) or data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) or data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"4D" => --EOR abs 4th part. |
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) xor data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) xor data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"5D" => --EOR, x abs 4th part. |
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) xor data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) xor data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"59" => --EOR, Y abs 4th part. |
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) xor data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) xor data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"6D" => --ADC abs 4th part. |
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"7D" => --ADC, x abs 4th part. |
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"79" => --ADC, Y abs 4th part. |
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"ED" => --SBC abs 4th part. |
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"FD" => --SBC, x abs 4th part. |
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"F9" => --SBC, Y abs 4th part. |
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"AE" => --LDX abs 4th part. |
reg_x <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
-- pc_inc_fg <= '1'; |
dat_out <= data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"BE" => --LDX, y abs 4th part. |
reg_x <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
-- pc_inc_fg <= '1'; |
dat_out <= data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"AC" => --LDY abs 4th part. |
reg_y <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"BC" => --LDY, x abs 4th part. |
reg_y <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
-- pc_inc_fg <= '1'; |
dat_out <= data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"2C" => --BIT abs 4th part. |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
pc_inc_fg <= '1'; |
dat_out <= reg_a(7 downto 0) and data_rd; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"CD" => --CMP abs 4th part. |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) > data_rd then |
dat_out <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
end if; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"DD" => --CMP, x abs 4th part. |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) > data_rd then |
dat_out <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
end if; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"D9" => --CMP, Y abs 4th part. |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) > data_rd then |
dat_out <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
end if; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"EC" => --CPX abs 4th part. |
if reg_x = data_rd then |
z_fg <= '1'; |
else |
z_fg <= '0'; |
end if; |
flags_fg <= "01"; |
dat_out <= reg_x - data_rd; |
if reg_x >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
end if; |
if reg_x < data_rd then |
n_fg <= '1'; |
else |
n_fg <= '0'; |
end if; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"CC" => --CPY abs 4th part. |
if reg_y = data_rd then |
z_fg <= '1'; |
else |
z_fg <= '0'; |
end if; |
flags_fg <= "01"; |
dat_out <= reg_y - data_rd; |
if reg_y >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
end if; |
if reg_y < data_rd then |
n_fg <= '1'; |
else |
n_fg <= '0'; |
end if; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
-- ................................................................................. |
when x"8D" => --STA abs 4th part. |
2459,86 → 2377,72
-- ........................................................................ |
|
when x"EE" => --INC abs 4th part. |
dat_out1 <= data_rd + x"01"; |
dat_out2 <= data_rd + x"01"; |
wr_ctr <= "01"; |
dat_out <= data_rd + x"01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"FE" => --INC, x abs 4th part. |
dat_out1 <= data_rd + x"01"; |
dat_out2 <= data_rd + x"01"; |
wr_ctr <= "01"; |
dat_out <= data_rd + x"01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"CE" => --DEC abs 4th part. |
dat_out1 <= data_rd - x"01"; |
dat_out2 <= data_rd - x"01"; |
wr_ctr <= "01"; |
dat_out <= data_rd - x"01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"DE" => --DEC, x abs 4th part. |
dat_out1 <= data_rd - x"01"; |
dat_out2 <= data_rd - x"01"; |
wr_ctr <= "01"; |
dat_out <= data_rd - x"01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"2E" => --ROL abs 4th part. |
dat_out1(7 downto 1) <= data_rd(6 downto 0); |
dat_out1(0) <= reg_a(8); |
dat_out2(7 downto 1) <= data_rd(6 downto 0); |
dat_out2(0) <= reg_a(8); |
dat_out(7 downto 1) <= data_rd(6 downto 0); |
dat_out(0) <= reg_a(8); |
flags_fg <= "01"; |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"3E" => --ROL, x abs 4th part. |
dat_out1(7 downto 1) <= data_rd(6 downto 0); |
dat_out1(0) <= reg_a(8); |
dat_out2(7 downto 1) <= data_rd(6 downto 0); |
dat_out2(0) <= reg_a(8); |
dat_out(7 downto 1) <= data_rd(6 downto 0); |
dat_out(0) <= reg_a(8); |
flags_fg <= "01"; |
wr_ctr <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"6E" => --ROR abs 4th part. |
reg_a(8) <= data_rd(0); |
dat_out1 <= reg_a(8) & data_rd(7 downto 1); |
dat_out2 <= reg_a(8) & data_rd(7 downto 1); |
wr_ctr <= "01"; |
dat_out <= reg_a(8) & data_rd(7 downto 1); |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"7E" => --ROR, x abs 4th part. |
reg_a(8) <= data_rd(0); |
dat_out1 <= reg_a(8) & data_rd(7 downto 1); |
dat_out2 <= reg_a(8) & data_rd(7 downto 1); |
wr_ctr <= "01"; |
dat_out <= reg_a(8) & data_rd(7 downto 1); |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"4E" => --LSR abs 4th part. |
dat_out1 <= '0' & reg_a(7 downto 1); |
dat_out2 <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & reg_a(7 downto 1); |
reg_a(8) <= data_rd(0); |
wr_ctr <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"5E" => --LSR, x abs 4th part. |
dat_out1 <= '0' & reg_a(7 downto 1); |
dat_out2 <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & reg_a(7 downto 1); |
reg_a(8) <= data_rd(0); |
wr_ctr <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"0E" => --ASL abs 4th part. |
reg_a(8) <= data_rd(7); |
dat_out1 <= data_rd(6 downto 0) & data_rd(0); |
dat_out2 <= data_rd(6 downto 0) & data_rd(0); |
wr_ctr <= "01"; |
dat_out <= data_rd(6 downto 0) & data_rd(0); |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"1E" => --ASL, x abs 4th part. |
reg_a(8) <= data_rd(7); |
dat_out1 <= data_rd(6 downto 0) & data_rd(0); |
dat_out2 <= data_rd(6 downto 0) & data_rd(0); |
wr_ctr <= "01"; |
dat_out <= data_rd(6 downto 0) & data_rd(0); |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
-- ............................................................................ |
2616,14 → 2520,10
|
|
when x"81" => --STA (zero,x) 4th part proto |
-- add_fg <= x"0"; |
-- pc_inc_fg <= '1'; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"91" => --STA (zero),y 4th part proto |
-- add_fg <= x"0"; |
-- pc_inc_fg <= '1'; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
-- ================================================================================== |
|
2636,10 → 2536,8
pc_inc_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"20" => --JSR indirect 4th part |
-- add_fg <= x"0"; |
wr_ctr <= "00"; |
wr_fg <= '0'; |
reg_sp <= reg_sp + "1"; |
-- pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"60" => --RTS fourth part |
dat2pc_fg <= '0'; |
2653,7 → 2551,7
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break forth extra part cyc 3 |
dat_out1 <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8); |
dat_out <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8); |
reg_sp <= reg_sp + "1"; |
cycle_ctr <= cycle_ctr + x"1"; |
|
2670,6 → 2568,10
when x"4" => |
case Instruction_in is |
-- ====================================================================================== |
when x"08" => --PHP 5th part accumulator onto stack |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
when x"F0" => --BEQ branch true 5th part. |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
2702,7 → 2604,7
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"F6" => --INC zero,X 5th part |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '0'; |
add_fg <= x"0"; |
cycle_ctr <= x"0"; |
2826,7 → 2728,7
cycle_ctr <= x"0"; |
|
when x"CD" => --CMP 5th part. |
wr_ctr <= "10"; pc_inc_fg <= '0'; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
when x"DD" => --CMP, x 5th part. |
pc_inc_fg <= '0'; |
2859,52 → 2761,52
-- ............................................................................ |
|
when x"EE" => --INC abs 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"FE" => --INC, x 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"CE" => --DEC 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"DE" => --DEC, x 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"2E" => --ROL 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"3E" => --ROL, x 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"6E" => --ROR 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"7E" => --ROR, x 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"4E" => --LSR 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"5E" => --LSR, x 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"0E" => --ASL 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"1E" => --ASL, x 5th part. |
wr_ctr <= "00"; |
wr_fg <= '0'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
-- ............................................................................ |
2912,13 → 2814,13
when x"A1" => --LDA (zero,x) 5th part proto |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
when x"B1" => --LDA (zero),y 5th part proto |
reg_a(7 downto 0) <= data_rd; |
flags_fg <= "01"; |
dat_out2 <= data_rd; |
dat_out <= data_rd; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
2925,13 → 2827,13
when x"21" => --AND (zero,x) 5th part proto |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
dat_out <= reg_a(7 downto 0) and data_rd; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
when x"31" => --AND (zero),y 5th part proto |
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) and data_rd; |
dat_out <= reg_a(7 downto 0) and data_rd; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
2938,13 → 2840,13
when x"42" => --EOR (zero,x) 5th part proto |
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) xor data_rd; |
dat_out <= reg_a(7 downto 0) xor data_rd; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
when x"51" => --EOR (zero),y 5th part proto |
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) xor data_rd; |
dat_out <= reg_a(7 downto 0) xor data_rd; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
2951,13 → 2853,13
when x"01" => --OR (zero,x) 5th part proto |
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) or data_rd; |
dat_out <= reg_a(7 downto 0) or data_rd; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
when x"11" => --OR (zero),y 5th part proto |
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) or data_rd; |
dat_out <= reg_a(7 downto 0) or data_rd; |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
2964,7 → 2866,7
when x"61" => --ADC (zero,x) 5th part proto |
flags_fg <= "01"; |
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); |
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
2971,7 → 2873,7
when x"71" => --ADC (zero),y 5th part proto |
flags_fg <= "01"; |
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); |
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
2978,7 → 2880,7
when x"E1" => --SBC (zero,x) 5th part proto |
flags_fg <= "01"; |
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); |
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
2985,13 → 2887,13
when x"F1" => --SBC (zero),y 5th part proto |
flags_fg <= "01"; |
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); |
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
dat_out <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
when x"C1" => --CMP (zero,x) 5th part proto |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) > data_rd then |
dat_out <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
3001,8 → 2903,8
|
when x"D1" => --CMP (zero),y 5th part proto |
flags_fg <= "01"; |
dat_out2 <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) > data_rd then |
dat_out <= reg_a(7 downto 0) - data_rd; |
if reg_a(7 downto 0) >= data_rd then |
reg_a(8) <= '1'; |
else |
reg_a(8) <= '0'; |
3042,7 → 2944,7
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break fifth part cyc 4 |
wr_ctr <= "00"; |
wr_fg <= '0'; |
reg_sp <= reg_sp + "1"; |
if nmi_fg = '0' then |
add_fg <= x"9"; --Complete stacking start getting vector |
3155,7 → 3057,6
-- ........................................................................................ |
when x"6C" => --JMP indirect 6th part |
pc_inc_fg <= '0'; |
-- dat2pc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
when x"60" => --RTS 6th part |
3178,9 → 3079,8
cycle_ctr <= cycle_ctr + "1"; |
|
when others => |
-- cycle_ctr <= x"0"; |
|
cycle_ctr <= cycle_ctr + x"1"; |
-- --get_inst_fg <= '0'; |
end case; --Cycle 5 |
|
------------------------------------------------------------------------ |
3255,13 → 3155,11
pc_inc_fg <= '1'; |
start_fg <= '0'; |
dat2pc_fg <= '0'; |
-- cycle_ctr <= x"0"; |
cycle_ctr <= cycle_ctr + "1"; |
|
|
when others => |
cycle_ctr <= x"0"; |
--get_inst_fg <= '0'; |
|
end case; --Cycle 7 |
-- Cycle 7 |