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doc/Readme.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/COPYING.LESSER =================================================================== --- doc/COPYING.LESSER (nonexistent) +++ doc/COPYING.LESSER (revision 2) @@ -0,0 +1,166 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. 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doc/COPYING.LESSER Property changes : Added: svn:executable Index: doc/Readme.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/Readme.pdf =================================================================== --- doc/Readme.pdf (nonexistent) +++ doc/Readme.pdf (revision 2)

doc/Readme.pdf Property changes : Added: svn:executable Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/COPYING =================================================================== --- doc/COPYING (nonexistent) +++ doc/COPYING (revision 2) @@ -0,0 +1,675 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. 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doc/COPYING Property changes : Added: svn:executable Index: ispLeaver/65C02.vhd =================================================================== --- ispLeaver/65C02.vhd (nonexistent) +++ ispLeaver/65C02.vhd (revision 2) @@ -0,0 +1,3338 @@ +------------------------------------------------------------------ +-- 6502 principal module. +-- +-- Copyright Ian Chapman October 28 2010 +-- +-- This file is part of the Lattice 6502 project +-- It is used to compile with Linux ghdl and ispLeaver. +-- +-- +-- To do +-- Detailed test of all instructions. +-- +-- ************************************************************* +-- Distributed under the GNU Lesser General Public License. * +-- This can be obtained from “www.gnu.org”. * +-- ************************************************************* +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see +-- +-- 65C02.vhd + + +--- Purpose to test and exercise my VHLD skills +---- I've decided not to support 65C02 instructions +---- nor BCD arithmetic. +---- I will make it run as fast as I can. Timing not per a real 6502 +---- Lattice EBI has clocked address inputs, so as not to add a cycle +---- 6502 address outputs are not latched. The data output of the EBI ROM and +---- RAM is not clocked. +---- To maintain speed the 6502 address to ROM/RAM is not clocked and the data +---- returned is not clocked by ROM/RAM. Structures of form address <= address + "1"; +---- cause a race condition. I had to store the address from the mux for +---- INC type instructions ie read then write. +---- +---- One boob I've just noticed jsr and pha in the 6502 work opposite to +---- what I expected ie jsr decrements the stack and I inc it. I guess +---- that was the way my first computer the SDS sigma 2 did it. I'll keep +---- like that for now in case a bigger stack is needed. Oh no a sigma 2 +---- did not have a stack only L link register. +---- +-- I used this to set the hold timing default "-exp parHoldLimit=999" +-- Also path based placement on +-- When generating a Lattice ROM/RAM untick latche outputs and use +-- the *.mem file generated with my asm2rom.pl script. +------------------------------------------------------------------------------------ +-- TO Do +-- 1 DONE Update all address modes of cmp, cpx and cpy per #mode +-- 2 DONE Add rol, ror, asl, lsr, per inc and dec +-- 3 DONE Correct flags in all modes of item 2 +-- 4 Update the stack instructions, I've it pushing up not down. +-- 5 Continue testing +-- 6 DONE Get a kernel up to test each and every instruction +-- 7 Test all instructions +-- 7 Add the 65C02 stuff. I think the most needed is phx, phy, plx +-- and ply are the most useful. +------------------------------------------------------------------------------------ + +library IEEE; --Use standard IEEE libs as recommended by Tristan. +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +entity P65C02 is + +Port ( + clock: in std_logic; + reset : in std_logic; + data_wr: out unsigned(7 downto 0); + data_rd: in unsigned(7 downto 0); + proc_write: inout std_logic; + irq: in std_logic; --Active 0 + nmi: in std_logic; --Neg transition. +-- cycle_mark : out std_logic; +-- add_hold : inout unsigned(15 downto 14); + address: inout unsigned(15 downto 0) + ); +end P65C02; + +architecture P65C02_architecture of P65C02 is +------------------------------------------------------------------------ +-- Signal Declarations +------------------------------------------------------------------------ +signal reg_pc : unsigned(15 downto 0); +signal add_hold : unsigned(15 downto 0); +signal reg_a : unsigned(8 downto 0); +signal reg_x, reg_y, reg_s, reg_sp : unsigned(7 downto 0); +signal Instruction_in, dat_in1, dat_in2, dat_out1, dat_out2 : unsigned(7 downto 0); +signal n_fg, v_fg, b_fg, d_fg, i_fg, z_fg, v_ff : std_logic; +signal cycle_ctr, add_fg : unsigned(3 downto 0); +signal wr_ctr, flags_fg : unsigned(1 downto 0); + + +signal reset_fg, irq_fg, nmi_fg, start_fg, pc_inc_fg, branch_fg: std_logic; +signal pc_dec_fg, dat2pc_fg : std_logic; +-- End of signal declarations + +begin --architecture +-- ======================================================= +read_mem:process (clock, reset) +begin +if reset = '0' then + dat_in1 <= (others => '0'); + dat_in2 <= (others => '0'); + instruction_in <= (others => '0'); + + elsif rising_edge(clock) then + dat_in2 <= dat_in1; + dat_in1 <= data_rd; + +-- if cycle_ctr = x"0" and start_fg = '0' then + if cycle_ctr = x"0" then + if irq = '0' or nmi = '0' or (reset = '1' and reset_fg = '0') then + Instruction_in <= x"00"; + else + Instruction_in <= data_rd; + end if; + end if; +end if; +end process read_mem; + +-- ======================================================= +Prog_ptr:process (clock, reset, pc_dec_fg) +begin +if reset = '0' then + reg_pc <= x"FFFC"; + elsif rising_edge(clock) then + if dat2pc_fg = '1' then + reg_pc(15 downto 8) <= data_rd; + reg_pc(7 downto 0) <= dat_in1; + + elsif (cycle_ctr = X"0" and not(irq = '0' or nmi = '0' )) or pc_inc_fg = '1' then + reg_pc <= reg_pc + x"0001"; + + elsif pc_dec_fg = '1' then + reg_pc <= reg_pc - x"0001"; + +-- elsif cycle_ctr = x"0" and irq = '0' and i_fg = '0' then +-- reg_pc <= reg_pc - x"0001"; + + elsif branch_fg = '1' then + reg_pc <= reg_pc + (dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1); + end if; +end if; +end process Prog_ptr; + +addressing:process (clock, reset, reg_PC, add_fg) +begin +if reset = '0' then +address <= reg_pc; +-- elsif rising_edge(clock) then + else + + Case add_fg is + when x"0" => + address <= reg_pc; + when x"1" => --Zero page + if proc_write = '0' then + address(7 downto 0) <= data_rd; + else + address(7 downto 0) <= dat_in1; + end if; + address(15 downto 8) <= x"00"; + when x"2" => --Zero page, x + if proc_write = '0' then + address(7 downto 0) <= data_rd + reg_x; + else + address(7 downto 0) <= dat_in1 + reg_x; + end if; + address(15 downto 8) <= x"00"; + + when x"3" => --Zero page, y + if proc_write = '0' then + address(7 downto 0) <= data_rd + reg_y; + else + address(7 downto 0) <= dat_in1 + reg_y; + end if; + address(15 downto 8) <= x"00"; + when x"4" => --Absolute Return sub etc + if proc_write = '0' then + address <= data_rd & dat_in1; + else + address <= dat_in1 & dat_in2; + end if; + when x"5" => --Absolute, x + if proc_write = '0' then + address <= data_rd & dat_in1 + reg_x; + else + address <= dat_in1 & dat_in2 + reg_x; + end if; + when x"6" => --Absolute, y + address <= (data_rd & dat_in1) + reg_y; + + if proc_write = '0' then + address <= data_rd & dat_in1 + reg_y; + else + address <= dat_in1 & dat_in2 + reg_y; + end if; + + when x"7" => --Stack pointer + address <= x"01" & reg_sp; --msb should be hex 01 + when x"8" => --Reset 1st byte + address <= x"FFFC"; + when x"9" => --IRQ and Break 1st byte + address <= x"FFFE"; + when x"A" => --NMI and Break 1st byte + address <= x"FFFA"; + when x"B" => --address + 1 + address <= add_hold + "1"; + when x"C" => --(zero),y + address(7 downto 0) <= dat_in1 + "1"; + address(15 downto 8) <= x"00"; + when x"D" => --(zero,x) + address(7 downto 0) <= dat_in1 + reg_x + "1"; + address(15 downto 8) <= x"00"; + when x"F" => --Hold address steady for INC etc +-- address <= address; + address <= add_hold; + when others => + address <= reg_pc; + end case; +end if; +end process addressing; + +hold_address:process(clock, reset, address) +begin --hold address bus for inc type instructions. +if reset = '0' then + add_hold <= (others => '0'); +elsif rising_edge(clock) then + add_hold <= address; +end if; +end process hold_address; + +memory_proc_write:process(clock, reset, wr_ctr) +begin +if reset = '0' then + data_wr <= (others => '0'); + proc_write <= '0'; +elsif rising_edge(clock) then + proc_write <= wr_ctr(0) or wr_ctr(1); + if wr_ctr = "01" then + data_wr <= dat_out1; + elsif wr_ctr = "10" then + data_wr <= dat_out2; + else + data_wr <= x"22"; + end if; +end if; +end process memory_proc_write; + +instruction_decode:process (clock, reset, irq, nmi) +begin +if reset = '0' then + cycle_ctr <= (others => '0'); +-- cycle_mark <= '0'; + pc_inc_fg <= '0'; + pc_dec_fg <= '0'; + dat2pc_fg <= '0'; + add_fg <= (others => '0'); + branch_fg <= '0'; + flags_fg <= (others => '0'); + wr_ctr <= "00"; + reg_a <= (others => '0'); + reg_x <= (others => '0'); + reg_y <= (others => '0'); + reg_s <= (others => '0'); + reg_sp <= (others => '0'); + n_fg <= '0'; + v_fg <= '0'; + b_fg <= '0'; + d_fg <= '0'; + i_fg <= '0'; + z_fg <= '0'; + reset_fg <= '0'; + start_fg <= '0'; + v_ff <= '0'; + nmi_fg <= '0'; + irq_fg <= '0'; + dat_out1 <= (others => '0'); + dat_out2<= (others => '0'); + +--elsif rising_edge(clock) and run_fg = '1' then +elsif rising_edge(clock) then +-- v_ff <= dat_out2(7); --Used to track the v_fg + reset_fg <= reset; + +-- This section is to get started + if reset = '1' and reset_fg = '0' then + start_fg <= '1'; + wr_ctr <= "00"; + add_fg <= x"8"; --get start up vectors FFFC FFFD + cycle_ctr <= x"5"; --Jump into cycle 5 add_fg <= x'8' +-- end if; + else + + + case cycle_ctr is --cycle counter case + when x"0" => + +-- cycle_mark <= '1'; + if reset_fg = '1' and reset = '1' then + + if flags_fg /= "00" then + n_fg <= dat_out2(7); + if dat_out2 = x"00" then + z_fg <= '1'; + else + z_fg <= '0'; + end if; + end if; + if flags_fg = "10" then + start_fg <= '0'; + v_fg <= reg_a(7) xnor v_ff; --Add V_ff true overflow possible +-- --Sub V_ff false underflow possible + end if; + flags_fg <= "00"; + end if; + + if irq = '0' and i_fg = '0' then + irq_fg <= '1'; + b_fg <= '0'; + pc_dec_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + elsif nmi = '0' and i_fg = '0' then + nmi_fg <= '1'; + b_fg <= '0'; + pc_dec_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + else + + case data_rd is + +-- =========================================================================================== + when x"48" => --PHA 1st part accumulator onto stack + wr_ctr <= "01"; + dat_out1 <= reg_a(7 downto 0); + pc_dec_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"08" => --PHP 1st part status onto stack + wr_ctr <= "01"; + dat_out1 <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8); + pc_dec_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"68" => --PLA 1st part Pull Accumulator from Stack + reg_sp <= reg_sp - "1"; + pc_dec_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"28" => --PLP 1st part pull old status from stack + reg_sp <= reg_sp - "1"; + pc_dec_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"18" => --CLC clear carry + reg_a(8) <= '0'; +-- pc_dec_fg <= '1'; + cycle_ctr <= x"0"; + + when x"38" => --SEC set carry + reg_a(8) <= '1'; + cycle_ctr <= x"0"; + when x"58" => --CLI Clear interrupt Disable Bit + i_fg <= '0'; + cycle_ctr <= x"0"; + + when x"78" => --SEI Set interrupt Disable Status + i_fg <= '1'; + cycle_ctr <= x"0"; + when x"88" => --DEY Decrement y reg + reg_y <= reg_y - "1"; + flags_fg <= "01"; + dat_out2 <= reg_y - "1"; + cycle_ctr <= x"0"; + when x"98" => --TYA transfer Y to A + reg_a(7 downto 0) <= reg_y; + flags_fg <= "01"; + dat_out2 <= reg_y; + cycle_ctr <= x"0"; + when x"A8" => --TAY transfer A to Y + reg_y <= reg_a(7 downto 0); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0); + cycle_ctr <= x"0"; + when x"B8" => --CLV clear overflow flag + v_fg <= '0'; + pc_dec_fg <= '1'; + cycle_ctr <= x"0"; + when x"C8" => --INY increment Y reg + reg_y <= reg_y + x"1"; + flags_fg <= "01"; + dat_out2 <= reg_y + x"1"; + cycle_ctr <= x"0"; + when x"D8" => --CLD Clear decimnal flag + d_fg <= '0'; + cycle_ctr <= x"0"; + when x"E8" => --INX increment X reg + reg_x <= reg_x + x"1"; + flags_fg <= "01"; + dat_out2 <= reg_x + x"1"; + cycle_ctr <= x"0"; + when x"F8" => --SLD Set decimnal flag + d_fg <= '1'; + cycle_ctr <= x"0"; + when x"2A" => --ROL A Rotate Left one bit 1st part. + reg_a(8 downto 1) <= reg_a(7 downto 0); + reg_a(0) <= reg_a(8); + dat_out2(7 downto 1) <= reg_a(6 downto 0); + dat_out2(0) <= reg_a(8); + flags_fg <= "01"; + cycle_ctr <= x"0"; + when x"6A" => --ROR A Rotateft right one bit 1st part. + reg_a(7 downto 0) <= reg_a(8 downto 1); + reg_a(8) <= reg_a(0); + dat_out2 <= reg_a(8 downto 1); + flags_fg <= "01"; + cycle_ctr <= x"0"; + when x"0A" => --ASL A Shift Left one bit 1st part. + reg_a <= reg_a(7 downto 0) & '0'; + dat_out2 <= reg_a(6 downto 0) & '0'; + flags_fg <= "01"; + cycle_ctr <= x"0"; + when x"4A" => --LSR A Logical Shift Right one bit 1st part. + reg_a(7 downto 0) <= '0' & reg_a(7 downto 1); + reg_a(8) <= reg_a(0); + dat_out2 <= '0' & reg_a(7 downto 1); + flags_fg <= "01"; + cycle_ctr <= x"0"; + when x"9A" => --TXS + reg_sp <= reg_x; + cycle_ctr <= x"0"; + when x"AA" => --TAX + reg_x <= reg_a(7 downto 0); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0); + cycle_ctr <= x"0"; + when x"8A" => --TXA + reg_a(7 downto 0) <= reg_x; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0); + cycle_ctr <= x"0"; + when x"BA" => --TSX + reg_x <= reg_sp; + flags_fg <= "01"; + dat_out2 <= reg_sp; + cycle_ctr <= x"0"; + when x"CA" => --DEX + reg_x <= reg_X - X"01"; + flags_fg <= "01"; + dat_out2 <= reg_x - X"01"; + cycle_ctr <= x"0"; +-- ============================================================================================= + when x"F0" => --BEQ branch true 1st part. + cycle_ctr <= cycle_ctr + "1"; + when x"D0" => --BNE branch true 1st part. + cycle_ctr <= cycle_ctr + "1"; + when x"10" => --BPL plus true 1st part. + cycle_ctr <= cycle_ctr + "1"; + when x"30" => --BM1 negative true 1st part. + cycle_ctr <= cycle_ctr + "1"; + when x"50" => --BVC overflow false 1st part. + cycle_ctr <= cycle_ctr + "1"; + when x"70" => --BVS overflow true 1st part. + cycle_ctr <= cycle_ctr + "1"; + when x"90" => --BCC carry false 1st part. + cycle_ctr <= cycle_ctr + "1"; + when x"B0" => --BCS carry true 1st part. + cycle_ctr <= cycle_ctr + "1"; + +-- ============================================================================================= + when x"A2" => --LDX #. 1st partProto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"A9" => --LDA #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"09" => --ORA #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"29" => --AND #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"49" => --EOR #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"69" => --ADC #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"A0" => --LDY #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"C0" => --CPY #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"C9" => --CMP #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"E0" => --CPX #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"E9" => --SBC #. 1st part Proto imediate instruction + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + +-- ============================================================================================= + when x"84" => --STY zero 1st part proto + dat_out1 <= reg_y; + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"85" => --STA zero 1st part proto + dat_out1 <= reg_a(7 downto 0); + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"86" => --STX zero 1st part proto + dat_out1 <= reg_x; + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"94" => --STY zero, X 1st part proto + dat_out1 <= reg_y; + add_fg <= x"2"; + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"95" => --STA zero, X 1st part proto + dat_out1 <= reg_a(7 downto 0); + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"96" => --STX zero, Y 1st part proto + dat_out1 <= reg_x; + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + +-- =============================================================================================== + + when x"A1" => --LDA (zero,x) 1st part proto + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + "1"; + when x"B1" => --LDA (zero),y 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + "1"; + + when x"21" => --AND (zero,x) 1st part proto + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + "1"; + when x"31" => --AND (zero),y 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + "1"; + + when x"41" => --EOR (zero,x) 1st part proto + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + "1"; + when x"51" => --EOR (zero),y 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + "1"; + + when x"01" => --OR (zero,x) 1st part proto + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + "1"; + when x"11" => --OR (zero),y 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + "1"; + + when x"61" => --ADC (zero,x) 1st part proto + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + "1"; + when x"71" => --ADC (zero),y 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + "1"; + + when x"E1" => --SBC (zero,x) 1st part proto + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + "1"; + when x"F1" => --SBC (zero),y 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + "1"; + + when x"C1" => --CMP (zero,x) 1st part proto + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + "1"; + when x"D1" => --CMP (zero),y 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + "1"; + + when x"81" => --STA (zero,x) 1st part proto + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + "1"; + when x"91" => --STA (zero),y 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + "1"; + + +-- ============================================================================================== + when x"A5" => --LDA zero 1st part proto + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"A4" => --LDY zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"A6" => --LDX zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"B5" => --LDA zero,x 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"B4" => --LDY zero,x 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"B6" => --LDX zero,y 1st part + add_fg <= x"3"; + cycle_ctr <= cycle_ctr + x"1"; + when x"05" => --ORA zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"15" => --ORA zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"24" => --BIT zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"25" => --AND zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"26" => --ROL zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"35" => --AND zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"36" => --ROL zero,X 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"45" => --EOR zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"46" => --LSR zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"55" => --EOR zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; +-- ========================================================================================= + when x"E6" => --INC zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"56" => --LSR zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"65" => --ADC zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"66" => --ROR zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"75" => --ADC zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"76" => --ROR zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"C4" => --CPY zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"C5" => --CMP zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"C6" => --DEC zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"D5" => --CMP zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"D6" => --DEC zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"E4" => --CPX zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"E5" => --SBC zero 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"F5" => --SBC zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"F6" => --INC zero,X 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; + when x"06" => --ASL zero, 1st part + add_fg <= x"1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"16" => --ASL zero, x 1st part + add_fg <= x"2"; + cycle_ctr <= cycle_ctr + x"1"; +-- ============================================================================== + when x"AD" => --LDA abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"BD" => --LDA, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"B9" => --LDA, Y abs 1st part + cycle_ctr <= cycle_ctr + x"1"; + + when x"2D" => --AND abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"3D" => --AND, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"39" => --AND, Y abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + + when x"0D" => --ORA abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"1D" => --ORA, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + + when x"19" => --ORA, Y abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + + when x"4D" => --EOR abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"5D" => --EOR, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"59" => --EOR, Y abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + + when x"6D" => --ADC abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"7D" => --ADC, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"79" => --ADC, Y abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + + when x"ED" => --SBC abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"FD" => --SBC, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"F9" => --SBC, Y abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + + when x"AE" => --LDX abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"BE" => --LDX, y abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"AC" => --LDY abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"BC" => --LDY, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"2C" => --BIT abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + + when x"CD" => --CMP abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"DD" => --CMP, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"D9" => --CMP, Y abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"EC" => --CPX abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"CC" => --CPY abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; +--......................................................................................... + when x"8D" => --STA abs 1st part. + dat_out1 <= reg_a(7 downto 0); + cycle_ctr <= cycle_ctr + x"1"; + when x"9D" => --STA,x abs 1st part. + dat_out1 <= reg_a(7 downto 0); + cycle_ctr <= cycle_ctr + x"1"; + when x"99" => --STA, y abs 1st part. + dat_out1 <= reg_a(7 downto 0); + cycle_ctr <= cycle_ctr + x"1"; + when x"8E" => --STX abs 1st part. + dat_out1 <= reg_x; + cycle_ctr <= cycle_ctr + x"1";-- + when x"8C" => --STY abs 1st part. + dat_out1 <= reg_y; + cycle_ctr <= cycle_ctr + x"1"; +--......................................................................................... + + when x"EE" => --INC abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"FE" => --INC, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"CE" => --DEC abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"DE" => --DEC, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"2E" => --ROL abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"3E" => --ROL, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"6E" => --ROR abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"7E" => --ROR, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"4E" => --LSR abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"5E" => --LSR, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"0E" => --ASL abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; + when x"1E" => --ASL, x abs 1st part. + cycle_ctr <= cycle_ctr + x"1"; +-- ............................................................................ +-- ============================================================================== + + + when x"4C" => --JMP abs first part + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"6C" => --JMP indirect first part + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"20" => --JSR abs first part + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"60" => --RTS first part + reg_sp <= reg_sp - "1"; + add_fg <= x"7"; + cycle_ctr <= cycle_ctr + x"1"; + when x"40" => --RTI 1st part pull old status from stack + reg_sp <= reg_sp - "1"; + add_fg <= x"7"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"00" => --Break first part cyc 0 + if irq_fg = '0' then --Start up, irq and nmi also use + b_fg <= '1'; --this set of logic. + else + b_fg <= '0'; + end if; + pc_dec_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when others => + cycle_ctr <= x"0"; + + end case; --Cycle 0 + end if; --Initiated by nmi irq detection. + + +-- End cycle 0 ========================================================= + + + when x"1" => +-- cycle_mark <= '0'; + + case Instruction_in is +-- ================================================================================================ + + when x"48" => --PHA 2nd part accumulator onto stack + pc_dec_fg <= '0'; + add_fg <= x"7"; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"08" => --PHP 2nd part Status reg onto stack + pc_dec_fg <= '0'; + add_fg <= x"7"; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"68" => --PLA 2nd part Pull Accumulator from Stack + add_fg <= x"7"; + pc_dec_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + when x"28" => --PLP 2nd part Pull Status from Stack + add_fg <= x"7"; + pc_dec_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"F0" => --BEQ branch true 2nd part. + if z_fg = '1' then --Should work like a nop + branch_fg <= '1'; --branch true 1st part. + else + pc_inc_fg <= '1'; + end if; + cycle_ctr <= cycle_ctr + x"1"; + when x"D0" => --BNE branch true 2nd part. + if z_fg = '0' then --Should work like a nop + branch_fg <= '1'; --branch true 1st part. + else + pc_inc_fg <= '1'; + end if; + cycle_ctr <= cycle_ctr + x"1"; + when x"10" => --BPL plus true 2nd part. + if n_fg = '0' then --Should work like a nop + branch_fg <= '1'; --branch true 1st part. + else + pc_inc_fg <= '1'; + end if; + cycle_ctr <= cycle_ctr + x"1"; + when x"30" => --BM1 negative true 2nd part. + if n_fg = '1' then --Should work like a nop + branch_fg <= '1'; --branch true 1st part. + else + pc_inc_fg <= '1'; + end if; + cycle_ctr <= cycle_ctr + x"1"; + when x"50" => --BVC overflow false 2nd part. + if v_fg = '0' then --Should work like a nop + branch_fg <= '1'; --branch true 1st part. + else + pc_inc_fg <= '1'; + end if; + cycle_ctr <= cycle_ctr + x"1"; + when x"70" => --BVS overflow true 2nd part. + if v_fg = '1' then --Should work like a nop + branch_fg <= '1'; --branch true 1st part. + else + pc_inc_fg <= '1'; + end if; + cycle_ctr <= cycle_ctr + x"1"; + when x"90" => --BCC carry false 2nd part. + if reg_a(8) = '0' then --Should work like a nop + branch_fg <= '1'; --branch true 1st part. + else + pc_inc_fg <= '1'; + end if; + cycle_ctr <= cycle_ctr + x"1"; + when x"B0" => --BCS carry true 2nd part. + if reg_a(8) = '1' then --Should work like a nop + branch_fg <= '1'; --branch true 1st part. + else + pc_inc_fg <= '1'; + end if; + cycle_ctr <= cycle_ctr + x"1"; +-- ================================================================================================ + + when x"A2" => --LDX #. 2nd part Proto imediate instruction + pc_inc_fg <= '0'; + reg_x <= data_rd; +-- flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"A9" => --LDA #. 2nd part Proto imediate instruction + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + flags_fg <= "01"; + reg_a(7 downto 0) <= data_rd; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"A0" => --LDY # + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + flags_fg <= "01"; + reg_y <= data_rd; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"09" => --ORA # + pc_inc_fg <= '0'; + add_fg <= x"0"; +-- flags_fg <= "01"; + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + dat_out2 <= reg_a(7 downto 0) and data_rd; + cycle_ctr <= x"0"; + when x"29" => --AND # 2nd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + flags_fg <= "01"; + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + dat_out2 <= reg_a(7 downto 0) and data_rd; + cycle_ctr <= x"0"; + when x"49" => --EOR # + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + flags_fg <= "01"; + reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; + dat_out2 <= reg_a(7 downto 0) xor data_rd; + cycle_ctr <= x"0"; + when x"69" => --ADC # + pc_inc_fg <= '0'; + v_ff <= not reg_a(7) and not data_rd(7); --Pos+Pos=Overflow possible + flags_fg <= "10"; + reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); + dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); + cycle_ctr <= x"0"; + when x"E9" => --SBC # 2nd part + pc_inc_fg <= '0'; + v_ff <= reg_a(7) and data_rd(7); --Neg-Neg=Underflow possible + flags_fg <= "10"; + reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); + dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); + cycle_ctr <= x"0"; + + when x"C9" => --CMP # 2nd part. + pc_inc_fg <= '0'; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd; + if reg_a(7 downto 0) > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + cycle_ctr <= x"0"; + when x"E0" => --CPX #. + pc_inc_fg <= '0'; + flags_fg <= "01"; + dat_out2 <= reg_x - data_rd; + if reg_x > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + cycle_ctr <= x"0"; + when x"C0" => --CPY #. + pc_inc_fg <= '0'; + flags_fg <= "01"; + dat_out2 <= reg_y - data_rd; + if reg_y > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + cycle_ctr <= x"0"; + +-- =================================================================================================== + when x"84" => --STY zero 2nd part proto + add_fg <= x"1"; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + "1"; + when x"85" => --STA zero 2nd part proto + add_fg <= x"1"; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + "1"; + when x"86" => --STX zero 2nd part proto + add_fg <= x"1"; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + "1"; + when x"94" => --STY zero, X 2nd part proto + add_fg <= x"2"; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + "1"; + when x"95" => --STA zero, X 2nd part proto + add_fg <= x"2"; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + "1"; + when x"96" => --STX zero, Y 2nd part proto + add_fg <= x"3"; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + "1"; + +-- ================================================================================= + when x"A5" => --LDA zero 2nd part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"A4" => --LDY zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"A6" => --LDX zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"B5" => --LDA zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"B4" => --LDY zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"B6" => --LDX zero,Y 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"05" => --ORA zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"15" => --ORA zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"24" => --BIT zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"25" => --AND zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"35" => --AND zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"45" => --EOR zero,Y 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"55" => --EOR zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"65" => --ADC zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"75" => --ADC zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"C4" => --CPY zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"C5" => --CMP zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"C6" => --DEC zero 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"D5" => --CMP zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"D6" => --DEC zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when x"E4" => --CPX zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"E5" => --SBC zero 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + when x"F5" => --SBC zero,X 2nd part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; +-- =================================================================================== + when x"E6" => --INC zero 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"F6" => --INC zero,X 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"46" => --LSR zero 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"56" => --LSR zero,X 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + + when x"66" => --ROR zero 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"76" => --ROR zero,X 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"26" => --ROL zero 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"36" => --ROL zero,X 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"06" => --ASL zero 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"16" => --ASL zero,X 2nd part + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + + +-- ============================================================================== + when x"A1" => --LDA (zero,x) 2nd part proto + add_fg <= x"D"; + cycle_ctr <= cycle_ctr + "1"; + when x"B1" => --LDA (zero),y 2nd part proto + add_fg <= x"C"; + cycle_ctr <= cycle_ctr + "1"; + + when x"21" => --AND (zero,x) 2nd part proto + add_fg <= x"D"; + cycle_ctr <= cycle_ctr + "1"; + when x"31" => --AND (zero),y 2nd part proto + add_fg <= x"C"; + cycle_ctr <= cycle_ctr + "1"; + + when x"41" => --EOR (zero,x) 2nd part proto + add_fg <= x"D"; + cycle_ctr <= cycle_ctr + "1"; + when x"51" => --EOR (zero),y 2nd part proto + add_fg <= x"C"; + cycle_ctr <= cycle_ctr + "1"; + + when x"01" => --OR (zero,x) 2nd part proto + add_fg <= x"D"; + cycle_ctr <= cycle_ctr + "1"; + when x"11" => --OR (zero),y 2nd part proto + add_fg <= x"C"; + cycle_ctr <= cycle_ctr + "1"; + + when x"61" => --ADC (zero,x) 2nd part proto + add_fg <= x"D"; + cycle_ctr <= cycle_ctr + "1"; + when x"71" => --ADC (zero),y 2nd part proto + add_fg <= x"C"; + cycle_ctr <= cycle_ctr + "1"; + + when x"E1" => --SBC (zero,x) 2nd part proto + add_fg <= x"D"; + cycle_ctr <= cycle_ctr + "1"; + when x"F1" => --SBC (zero),y 2nd part proto + add_fg <= x"C"; + cycle_ctr <= cycle_ctr + "1"; + + when x"C1" => --CMP (zero,x) 2nd part proto + add_fg <= x"D"; + cycle_ctr <= cycle_ctr + "1"; + when x"D1" => --CMP (zero),y 2nd part proto + add_fg <= x"C"; + cycle_ctr <= cycle_ctr + "1"; + + when x"81" => --STA (zero,x) 2nd part proto + add_fg <= x"D"; + cycle_ctr <= cycle_ctr + "1"; + when x"91" => --STA (zero),y 2nd part proto + add_fg <= x"C"; + cycle_ctr <= cycle_ctr + "1"; +-- ============================================================================== + when x"AD" => --LDA abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"BD" => --LDA, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"B9" => --LDA, Y abs 2nd part. + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"2D" => --AND abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"3D" => --AND, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"39" => --AND, Y abs 2nd part. + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"0D" => --ORA abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"1D" => --ORA, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"19" => --ORA, Y abs 2nd part. + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"4D" => --EOR abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"5D" => --EOR, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"59" => --EOR, Y abs 2nd part. + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"6D" => --ADC abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"7D" => --ADC, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"79" => --ADC, Y abs 2nd part. + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"ED" => --SBC abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"FD" => --SBC, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"F9" => --SBC, Y abs 2nd part. + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"AE" => --LDX abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"BE" => --LDX, y abs 2nd part. + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + x"1"; + when x"AC" => --LDY abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"BC" => --LDY, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"2C" => --BIT abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"CD" => --CMP abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"DD" => --CMP, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"D9" => --CMP, Y abs 2nd part. + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + x"1"; + when x"EC" => --CPX abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"CC" => --CPY abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; +-- ............................................................................... + when x"8D" => --STA abs 2nd part. + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"9D" => --STA,x abs 2nd part. + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"99" => --STA, y abs 2nd part. + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"8E" => --STX abs 2nd part. + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"8C" => --STY abs 2nd part. + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + x"1"; +-- ........................................................................ + + when x"EE" => --INC abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"FE" => --INC, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"CE" => --DEC abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"DE" => --DEC, x abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"2E" => --ROL abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"3E" => --ROL, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"6E" => --ROR abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"7E" => --ROR, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"4E" => --LSR abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"5E" => --LSR, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; + when x"0E" => --ASL abs 2nd part. + add_fg <= x"4"; + cycle_ctr <= cycle_ctr + x"1"; + when x"1E" => --ASL, x abs 2nd part. + add_fg <= x"5"; + cycle_ctr <= cycle_ctr + x"1"; +-- ............................................................................ +-- ============================================================================== + when x"4C" => --JMP abs 2nd part + pc_inc_fg <= '0'; + dat2pc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"6C" => --JMP indirect 2nd part + add_fg <= x"4"; + pc_inc_fg <= '0'; + cycle_ctr <= cycle_ctr + "1"; + when x"20" => --JSR abs 2nd part + dat2pc_fg <= '1'; + pc_inc_fg <= '0'; + wr_ctr <= "10"; +-- add_fg <= x"7"; + dat_out1 <= reg_pc(7 downto 0); + dat_out2 <= reg_pc(15 downto 8); + cycle_ctr <= cycle_ctr + x"1"; + + when x"60" => --RTS second part + reg_sp <= reg_sp - "1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"40" => --RTI second part pull old status from stack + reg_sp <= reg_sp - "1"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"00" => --Break second part cyc 1 + wr_ctr <= "01"; --put dat_out2 onto stack + dat_out1 <= reg_pc(15 downto 8); + add_fg <= x"7"; + dat2pc_fg <= '0'; + pc_dec_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + + when others => + cycle_ctr <= cycle_ctr + x"1"; + end case; --Cycle 1 + + +-- End cycle 1 ========================================================= + + when x"2" => + + case instruction_in(7 downto 0) is +-- ==================================================================================== + + when x"48" => --PHA 3rd part accumulator onto stack + pc_inc_fg <= '1'; + add_fg <= x"0"; + reg_sp <= reg_sp + "1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"08" => --PHP 3rd part Status reg onto stack + pc_inc_fg <= '1'; + add_fg <= x"0"; + reg_sp <= reg_sp + "1"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"68" => --PLA 3rd part Pull Accumulator from Stack + pc_dec_fg <= '0'; + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"28" => --PLP 3rd part Pull Status from Stack + pc_dec_fg <= '0'; + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"F0" => --BEQ branch true 3rd part. + if branch_fg = '1' then + branch_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + else + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + end if; + when x"D0" => --BNE branch true 3rd part. + if branch_fg = '1' then + branch_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + else + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + end if; + when x"10" => --BPL plus true 3rd part. + if branch_fg = '1' then + branch_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + else + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + end if; + when x"30" => --BM1 negative true 3rd part. + if branch_fg = '1' then + branch_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + else + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + end if; + when x"50" => --BVC overflow false 3rd part. + if branch_fg = '1' then + branch_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + else + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + end if; + when x"70" => --BVS overflow true 3rd part. + if branch_fg = '1' then + branch_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + else + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + end if; + when x"90" => --BCC carry false 3rd part. + if branch_fg = '1' then + branch_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + else + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + end if; + when x"B0" => --BCS carry true 3rd part. + if branch_fg = '1' then + branch_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + else + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + end if; +-- ==================================================================================== + when x"84" => --STY zero 3rd part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"85" => --STA zero 3rd part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"86" => --STX zero 3rd part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"94" => --STY zero, X 3rd part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"95" => --STA zero, X 3rd part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"96" => --STX zero, Y 3rd part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + +-- ======================================================================================== + when x"A5" => --LDA zero 3rd part proto + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"A4" => --LDY zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_y <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"A6" => --LDX zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_x <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"B5" => --LDA zero,X 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"B4" => --LDY zero,X 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_y <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"B6" => --LDX zero,Y 3rd part + wr_ctr <= "00"; + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_x <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"05" => --ORA zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) or data_rd; + cycle_ctr <= x"0"; + when x"15" => --ORA zero,X 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) or data_rd; + cycle_ctr <= x"0"; + when x"24" => --BIT zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + n_fg <= data_rd(7); + v_fg <= data_rd(6); + dat_out2 <= reg_a(7 downto 0) and data_rd; + flags_fg <= "01"; + cycle_ctr <= x"0"; + when x"25" => --AND zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) and data_rd; + cycle_ctr <= x"0"; + + when x"35" => --AND zero,X 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) and data_rd; + cycle_ctr <= x"0"; + + when x"45" => --EOR zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) xor data_rd; + cycle_ctr <= x"0"; + + when x"55" => --EOR zero,X 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) xor data_rd; + cycle_ctr <= x"0"; + + when x"65" => --ADC zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); + cycle_ctr <= x"0"; + + when x"75" => --ADC zero,X 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); + cycle_ctr <= x"0"; + + when x"C4" => --CPY zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"C5" => --CMP zero 3rd part + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd; + if reg_a(7 downto 0) > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"C6" => --DEC zero 3rd part + dat_out1 <= data_rd - x"01"; + dat_out2 <= data_rd - x"01"; + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"D5" => --CMP zero,X 3rd part + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd; + if reg_a(7 downto 0) > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"D6" => --DEC zero,X 3rd part + pc_inc_fg <= '0'; + add_fg <= x"0"; + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= cycle_ctr + "1"; + when x"E4" => --CPX zero 3rd part + pc_inc_fg <= '0'; + add_fg <= x"0"; + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= x"0"; + when x"E5" => --SBC zero 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); + dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); + flags_fg <= "01"; + cycle_ctr <= x"0"; + + + when x"F5" => --SBC zero,X 3rd part + pc_inc_fg <= '0'; +-- add_fg <= x"0"; + reg_a <= reg_a - ('0' & data_rd) - ("00000000" & reg_a(8)); + dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); + flags_fg <= "01"; + cycle_ctr <= x"0"; + + when x"E6" => --INC zero 3rd part + dat_out1 <= data_rd + x"01"; + dat_out2 <= data_rd + x"01"; + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"F6" => --INC zero,X 3rd part + dat_out1 <= data_rd + x"01"; + dat_out2 <= data_rd + x"01"; + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + + when x"66" => --ROR zero 3rd part + reg_a(8) <= data_rd(0); + dat_out1 <= reg_a(8) & data_rd(7 downto 1); + dat_out2 <= reg_a(8) & data_rd(7 downto 1); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + + when x"76" => --ROR zero,X 3rd part + reg_a(8) <= data_rd(0); + dat_out1 <= reg_a(8) & data_rd(7 downto 1); + dat_out2 <= reg_a(8) & data_rd(7 downto 1); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + + when x"26" => --ROL zero 3rd part + dat_out1(7 downto 1) <= data_rd(6 downto 0); + dat_out1(0) <= reg_a(8); + dat_out2(7 downto 1) <= data_rd(6 downto 0); + dat_out2(0) <= reg_a(8); + flags_fg <= "01"; + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"36" => --ROL zero,X 3rd part + dat_out1(7 downto 1) <= data_rd(6 downto 0); + dat_out1(0) <= reg_a(8); + dat_out2(7 downto 1) <= data_rd(6 downto 0); + dat_out2(0) <= reg_a(8); + flags_fg <= "01"; + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"46" => --LSR zero 3rd part + dat_out1 <= '0' & reg_a(7 downto 1); + dat_out2 <= '0' & reg_a(7 downto 1); + reg_a(8) <= data_rd(0); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"56" => --LSR zero,X 3rd part + dat_out1 <= '0' & reg_a(7 downto 1); + dat_out2 <= '0' & reg_a(7 downto 1); + reg_a(8) <= data_rd(0); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"06" => --ASL zero 3rd part + reg_a(8) <= data_rd(7); + dat_out1 <= data_rd(6 downto 0) & '0'; + dat_out2 <= data_rd(6 downto 0) & '0'; + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"16" => --ASL zero,X 3rd part + reg_a(8) <= data_rd(7); + dat_out1 <= data_rd(6 downto 0) & data_rd(0); + dat_out2 <= data_rd(6 downto 0) & data_rd(0); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + +-- ============================================================================================= + when x"A1" => --LDA (zero,x) 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + when x"B1" => --LDA (zero),y 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + + when x"21" => --AMD (zero,x) 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + when x"31" => --AND (zero),y 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + + when x"41" => --EOR (zero,x) 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + when x"51" => --EOR (zero),y 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + + when x"01" => --OR (zero,x) 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + when x"11" => --OR (zero),y 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + + when x"61" => --ADC (zero,x) 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + when x"71" => --ADC (zero),y 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + + when x"E1" => --SBC (zero,x) 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + when x"F1" => --SBC (zero),y 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + + when x"C1" => --CMP (zero,x) 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + when x"D1" => --CMP (zero),y 3rd part proto + add_fg <= x"6"; + cycle_ctr <= cycle_ctr + "1"; + + when x"81" => --STA (zero,x) 3rd part proto + add_fg <= x"4"; + wr_ctr <= "01"; + dat_out1 <= reg_a(7 downto 0); + cycle_ctr <= cycle_ctr + "1"; + when x"91" => --STA (zero),y 3rd part proto + add_fg <= x"6"; + wr_ctr <= "01"; + dat_out1 <= reg_a(7 downto 0); + cycle_ctr <= cycle_ctr + "1"; +-- ============================================================================== + when x"AD" => --LDA abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"BD" => --LDA, x abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"B9" => --LDA, Y abs 3rd part + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + + when x"2D" => --AND abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"3D" => --AND, x abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"39" => --AND, Y abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"0D" => --ORA abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"1D" => --ORA, x abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"19" => --ORA, Y abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"4D" => --EOR abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"5D" => --EOR, x abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"59" => --EOR, Y abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"6D" => --ADC abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"7D" => --ADC, x abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"79" => --ADC, Y abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"ED" => --SBC abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"FD" => --SBC, x abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"F9" => --SBC, Y abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"AE" => --LDX abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"BE" => --LDX, y abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"AC" => --LDY abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"BC" => --LDY, x abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"2C" => --BIT abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"CD" => --CMP abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"DD" => --CMP, x abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"D9" => --CMP, Y abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"EC" => --CPX abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"CC" => --CPY abs 3rd part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + +-- ................................................................................ + when x"8D" => --STA abs 3rd part. + wr_ctr <= "00"; + add_fg <= x"4"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"9D" => --STA,x abs 3rd part. + wr_ctr <= "00"; + add_fg <= x"5"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"99" => --STA, y abs 3rd part. + wr_ctr <= "00"; + add_fg <= x"6"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"8E" => --STX abs 3rd part. + wr_ctr <= "00"; + add_fg <= x"4"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + when x"8C" => --STY abs 3rd part. + wr_ctr <= "00"; + add_fg <= x"4"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; +-- ................................................................................ + + when x"EE" => --INC abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"FE" => --INC, x abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"CE" => --DEC abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"DE" => --DEC, x abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"2E" => --ROL abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"3E" => --ROL, x abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"6E" => --ROR abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"7E" => --ROR, x abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"4E" => --LSR abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"5E" => --LSR, x abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"0E" => --ASL abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; + when x"1E" => --ASL, x abs 3rd part. + add_fg <= x"f"; + cycle_ctr <= cycle_ctr + "1"; +-- ............................................................................ +-- ============================================================================== + when x"4C" => --JMP abs 3rd part + dat2pc_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + when x"6C" => --JMP indirect 3rd part + add_fg <= x"B"; + cycle_ctr <= cycle_ctr + x"1"; + when x"20" => --JSR abs 3rd part + dat2pc_fg <= '0'; + add_fg <= x"7"; + wr_ctr <= "01"; +-- reg_sp <= reg_sp + "1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"60" => --RTS third part + dat2pc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"40" => --RTI 3rd part pull old status from stack + pc_dec_fg <= '0'; --Get 1st PC byte + n_fg <= data_rd(7); --cyc 6 + v_fg <= data_rd(6); + b_fg <= data_rd(4); + d_fg <= data_rd(3); + i_fg <= data_rd(2); + z_fg <= data_rd(1); + reg_a(8) <= data_rd(0); + reg_sp <= reg_sp - "1"; + dat2pc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"00" => --Break third part cyc 2 + dat_out1 <= reg_pc(7 downto 0); --put dat_out1 onto stack set up dat_out2 + reg_sp <= reg_sp + "1"; + cycle_ctr <= cycle_ctr + x"1"; + + when others => + cycle_ctr <= cycle_ctr + x"1"; + end case; --Cycle 2 + +------------------------------------------------------------------------ +-- Cycle 3 is for single byte instructions ie TAY + when x"3" => + + + + if instruction_in(7 downto 0) /= x"A2" and + ( + instruction_in(3 downto 0) = x"3" or + instruction_in(3 downto 0) = x"7" or + instruction_in(3 downto 0) = x"B" or + instruction_in(3 downto 0) = x"F" + ) then --NOPs + cycle_ctr <= x"0"; + pc_dec_fg <= '1'; + else + + case instruction_in(7 downto 0) is +-- ====================================================================================== + when x"84" => --STY zero 4th part proto + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"85" => --STA zero 4th part proto + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"86" => --STX zero 4th part proto + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"94" => --STY zero, X 4th part proto + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"95" => --STA zero, X 4th part proto + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"96" => --STX zero, Y 4th part proto + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; +-- ======================================================================================= + + + when x"08" => --PHP 4th part accumulator onto stack + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"48" => --PHA 4th part accumulator onto stack + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + + when x"68" => --PLA 4th part Pull Accumulator from Stack + reg_a(7 downto 0) <= data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"28" => --PLP 4th part Pull Status from Stack + n_fg <= data_rd(7); + v_fg <= data_rd(6); +-- b_fg <= data_rd(4); + d_fg <= data_rd(3); + i_fg <= data_rd(2); + z_fg <= data_rd(1); + reg_a(8) <= data_rd(0); + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"F0" => --BEQ branch true 4th part. + branch_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"D0" => --BNE branch true 4th part. + branch_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"10" => --BPL plus true 4th part. + branch_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"30" => --BM1 negative true 4th part. + branch_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"50" => --BVC overflow false 4th part. + branch_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"70" => --BVS overflow true 4th part. + branch_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"90" => --BCC carry false 4th part. + branch_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"B0" => --BCS carry true 4th part. + branch_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + +-- ====================================================================================== + + when x"E6" => --INC zero fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"F6" => --INC zero,X fourth part + wr_ctr <= "00"; + cycle_ctr <= x"0"; + when x"C6" => --DEC zero fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"D6" => --DEC zero,X fourth part + wr_ctr <= "00"; + cycle_ctr <= x"0"; + + when x"26" => --ROL zero fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"36" => --ROL zero,X fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"66" => --ROR zero fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"76" => --ROR zero,X fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"06" => --ASL zero fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"16" => --ASL zero,X fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"46" => --LSR zero fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"56" => --LSR zero,X fourth part + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; +-- +-- ============================================================================== + when x"AD" => --LDA abs 4th part. + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"BD" => --LDA, x abs 4th part. + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"B9" => --LDA, Y abs 4th part + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + + when x"2D" => --AND abs 4th part. + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) and data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"3D" => --AND, x abs 4th part. + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) and data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"39" => --AND, Y abs 4th part. + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) and data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"0D" => --ORA abs 4th part. + reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) or data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"1D" => --ORA, x abs 4th part. + reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) or data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"19" => --ORA, Y abs 4th part. + reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) or data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"4D" => --EOR abs 4th part. + reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) xor data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"5D" => --EOR, x abs 4th part. + reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) xor data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"59" => --EOR, Y abs 4th part. + + reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) xor data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"6D" => --ADC abs 4th part. + reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"7D" => --ADC, x abs 4th part. + reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"79" => --ADC, Y abs 4th part. + reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"ED" => --SBC abs 4th part. + reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"FD" => --SBC, x abs 4th part. + reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"F9" => --SBC, Y abs 4th part. + reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"AE" => --LDX abs 4th part. + reg_x <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; +-- pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"BE" => --LDX, y abs 4th part. + reg_x <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; +-- pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"AC" => --LDY abs 4th part. + reg_y <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + cycle_ctr <= cycle_ctr + x"1"; + when x"BC" => --LDY, x abs 4th part. + reg_y <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; +-- pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"2C" => --BIT abs 4th part. + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) and data_rd; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"CD" => --CMP abs 4th part. + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd; + if reg_a(7 downto 0) > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"DD" => --CMP, x abs 4th part. + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd; + if reg_a(7 downto 0) > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"D9" => --CMP, Y abs 4th part. + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd; + if reg_a(7 downto 0) > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"EC" => --CPX abs 4th part. + if reg_x = data_rd then + z_fg <= '1'; + else + z_fg <= '0'; + end if; + if reg_x >= data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + if reg_x < data_rd then + n_fg <= '1'; + else + n_fg <= '0'; + end if; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"CC" => --CPY abs 4th part. + if reg_y = data_rd then + z_fg <= '1'; + else + z_fg <= '0'; + end if; + if reg_y >= data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + if reg_y < data_rd then + n_fg <= '1'; + else + n_fg <= '0'; + end if; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; +-- ................................................................................. + when x"8D" => --STA abs 4th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"9D" => --STA,x abs 4th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"99" => --STA, y abs 4th part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"8E" => --STX abs 4th part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"8C" => --STY abs 4th part. + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; +-- ........................................................................ + + when x"EE" => --INC abs 4th part. + dat_out1 <= data_rd + x"01"; + dat_out2 <= data_rd + x"01"; + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"FE" => --INC, x abs 4th part. + dat_out1 <= data_rd + x"01"; + dat_out2 <= data_rd + x"01"; + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"CE" => --DEC abs 4th part. + dat_out1 <= data_rd - x"01"; + dat_out2 <= data_rd - x"01"; + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"DE" => --DEC, x abs 4th part. + dat_out1 <= data_rd - x"01"; + dat_out2 <= data_rd - x"01"; + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"2E" => --ROL abs 4th part. + dat_out1(7 downto 1) <= data_rd(6 downto 0); + dat_out1(0) <= reg_a(8); + dat_out2(7 downto 1) <= data_rd(6 downto 0); + dat_out2(0) <= reg_a(8); + flags_fg <= "01"; + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"3E" => --ROL, x abs 4th part. + dat_out1(7 downto 1) <= data_rd(6 downto 0); + dat_out1(0) <= reg_a(8); + dat_out2(7 downto 1) <= data_rd(6 downto 0); + dat_out2(0) <= reg_a(8); + flags_fg <= "01"; + wr_ctr <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"6E" => --ROR abs 4th part. + reg_a(8) <= data_rd(0); + dat_out1 <= reg_a(8) & data_rd(7 downto 1); + dat_out2 <= reg_a(8) & data_rd(7 downto 1); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"7E" => --ROR, x abs 4th part. + reg_a(8) <= data_rd(0); + dat_out1 <= reg_a(8) & data_rd(7 downto 1); + dat_out2 <= reg_a(8) & data_rd(7 downto 1); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"4E" => --LSR abs 4th part. + dat_out1 <= '0' & reg_a(7 downto 1); + dat_out2 <= '0' & reg_a(7 downto 1); + reg_a(8) <= data_rd(0); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"5E" => --LSR, x abs 4th part. + dat_out1 <= '0' & reg_a(7 downto 1); + dat_out2 <= '0' & reg_a(7 downto 1); + reg_a(8) <= data_rd(0); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + "1"; + when x"0E" => --ASL abs 4th part. + reg_a(8) <= data_rd(7); + dat_out1 <= data_rd(6 downto 0) & data_rd(0); + dat_out2 <= data_rd(6 downto 0) & data_rd(0); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + x"1"; + when x"1E" => --ASL, x abs 4th part. + reg_a(8) <= data_rd(7); + dat_out1 <= data_rd(6 downto 0) & data_rd(0); + dat_out2 <= data_rd(6 downto 0) & data_rd(0); + wr_ctr <= "01"; + flags_fg <= "01"; + cycle_ctr <= cycle_ctr + x"1"; +-- ............................................................................ +-- ============================================================================== + when x"A1" => --LDA (zero,x) 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"B1" => --LDA (zero),y 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"21" => --AND (zero,x) 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"31" => --AND (zero),y 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"41" => --EOR (zero,x) 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"51" => --EOR (zero),y 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"01" => --OR (zero,x) 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"11" => --OR (zero),y 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + + when x"61" => --ADC (zero,x) 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"71" => --ADC (zero),y 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"E1" => --SBC (zero,x) 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"F1" => --SBC (zero),y 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"C1" => --CMP (zero,x) 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + when x"D1" => --CMP (zero),y 4th part proto + add_fg <= x"0"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + "1"; + + + when x"81" => --STA (zero,x) 4th part proto +-- add_fg <= x"0"; +-- pc_inc_fg <= '1'; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + "1"; + when x"91" => --STA (zero),y 4th part proto +-- add_fg <= x"0"; +-- pc_inc_fg <= '1'; + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + "1"; +-- ================================================================================== + + when x"4C" => --JMP abs 4th part + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"6C" => --JMP abs 4th part + add_fg <= x"0"; + dat2pc_fg <= '1'; + pc_inc_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + when x"20" => --JSR indirect 4th part +-- add_fg <= x"0"; + wr_ctr <= "00"; + reg_sp <= reg_sp + "1"; +-- pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"60" => --RTS fourth part + dat2pc_fg <= '0'; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"40" => --RTI forth part +-- reg_sp <= reg_sp - "1"; + add_fg <= x"7"; --Get 2nd PC byte + dat2pc_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"00" => --Break forth extra part cyc 3 + dat_out1 <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8); + reg_sp <= reg_sp + "1"; + cycle_ctr <= cycle_ctr + x"1"; + +-------------------------------------------------------------------------------------- + when others => + cycle_ctr <= cycle_ctr + x"1"; + + end case; --Cycle 3 + end if; --End single byte stuff + +-- End of cycle 3 +-- Cycle 4 is for 2 byte/cycle instructions ie LDA # +-- + when x"4" => + case Instruction_in is +-- ====================================================================================== + when x"F0" => --BEQ branch true 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"D0" => --BNE branch true 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"10" => --BPL plus true 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"30" => --BM1 negative true 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"50" => --BVC overflow false 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"70" => --BVS overflow true 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"90" => --BCC carry false 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"B0" => --BCS carry true 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; +-- ====================================================================================== + + when x"E6" => --INC zero 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"F6" => --INC zero,X 5th part + wr_ctr <= "00"; + pc_inc_fg <= '0'; + add_fg <= x"0"; + cycle_ctr <= x"0"; + when x"c6" => --DEC zero 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"46" => --LSR zero 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"56" => --LSR zero,X 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"66" => --ROR zero 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"76" => --ROR zero,X 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"26" => --ROL zero 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"36" => --ROL zero,X 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"06" => --ASL zero 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"16" => --ASL zero,X 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + + +-- +-- ====================================================================================== + when x"AD" => --LDA 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"BD" => --LDA, x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"B9" => --LDA, Y 5th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"2D" => --AND 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"3D" => --AND, x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"39" => --AND, Y 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"0D" => --ORA 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"1D" => --ORA, x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"19" => --ORA, Y 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"4D" => --EOR 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"5D" => --EOR, x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"59" => --EOR, Y 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"6D" => --ADC 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"7D" => --ADC, x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"79" => --ADC, Y 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"ED" => --SBC 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"FD" => --SBC, x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"F9" => --SBC, Y 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"AE" => --LDX 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"BE" => --LDX, y 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"AC" => --LDY 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"BC" => --LDY, x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"2C" => --BIT 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"CD" => --CMP 5th part. + wr_ctr <= "10"; pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"DD" => --CMP, x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"D9" => --CMP, Y 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"EC" => --CPX 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"CC" => --CPY 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; +-- ............................................................................ + when x"8D" => --STA 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"9D" => --STA,x 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"99" => --STA, y 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"8E" => --STX 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"8C" => --STY 5th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; +-- ............................................................................ + + when x"EE" => --INC abs 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"FE" => --INC, x 5th part. + wr_ctr <= "00"; + cycle_ctr <= cycle_ctr + x"1"; + when x"CE" => --DEC 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"DE" => --DEC, x 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"2E" => --ROL 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"3E" => --ROL, x 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"6E" => --ROR 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"7E" => --ROR, x 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"4E" => --LSR 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"5E" => --LSR, x 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"0E" => --ASL 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + when x"1E" => --ASL, x 5th part. + wr_ctr <= "00"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; +-- ............................................................................ +-- ============================================================================== + when x"A1" => --LDA (zero,x) 5th part proto + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"B1" => --LDA (zero),y 5th part proto + reg_a(7 downto 0) <= data_rd; + flags_fg <= "01"; + dat_out2 <= data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"21" => --AND (zero,x) 5th part proto + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) and data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"31" => --AND (zero),y 5th part proto + reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) and data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"42" => --EOR (zero,x) 5th part proto + reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) xor data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"51" => --EOR (zero),y 5th part proto + reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) xor data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"01" => --OR (zero,x) 5th part proto + reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) or data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"11" => --OR (zero),y 5th part proto + reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd; + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) or data_rd; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"61" => --ADC (zero,x) 5th part proto + flags_fg <= "01"; + reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); + dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"71" => --ADC (zero),y 5th part proto + flags_fg <= "01"; + reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8)); + dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8)); + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"E1" => --SBC (zero,x) 5th part proto + flags_fg <= "01"; + reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); + dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"F1" => --SBC (zero),y 5th part proto + flags_fg <= "01"; + reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8)); + dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8)); + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"C1" => --CMP (zero,x) 5th part proto + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd; + if reg_a(7 downto 0) > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"D1" => --CMP (zero),y 5th part proto + flags_fg <= "01"; + dat_out2 <= reg_a(7 downto 0) - data_rd; + if reg_a(7 downto 0) > data_rd then + reg_a(8) <= '1'; + else + reg_a(8) <= '0'; + end if; + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"81" => --STA (zero,x) 5th part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"91" => --STA (zero),y 5th part proto + pc_inc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; +-- ============================================================================== + when x"4C" => --JMP abs 5th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"6C" => --JMP indirect 5th part + pc_inc_fg <= '1'; + dat2pc_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + when x"20" => --JSR 5th part + pc_inc_fg <= '1'; + add_fg <= x"0"; + reg_sp <= reg_sp + "1"; + cycle_ctr <= cycle_ctr + x"1"; + when x"60" => --RTS fifth part + dat2pc_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"40" => --RTI fifth part +-- reg_sp <= reg_sp + "1"; + add_fg <= x"0"; +-- dat2pc_fg <= '0'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"00" => --Break fifth part cyc 4 + wr_ctr <= "00"; + reg_sp <= reg_sp + "1"; + if nmi_fg = '0' then + add_fg <= x"9"; --Complete stacking start getting vector + else + add_fg <= x"A"; + end if; + cycle_ctr <= cycle_ctr + x"1"; + + + when others => + cycle_ctr <= cycle_ctr + x"1"; + + end case; --Cycle 4 +-- end if; +------------------------------------------------------------------------ +-- End of cycle 4 +-- Cycle 5 is for 3 byte instructions ie LDA abs + + when x"5" => + case Instruction_in is +-- ========================================================================= + when x"81" => --STA (zero,x) 6th part proto + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"91" => --STA (zero),y 6th part proto + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + +-- ........................................................................................ + when x"E6" => --INC zero 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"c6" => --dec zero 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"26" => --ROL zero 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"F6" => --INC zero,X 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"46" => --LSR zero 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"56" => --LSR zero,X 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"66" => --ROR zero 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"76" => --ROR zero,X 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"36" => --ROL zero,X 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"06" => --ASL zero 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"16" => --ASL zero,X 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + +--================================================== + + + when x"EE" => --INC abs 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"FE" => --INC, x 6th part. + add_fg <= x"0"; + cycle_ctr <= x"0"; + when x"CE" => --DEC 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"DE" => --DEC, x 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + + when x"2E" => --ROL 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"3E" => --ROL, x 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"6E" => --ROR 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"7E" => --ROR, x 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"4E" => --LSR 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"5E" => --LSR, x 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"0E" => --ASL 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; + when x"1E" => --ASL, x 6th part. + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; +-- ........................................................................................ + when x"6C" => --JMP indirect 6th part + pc_inc_fg <= '0'; +-- dat2pc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"60" => --RTS 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"40" => --RTI sixth part + cycle_ctr <= cycle_ctr + x"1"; + pc_inc_fg <= '1'; + cycle_ctr <= cycle_ctr + x"1"; + + when x"20" => --JSR 6th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"00" => --Break 6th part cyc 5 + add_fg <= x"B"; + irq_fg <= '0'; + nmi_fg <= '0'; + cycle_ctr <= cycle_ctr + "1"; + + when others => +-- cycle_ctr <= x"0"; + cycle_ctr <= cycle_ctr + x"1"; +-- --get_inst_fg <= '0'; + end case; --Cycle 5 + +------------------------------------------------------------------------ +-- End of cycle 5 +-- Cycle 6 is for 3 byte instructions ie LDA abs + + when x"6" => + case Instruction_in is + + when x"EE" => --INC abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"cE" => --DEC abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"2E" => --ROL abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"3E" => --ROL, x abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"6E" => --ROR abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"7E" => --ROR, x abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"4E" => --LSR abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"5E" => --LSR, x abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"0E" => --ASL abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + when x"1E" => --ASL, x abs 7th part. + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; +--============================================================================= + + when x"40" => --RTI 7th part + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when x"00" => --Break 7th part cyc 6 + dat2pc_fg <= '1'; + add_fg <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + when others => + cycle_ctr <= x"0"; + --get_inst_fg <= '0'; + + + end case; --Cycle 6 +-- End of cycle 6 + + +-- Cycle 8 is for 3 byte instructions ie LDA abs + + when x"7" => + case Instruction_in is + + when x"40" => --RTI 8th cyc + cycle_ctr <= x"0"; + + when x"00" => --Break 8th part cyc 7 + if start_fg = '0' then --When starting don't mess with this + i_fg <= '1'; --Break irq and start use this logic. + end if; + pc_inc_fg <= '1'; + start_fg <= '0'; + dat2pc_fg <= '0'; +-- cycle_ctr <= x"0"; + cycle_ctr <= cycle_ctr + "1"; + + + when others => + cycle_ctr <= x"0"; + --get_inst_fg <= '0'; + + end case; --Cycle 7 +-- Cycle 7 + when x"8" => + case Instruction_in is + + when x"00" => --Break 10th part cyc 8 + pc_inc_fg <= '0'; + cycle_ctr <= x"0"; + + when others => + cycle_ctr <= cycle_ctr + "1"; + pc_inc_fg <= '0'; + + end case; --Cycle 8 +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +-- Cycle 9 + when x"9" => + case Instruction_in is + + when others => + cycle_ctr <= cycle_ctr + "1"; + pc_inc_fg <= '0'; + + end case; --Cycle 9 +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +-- Cycle A + + when x"A" => + case Instruction_in is + + + when others => + cycle_ctr <= cycle_ctr + "1"; + pc_inc_fg <= '0'; + + end case; --Cycle A +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +-- Cycle B + + when x"B" => + case Instruction_in is + + when others => + cycle_ctr <= cycle_ctr + "1"; + pc_inc_fg <= '0'; + + end case; --Cycle B +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +-- Cycle C + + when x"C" => + case Instruction_in is + + + when others => + cycle_ctr <= x"0"; + + end case; --Cycle C + +-- ========================================================================== + + + when others => + cycle_ctr<= x"0"; + end case; --cycle_ctr +end if; --Reset stuff + +end if; --rising edge + +end process instruction_decode; + +end P65C02_architecture; +

ispLeaver/65C02.vhd Property changes : Added: svn:executable Index: ispLeaver/Processor.vhd =================================================================== --- ispLeaver/Processor.vhd (nonexistent) +++ ispLeaver/Processor.vhd (revision 2) @@ -0,0 +1,289 @@ +------------------------------------------------------------------ +-- 6502 Top module. +-- +-- Copyright Ian Chapman October 28 2010 +-- +-- This file is part of the Lattice 6502 project +-- It is used to compile with ispLeaver not Linux ghdl. +-- It is the address mapping and connecting the other modules. +-- It is replaced by Processor.vhd when running ispLeaver. +-- +-- To do +-- This will be work in process or replaced whatever +-- project file is needed to control other modules. +-- +-- ************************************************************* +-- Distributed under the GNU Lesser General Public License. * +-- This can be obtained from “www.gnu.org”. * +-- ************************************************************* +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see +-- +-- Processor.vhd +------------------------------------------------------------------ +library IEEE; --Use standard IEEE libs as recommended by Tristan. +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +entity Processor is + +Port ( +-- data_wr : inout unsigned(7 downto 0); + clk_pin : in std_logic; +-- clk_out : out std_logic; +-- u802 : out std_logic; +-- u702 : out std_logic; +-- u602 : out std_logic; +-- u1101 : out std_logic; +-- u801 : out std_logic; +-- u701 : out std_logic; + u601 : out std_logic; + rst_pin : in std_logic; + irq_pin : in std_logic; + nmi_pin : in std_logic; + RX_pin : in std_logic; +-- PG_pin : in std_logic; + TX_pin : out std_logic; + Pwr_on_pin : out std_logic + ); +end Processor; + +architecture structure of Processor is + +-- COMPONENT DECLARATIONS + +component P65C02 +port( + data_rd: in unsigned(7 downto 0); + data_wr: out unsigned(7 downto 0); +-- cycle_mark : out std_logic; --Used to signal the cycle usually cycle 0. + address: inout unsigned(15 downto 0); + proc_write : inout std_logic; + reset, clock : in std_logic; + irq : in std_logic; + nmi : in std_logic); +end component; + +component UART_RX is +port( + PG, OSC_10MHz,RX, csr_usart :in std_logic; + RX_rdy : out std_logic; + rx_reg : out unsigned(7 downto 0) + ); +end component; + +component UART_TX is +port( + OSC_10MHz, PG, csw_usart :in std_logic; + tx_dat : in unsigned(7 downto 0); + TX ,tx_rdy : out std_logic + ); +end component; + +component Lattice_rom +port ( + OutClock: in std_logic; + OutClockEn: in std_logic; + Reset: in std_logic; + Address: in std_logic_vector(9 downto 0); + Q: out std_logic_vector(7 downto 0)); +end component; + +component Lattice_ram +port ( + Clock: in std_logic; + ClockEn: in std_logic; + Reset: in std_logic; + WE: in std_logic; + Address: in std_logic_vector(9 downto 0); + Data: in std_logic_vector(7 downto 0); + Q: out std_logic_vector(7 downto 0)); +end component; + +--component ghdl_rom +--port ( +-- rom_dat: out unsigned(7 downto 0); +-- wr, clk, rst: in std_logic; +-- address: in unsigned(15 downto 0) +-- ); +--end component; + +--component ghdl_ram +--port ( +-- ram_dat: out unsigned(7 downto 0); +-- data_wr : in unsigned(7 downto 0); +-- clk, wr, rst: in std_logic; +-- address: in unsigned(15 downto 0) +-- ); +--end component; + + +------------------------------------------------------------------------ +-- Signal Declarations +------------------------------------------------------------------------ +signal address : unsigned(15 downto 0); +signal add : unsigned(15 downto 0); +signal proc_rd_dat, rom_dat, ram_dat, data_wr : unsigned(7 downto 0); +signal rx_dat : unsigned(7 downto 0); +signal proc_write : std_logic; +signal one, RX_rdy, csw_usart, csr_usart, tx_rdy : std_logic; +signal rst_bar : std_logic; + +signal clk : std_logic; +--signal clk_pin : std_logic; +signal counter : unsigned(3 downto 0); +signal ram_write : std_logic; + +-- I/O ports +constant led_port : unsigned (15 downto 0) := x"4007"; +constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output +constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here +constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting + +begin + +U1 : P65C02 port map( + reset => rst_pin, + Clock => clk_pin, + data_rd => proc_rd_dat, + data_wr => data_wr, + address => address, + proc_write => proc_write, + irq => irq_pin, +-- cycle_mark => cycle_mark); + nmi => nmi_pin); + + +U2 : UART_RX port map ( + PG => rst_pin, + OSC_10MHz => clk_pin, + RX => RX_pin, + rx_reg => rx_dat, + csr_usart => csr_usart, + RX_rdy => RX_rdy); + +U3 : UART_TX port map ( + PG => rst_pin, + TX => TX_pin, + tx_rdy => tx_rdy, + OSC_10MHz => clk_pin, + tx_dat => data_wr, + csw_usart => csw_usart); + +--R1 : ghdl_rom port map( +-- rom_dat=>rom_dat, +-- address=>address, +-- wr=>proc_write, +-- clk=>clk_pin, +-- rst=>rst_pin); + +--R2 : ghdl_ram port map( +-- clk=>clk_pin, +-- rst=>rst_pin, +-- ram_dat=>ram_dat, +-- data_wr=>data_wr, +-- address=>address, +-- wr=>ram_write); + +R3 : Lattice_rom port map( + Reset => rst_bar, + OutClock => clk_pin, + (address(9 downto 0)) => std_logic_vector(Address(9 downto 0)), + unsigned(Q) => rom_dat, + OutClockEn => one); + +R4 : Lattice_ram port map( + Reset => rst_bar, + Clock => clk_pin, + WE => ram_write, + address(9 downto 0) => std_logic_vector(Address(9 downto 0)), + Data => std_logic_vector(data_wr), + unsigned(Q) => ram_dat, ClockEn => one); + +-- address(9 downto 0) => (Address(9 downto 0)), +-- Data => (data_wr), +-- (Q) => ram_dat, ClockEn => one); + +one <= '1'; +rst_bar <= not rst_pin; +one <= '1'; +--u601 <= cycle_mark; + + + +mux_add : process(rst_pin, clk_pin) +begin +if rst_pin = '0' then +add <= (others => '0'); +elsif rising_edge(clk_pin) then + add <= address; +end if; +end process; + +ram_address : process (proc_write, address(15 downto 14)) +begin + if proc_write = '1' and address(15 downto 14) = "00" then + ram_write <= '1'; + else + ram_write <= '0'; + end if; +end process; + + +-- =================================================================== +-- Updated muxer process +muxer : process (add(15 downto 14), rom_dat, ram_dat, rx_dat, tx_rdy, rx_rdy) +begin +if add(15 downto 14) = "11" then + proc_rd_dat <= rom_dat; +end if; +if add(15 downto 14) = "00" then + proc_rd_dat <= ram_dat; +end if; +if add(15 downto 0) = rs232_dat then + proc_rd_dat <= rx_dat; +end if; +if add(15 downto 0) = uart_stat then + proc_rd_dat <= tx_rdy & rx_rdy & "000000"; +end if; +end process; +-- =================================================================== + +rs232_cs : process (rst_pin, clk_pin, address, proc_write) +begin +if proc_write = '0' and address = uart then + csr_usart <= '1'; +else + csr_usart <= '0'; +end if; + +if proc_write = '1' and address = uart then + csw_usart <= '1'; +else + csw_usart <= '0'; +end if; +end process; + + + +relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin) +begin +if rst_pin = '0' then + Pwr_on_pin <= '0'; + elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then + Pwr_on_pin <= data_wr(7); +end if; +end process; + + +end structure;

ispLeaver/Processor.vhd Property changes : Added: svn:executable Index: ispLeaver/UART_RX.vhd =================================================================== --- ispLeaver/UART_RX.vhd (nonexistent) +++ ispLeaver/UART_RX.vhd (revision 2) @@ -0,0 +1,206 @@ +------------------------------------------------------------------ +-- 6502 support module. +-- +-- Copyright Ian Chapman October 28 2010 +-- +-- This file is part of the Lattice 6502 project +-- It is used to compile with Linux ghdl and ispLeaver. +-- The baude rate is 9600. +-- +-- To do +-- Nothing. +-- +-- ************************************************************* +-- Distributed under the GNU Lesser General Public License. * +-- This can be obtained from “www.gnu.org”. * +-- ************************************************************* +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see +-- +-- UART_RX.vhd +-- ************************************************************* +-- +library IEEE; +--Library UNISIM; +--library WORK; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; --Needed for GHDL +--use UNISIM.vcomponents.all; +--use WORK.ALFT_GLOBAL_lib.all; + + +-- RX baude rate generator. Zero sync to transitions on RX +entity UART_RX is +port( + RX, OSC_10MHz, csr_usart :in std_logic; + PG : in std_logic; --Power Good. + RX_rdy : out std_logic; + rx_reg : out unsigned(7 downto 0) + ); +end UART_RX; + +Architecture behavioral of UART_RX is + +--constant define_rx_baude_rate : unsigned (5 downto 0) := "101011"; --115.2 Kbps +constant define_rx_baude_rate : unsigned (10 downto 0) := "10000010010"; --9.6 Kbps +constant define_rx_mid_strob : unsigned (10 downto 0) := "01000001001"; +constant define_rx_bits : unsigned (3 downto 0) := x"A"; --start+8+stop +signal rx_start_pul, br_start_pul, RX_BR_clk : std_logic; +signal RX_sr : std_logic_vector (1 downto 0); +signal rx_clk_int : unsigned (3 downto 0); +signal rx_br_ctr_int : unsigned (10 downto 0); +signal br_strob, br_mid_strob, end_ff : std_logic; + +-- ============================================================= +-- Synchronize BR counter to RX data transitions. + +begin +Start_up:process (OSC_10MHz, PG, RX) +begin +if PG = '0' then + rx_start_pul <= '0'; +elsif falling_edge (OSC_10MHz) then + RX_sr <= RX_sr(0) & RX; + if RX_sr = "10" and RX = '0' and rx_clk_int = define_rx_bits then + rx_start_pul <= '1'; --Used to sync the BR clock + else + rx_start_pul <= '0'; + end if; +end if; +end process; +--==================================== +-- The receive counter sits at end of count until transition +-- on the RX data in line then it is set to zero +Init_BR:process (rx_start_pul, rx_clk_int) +begin +if rx_clk_int = define_rx_bits then + br_start_pul <= rx_start_pul; --rx_start_pul is the transition +else + br_start_pul <= '0'; --Used to start the Receive counter +end if; +end process; +-- ================================================= + +-- This divides the 10MHz down to the baud rate +-- The baude rate clock the receive counter +-- that counts the RX data bits into a register. + +RX_BR_counter:process (OSC_10MHz, PG, rx_start_pul, rx_br_ctr_int, rx_clk_int, br_start_pul) +begin +if PG = '0' then + rx_br_ctr_int <= define_rx_baude_rate; + br_strob <= '0'; + br_mid_strob <= '0'; +elsif rising_edge (OSC_10MHz) then + if rx_start_pul = '1' or rx_br_ctr_int = define_rx_baude_rate then + rx_br_ctr_int <= (others => '0'); + else + rx_br_ctr_int <= rx_br_ctr_int + "1"; -- + 1; + end if; + if rx_br_ctr_int = define_rx_baude_rate then + br_strob <= '1'; + else + br_strob <= '0'; + end if; + if rx_br_ctr_int = define_rx_mid_strob then + br_mid_strob <= '1'; + else + br_mid_strob <= '0'; + end if; +end if; +end process; + +-- ================================================= + +-- This flip flop clocks the counter and Rx data + +RX_clock:process (OSC_10MHz, br_strob, br_start_pul, rx_clk_int, rx_br_ctr_int) +begin +if br_start_pul = '1' then + RX_BR_clk <= '0'; +elsif falling_edge (OSC_10MHz) then + if br_strob = '1' then + RX_BR_clk <= not RX_BR_clk; + end if; +end if; +end process; +-- ==================================================== + +-- This process counts the bits starting with the start bit + +receive_ctr:process(OSC_10MHz, br_strob, br_start_pul, RX_BR_clk, RX,rx_clk_int) +begin +if PG = '0' then + rx_clk_int <= define_rx_bits; +elsif rising_edge (OSC_10MHz) then + if (rx_clk_int /= define_rx_bits and br_strob = '1') then + rx_clk_int <= rx_clk_int + X"1"; + elsif br_start_pul = '1' then + rx_clk_int <= (others => '0'); + end if; +end if; +end process; + +Receiver:process (OSC_10MHz, RX, RX_BR_clk, rx_clk_int) +begin +if PG = '0' then + rx_reg <= (others => '0'); + +elsif rising_edge (OSC_10MHz) then + if br_mid_strob = '1' then + case rx_clk_int is + when X"1" => + rx_reg(0) <= RX; + when X"2" => + rx_reg(1) <= RX; + when X"3" => + rx_reg(2) <= RX; + when X"4" => + rx_reg(3) <= RX; + when X"5" => + rx_reg(4) <= RX; + when X"6" => + rx_reg(5) <= RX; + when X"7" => + rx_reg(6) <= RX; + when X"8" => + rx_reg(7) <= RX; + when others => + null; + end case; + end if; +end if; +end process; + +Set_rdy :process (OSC_10MHz, rx_start_pul, rx_clk_int) +begin +if PG = '0' then + RX_rdy <= '0'; + end_ff <= '0'; +elsif rising_edge (OSC_10MHz) then + if rx_clk_int = 9 then + end_ff <= '1'; + end if; + if rx_clk_int = 9 and end_ff ='0' then + RX_rdy <= '1'; + elsif csr_usart = '1' then + RX_rdy <= '0'; + elsif rx_start_pul = '1'then + end_ff <= '0'; + end if; +end if; +end process; + +end behavioral; +

ispLeaver/UART_RX.vhd Property changes : Added: svn:executable Index: ispLeaver/UART_TX.vhd =================================================================== --- ispLeaver/UART_TX.vhd (nonexistent) +++ ispLeaver/UART_TX.vhd (revision 2) @@ -0,0 +1,157 @@ +------------------------------------------------------------------ +-- 6502 support module. +-- +-- Copyright Ian Chapman October 28 2010 +-- +-- This file is part of the Lattice 6502 project +-- It is used to compile with Linux ghdl and ispLeaver. +-- The baude rate is 9600. +-- +-- To do +-- Nothing. +-- +-- ************************************************************* +-- Distributed under the GNU Lesser General Public License. * +-- This can be obtained from “www.gnu.org”. * +-- ************************************************************* +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see +-- +-- UART_TX.vhd +-- ************************************************************* +-- +library IEEE; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; --Needed for GHDL + +-- RX baude rate generator. Zero sync to transitions on RX +entity UART_TX is +port( + OSC_10MHz, PG, csw_usart :in std_logic; + tx_dat : in unsigned(7 downto 0); + TX, tx_rdy : out std_logic + ); +end UART_TX; + +Architecture behavioral of UART_TX is + +--constant define_tx_baude_rate : unsigned (6 downto 0) := "1010111"; --115.2 Kbps +constant define_tx_baude_rate : unsigned (10 downto 0) := "10000010010"; --9.6 Kbps +constant define_tx_bits : unsigned (3 downto 0) := x"B"; --start+8+stop+extra + +signal tx_clk_int : unsigned (3 downto 0); +-- signal tx_clk : unsigned (3 downto 0); +signal br_ctr_tx_int : unsigned (10 downto 0); +signal br_strob : std_logic; +signal reg_tx_dat : unsigned (7 downto 0); + +begin + +-- ================================================= +-- Load data to be transmitted +ld_tx : process (osc_10MHz, csw_usart, PG) +begin +if PG = '0' then + reg_tx_dat <= (others => '0'); +elsif rising_edge(osc_10MHz)then + if csw_usart = '1' then + reg_tx_dat <= tx_dat; + end if; +end if; +end process; +-- ================================================= +-- TX baude rate generator +TX_brg:process (OSC_10MHz, csw_usart, br_ctr_tx_int) +begin +if PG = '0' then + br_ctr_tx_int <= (others => '0'); + br_strob <= '0'; +elsif rising_edge (OSC_10MHz) then + if br_ctr_tx_int = define_tx_baude_rate or csw_usart = '1' then + br_ctr_tx_int <= (others => '0'); + else + br_ctr_tx_int <= br_ctr_tx_int + 1; + end if; + + if br_ctr_tx_int = define_tx_baude_rate then + br_strob <= '1'; + else + br_strob <= '0'; + end if; +end if; +end process; + +-- ================================================= +-- TX process gen clk for uart tx +transmit_ctr:process(osc_10MHz, csw_usart, br_strob, tx_clk_int, reg_tx_dat) +begin + +if PG = '0' then + tx_clk_int <= define_tx_bits; + TX <= '1'; +elsif rising_edge (osc_10MHz) then + if csw_usart = '1' then + tx_clk_int <= (others => '0'); + elsif tx_clk_int /= define_tx_bits and br_strob = '1' then + tx_clk_int <= tx_clk_int + 1; + end if; +end if; +-------------------------------------- +case tx_clk_int is +-- Start bit + when X"0" => + TX <= '0'; + tx_rdy <= '1'; + when X"1" => + TX <= reg_tx_dat(0); + when X"2" => + TX <= reg_tx_dat(1); + when X"3" => + TX <= reg_tx_dat(2); + when X"4" => + TX <= reg_tx_dat(3); + when X"5" => + TX <= reg_tx_dat(4); + when X"6" => + TX <= reg_tx_dat(5); + when X"7" => + TX <= reg_tx_dat(6); + when X"8" => + TX <= reg_tx_dat(7); +-- Stop bit + when X"9" => + TX <= '1'; + + when X"A" => + TX <= '1'; +-- tx_rdy <= '0'; + when X"b" => + TX <= '1'; + tx_rdy <= '0'; +-- when X"c" => +-- TX <= '1'; +-- tx_rdy <= '0'; +-- when X"d" => +-- TX <= '1'; +-- tx_rdy <= '0'; + when others => + TX <= '1'; + tx_rdy <= '0'; + end case; +--end if; +end process; + +end behavioral; + +

ispLeaver/UART_TX.vhd Property changes : Added: svn:executable Index: ghdl/kernel4.mem =================================================================== --- ghdl/kernel4.mem (nonexistent) +++ ghdl/kernel4.mem (revision 2) @@ -0,0 +1,1030 @@ +#Format=Hex +#Depth=1024 +#Width=8 +#AddrRadix=3 +#DataRadix=3 +#Data +A2 +00 +9A +8E +80 +02 +8E +81 +02 +8E +82 +02 +8E +83 +02 +8E +84 +02 +A9 +3F +20 +0D +FE +4C +23 +FC +4C +4A +FC +4C +AD +FC +4C +17 +FC +4C +38 +FC +AE +83 +02 +9D +00 +02 +A8 +E8 +8A +29 +3F +8D +83 +02 +98 +4C +1A +FC +AD +01 +40 +29 +40 +F0 +06 +AD +00 +40 +4C +26 +FC +A9 +00 +4C +1A +FC +F0 +0D +48 +20 +0D +FE +68 +C9 +0D +F0 +07 +C9 +0A +F0 +03 +4C +1D +FC +AE +84 +02 +BD +00 +02 +20 +85 +FE +C9 +72 +F0 +6E +C9 +52 +D0 +03 +4C +F8 +FC +C9 +77 +D0 +03 +4C +31 +FD +C9 +46 +D0 +03 +4C +53 +FD +C9 +47 +D0 +03 +4C +8D +FD +C9 +67 +D0 +06 +20 +85 +FE +4C +90 +02 +C9 +53 +D0 +10 +AE +84 +02 +BD +00 +02 +20 +85 +FE +C9 +31 +D0 +03 +4C +93 +FD +C9 +39 +D0 +03 +4C +07 +FE +4C +00 +FC +AD +01 +40 +29 +80 +D0 +06 +4C +BD +FC +8D +00 +40 +4C +20 +FC +AD +82 +02 +F0 +F8 +CE +82 +02 +AD +80 +02 +A8 +AA +C8 +98 +29 +3F +8D +80 +02 +BD +40 +02 +4C +B7 +FC +20 +34 +FE +A5 +03 +20 +6B +FE +A5 +02 +20 +6B +FE +A9 +20 +20 +0D +FE +A0 +00 +B1 +02 +20 +6B +FE +A9 +0D +20 +0D +FE +4C +1D +FC +20 +34 +FE +A5 +03 +85 +01 +20 +6B +FE +A5 +02 +29 +F0 +85 +00 +20 +6B +FE +A9 +00 +8D +88 +02 +A9 +20 +20 +0D +FE +AC +88 +02 +B1 +00 +20 +6B +FE +AC +88 +02 +C8 +98 +8D +88 +02 +C9 +10 +D0 +E7 +A9 +0D +20 +0D +FE +4C +1D +FC +20 +34 +FE +A5 +03 +85 +01 +20 +6B +FE +A5 +02 +85 +00 +20 +6B +FE +20 +34 +FE +A5 +02 +A0 +00 +91 +00 +A9 +0D +20 +0D +FE +4C +1D +FC +20 +34 +FE +A5 +03 +48 +A5 +02 +48 +20 +34 +FE +A5 +02 +48 +20 +34 +FE +A5 +02 +8D +85 +02 +68 +A8 +68 +85 +02 +68 +85 +03 +98 +48 +A0 +00 +8D +88 +02 +68 +91 +02 +C8 +8D +88 +02 +CC +85 +02 +D0 +F5 +A9 +0D +20 +0D +FE +4C +1D +FC +20 +34 +FE +6C +02 +00 +A2 +02 +20 +D6 +FD +A5 +02 +18 +E9 +03 +8D +89 +02 +A2 +04 +20 +D6 +FD +A5 +02 +85 +00 +A5 +03 +85 +01 +A9 +00 +8D +8A +02 +A2 +02 +20 +D6 +FD +AC +8A +02 +91 +00 +C8 +8C +8A +02 +CC +89 +02 +D0 +ED +A9 +0D +20 +0D +FE +20 +85 +FE +20 +85 +FE +20 +85 +FE +4C +1D +FC +A9 +00 +85 +02 +85 +03 +8E +87 +02 +AE +87 +02 +F0 +22 +AE +84 +02 +BD +00 +02 +20 +85 +FE +AE +87 +02 +A0 +00 +D9 +93 +FE +D0 +0A +CA +8E +87 +02 +20 +56 +FE +4C +DF +FD +C8 +C0 +10 +D0 +EC +60 +20 +D6 +FD +4C +1D +FC +48 +8C +86 +02 +AD +82 +02 +C9 +3F +10 +17 +EE +82 +02 +AD +81 +02 +A8 +AA +C8 +98 +29 +3F +8D +81 +02 +68 +9D +40 +02 +AC +86 +02 +60 +68 +AC +86 +02 +60 +A0 +00 +84 +02 +84 +03 +AE +84 +02 +BD +00 +02 +20 +85 +FE +A0 +00 +D9 +93 +FE +D0 +06 +20 +56 +FE +4C +3A +FE +C8 +C0 +10 +D0 +F0 +60 +8E +85 +02 +A2 +04 +06 +02 +26 +03 +CA +D0 +F9 +98 +05 +02 +85 +02 +AE +85 +02 +60 +A8 +18 +6A +6A +6A +6A +29 +0F +AA +BD +93 +FE +20 +0D +FE +98 +29 +0F +AA +BD +93 +FE +20 +0D +FE +60 +48 +EE +84 +02 +AD +84 +02 +29 +3F +8D +84 +02 +68 +60 +30 +31 +32 +33 +34 +35 +36 +37 +38 +39 +41 +42 +43 +44 +45 +46 +A9 +4E +20 +0D +FE +40 +A9 +49 +20 +0D +FE +40 +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +EA +4C +0D +FE +4C +6B +FE +1D +FC +00 +FC +A3 +FE +00 +FC +A9 +FE

ghdl/kernel4.mem Property changes : Added: svn:executable Index: ghdl/kernel4.asm =================================================================== --- ghdl/kernel4.asm (nonexistent) +++ ghdl/kernel4.asm (revision 2) @@ -0,0 +1,476 @@ +; Kernel +; Reads uart input +; Processes the command +; raddress = reads one byte outs to uart +; Raddress = reads 16 bytes outs to uart +; waddress data = write one databyte to address location +; Faddress data nn = Fill databyte into nn locations +; S1bcadd d d d d d chksum= see Motorolla hex format used to load short program +; Gaddress start from this address +; Sends the stuff in the output buffer to uart tx. +; +; + cpu 6502 +PAGE 40,120 + +led equ $4007 +dat232 equ $4000 +stat232 equ $4001 +tx232 equ $4000 + +;dat232 equ $290 ;used to help debug +;stat232 equ $291 +;tx232 equ $292 + +tx_rdy equ $80 ;bit 7 +rx_rdy equ $40 ;bit 6 +; +inbuflen equ $40 ;input buffer table length +otbuflen equ $40 ;output buffer table length +cr equ $0d ;cariage return + + +; ZERO PAGE STUFF +* = $0 +ptr dw $0 ;reserve 2 bytes +hexword dw $0 ;accumulates hex word + + +; STUFF IN UPPER MEMORY +* = $200 + +inbuff db 0 ;reserve 64 bytes for command input +* = inbuff + inbuflen +outbuff db 0 +* = outbuff + otbuflen + +txoutpt db 0 ;output pointer index +txinpt db 0 ;input pointer index +txoutct db 0 ;Counter +inbufpt db 0 ;Ponts where to put kb text +txtpt db 0 ;Points to text to be processed +sp1 db $0 +sp2 db $0 +sp3 db $0 +temp_y db 0 +bytcnt db 0 +n db 0 + + +page +* = $fc00 +; This is the main loop. +; +main ldx #$0 + txs ;Set stack pointer to x100 + stx txoutpt + stx txinpt + stx txoutct + stx inbufpt + stx txtpt + + lda #"?" ;Illegal char or restart + jsr sendtxt ;or bad frap + +loop jmp input ;Read serial character +back1 jmp process ;It's in reg a and stored in inbuff +back2 jmp sendbuf +back3 jmp loop +; +; +page +; This is where the uart receiver character is picked up and dumped +; into the input buffer (inbuff) +code +input jmp getchar +; beq back1 ;No new character +.loop ldx inbufpt ;Returns with it in y + sta inbuff,x ;input buffer + tay + inx + txa + and #inbuflen - 1 + sta inbufpt + tya + jmp back1 ;return with character in a + +getchar lda stat232 + and #rx_rdy + beq .exit + lda dat232 ;Character in a + jmp .loop +.exit lda #$0 + jmp back1 +code +page +code +; This is where the complicated stuff is done +process beq .exit ;It's a null character + pha + jsr sendtxt ;Echo character to terminal + pla + cmp #"\r" + beq got_cr + cmp #"\n" + beq got_cr +.exit jmp back2 + +got_cr ldx txtpt ;Decode the KB input + lda inbuff,x + jsr inctxt + cmp #"r" + beq read1 ;Read one byte rnnnn + + cmp #"R" + bne next0 + jmp readn + +next0 cmp #"w" ;Write one byte wnnnn xx + bne next1 + jmp write1 + +next1 cmp #"F" ;Fill Fnnnn nn xx + bne next2 + jmp fill + +next2 cmp #"G" ;goto nnnn + bne next3 + jmp goto + +next3 cmp #"g" ;goto 290 + bne next4 + jsr inctxt ;Get to end of buffer + jmp $290 + + +next4 cmp #"S" + bne next5 + ldx txtpt + lda inbuff,x + jsr inctxt + cmp #"1" + bne next5 + jmp scode +next5 cmp #"9" + bne next6 + jmp flush ;Last S code packet not used so flush + +next6 jmp main ;restart bad input + + + + +code +page +code +; This is where stuff is pulled from the output buffer (outbuff) +; and sent to the terminal +sendbuf lda stat232 ;All regs destroyed + and #tx_rdy ;Test uart tx status + bne .exit ;In use + jmp .gettxt ;char in A for return +.bak sta tx232 ;Byte to terminal +.exit jmp back3 +; Pull txt from buffer if not empty +.gettxt lda txoutct + beq .exit + dec txoutct + lda txoutpt ;out text out pointer + tay + tax + iny + tya + and #inbuflen - 1 + sta txoutpt + lda outbuff,x + jmp .bak + +code +page + +page ;This routing reads one byt"\n"e from address +read1 jsr txt2hex ;Convert string to 16 bit word + + lda hexword + 1 + jsr hex2txt + + lda hexword + jsr hex2txt + + lda #" " + jsr sendtxt + ldy #$0 + lda (hexword),y + jsr hex2txt + lda #"\r" + jsr sendtxt + jmp back2 +; =============================================== + +readn jsr txt2hex ;Convert string to 16 bit word + + lda hexword + 1 + sta ptr + 1 + jsr hex2txt + + lda hexword + and #$f0 + sta ptr + jsr hex2txt + + lda #$0 + sta temp_y +read_lp lda #" " + jsr sendtxt + ldy temp_y + lda (ptr),y + jsr hex2txt + ldy temp_y + iny + tya + sta temp_y + cmp #$10 + bne read_lp + + lda #"\r" + jsr sendtxt + jmp back2 +; ================================================== + +; This routine writes one byte to memory +; address space data +write1 jsr txt2hex ;Convert string to 16 bit word + + lda hexword + 1 ;Save these locations + sta ptr + 1 + jsr hex2txt + + lda hexword + sta ptr + jsr hex2txt + + jsr txt2hex ;Convert data + lda hexword + + ldy #$0 + sta (ptr),y + lda #"\r" + jsr sendtxt + jmp back2 +; ================================================== +fill jsr txt2hex ;Convert string to 16 bit word + + lda hexword + 1 ;Save these locations + pha + lda hexword + pha + + jsr txt2hex ;Convert data + lda hexword + pha ;Data on stack + + jsr txt2hex ;how many bytes? + lda hexword + sta sp1 ;Number of bytes to fill in sp1 + + pla + tay ;Data into y + pla ;Restore hexword + sta hexword + pla + sta hexword + 1 + tya + pha + + ldy #$0 + sta temp_y + pla +fill_lp sta (hexword),y + iny + sta temp_y + cpy sp1 + bne fill_lp + + lda #"\r" + jsr sendtxt + jmp back2 + +goto jsr txt2hex + jmp (hexword) ;goto user code best return to main x"fc00" + +page +code +; This routine takes the Motorolla S code generated +; by crasm and loads it into RAM. +; The checksum is not checked since there is no comms. + +scode ldx #$2 ;convert two bytes byte count + jsr cod2hex + lda hexword + clc + sbc #3 + sta bytcnt ;total bytes to transfer + + ldx #$4 ;convert four bytes to address + jsr cod2hex ;hexword points to where data goes + lda hexword + sta ptr + lda hexword + 1 + sta ptr + 1 ;ptr holds point + + lda #$0 + sta n + +scodelp ldx #$2 ;4 or 2 bytes to form number + jsr cod2hex + ldy n + sta (ptr),y + iny + sty n + cpy bytcnt + bne scodelp + lda #"\r" + jsr sendtxt + jsr inctxt ;skip checksum 1 + jsr inctxt ;and cs2 + jsr inctxt ;and cr + jmp back2 + +cod2hex lda #$0 + sta hexword + sta hexword + 1 + stx sp3 ;Save No of bytes to convert this time + +.lphex ldx sp3 + beq .exit + ldx txtpt + lda inbuff,x + jsr inctxt + ldx sp3 + + ldy #$0 +.nothis cmp asctbl,y + bne .next + dex ;Got 1 match + stx sp3 + jsr accum + jmp .lphex +.next iny + cpy #$10 + bne .nothis ;next hex char +.exit rts ;last char + +flush jsr cod2hex ;empty buffer + jmp back2 ;result of subroutine ignored + + +code + + +page +; This is where the output buffer (outbuf) is loaded. +code +sendtxt pha ;A hold character to be place in buffer + sty sp2 + lda txoutct + cmp #otbuflen -1 + bpl .exit ;buffer should never be full + inc txoutct + lda txinpt ;out text out pointer + tay + tax + iny + tya + and #otbuflen - 1 + sta txinpt + pla + sta outbuff,x + ldy sp2 + rts +.exit pla + ldy sp2 + rts + + +code +page +code +txt2hex ldy #$0 + sty hexword + sty hexword + 1 + +loophex ldx txtpt + lda inbuff,x ;input buffer + jsr inctxt ;inc counter + ldy #$0 +nomatch cmp asctbl,y + bne .next + jsr accum + jmp loophex +.next iny + cpy #$10 + bne nomatch ;next hex char + rts ;not hex char + + +accum stx sp1 + ldx #$4 ;y holds hex of character +accloop asl hexword + rol hexword + 1 + dex + bne accloop + tya + ora hexword + sta hexword + ldx sp1 + rts + + +hex2txt tay ;A holds byte to convert + clc + ror a + ror a + ror a + ror a + and #$0f + tax + lda asctbl,x + jsr sendtxt + tya + and #$0f + tax + lda asctbl,x + jsr sendtxt + rts +; inc after reading from inbuff +inctxt pha ;NOT before + inc txtpt + lda txtpt + and #inbuflen - 1 + sta txtpt + pla + rts + +asctbl asc "0123456789ABCDEF" +code + +page ;All the start up stuff + +nmi_srv lda #"N" + jsr sendtxt + rti + +irq_srv lda #"I" + jsr sendtxt + rti +* =$fff0 + jmp sendtxt ;Links for usrcode + jmp hex2txt + dw back2 + +* = $fff8 +; +indjmp dw main +nmi dw nmi_srv +rst dw main ;Should be main, this is for test only +irq dw irq_srv

ghdl/kernel4.asm Property changes : Added: svn:executable Index: ghdl/usrcode.asm =================================================================== --- ghdl/usrcode.asm (nonexistent) +++ ghdl/usrcode.asm (revision 2) @@ -0,0 +1,111 @@ +; + cpu 6502 +PAGE 40,120 +; **************************************************************************************** +; This is intended to be the template for the user code +; **************************************************************************************** + +* = $290 ;user code starts at $290 +return equ $fff6 ;jump to fcoo to return control and restart +sendtxt equ $fff0 +hex2txt equ $fff3 + + +main ldy #$55 + ldx #$aa + lda #$7e + clc + adc #$6 ;9-3=6 carry=0 + php + pha + txa + pha + tya + pha + + lda #"Y" ;Display Y register + jsr sendtxt + lda #"=" + jsr sendtxt + pla + jsr hex2txt + lda #" " + jsr sendtxt + + lda #"X" ;Display X register + jsr sendtxt + lda #"=" + jsr sendtxt + pla + jsr hex2txt + lda #" " + jsr sendtxt + + lda #"A" ;Display A register + jsr sendtxt + lda #"=" + jsr sendtxt + pla + jsr hex2txt + lda #" " + jsr sendtxt + + lda #"C" ;Display carry + jsr sendtxt + lda #"=" + jsr sendtxt + plp + php + bcc clear1 + lda #"1" + jmp cont1 +clear1 lda #"0" +cont1 jsr sendtxt + lda #" " + jsr sendtxt + + lda #"V" ;Display overflow + jsr sendtxt + lda #"=" + jsr sendtxt + plp + php + bvc clear2 + lda #"1" + jmp cont2 +clear2 lda #"0" +cont2 jsr sendtxt + lda #" " + jsr sendtxt + + lda #"Z" ;Display zero + jsr sendtxt + lda #"=" + jsr sendtxt + plp + php + beq clear3 + lda #"1" + jmp cont3 +clear3 lda #"0" +cont3 jsr sendtxt + lda #" " + jsr sendtxt + + lda #"M" ;Display minus + jsr sendtxt + lda #"=" + jsr sendtxt + plp + bpl clear4 + lda #"1" + jmp cont4 +clear4 lda #"0" +cont4 jsr sendtxt + + + lda #"\r" + jsr sendtxt + jmp (return) + +; end of program

ghdl/usrcode.asm Property changes : Added: svn:executable Index: ghdl/crasm.lang =================================================================== --- ghdl/crasm.lang (nonexistent) +++ ghdl/crasm.lang (revision 2) @@ -0,0 +1,227 @@ + + + + + text/x-crasm + *.asm + ; + + + +