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URL https://opencores.org/ocsvn/lcd_block/lcd_block/trunk

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    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/trunk/hdl/iseProject/ipcore_dir/coreILA.xco
0,0 → 1,141
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Tue May 22 22:48:20 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=false
CSET component_name=coreILA
CSET constraint_type=external
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=17
CSET data_same_as_trigger=false
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET example_design=true
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=16384
CSET sample_on=Rising
CSET trigger_port_width_1=1
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=true
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-01-07T09:19:41Z
# END Extra information
GENERATE
# CRC: 52a8bb9b
/trunk/hdl/iseProject/ipcore_dir/coreICON.xco
0,0 → 1,56
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Tue May 22 22:08:27 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=coreICON
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=true
CSET number_control_ports=2
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-01-07T09:19:07Z
# END Extra information
GENERATE
# CRC: d9309160
/trunk/hdl/iseProject/ipcore_dir/coreVIO.xco
0,0 → 1,59
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Tue May 22 23:21:52 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=19
CSET component_name=coreVIO
CSET constraint_type=external
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=true
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=false
CSET example_design=true
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-01-07T09:20:13Z
# END Extra information
GENERATE
# CRC: 8c8e6067
/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
8,11 → 8,8
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/lcd_block/hdl/iseProject/lcd_controller.v&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/lcd_block/hdl/iseProject/top_hw_testbench.v&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/lcd_block/hdl/iseProject/lcd_wishbone_slave.v&quot; into library work</arg>
</msg>
 
</messages>
 
/trunk/hdl/iseProject/pins_hw_testbench.ucf
0,0 → 1,12
# Pins used by Spartan3E starter Kit
#NET "lcd_e" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_rs" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_rw" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# The LCD four-bit data interface is shared with the StrataFlash.
#NET "lcd_nibble<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_nibble<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_nibble<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "lcd_nibble<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 
#NET "rst" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
/trunk/hdl/iseProject/top_hw_testbench.v
0,0 → 1,64
`timescale 1ns / 1ps
/*
Top module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
*/
module top_hw_testbench(
input clk
);
// Declare some wires to connect the components
wire rst;
wire rs_in,strobe_in;
wire[7:0] data_in, period_clk_ns;
wire [3:0] lcd_nibble;
wire lcd_e,lcd_rs,lcd_rw,disable_flash,done;
// Declare the ICON wires
wire [35: 0] control0;
wire [35: 0] control1;
// Declare VIO wires
wire [18: 0] async_out;
// Declare ILA wires
wire trig_0;
wire [16:0] data;
// Instantiate our Device under test
lcd_controller DUT (
rst,
clk,
rs_in,
data_in,
strobe_in,
period_clk_ns,
lcd_e,
lcd_nibble,
lcd_rs,
lcd_rw,
disable_flash,
done
);
coreICON integratedController (
.CONTROL0(control0), // INOUT BUS [35:0]
.CONTROL1(control1)
); // INOUT BUS [35:0]
coreILA integratedLogicAnalyser (
.CONTROL(control0), // INOUT BUS [35:0]
.CLK(clk), // IN
.DATA(data), // DATA [16:0];
.TRIG0(trig_0)
); // IN BUS [0:0]
coreVIO VIO_inst
(
.CONTROL(control1), // INOUT BUS [35:0]
.ASYNC_OUT(async_out)
); // IN BUS [18:0]
assign trig_0 = lcd_e;
assign {rst, rs_in, data_in, strobe_in, period_clk_ns} = async_out;
assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
 
endmodule
/trunk/hdl/iseProject/top_hw_testbench.cpj
0,0 → 1,543
#ChipScope Pro Analyzer Project File, Version 3.0
#Wed May 23 02:07:27 CEST 2012
device.0.configFileDir=E\:\\lcd_block\\hdl\\iseProject
device.0.configFilename=top_hw_testbench.bit
device.0.inserterCDCFileDir=E\:\\lcd_block\\hdl\\iseProject
device.0.inserterCDCFilename=
deviceChain.deviceName0=XC3S500E
deviceChain.deviceName1=XCF04S
deviceChain.deviceName2=XC2C64A
deviceChain.iRLength0=6
deviceChain.iRLength1=8
deviceChain.iRLength2=8
deviceChain.name0=MyDevice0
deviceChain.name1=MyDevice1
deviceChain.name2=MyDevice2
deviceIds=41c22093f504609306e5e093
mdiAreaHeight=0.7407407407407407
mdiAreaHeightLast=0.6990740740740741
mdiCount=3
mdiDevice0=0
mdiDevice1=0
mdiDevice2=0
mdiType0=1
mdiType1=0
mdiType2=6
mdiUnit0=0
mdiUnit1=0
mdiUnit2=1
navigatorHeight=0.17708333333333334
navigatorHeightLast=0.17939814814814814
navigatorWidth=0.1794871794871795
navigatorWidthLast=0.1794871794871795
signalDisplayPath=0
unit.0.0.0.HEIGHT0=0.36263737
unit.0.0.0.TriggerRow0=1
unit.0.0.0.TriggerRow1=1
unit.0.0.0.TriggerRow2=1
unit.0.0.0.WIDTH0=0.6702786
unit.0.0.0.X0=0.0
unit.0.0.0.Y0=0.0
unit.0.0.1.HEIGHT1=0.62166405
unit.0.0.1.WIDTH1=1.0
unit.0.0.1.X1=0.0015479876
unit.0.0.1.Y1=0.3610675
unit.0.0.MFBitsA0=R
unit.0.0.MFBitsB0=0
unit.0.0.MFCompareA0=0
unit.0.0.MFCompareB0=999
unit.0.0.MFCount=1
unit.0.0.MFDisplay0=0
unit.0.0.MFEventType0=3
unit.0.0.RunMode=REPETITIVE RUN
unit.0.0.SQCondition=All Data
unit.0.0.SQContiguous0=0
unit.0.0.SequencerOn=0
unit.0.0.TCActive=0
unit.0.0.TCAdvanced0=0
unit.0.0.TCCondition0_0=M0
unit.0.0.TCCondition0_1=
unit.0.0.TCConditionType0=0
unit.0.0.TCCount=1
unit.0.0.TCEventCount0=1
unit.0.0.TCEventType0=3
unit.0.0.TCName0=TriggerCondition0
unit.0.0.TCOutputEnable0=0
unit.0.0.TCOutputHigh0=1
unit.0.0.TCOutputMode0=0
unit.0.0.browser_tree_state<Data\ Port>=1
unit.0.0.coretype=ILA
unit.0.0.eventCount0=1
unit.0.0.port.-1.b.0.alias=lcd_nibble
unit.0.0.port.-1.b.0.channellist=5 6 7 8
unit.0.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.b.0.name=DataPort
unit.0.0.port.-1.b.0.orderindex=-1
unit.0.0.port.-1.b.0.radix=Hex
unit.0.0.port.-1.b.0.signedOffset=0.0
unit.0.0.port.-1.b.0.signedPrecision=0
unit.0.0.port.-1.b.0.signedScaleFactor=1.0
unit.0.0.port.-1.b.0.tokencount=0
unit.0.0.port.-1.b.0.unsignedOffset=0.0
unit.0.0.port.-1.b.0.unsignedPrecision=0
unit.0.0.port.-1.b.0.unsignedScaleFactor=1.0
unit.0.0.port.-1.b.0.visible=1
unit.0.0.port.-1.buscount=1
unit.0.0.port.-1.channelcount=17
unit.0.0.port.-1.s.0.alias=strobe_in
unit.0.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.0.name=DataPort[0]
unit.0.0.port.-1.s.0.orderindex=-1
unit.0.0.port.-1.s.0.visible=1
unit.0.0.port.-1.s.1.alias=done
unit.0.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.1.name=DataPort[1]
unit.0.0.port.-1.s.1.orderindex=-1
unit.0.0.port.-1.s.1.visible=1
unit.0.0.port.-1.s.10.alias=
unit.0.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.10.name=DataPort[10]
unit.0.0.port.-1.s.10.orderindex=-1
unit.0.0.port.-1.s.10.visible=1
unit.0.0.port.-1.s.11.alias=
unit.0.0.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.11.name=DataPort[11]
unit.0.0.port.-1.s.11.orderindex=-1
unit.0.0.port.-1.s.11.visible=1
unit.0.0.port.-1.s.12.alias=
unit.0.0.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.12.name=DataPort[12]
unit.0.0.port.-1.s.12.orderindex=-1
unit.0.0.port.-1.s.12.visible=1
unit.0.0.port.-1.s.13.alias=
unit.0.0.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.13.name=DataPort[13]
unit.0.0.port.-1.s.13.orderindex=-1
unit.0.0.port.-1.s.13.visible=1
unit.0.0.port.-1.s.14.alias=
unit.0.0.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.14.name=DataPort[14]
unit.0.0.port.-1.s.14.orderindex=-1
unit.0.0.port.-1.s.14.visible=1
unit.0.0.port.-1.s.15.alias=
unit.0.0.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.15.name=DataPort[15]
unit.0.0.port.-1.s.15.orderindex=-1
unit.0.0.port.-1.s.15.visible=1
unit.0.0.port.-1.s.16.alias=
unit.0.0.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.16.name=DataPort[16]
unit.0.0.port.-1.s.16.orderindex=-1
unit.0.0.port.-1.s.16.visible=1
unit.0.0.port.-1.s.2.alias=disable_flash
unit.0.0.port.-1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.2.name=DataPort[2]
unit.0.0.port.-1.s.2.orderindex=-1
unit.0.0.port.-1.s.2.visible=1
unit.0.0.port.-1.s.3.alias=lcd_rw
unit.0.0.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.3.name=DataPort[3]
unit.0.0.port.-1.s.3.orderindex=-1
unit.0.0.port.-1.s.3.visible=1
unit.0.0.port.-1.s.4.alias=lcd_rs
unit.0.0.port.-1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.4.name=DataPort[4]
unit.0.0.port.-1.s.4.orderindex=-1
unit.0.0.port.-1.s.4.visible=1
unit.0.0.port.-1.s.5.alias=
unit.0.0.port.-1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.5.name=DataPort[5]
unit.0.0.port.-1.s.5.orderindex=-1
unit.0.0.port.-1.s.5.visible=0
unit.0.0.port.-1.s.6.alias=
unit.0.0.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.6.name=DataPort[6]
unit.0.0.port.-1.s.6.orderindex=-1
unit.0.0.port.-1.s.6.visible=0
unit.0.0.port.-1.s.7.alias=
unit.0.0.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.7.name=DataPort[7]
unit.0.0.port.-1.s.7.orderindex=-1
unit.0.0.port.-1.s.7.visible=0
unit.0.0.port.-1.s.8.alias=
unit.0.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.8.name=DataPort[8]
unit.0.0.port.-1.s.8.orderindex=-1
unit.0.0.port.-1.s.8.visible=0
unit.0.0.port.-1.s.9.alias=lcd_e
unit.0.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.9.name=DataPort[9]
unit.0.0.port.-1.s.9.orderindex=-1
unit.0.0.port.-1.s.9.visible=1
unit.0.0.port.0.b.0.alias=
unit.0.0.port.0.b.0.channellist=0
unit.0.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.b.0.name=TriggerPort0
unit.0.0.port.0.b.0.orderindex=-1
unit.0.0.port.0.b.0.radix=Hex
unit.0.0.port.0.b.0.signedOffset=0.0
unit.0.0.port.0.b.0.signedPrecision=0
unit.0.0.port.0.b.0.signedScaleFactor=1.0
unit.0.0.port.0.b.0.unsignedOffset=0.0
unit.0.0.port.0.b.0.unsignedPrecision=0
unit.0.0.port.0.b.0.unsignedScaleFactor=1.0
unit.0.0.port.0.b.0.visible=1
unit.0.0.port.0.buscount=1
unit.0.0.port.0.channelcount=1
unit.0.0.port.0.s.0.alias=
unit.0.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.0.name=TriggerPort0[0]
unit.0.0.port.0.s.0.orderindex=-1
unit.0.0.port.0.s.0.visible=1
unit.0.0.portcount=1
unit.0.0.rep_trigger.clobber=1
unit.0.0.rep_trigger.dir=E\:\\lcd_block\\hdl\\iseProject
unit.0.0.rep_trigger.filename=waveform
unit.0.0.rep_trigger.format=ASCII
unit.0.0.rep_trigger.loggingEnabled=0
unit.0.0.rep_trigger.signals=All Signals/Buses
unit.0.0.samplesPerTrigger=1
unit.0.0.triggerCapture=1
unit.0.0.triggerNSamplesTS=0
unit.0.0.triggerPosition=0
unit.0.0.triggerWindowCount=1
unit.0.0.triggerWindowDepth=16384
unit.0.0.triggerWindowTS=0
unit.0.0.username=MyILA0
unit.0.0.waveform.count=14
unit.0.0.waveform.posn.0.channel=0
unit.0.0.waveform.posn.0.name=strobe_in
unit.0.0.waveform.posn.0.type=signal
unit.0.0.waveform.posn.1.channel=1
unit.0.0.waveform.posn.1.name=done
unit.0.0.waveform.posn.1.type=signal
unit.0.0.waveform.posn.10.channel=13
unit.0.0.waveform.posn.10.name=DataPort[13]
unit.0.0.waveform.posn.10.type=signal
unit.0.0.waveform.posn.11.channel=14
unit.0.0.waveform.posn.11.name=DataPort[14]
unit.0.0.waveform.posn.11.type=signal
unit.0.0.waveform.posn.12.channel=15
unit.0.0.waveform.posn.12.name=DataPort[15]
unit.0.0.waveform.posn.12.type=signal
unit.0.0.waveform.posn.13.channel=16
unit.0.0.waveform.posn.13.name=DataPort[16]
unit.0.0.waveform.posn.13.type=signal
unit.0.0.waveform.posn.14.channel=16
unit.0.0.waveform.posn.14.name=DataPort[16]
unit.0.0.waveform.posn.14.type=signal
unit.0.0.waveform.posn.15.channel=16
unit.0.0.waveform.posn.15.name=DataPort[16]
unit.0.0.waveform.posn.15.type=signal
unit.0.0.waveform.posn.16.channel=16
unit.0.0.waveform.posn.16.name=DataPort[16]
unit.0.0.waveform.posn.16.type=signal
unit.0.0.waveform.posn.2.channel=2
unit.0.0.waveform.posn.2.name=disable_flash
unit.0.0.waveform.posn.2.type=signal
unit.0.0.waveform.posn.3.channel=3
unit.0.0.waveform.posn.3.name=lcd_rw
unit.0.0.waveform.posn.3.type=signal
unit.0.0.waveform.posn.4.channel=4
unit.0.0.waveform.posn.4.name=lcd_rs
unit.0.0.waveform.posn.4.type=signal
unit.0.0.waveform.posn.5.channel=2147483646
unit.0.0.waveform.posn.5.name=lcd_nibble
unit.0.0.waveform.posn.5.radix=1
unit.0.0.waveform.posn.5.type=bus
unit.0.0.waveform.posn.6.channel=9
unit.0.0.waveform.posn.6.name=lcd_e
unit.0.0.waveform.posn.6.type=signal
unit.0.0.waveform.posn.7.channel=10
unit.0.0.waveform.posn.7.name=DataPort[10]
unit.0.0.waveform.posn.7.type=signal
unit.0.0.waveform.posn.8.channel=11
unit.0.0.waveform.posn.8.name=DataPort[11]
unit.0.0.waveform.posn.8.type=signal
unit.0.0.waveform.posn.9.channel=12
unit.0.0.waveform.posn.9.name=DataPort[12]
unit.0.0.waveform.posn.9.type=signal
unit.0.0.waveform.rulerdisplay=1
unit.0.0.waveform.shownegative=0
unit.0.0.waveform.showtriggermarkers=1
unit.0.0.waveform.showwindowmarkers=1
unit.0.1.6.HEIGHT6=0.33751962
unit.0.1.6.WIDTH6=0.33049536
unit.0.1.6.X6=0.67105263
unit.0.1.6.Y6=0.007849294
unit.0.1.browser_tree_state<Async\ Output\ Port>=1
unit.0.1.coretype=VIO
unit.0.1.port.-1.buscount=0
unit.0.1.port.-1.channelcount=0
unit.0.1.port.0.buscount=0
unit.0.1.port.0.channelcount=0
unit.0.1.port.1.b.0.alias=data_in
unit.0.1.port.1.b.0.channellist=9 10 11 12 13 14 15 16
unit.0.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.b.0.display=0
unit.0.1.port.1.b.0.name=AsyncOut_1
unit.0.1.port.1.b.0.orderindex=-1
unit.0.1.port.1.b.0.radix=Ascii
unit.0.1.port.1.b.0.signedOffset=0.0
unit.0.1.port.1.b.0.signedPrecision=0
unit.0.1.port.1.b.0.signedScaleFactor=1.0
unit.0.1.port.1.b.0.tokencount=0
unit.0.1.port.1.b.0.unsignedOffset=0.0
unit.0.1.port.1.b.0.unsignedPrecision=0
unit.0.1.port.1.b.0.unsignedScaleFactor=1.0
unit.0.1.port.1.b.0.value=A
unit.0.1.port.1.b.0.visible=1
unit.0.1.port.1.b.1.alias=period_clk_ns
unit.0.1.port.1.b.1.channellist=0 1 2 3 4 5 6 7
unit.0.1.port.1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.b.1.display=0
unit.0.1.port.1.b.1.name=AsyncOut
unit.0.1.port.1.b.1.orderindex=-1
unit.0.1.port.1.b.1.radix=Unsigned
unit.0.1.port.1.b.1.signedOffset=0.0
unit.0.1.port.1.b.1.signedPrecision=0
unit.0.1.port.1.b.1.signedScaleFactor=1.0
unit.0.1.port.1.b.1.tokencount=0
unit.0.1.port.1.b.1.unsignedOffset=0.0
unit.0.1.port.1.b.1.unsignedPrecision=0
unit.0.1.port.1.b.1.unsignedScaleFactor=1.0
unit.0.1.port.1.b.1.value=20
unit.0.1.port.1.b.1.visible=1
unit.0.1.port.1.buscount=2
unit.0.1.port.1.channelcount=19
unit.0.1.port.1.s.0.alias=
unit.0.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.0.display=0
unit.0.1.port.1.s.0.name=AsyncOut[0]
unit.0.1.port.1.s.0.orderindex=-1
unit.0.1.port.1.s.0.persistence=0
unit.0.1.port.1.s.0.value=0
unit.0.1.port.1.s.0.visible=0
unit.0.1.port.1.s.1.alias=
unit.0.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.1.display=0
unit.0.1.port.1.s.1.name=AsyncOut[1]
unit.0.1.port.1.s.1.orderindex=-1
unit.0.1.port.1.s.1.persistence=0
unit.0.1.port.1.s.1.value=0
unit.0.1.port.1.s.1.visible=0
unit.0.1.port.1.s.10.alias=
unit.0.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.10.display=0
unit.0.1.port.1.s.10.name=AsyncOut[10]
unit.0.1.port.1.s.10.orderindex=-1
unit.0.1.port.1.s.10.persistence=0
unit.0.1.port.1.s.10.value=0
unit.0.1.port.1.s.10.visible=0
unit.0.1.port.1.s.11.alias=
unit.0.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.11.display=0
unit.0.1.port.1.s.11.name=AsyncOut[11]
unit.0.1.port.1.s.11.orderindex=-1
unit.0.1.port.1.s.11.persistence=0
unit.0.1.port.1.s.11.value=0
unit.0.1.port.1.s.11.visible=0
unit.0.1.port.1.s.12.alias=
unit.0.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.12.display=0
unit.0.1.port.1.s.12.name=AsyncOut[12]
unit.0.1.port.1.s.12.orderindex=-1
unit.0.1.port.1.s.12.persistence=0
unit.0.1.port.1.s.12.value=0
unit.0.1.port.1.s.12.visible=0
unit.0.1.port.1.s.13.alias=
unit.0.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.13.display=0
unit.0.1.port.1.s.13.name=AsyncOut[13]
unit.0.1.port.1.s.13.orderindex=-1
unit.0.1.port.1.s.13.persistence=0
unit.0.1.port.1.s.13.value=0
unit.0.1.port.1.s.13.visible=0
unit.0.1.port.1.s.14.alias=
unit.0.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.14.display=0
unit.0.1.port.1.s.14.name=AsyncOut[14]
unit.0.1.port.1.s.14.orderindex=-1
unit.0.1.port.1.s.14.persistence=0
unit.0.1.port.1.s.14.value=0
unit.0.1.port.1.s.14.visible=0
unit.0.1.port.1.s.15.alias=
unit.0.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.15.display=0
unit.0.1.port.1.s.15.name=AsyncOut[15]
unit.0.1.port.1.s.15.orderindex=-1
unit.0.1.port.1.s.15.persistence=0
unit.0.1.port.1.s.15.value=1
unit.0.1.port.1.s.15.visible=0
unit.0.1.port.1.s.16.alias=
unit.0.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.16.display=0
unit.0.1.port.1.s.16.name=AsyncOut[16]
unit.0.1.port.1.s.16.orderindex=-1
unit.0.1.port.1.s.16.persistence=0
unit.0.1.port.1.s.16.value=0
unit.0.1.port.1.s.16.visible=0
unit.0.1.port.1.s.17.alias=rs_in
unit.0.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.17.display=3
unit.0.1.port.1.s.17.name=AsyncOut[17]
unit.0.1.port.1.s.17.orderindex=-1
unit.0.1.port.1.s.17.persistence=0
unit.0.1.port.1.s.17.value=0
unit.0.1.port.1.s.17.visible=1
unit.0.1.port.1.s.18.alias=rst
unit.0.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.18.display=1
unit.0.1.port.1.s.18.name=AsyncOut[18]
unit.0.1.port.1.s.18.orderindex=-1
unit.0.1.port.1.s.18.persistence=0
unit.0.1.port.1.s.18.value=0
unit.0.1.port.1.s.18.visible=1
unit.0.1.port.1.s.2.alias=
unit.0.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.2.display=0
unit.0.1.port.1.s.2.name=AsyncOut[2]
unit.0.1.port.1.s.2.orderindex=-1
unit.0.1.port.1.s.2.persistence=0
unit.0.1.port.1.s.2.value=1
unit.0.1.port.1.s.2.visible=0
unit.0.1.port.1.s.3.alias=
unit.0.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.3.display=0
unit.0.1.port.1.s.3.name=AsyncOut[3]
unit.0.1.port.1.s.3.orderindex=-1
unit.0.1.port.1.s.3.persistence=0
unit.0.1.port.1.s.3.value=0
unit.0.1.port.1.s.3.visible=0
unit.0.1.port.1.s.4.alias=
unit.0.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.4.display=0
unit.0.1.port.1.s.4.name=AsyncOut[4]
unit.0.1.port.1.s.4.orderindex=-1
unit.0.1.port.1.s.4.persistence=0
unit.0.1.port.1.s.4.value=1
unit.0.1.port.1.s.4.visible=0
unit.0.1.port.1.s.5.alias=
unit.0.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.5.display=0
unit.0.1.port.1.s.5.name=AsyncOut[5]
unit.0.1.port.1.s.5.orderindex=-1
unit.0.1.port.1.s.5.persistence=0
unit.0.1.port.1.s.5.value=0
unit.0.1.port.1.s.5.visible=0
unit.0.1.port.1.s.6.alias=
unit.0.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.6.display=0
unit.0.1.port.1.s.6.name=AsyncOut[6]
unit.0.1.port.1.s.6.orderindex=-1
unit.0.1.port.1.s.6.persistence=0
unit.0.1.port.1.s.6.value=0
unit.0.1.port.1.s.6.visible=0
unit.0.1.port.1.s.7.alias=
unit.0.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.7.display=0
unit.0.1.port.1.s.7.name=AsyncOut[7]
unit.0.1.port.1.s.7.orderindex=-1
unit.0.1.port.1.s.7.persistence=0
unit.0.1.port.1.s.7.value=0
unit.0.1.port.1.s.7.visible=0
unit.0.1.port.1.s.8.alias=strobe_in
unit.0.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.8.display=1
unit.0.1.port.1.s.8.name=AsyncOut[8]
unit.0.1.port.1.s.8.orderindex=-1
unit.0.1.port.1.s.8.persistence=0
unit.0.1.port.1.s.8.value=0
unit.0.1.port.1.s.8.visible=1
unit.0.1.port.1.s.9.alias=
unit.0.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.1.port.1.s.9.display=0
unit.0.1.port.1.s.9.name=AsyncOut[9]
unit.0.1.port.1.s.9.orderindex=-1
unit.0.1.port.1.s.9.persistence=0
unit.0.1.port.1.s.9.value=1
unit.0.1.port.1.s.9.visible=0
unit.0.1.port.2.buscount=0
unit.0.1.port.2.channelcount=0
unit.0.1.portcount=3
unit.0.1.username=MyVIO1
unit.0.1.vio.count=5
unit.0.1.vio.posn.0.channel=2147483646
unit.0.1.vio.posn.0.name=period_clk_ns
unit.0.1.vio.posn.0.port=1
unit.0.1.vio.posn.0.radix=4
unit.0.1.vio.posn.0.type=bus
unit.0.1.vio.posn.1.channel=8
unit.0.1.vio.posn.1.name=strobe_in
unit.0.1.vio.posn.1.port=1
unit.0.1.vio.posn.1.type=signal
unit.0.1.vio.posn.10.channel=18
unit.0.1.vio.posn.10.name=AsyncOut[18]
unit.0.1.vio.posn.10.port=1
unit.0.1.vio.posn.10.type=signal
unit.0.1.vio.posn.11.channel=18
unit.0.1.vio.posn.11.name=AsyncOut[18]
unit.0.1.vio.posn.11.port=1
unit.0.1.vio.posn.11.type=signal
unit.0.1.vio.posn.12.channel=18
unit.0.1.vio.posn.12.name=AsyncOut[18]
unit.0.1.vio.posn.12.port=1
unit.0.1.vio.posn.12.type=signal
unit.0.1.vio.posn.13.channel=18
unit.0.1.vio.posn.13.name=AsyncOut[18]
unit.0.1.vio.posn.13.port=1
unit.0.1.vio.posn.13.type=signal
unit.0.1.vio.posn.14.channel=18
unit.0.1.vio.posn.14.name=AsyncOut[18]
unit.0.1.vio.posn.14.port=1
unit.0.1.vio.posn.14.type=signal
unit.0.1.vio.posn.15.channel=18
unit.0.1.vio.posn.15.name=AsyncOut[18]
unit.0.1.vio.posn.15.port=1
unit.0.1.vio.posn.15.type=signal
unit.0.1.vio.posn.16.channel=18
unit.0.1.vio.posn.16.name=AsyncOut[18]
unit.0.1.vio.posn.16.port=1
unit.0.1.vio.posn.16.type=signal
unit.0.1.vio.posn.17.channel=18
unit.0.1.vio.posn.17.name=AsyncOut[18]
unit.0.1.vio.posn.17.port=1
unit.0.1.vio.posn.17.type=signal
unit.0.1.vio.posn.18.channel=18
unit.0.1.vio.posn.18.name=AsyncOut[18]
unit.0.1.vio.posn.18.port=1
unit.0.1.vio.posn.18.type=signal
unit.0.1.vio.posn.2.channel=2147483646
unit.0.1.vio.posn.2.name=data_in
unit.0.1.vio.posn.2.port=1
unit.0.1.vio.posn.2.radix=5
unit.0.1.vio.posn.2.type=bus
unit.0.1.vio.posn.3.channel=17
unit.0.1.vio.posn.3.name=rs_in
unit.0.1.vio.posn.3.port=1
unit.0.1.vio.posn.3.type=signal
unit.0.1.vio.posn.4.channel=18
unit.0.1.vio.posn.4.name=rst
unit.0.1.vio.posn.4.port=1
unit.0.1.vio.posn.4.type=signal
unit.0.1.vio.posn.5.channel=18
unit.0.1.vio.posn.5.name=AsyncOut[18]
unit.0.1.vio.posn.5.port=1
unit.0.1.vio.posn.5.type=signal
unit.0.1.vio.posn.6.channel=18
unit.0.1.vio.posn.6.name=AsyncOut[18]
unit.0.1.vio.posn.6.port=1
unit.0.1.vio.posn.6.type=signal
unit.0.1.vio.posn.7.channel=18
unit.0.1.vio.posn.7.name=AsyncOut[18]
unit.0.1.vio.posn.7.port=1
unit.0.1.vio.posn.7.type=signal
unit.0.1.vio.posn.8.channel=18
unit.0.1.vio.posn.8.name=AsyncOut[18]
unit.0.1.vio.posn.8.port=1
unit.0.1.vio.posn.8.type=signal
unit.0.1.vio.posn.9.channel=18
unit.0.1.vio.posn.9.name=AsyncOut[18]
unit.0.1.vio.posn.9.port=1
unit.0.1.vio.posn.9.type=signal
unit.0.1.vio.readperiod=0
/trunk/hdl/iseProject/iseProject.gise
24,6 → 24,7
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
30,6 → 31,9
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="ipcore_dir/coreILA_readme.txt"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="ipcore_dir/coreVIO_readme.txt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
71,6 → 75,46
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testLcd_controller_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testLcd_controller_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testLcd_controller_isim_beh.wdb"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top_hw_testbench.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="top_hw_testbench.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top_hw_testbench.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top_hw_testbench.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="top_hw_testbench.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="top_hw_testbench.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_hw_testbench.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="top_hw_testbench.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="top_hw_testbench.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="top_hw_testbench.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="top_hw_testbench.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="top_hw_testbench.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="top_hw_testbench.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="top_hw_testbench.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="top_hw_testbench.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="top_hw_testbench.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="top_hw_testbench.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="top_hw_testbench.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="top_hw_testbench.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="top_hw_testbench.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top_hw_testbench.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="top_hw_testbench.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top_hw_testbench.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_hw_testbench_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="top_hw_testbench_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_hw_testbench_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_hw_testbench_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_hw_testbench_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="top_hw_testbench_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_hw_testbench_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_hw_testbench_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="top_hw_testbench_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="top_hw_testbench_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_hw_testbench_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_hw_testbench_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="top_hw_testbench_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="top_hw_testbench_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_hw_testbench_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
78,35 → 122,112
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1337721900" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1337721900">
<transform xil_pn:end_ts="1337725474" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1337725474">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1337721900" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2122166099024610513" xil_pn:start_ts="1337721900">
<transform xil_pn:end_ts="1337725474" xil_pn:in_ck="-1571781140027199433" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1337725474">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="lcd_controller.v"/>
<outfile xil_pn:name="lcd_wishbone_slave.v"/>
<outfile xil_pn:name="testLcd_controller.v"/>
<outfile xil_pn:name="top_hw_testbench.v"/>
</transform>
<transform xil_pn:end_ts="1337721949" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3310231177499090293" xil_pn:start_ts="1337721949">
<transform xil_pn:end_ts="1337725474" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="2836371237087295533" xil_pn:start_ts="1337725474">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337721900" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1337721900">
<transform xil_pn:end_ts="1337725474" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-8989249124739507793" xil_pn:start_ts="1337725474">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337721900" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4015078847939689069" xil_pn:start_ts="1337721900">
<transform xil_pn:end_ts="1337725474" xil_pn:in_ck="-5203437565094583721" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1337690299192448305" xil_pn:start_ts="1337725474">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1337721949" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1337721949">
<transform xil_pn:end_ts="1337725474" xil_pn:in_ck="-1571781140027199433" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1337725474">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="lcd_controller.v"/>
<outfile xil_pn:name="lcd_wishbone_slave.v"/>
<outfile xil_pn:name="testLcd_controller.v"/>
<outfile xil_pn:name="top_hw_testbench.v"/>
</transform>
<transform xil_pn:end_ts="1337721949" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="794791264610146815" xil_pn:start_ts="1337721949">
<transform xil_pn:end_ts="1337725476" xil_pn:in_ck="-5536755233409236506" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6792445466142746427" xil_pn:start_ts="1337725474">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testLcd_controller_beh.prj"/>
<outfile xil_pn:name="testLcd_controller_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1337721955" xil_pn:in_ck="-3373480295076389399" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="5995599997315708924" xil_pn:start_ts="1337721949">
<transform xil_pn:end_ts="1337725476" xil_pn:in_ck="8162874102102850794" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-3767764390934071859" xil_pn:start_ts="1337725476">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testLcd_controller_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1337728079" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1337728079">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1337728079" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3842871176298448887" xil_pn:start_ts="1337728079">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337729185" xil_pn:in_ck="-8399759803742926499" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1337690299192448305" xil_pn:start_ts="1337729185">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/coreICON.ngc"/>
<outfile xil_pn:name="ipcore_dir/coreICON.v"/>
<outfile xil_pn:name="ipcore_dir/coreILA.ngc"/>
<outfile xil_pn:name="ipcore_dir/coreILA.v"/>
<outfile xil_pn:name="ipcore_dir/coreVIO.ngc"/>
<outfile xil_pn:name="ipcore_dir/coreVIO.v"/>
</transform>
<transform xil_pn:end_ts="1337728079" xil_pn:in_ck="6469636052167902378" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1337728079">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337728079" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1895521384966110919" xil_pn:start_ts="1337728079">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337728079" xil_pn:in_ck="6469636052167902378" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1337728079">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337728079" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7913111547471294937" xil_pn:start_ts="1337728079">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337731537" xil_pn:in_ck="4747555295481960126" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-5172275256582554922" xil_pn:start_ts="1337731528">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
113,63 → 234,90
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="lcd_controller.lso"/>
<outfile xil_pn:name="lcd_controller.ngc"/>
<outfile xil_pn:name="lcd_controller.ngr"/>
<outfile xil_pn:name="lcd_controller.prj"/>
<outfile xil_pn:name="lcd_controller.stx"/>
<outfile xil_pn:name="lcd_controller.syr"/>
<outfile xil_pn:name="lcd_controller.xst"/>
<outfile xil_pn:name="lcd_controller_xst.xrpt"/>
<outfile xil_pn:name="top_hw_testbench.lso"/>
<outfile xil_pn:name="top_hw_testbench.ngc"/>
<outfile xil_pn:name="top_hw_testbench.ngr"/>
<outfile xil_pn:name="top_hw_testbench.prj"/>
<outfile xil_pn:name="top_hw_testbench.stx"/>
<outfile xil_pn:name="top_hw_testbench.syr"/>
<outfile xil_pn:name="top_hw_testbench.xst"/>
<outfile xil_pn:name="top_hw_testbench_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1337721906" xil_pn:in_ck="-1193843947586956397" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8935888196922174056" xil_pn:start_ts="1337721906">
<transform xil_pn:end_ts="1337728164" xil_pn:in_ck="-296097539435913693" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4191577380043050738" xil_pn:start_ts="1337728164">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337721959" xil_pn:in_ck="2374925806358312879" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-6398839547613259080" xil_pn:start_ts="1337721955">
<transform xil_pn:end_ts="1337731541" xil_pn:in_ck="-5772489953451663748" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337731537">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="lcd_controller.bld"/>
<outfile xil_pn:name="lcd_controller.ngd"/>
<outfile xil_pn:name="lcd_controller_ngdbuild.xrpt"/>
<outfile xil_pn:name="top_hw_testbench.bld"/>
<outfile xil_pn:name="top_hw_testbench.ngd"/>
<outfile xil_pn:name="top_hw_testbench_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1337721964" xil_pn:in_ck="5266274180289747408" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1337721959">
<transform xil_pn:end_ts="1337731545" xil_pn:in_ck="-7080687810229386214" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1337731541">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="lcd_controller.pcf"/>
<outfile xil_pn:name="lcd_controller_map.map"/>
<outfile xil_pn:name="lcd_controller_map.mrp"/>
<outfile xil_pn:name="lcd_controller_map.ncd"/>
<outfile xil_pn:name="lcd_controller_map.ngm"/>
<outfile xil_pn:name="lcd_controller_map.xrpt"/>
<outfile xil_pn:name="lcd_controller_summary.xml"/>
<outfile xil_pn:name="lcd_controller_usage.xml"/>
<outfile xil_pn:name="top_hw_testbench.pcf"/>
<outfile xil_pn:name="top_hw_testbench_map.map"/>
<outfile xil_pn:name="top_hw_testbench_map.mrp"/>
<outfile xil_pn:name="top_hw_testbench_map.ncd"/>
<outfile xil_pn:name="top_hw_testbench_map.ngm"/>
<outfile xil_pn:name="top_hw_testbench_map.xrpt"/>
<outfile xil_pn:name="top_hw_testbench_summary.xml"/>
<outfile xil_pn:name="top_hw_testbench_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1337721980" xil_pn:in_ck="-9064924434578262903" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1337721964">
<transform xil_pn:end_ts="1337731578" xil_pn:in_ck="6001200367856259123" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1337731545">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="lcd_controller.ncd"/>
<outfile xil_pn:name="lcd_controller.pad"/>
<outfile xil_pn:name="lcd_controller.par"/>
<outfile xil_pn:name="lcd_controller.ptwx"/>
<outfile xil_pn:name="lcd_controller.unroutes"/>
<outfile xil_pn:name="lcd_controller.xpi"/>
<outfile xil_pn:name="lcd_controller_pad.csv"/>
<outfile xil_pn:name="lcd_controller_pad.txt"/>
<outfile xil_pn:name="lcd_controller_par.xrpt"/>
<outfile xil_pn:name="top_hw_testbench.ncd"/>
<outfile xil_pn:name="top_hw_testbench.pad"/>
<outfile xil_pn:name="top_hw_testbench.par"/>
<outfile xil_pn:name="top_hw_testbench.ptwx"/>
<outfile xil_pn:name="top_hw_testbench.unroutes"/>
<outfile xil_pn:name="top_hw_testbench.xpi"/>
<outfile xil_pn:name="top_hw_testbench_pad.csv"/>
<outfile xil_pn:name="top_hw_testbench_pad.txt"/>
<outfile xil_pn:name="top_hw_testbench_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1337721980" xil_pn:in_ck="-7456829704468578100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1337721977">
<transform xil_pn:end_ts="1337731607" xil_pn:in_ck="5725138416503842291" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1337731578">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="top_hw_testbench.bgn"/>
<outfile xil_pn:name="top_hw_testbench.bit"/>
<outfile xil_pn:name="top_hw_testbench.drc"/>
<outfile xil_pn:name="top_hw_testbench.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1337731654" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1337731653">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337731691" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337731690">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337731578" xil_pn:in_ck="-7080687810229386346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1337731575">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="lcd_controller.twr"/>
<outfile xil_pn:name="lcd_controller.twx"/>
<outfile xil_pn:name="top_hw_testbench.twr"/>
<outfile xil_pn:name="top_hw_testbench.twx"/>
</transform>
</transforms>
 
/trunk/hdl/iseProject/iseProject.xise
29,9 → 29,34
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="pins_hardware.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="ipcore_dir/coreVIO.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ipcore_dir/coreICON.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="top_hw_testbench.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="ipcore_dir/coreILA.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="pins_hw_testbench.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/coreVIO.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/coreICON.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/coreILA.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
 
<properties>
154,9 → 179,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|lcd_controller" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="lcd_controller.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/lcd_controller" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|top_hw_testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="top_hw_testbench.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top_hw_testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
220,7 → 245,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="lcd_controller" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="top_hw_testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
235,10 → 260,10
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="lcd_controller_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="lcd_controller_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="lcd_controller_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="lcd_controller_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_hw_testbench_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_hw_testbench_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_hw_testbench_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_hw_testbench_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
289,8 → 314,8
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testLcd_controller" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testLcd_controller" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/coreILA" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.coreILA" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
308,7 → 333,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testLcd_controller" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.coreILA" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
383,7 → 408,7
</properties>
 
<bindings>
<binding xil_pn:location="/lcd_controller" xil_pn:name="pins_hardware.ucf"/>
<binding xil_pn:location="/top_hw_testbench" xil_pn:name="pins_hw_testbench.ucf"/>
</bindings>
 
<libraries/>

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