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URL https://opencores.org/ocsvn/lcd_block/lcd_block/trunk

Subversion Repositories lcd_block

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  • This comparison shows the changes necessary to convert path 
    /lcd_block
    from Rev 12 to Rev 13
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  •

Rev 12 → Rev 13

/trunk/hdl/iseProject/pins_hw_testbench.ucf
1,14 → 1,14
# Pins used by Spartan3E starter Kit
#NET "hw_lcd_e" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_rs" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_rw" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "hw_lcd_e" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "hw_lcd_rs" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "hw_lcd_rw" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# The LCD four-bit data interface is shared with the StrataFlash.
#NET "hw_lcd_nibble<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_nibble<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_nibble<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "hw_lcd_nibble<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "hw_lcd_nibble<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "hw_lcd_nibble<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "hw_lcd_nibble<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "hw_lcd_nibble<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 
#NET "hw_strata_flash_disable" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "hw_strata_flash_disable" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 
#NET "rst" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
/trunk/hdl/iseProject/top_hw_testbench.v
3,12 → 3,12
Top module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
*/
module top_hw_testbench(
input clk/*,
input clk,
output hw_lcd_e,
output hw_lcd_rs,
output hw_lcd_rw,
output [3:0] hw_lcd_nibble,
output hw_strata_flash_disable*/
output hw_strata_flash_disable
);
// Declare some wires to connect the components
67,10 → 67,10
assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
// Send all interest output to outside
/*assign hw_lcd_e = lcd_e;
assign hw_lcd_e = lcd_e;
assign hw_lcd_rs = lcd_rs;
assign hw_lcd_rw = lcd_rw;
assign hw_lcd_nibble = lcd_nibble;
assign hw_strata_flash_disable = disable_flash;*/
assign hw_strata_flash_disable = disable_flash;
 
endmodule
/trunk/hdl/iseProject/iseProject.gise
226,7 → 226,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337733755" xil_pn:in_ck="4747555295481960126" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-5172275256582554922" xil_pn:start_ts="1337733747">
<transform xil_pn:end_ts="1337734081" xil_pn:in_ck="4747555295481960126" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-5172275256582554922" xil_pn:start_ts="1337734072">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
246,11 → 246,11
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1337733755" xil_pn:in_ck="-296097539435913693" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4191577380043050738" xil_pn:start_ts="1337733755">
<transform xil_pn:end_ts="1337734087" xil_pn:in_ck="-296097539435913693" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4191577380043050738" xil_pn:start_ts="1337734087">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337733760" xil_pn:in_ck="-5772489953451663748" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337733755">
<transform xil_pn:end_ts="1337734091" xil_pn:in_ck="-5772489953451663748" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337734087">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
260,7 → 260,7
<outfile xil_pn:name="top_hw_testbench.ngd"/>
<outfile xil_pn:name="top_hw_testbench_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1337733763" xil_pn:in_ck="-7080687810229386214" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1337733760">
<transform xil_pn:end_ts="1337734095" xil_pn:in_ck="-7080687810229386214" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1337734091">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
276,7 → 276,7
<outfile xil_pn:name="top_hw_testbench_summary.xml"/>
<outfile xil_pn:name="top_hw_testbench_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1337733796" xil_pn:in_ck="6001200367856259123" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1337733763">
<transform xil_pn:end_ts="1337734115" xil_pn:in_ck="6001200367856259123" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1337734095">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
291,7 → 291,7
<outfile xil_pn:name="top_hw_testbench_pad.txt"/>
<outfile xil_pn:name="top_hw_testbench_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1337733836" xil_pn:in_ck="5725138416503842291" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1337733805">
<transform xil_pn:end_ts="1337734147" xil_pn:in_ck="5725138416503842291" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1337734118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
307,12 → 307,14
<transform xil_pn:end_ts="1337733856" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1337733855">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1337733889" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337733889">
<transform xil_pn:end_ts="1337734167" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337734166">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337733796" xil_pn:in_ck="-7080687810229386346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1337733794">
<transform xil_pn:end_ts="1337734115" xil_pn:in_ck="-7080687810229386346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1337734112">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

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