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URL https://opencores.org/ocsvn/lcd_block/lcd_block/trunk

Subversion Repositories lcd_block

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  • This comparison shows the changes necessary to convert path 
    /lcd_block
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
11,11 → 11,5
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/lcd_block/hdl/iseProject/lcd_controller.v&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/lcd_block/hdl/iseProject/lcd_wishbone_slave.v&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/lcd_block/hdl/iseProject/testLcd_controller.v&quot; into library work</arg>
</msg>
 
</messages>
 
/trunk/hdl/iseProject/lcd_controller.v
26,14 → 26,25
localparam lcd_init_write_02 = 9;
localparam lcd_init_wait_50us = 10;
localparam lcd_init_strobe = 11;
reg [3:0] lcd_init_states, lcd_init_state_next;
reg [3:0] lcd_init_states, lcd_init_state_next; // Declare two variables of 4 bits to hold the FSM states
reg [19:0] counter_wait_lcd_init;
reg [3:0] counter_wait_strobe_lcd_init;
reg [7:0] counter_wait_strobe_lcd_init;
reg [19:0] time_wait_lcd_init;
reg [3:0] lcd_init_data_out;
reg lcd_init_e_out;
reg [3:0] lcd_init_data_out; // FSM output LCD_DATA
reg lcd_init_e_out; // FSM output LCD_E
reg lcd_init_done;
// States for FSM that send data to LCD
localparam lcd_data_rst = 1;
localparam lcd_data_wait = 2;
localparam lcd_data_wr_nibble_high = 3;
localparam lcd_data_wr_nibble_low = 4;
localparam lcd_data_strobe = 5;
reg [3:0] lcd_data_states, lcd_data_state_next; // Declare two variables of 4 bits to hold the FSM states
reg [3:0] lcd_data_data_out; // FSM output LCD_DATA
reg lcd_data_e_out; // FSM output LCD_E
/*
Initialize LCD...
*/
44,6 → 55,8
lcd_init_states <= lcd_init_rst;
counter_wait_lcd_init <= 0;
counter_wait_strobe_lcd_init <= 0;
lcd_init_e_out <= 0;
lcd_init_done <= 0;
end
else
begin
133,7 → 146,8
begin
time_wait_lcd_init <= 100000; // Wait for 100us
lcd_init_states <= lcd_init_wait;
lcd_init_state_next <= lcd_init_write_02;
lcd_init_state_next <= lcd_init_wait_50us;
lcd_init_done <= 1;
end
endcase;
end;
141,5 → 155,16
assign lcd_e = lcd_init_e_out;
assign lcd_nibble = lcd_init_data_out;
/*
FSM that deals to send data to the LCD (nibble High + nibble Low)
*/
always @ (posedge clk)
begin
if (~lcd_init_done)
begin
end
end;
 
endmodule
/trunk/hdl/iseProject/testLcd_controller.v
32,16 → 32,25
.done(done)
);
 
initial begin
// Create clock
always
begin
#10 clk = ~clk; // Toogle the clock each 10ns (20ns period is 50Mhz)
end
initial
begin
// Initialize Inputs
rst = 0;
$display($time, " << Starting the Simulation >>");
rst = 1;
clk = 0;
data_in = 0;
strobe_in = 0;
period_clk_ns = 0;
period_clk_ns = 20; // Indicate the number of time at each cycle (20 ns in our case)
 
// Wait 100 ns for global reset to finish
#100;
// Wait for one clock cycle to reset
#20;
rst = 0;
// Add stimulus here
 
/trunk/hdl/iseProject/lcd_wishbone_slave_summary.html
73,8 → 73,9
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='E:/lcd_block/hdl/iseProject\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>dom 20. mai 16:05:30 2012</TD></TR>
</TABLE>
 
 
<br><center><b>Date Generated:</b> 05/20/2012 - 02:58:12</center>
<br><center><b>Date Generated:</b> 05/20/2012 - 16:45:26</center>
</BODY></HTML>
/trunk/hdl/iseProject/iseProject.gise
46,11 → 46,11
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1337475576" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1337475576">
<transform xil_pn:end_ts="1337522725" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1337522725">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337475576" xil_pn:in_ck="-5497409596377948253" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1337475576">
<transform xil_pn:end_ts="1337576939" xil_pn:in_ck="-5497409596377948253" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1337576939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="lcd_controller.v"/>
57,19 → 57,19
<outfile xil_pn:name="lcd_wishbone_slave.v"/>
<outfile xil_pn:name="testLcd_controller.v"/>
</transform>
<transform xil_pn:end_ts="1337475576" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="2836371237087295533" xil_pn:start_ts="1337475576">
<transform xil_pn:end_ts="1337522725" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="2836371237087295533" xil_pn:start_ts="1337522725">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337475576" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-2387588251019774503" xil_pn:start_ts="1337475576">
<transform xil_pn:end_ts="1337522725" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-2387588251019774503" xil_pn:start_ts="1337522725">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337475576" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1645243788895470835" xil_pn:start_ts="1337475576">
<transform xil_pn:end_ts="1337522725" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1645243788895470835" xil_pn:start_ts="1337522725">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1337475576" xil_pn:in_ck="-5497409596377948253" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1337475576">
<transform xil_pn:end_ts="1337576939" xil_pn:in_ck="-5497409596377948253" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1337576939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="lcd_controller.v"/>
76,7 → 76,7
<outfile xil_pn:name="lcd_wishbone_slave.v"/>
<outfile xil_pn:name="testLcd_controller.v"/>
</transform>
<transform xil_pn:end_ts="1337475581" xil_pn:in_ck="-5497409596377948253" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-1659802317889134806" xil_pn:start_ts="1337475576">
<transform xil_pn:end_ts="1337576940" xil_pn:in_ck="-5497409596377948253" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-1659802317889134806" xil_pn:start_ts="1337576939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
85,7 → 85,7
<outfile xil_pn:name="testLcd_controller_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1337475581" xil_pn:in_ck="2483329315479921445" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5883582692330391981" xil_pn:start_ts="1337475581">
<transform xil_pn:end_ts="1337576941" xil_pn:in_ck="2483329315479921445" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="2007445876491768972" xil_pn:start_ts="1337576940">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
123,6 → 123,8
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="lcd_controller.lso"/>
<outfile xil_pn:name="lcd_controller.ngc"/>
/trunk/hdl/iseProject/iseProject.xise
277,7 → 277,7
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="10 ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>

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