URL
https://opencores.org/ocsvn/leros/leros/trunk
Subversion Repositories leros
Compare Revisions
- This comparison shows the changes necessary to convert path
/leros/trunk/java/src
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/leros/asm/LerosAsm.java
File deleted
leros/asm/LerosAsm.java
Property changes :
Deleted: svn:eol-style
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\ No newline at end of property
Index: leros/sim/LerosIO.java
===================================================================
--- leros/sim/LerosIO.java (revision 3)
+++ leros/sim/LerosIO.java (nonexistent)
@@ -1,86 +0,0 @@
-/*
- Copyright 2011 Martin Schoeberl ,
- Technical University of Denmark, DTU Informatics.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- The views and conclusions contained in the software and documentation are
- those of the authors and should not be interpreted as representing official
- policies, either expressed or implied, of the copyright holder.
- */
-
-package leros.sim;
-
-import java.io.IOException;
-
-/**
- * Simulation of IO devices connected to Leros. IO mapping is at the moment not
- * the same as in VHDL.
- *
- * @author martin
- *
- */
-public class LerosIO {
-
- final static int UART = 0;
-
- public void write(int addr, int data) {
- switch (addr) {
- case UART+1: // data register
- System.out.print((char) data);
- break;
-
- default:
- System.out.println("IO address " + addr + " not defined");
- break;
- }
- }
-
- public int read(int addr) {
-
- int ret = 0;
- switch (addr) {
- case UART: // status register
- ret = 1;
- try {
- if (System.in.available()!=0) {
- ret |= 2;
- }
- } catch (IOException e) {
- e.printStackTrace();
- }
- break;
- case UART+1: // data registers
- try {
- ret = System.in.read();
- } catch (IOException e) {
- e.printStackTrace();
- }
- break;
- default:
- System.out.println("IO address " + addr + " not defined");
- break;
- }
- return ret;
- }
-}
leros/sim/LerosIO.java
Property changes :
Deleted: svn:eol-style
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\ No newline at end of property
Index: leros/sim/LerosSim.java
===================================================================
--- leros/sim/LerosSim.java (revision 3)
+++ leros/sim/LerosSim.java (nonexistent)
@@ -1,282 +0,0 @@
-/*
- Copyright 2011 Martin Schoeberl ,
- Technical University of Denmark, DTU Informatics.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- The views and conclusions contained in the software and documentation are
- those of the authors and should not be interpreted as representing official
- policies, either expressed or implied, of the copyright holder.
- */
-
-package leros.sim;
-
-import java.io.*;
-
-/**
- * A crude simulation of Leros. Pipeline effects (branch delay slots) are
- * currently ignored.
- *
- * @author Martin Schoeberl
- *
- */
-public class LerosSim {
-
- String fname;
- // no real use of dstDir
- String dstDir = "./";
- String srcDir = "./";
- boolean log;
-
- LerosIO io;
-
- final static int IM_SIZE = 1024;
- final static int DM_SIZE = 1024;
- char im[] = new char[IM_SIZE];
- char dm[] = new char[DM_SIZE];
- int progSize = 0;
-
- public LerosSim(LerosIO io, String[] args) {
-
- this.io = io;
-
- String s = System.getProperty("log");
- if (s != null) {
- log = s.equals("true");
- }
-
- srcDir = System.getProperty("user.dir");
- dstDir = System.getProperty("user.dir");
- processOptions(args);
- if (!srcDir.endsWith(File.separator))
- srcDir += File.separator;
- if (!dstDir.endsWith(File.separator))
- dstDir += File.separator;
-
- BufferedReader instr = null;
- try {
- instr = new BufferedReader(new FileReader(srcDir + fname));
- String l;
- while ((l = instr.readLine()) != null) {
- im[progSize] = (char) Integer.parseInt(l);
- ++progSize;
- }
- System.out.println("Instruction memory " + (progSize * 2)
- + " bytes");
- } catch (IOException e) {
- e.printStackTrace();
- } finally {
- if (instr != null) {
- try {
- instr.close();
- } catch (IOException e) {
- e.printStackTrace();
- }
- }
-
- }
- }
-
- private boolean processOptions(String clist[]) {
- boolean success = true;
-
- for (int i = 0; i < clist.length; i++) {
- if (clist[i].equals("-s")) {
- srcDir = clist[++i];
- } else if (clist[i].equals("-d")) {
- dstDir = clist[++i];
- } else {
- fname = clist[i];
- }
- }
-
- return success;
- }
-
- /**
- * Run the simulation. First instruction is not executed as in the hardware.
- */
- public void simulate() {
-
- int ar, pc, accu;
- int accu_dly, accu_dly1;
-
- pc = 1;
- accu = 0;
- ar = 0;
- accu_dly = accu_dly1 = 0;
-
- for (;;) {
-
- // two cycles delay for branch
- // condition modeling
- // We should model the 'real' pipeline in the simulator...
- accu_dly = accu_dly1;
- accu_dly1 = accu;
-
- int next_pc = pc + 1;
- if (pc >= progSize) {
- return;
- }
- int instr = im[pc];
- int val;
- // immediate value
- if ((instr & 0x0100) != 0) {
- // take o bit from the instruction
- val = instr & 0xff;
- // sign extension to 16 bit
- if ((val & 0x80)!=0) { val |= 0xff00; }
- } else {
- val = dm[instr & 0xff];
- }
-
- switch (instr & 0xfe00) {
- case 0x0000: // nop
- break;
- case 0x0800: // add
- accu += val;
- break;
- case 0x0c00: // sub
- accu -= val;
- break;
- case 0x1000: // shr
- accu >>>= 1;
- break;
- case 0x2000: // load
- accu = val;
- break;
- case 0x2200: // and
- accu &= val;
- break;
- case 0x2400: // or
- accu |= val;
- break;
- case 0x2600: // xor
- accu ^= val;
- break;
- case 0x2800: // loadh
- accu = (accu & 0xff) + (val << 8);
- break;
- case 0x3000: // store
- dm[instr & 0x00ff] = (char) accu;
- break;
- case 0x3800: // out
- io.write(instr & 0xff, accu);
- break;
- case 0x3c00: // in
- accu = io.read(instr & 0xff);
- break;
- case 0x4000: // jal
- dm[instr & 0xff] = (char) (pc+1);
- next_pc = accu_dly;
- break;
- case 0x5000: // loadaddr
- // nop, as it is only available one cycle later
- break;
- case 0x6000: // load indirect
- accu = dm[ar + (instr & 0xff)];
- break;
- case 0x7000: // store indirect
- dm[ar + (instr & 0xff)] = (char) accu;
- break;
- // case 7: // I/O (ld/st indirect)
- // break;
- // case 8: // brl
- // break;
- // case 9: // br conditional
- // break;
- default:
- // branches use the immediate bit for decode
- // TODO: we could change the encoding so it
- // does not 'consume' the immediate bit - would
- // this be simpler (and lead to less HW?)
- switch (instr & 0xff00) {
- case 0x4800: // branch
- // at the moment just 8 bits offset (sign extension)
- next_pc = pc + ((instr << 24) >> 24);
- break;
- case 0x4900: // brz
- if (accu_dly == 0) {
- // at the moment just 8 bits offset (sign extension)
- next_pc = pc + ((instr << 24) >> 24);
- }
- break;
- case 0x4a00: // brnz
- if (accu_dly != 0) {
- // at the moment just 8 bits offset (sign extension)
- next_pc = pc + ((instr << 24) >> 24);
- }
- break;
- case 0x4b00: // brp
- if ((accu_dly & 0x8000) == 0) {
- // at the moment just 8 bits offset (sign extension)
- next_pc = pc + ((instr << 24) >> 24);
- }
- break;
- case 0x4c00: // brn
- if ((accu_dly & 0x8000) != 0) {
- // at the moment just 8 bits offset (sign extension)
- next_pc = pc + ((instr << 24) >> 24);
- }
- break;
-
- default:
- throw new Error("Instruction " + instr + " at address " + pc
- + " not implemented");
- }
- }
-
-
- // keep it in 16 bit
- accu &= 0xffff;
- // the address register is only available for one
- // cycle later
- ar = dm[instr & 0xff];
-
- if (log) {
- System.out.print("PC: " + pc + " accu: " + accu + " "
- + accu_dly + " ar: " + ar + " Mem: ");
- for (int i = 0; i < 16; ++i) {
- System.out.print(((int) dm[i]) + " ");
- }
- System.out.println();
- }
- pc = next_pc;
-
- }
- }
-
- /**
- * @param args
- */
- public static void main(String[] args) {
-
- if (args.length < 1) {
- System.out.println("usage: java LerosSim [-s srcDir] filename");
- System.exit(-1);
- }
- LerosSim ls = new LerosSim(new LerosIO(), args);
- ls.simulate();
- }
-
-}
leros/sim/LerosSim.java
Property changes :
Deleted: svn:eol-style
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\ No newline at end of property
Index: grammar/Leros.g
===================================================================
--- grammar/Leros.g (revision 3)
+++ grammar/Leros.g (nonexistent)
@@ -1,234 +0,0 @@
-/*
- Copyright 2011 Martin Schoeberl ,
- Technical University of Denmark, DTU Informatics.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS
- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
- The views and conclusions contained in the software and documentation are
- those of the authors and should not be interpreted as representing official
- policies, either expressed or implied, of the copyright holder.
- */
-
-//
-// Grammar and lexical rules for the Leros assembler
-// Start with a copy of Patmos
-
-grammar Leros;
-
-@header {
-package leros.asm.generated;
-
-import java.util.HashMap;
-import java.util.List;
-
-}
-
-@lexer::header {package leros.asm.generated;}
-
-
-@members {
-/** Map symbol to Integer object holding the value or address */
-HashMap symbols = new HashMap();
-// Mapping of register names
-HashMap reg = new HashMap();
-int pc = 0;
-int code[];
-boolean pass2 = false;
-
-static {
- // some default names for registers
- for (int i=0; i<16; ++i) {
-// reg.put("r"+i, new Integer(i));
- }
-}
-
-public static String niceHex(int val) {
- String s = Integer.toHexString(val);
- while (s.length() < 4) {
- s = "0"+s;
- }
- s = "0x"+s;
- return s;
-}
-}
-
-pass1: statement+;
-
-dump: {System.out.println(symbols);};
-
-// Don't know how to return a simple int array :-(
-pass2 returns [List mem]
-@init{
- System.out.println(pc+" "+symbols);
- code = new int[pc];
- pc = 0;
- pass2 = true;
-}
- : statement+ {
- $mem = new ArrayList(pc);
- for (int i=0; i255) throw new Error("Wrong register name");};
-
-// at the moment just 8 bit immediate
-// can be signed or unsigned
-imm_val returns [int value]:
- INT {$value = Integer.parseInt($INT.text);
- if ($value<-128 || $value>255) throw new Error("Wrong immediate");} |
- '-' INT {$value = (-Integer.parseInt($INT.text)) & 0xff;
- if ($value<-128 || $value>255) throw new Error("Wrong immediate");} |
- '<' ID
- {
- int val = 0;
- if (pass2) {
- Integer v = (Integer) symbols.get($ID.text);
- if ( v!=null ) {
- val = v.intValue() & 0xff;
- } else {
- throw new Error("Undefined label "+$ID.text);
- }
- }
- $value = val;
- } |
- '>' ID
- {
- int val = 0;
- if (pass2) {
- Integer v = (Integer) symbols.get($ID.text);
- if ( v!=null ) {
- val = (v.intValue()>>8) & 0xff;
- } else {
- throw new Error("Undefined label "+$ID.text);
- }
- }
- $value = val;
- }
- ;
-
-
-
-
-
-
-/* Lexer rules (start with upper case) */
-
-INT : '0'..'9'+ ;
-REG: 'r' INT;
-//SINT: '-'? INT;
-
-ID: ('a'..'z'|'A'..'Z'|'_') ('a'..'z'|'A'..'Z'|'_' | '0'..'9')*;
-
-COMMENT: '//' ~('\n'|'\r')* ;
-
-NEWLINE: '\r'? '\n' ;
-WHITSPACE: (' '|'\t')+ {skip();} ;
-