URL
https://opencores.org/ocsvn/lfsr_randgen/lfsr_randgen/trunk
Subversion Repositories lfsr_randgen
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- This comparison shows the changes necessary to convert path
/lfsr_randgen
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/lfsr_tb.vhd
47,8 → 47,8
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architecture behavior of lfsr_tb is |
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signal width : integer :=8; --change the width value here for a different regsiter width. |
signal clk,set_seed,out_enable : std_logic := '0'; |
constant width : integer :=8; --change the width value here for a different regsiter width. |
signal clk,set_seed : std_logic := '0'; |
signal seed : std_logic_vector(width-1 downto 0) := (0 => '1',others => '0'); |
signal rand_out : std_logic_vector(width-1 downto 0); |
-- clock period definitions |
57,11 → 57,10
begin |
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-- entity instantiation for the lfsr component. |
uut: entity work.lfsr generic map (width => 8) --change the width value here for a different regsiter width. |
uut: entity work.lfsr generic map (width => width) --change the width value here for a different regsiter width. |
PORT MAP ( |
clk => clk, |
set_seed => set_seed, |
out_enable => out_enable, |
seed => seed, |
rand_out => rand_out |
); |
83,7 → 82,6
wait for 1 ns; |
set_seed <= '0'; |
wait for 20 ns; |
out_enable <= '1'; |
wait; |
end process; |
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