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/boards/avnet_s3aeval/Avnet_Sp3A_Eval.ucf
0,0 → 1,178
#***********************************************************************************
#* Project: Avnet Spartan-3A Evaluation Board (XC3S400A-4FTG256C)
#*
#* File Name: Avnet_Sp3A_Eval.ucf
#* Revision: 1.1
#* Date: December 1, 2008
#*
#* Description: Master UCF for the Sp3A Eval board
#*
#************************************************************************************
 
CONFIG VCCAUX = "3.3" ;
 
# Clock Period Constraint, 16 MHz on-board clock
Net CLK_16MHZ TNM_NET = CLK_16MHZ;
TIMESPEC TS_CLK_16MHZ = PERIOD CLK_16MHZ 62.50 ns;
 
# I/O Timing Constraints
OFFSET = IN 10 ns BEFORE CLK_16MHZ;
OFFSET = OUT 10 ns AFTER CLK_16MHZ;
 
 
# I/O Location Constraints
 
# Clocks
NET CLK_12MHZ LOC = N9 | IOSTANDARD = LVCMOS33 ; # CLK_12MHZ
NET CLK_16MHZ LOC = C10 | IOSTANDARD = LVCMOS33 ; # CLK_16MHZ
NET CLK_32KHZ LOC = T7 | IOSTANDARD = LVCMOS33 ; # CLK_32KHZ
 
# Parallel Flash
NET FLASH_A[0] LOC = P16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[0, also D15
NET FLASH_A[1] LOC = N16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[1
NET FLASH_A[2] LOC = L13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[2
NET FLASH_A[3] LOC = K13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[3
NET FLASH_A[4] LOC = M15 | IOSTANDARD = LVCMOS33 ; # FLASH_A[4
NET FLASH_A[5] LOC = M16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[5
NET FLASH_A[6] LOC = L14 | IOSTANDARD = LVCMOS33 ; # FLASH_A[6
NET FLASH_A[7] LOC = L16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[7
NET FLASH_A[8] LOC = J12 | IOSTANDARD = LVCMOS33 ; # FLASH_A[8
NET FLASH_A[9] LOC = J13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[9
NET FLASH_A[10] LOC = G16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[10
NET FLASH_A[11] LOC = F16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[11
NET FLASH_A[12] LOC = H13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[12
NET FLASH_A[13] LOC = G14 | IOSTANDARD = LVCMOS33 ; # FLASH_A[13
NET FLASH_A[14] LOC = E16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[14
NET FLASH_A[15] LOC = F15 | IOSTANDARD = LVCMOS33 ; # FLASH_A[15
NET FLASH_A[16] LOC = G13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[16
NET FLASH_A[17] LOC = F14 | IOSTANDARD = LVCMOS33 ; # FLASH_A[17
NET FLASH_A[18] LOC = E14 | IOSTANDARD = LVCMOS33 ; # FLASH_A[18
NET FLASH_A[19] LOC = F13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[19
NET FLASH_A[20] LOC = D16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[20
NET FLASH_A[21] LOC = D15 | IOSTANDARD = LVCMOS33 ; # FLASH_A[21
NET FLASH_BYTEn LOC = N14 | IOSTANDARD = LVCMOS33 ; # FLASH_BYTE#
NET FLASH_CEn LOC = P15 | IOSTANDARD = LVCMOS33 ; # FLASH_CE#
NET FLASH_D[0] LOC = T14 | IOSTANDARD = LVCMOS33 ; # FLASH_D0
NET FLASH_D[1] LOC = R13 | IOSTANDARD = LVCMOS33 ; # FLASH_D1
NET FLASH_D[2] LOC = T13 | IOSTANDARD = LVCMOS33 ; # FLASH_D2
NET FLASH_D[3] LOC = P12 | IOSTANDARD = LVCMOS33 ; # FLASH_D3
NET FLASH_D[4] LOC = N8 | IOSTANDARD = LVCMOS33 ; # FLASH_D4
NET FLASH_D[5] LOC = P7 | IOSTANDARD = LVCMOS33 ; # FLASH_D5
NET FLASH_D[6] LOC = T6 | IOSTANDARD = LVCMOS33 ; # FLASH_D6
NET FLASH_D[7] LOC = T5 | IOSTANDARD = LVCMOS33 ; # FLASH_D7
NET FLASH_D[8] LOC = P11 | IOSTANDARD = LVCMOS33 ; # FLASH_D8
NET FLASH_D[9] LOC = R3 | IOSTANDARD = LVCMOS33 ; # FLASH_D9
NET FLASH_D[10] LOC = N11 | IOSTANDARD = LVCMOS33 ; # FLASH_D10
NET FLASH_D[11] LOC = N7 | IOSTANDARD = LVCMOS33 ; # FLASH_D11
NET FLASH_D[12] LOC = R5 | IOSTANDARD = LVCMOS33 ; # FLASH_D12
NET FLASH_D[13] LOC = T4 | IOSTANDARD = LVCMOS33 ; # FLASH_D13
NET FLASH_D[14] LOC = P6 | IOSTANDARD = LVCMOS33 ; # FLASH_D14
NET FLASH_OEn LOC = R15 | IOSTANDARD = LVCMOS33 ; # FLASH_OE#
NET FLASH_RESETn LOC = T10 | IOSTANDARD = LVCMOS33 ; # FLASH_RESET#
NET FLASH_RY_BYn LOC = A4 | IOSTANDARD = LVCMOS33 ; # FLASH_RY/BY#
NET FLASH_WEn LOC = N13 | IOSTANDARD = LVCMOS33 ; # FLASH_WE#
 
# Serial flash
NET FPGA_MOSI LOC = P10 | IOSTANDARD = LVCMOS33 ; # NetR53_2
NET FPGA_SPI_SELn LOC = T2 | IOSTANDARD = LVCMOS33 ; # FPGA_SPI_SEL#
NET SF_HOLDn LOC = P13 | IOSTANDARD = LVCMOS33 ; # SF_HOLD#
NET SF_Wn LOC = N12 | IOSTANDARD = LVCMOS33 ; # SF_W#
NET SPI_CLK LOC = R14 | IOSTANDARD = LVCMOS33 ; # SPI_CLK
#NET FLASH_D00 LOC = T14 | IOSTANDARD = LVCMOS33 ; # MISO, shared with parallel flash
 
# User I/O
NET FPGA_RESET LOC = H4 | IOSTANDARD = LVCMOS33 ; # FPGA_RESET
NET FPGA_PUSH_A LOC = K3 | IOSTANDARD = LVCMOS33 ; # FPGA_PUSH_A
NET FPGA_PUSH_B LOC = H5 | IOSTANDARD = LVCMOS33 ; # FPGA_PUSH_B
NET FPGA_PUSH_C LOC = L3 | IOSTANDARD = LVCMOS33 ; # FPGA_PUSH_C
NET LEDS[0] LOC = D14 | IOSTANDARD = LVCMOS33 ; # LED1
NET LEDS[1] LOC = C16 | IOSTANDARD = LVCMOS33 ; # LED2
NET LEDS[2] LOC = C15 | IOSTANDARD = LVCMOS33 ; # LED3
NET LEDS[3] LOC = B15 | IOSTANDARD = LVCMOS33 ; # LED4
 
# I2C
NET IIC_SCL LOC = M14 | IOSTANDARD = LVCMOS33 ; # IIC_SCL
NET IIC_SDA LOC = M13 | IOSTANDARD = LVCMOS33 ; # IIC_SDA
 
# PSoC
NET PSOC_P0_4 LOC = J1 | IOSTANDARD = LVCMOS33 ; # PSOC_P0_4
NET PSOC_P2_1 LOC = F1 | IOSTANDARD = LVCMOS33 ; # PSOC_P2_1
NET PSOC_P2_3 LOC = G2 | IOSTANDARD = LVCMOS33 ; # PSOC_P2_3
NET PSOC_P2_5 LOC = H3 | IOSTANDARD = LVCMOS33 ; # PSOC_P2_5
NET PSOC_P2_7 LOC = H1 | IOSTANDARD = LVCMOS33 ; # PSOC_P2_7
NET PSOC_P4_6 LOC = J2 | IOSTANDARD = LVCMOS33 ; # PSOC_P4_6
NET PSOC_P5_3 LOC = L2 | IOSTANDARD = LVCMOS33 ; # PSOC_P5_3
NET PSOC_P5_4 LOC = M3 | IOSTANDARD = LVCMOS33 ; # PSOC_P5_4
NET PSOC_P5_6 LOC = M4 | IOSTANDARD = LVCMOS33 ; # PSOC_P5_6
NET PSOC_P5_7 LOC = L1 | IOSTANDARD = LVCMOS33 ; # PSOC_P5_7
NET PSOC_P7_0 LOC = N3 | IOSTANDARD = LVCMOS33 ; # PSOC_P7_0
NET PSOC_P7_7 LOC = K16 | IOSTANDARD = LVCMOS33 ; # PSOC_P7_7
 
# UART
# Net names UART_RXD and UART_TXD on the schematic are named in terms of the PSoC connection.
# Net UART_RXD is an output from the FPGA and an input to the PSoC. Connect to FPGA Tx.
# Net UART_TXD is an input to the FPGA and an output from the PSoC. Connect to FPGA Rxx.
NET UART_RXD LOC = B3 | IOSTANDARD = LVCMOS33 ; # UART_RXD
NET UART_TXD LOC = A3 | IOSTANDARD = LVCMOS33 ; # UART_TXD
 
# GPIO
#NET BANK0_IO01 LOC = A14 | IOSTANDARD = LVCMOS33 ; # BANK0_IO1
#NET BANK0_IO02 LOC = C4 | IOSTANDARD = LVCMOS33 ; # BANK0_IO2
#NET BANK0_IO03 LOC = A13 | IOSTANDARD = LVCMOS33 ; # BANK0_IO3
#NET BANK0_IO04 LOC = B14 | IOSTANDARD = LVCMOS33 ; # BANK0_IO4
#NET BANK0_IO05 LOC = C13 | IOSTANDARD = LVCMOS33 ; # BANK0_IO5
#NET BANK0_IO06 LOC = D13 | IOSTANDARD = LVCMOS33 ; # BANK0_IO6
#NET BANK0_IO07 LOC = A12 | IOSTANDARD = LVCMOS33 ; # BANK0_IO7
#NET BANK0_IO08 LOC = C12 | IOSTANDARD = LVCMOS33 ; # BANK0_IO8
#NET BANK0_IO09 LOC = B12 | IOSTANDARD = LVCMOS33 ; # BANK0_IO9
#NET BANK0_IO10 LOC = D11 | IOSTANDARD = LVCMOS33 ; # BANK0_IO10
#NET BANK0_IO11 LOC = A11 | IOSTANDARD = LVCMOS33 ; # BANK0_IO11
#NET BANK0_IO12 LOC = C11 | IOSTANDARD = LVCMOS33 ; # BANK0_IO12
#NET BANK0_IO13 LOC = A10 | IOSTANDARD = LVCMOS33 ; # BANK0_IO13
#NET BANK0_IO14 LOC = D10 | IOSTANDARD = LVCMOS33 ; # BANK0_IO14
#NET BANK0_IO15 LOC = A9 | IOSTANDARD = LVCMOS33 ; # BANK0_IO15
#NET BANK0_IO16 LOC = E10 | IOSTANDARD = LVCMOS33 ; # BANK0_IO16
#NET BANK0_IO17 LOC = C9 | IOSTANDARD = LVCMOS33 ; # BANK0_IO17
#NET BANK0_IO18 LOC = D9 | IOSTANDARD = LVCMOS33 ; # BANK0_IO18
#NET BANK0_IO19 LOC = A8 | IOSTANDARD = LVCMOS33 ; # BANK0_IO19
#NET BANK0_IO20 LOC = C8 | IOSTANDARD = LVCMOS33 ; # BANK0_IO20
#NET BANK0_IO21 LOC = B8 | IOSTANDARD = LVCMOS33 ; # BANK0_IO21
#NET BANK0_IO22 LOC = E7 | IOSTANDARD = LVCMOS33 ; # BANK0_IO22
#NET BANK0_IO23 LOC = A7 | IOSTANDARD = LVCMOS33 ; # BANK0_IO23
#NET BANK0_IO24 LOC = D8 | IOSTANDARD = LVCMOS33 ; # BANK0_IO24
#NET BANK0_IO25 LOC = C7 | IOSTANDARD = LVCMOS33 ; # BANK0_IO25
#NET BANK0_IO26 LOC = D7 | IOSTANDARD = LVCMOS33 ; # BANK0_IO26
#NET BANK0_IO27 LOC = A6 | IOSTANDARD = LVCMOS33 ; # BANK0_IO27
#NET BANK0_IO28 LOC = C6 | IOSTANDARD = LVCMOS33 ; # BANK0_IO28
#NET BANK0_IO29 LOC = B6 | IOSTANDARD = LVCMOS33 ; # BANK0_IO29
#NET BANK0_IO30 LOC = C5 | IOSTANDARD = LVCMOS33 ; # BANK0_IO30
#NET BANK0_IO31 LOC = A5 | IOSTANDARD = LVCMOS33 ; # BANK0_IO31
#NET BANK0_IO32 LOC = B4 | IOSTANDARD = LVCMOS33 ; # BANK0_IO32
#NET BANK1_IO01 LOC = E13 | IOSTANDARD = LVCMOS33 ; # BANK1_IO1
#NET BANK3_IO01 LOC = D3 | IOSTANDARD = LVCMOS33 ; # BANK3_IO1
#NET BANK3_IO02 LOC = D4 | IOSTANDARD = LVCMOS33 ; # BANK3_IO2
 
# Digi Headers
NET DIGI1[0] LOC = R1 | IOSTANDARD = LVCMOS33 ; # DIGI1_0
NET DIGI1[1] LOC = P2 | IOSTANDARD = LVCMOS33 ; # DIGI1_1
NET DIGI1[2] LOC = P1 | IOSTANDARD = LVCMOS33 ; # DIGI1_2
NET DIGI1[3] LOC = N2 | IOSTANDARD = LVCMOS33 ; # DIGI1_3
NET DIGI2[0] LOC = N1 | IOSTANDARD = LVCMOS33 ; # DIGI2_0
NET DIGI2[1] LOC = M1 | IOSTANDARD = LVCMOS33 ; # DIGI2_1
NET DIGI2[2] LOC = K1 | IOSTANDARD = LVCMOS33 ; # DIGI2_2
NET DIGI2[3] LOC = G1 | IOSTANDARD = LVCMOS33 ; # DIGI2_3
 
# Miscellaneous
#NET AWAKE LOC = T11 | IOSTANDARD = LVCMOS33 ; # AWAKE
#NET DOUT LOC = R11 | IOSTANDARD = LVCMOS33 ; # DOUT
#NET FPGA_VS0 LOC = P5 | IOSTANDARD = LVCMOS33 ; # FPGA_VS0
#NET FPGA_VS1 LOC = N6 | IOSTANDARD = LVCMOS33 ; # FPGA_VS1
#NET FPGA_VS2 LOC = T3 | IOSTANDARD = LVCMOS33 ; # FPGA_VS2
 
# Prohibit Special Pins
# CONFIG PROHIBIT = [pin]; # Reserved for [signal]
CONFIG PROHIBIT = T12 ; # FPGA_INIT_B
CONFIG PROHIBIT = D5 ; # FPGA_PUDC
CONFIG PROHIBIT = P4 ; # PSOC_FPGA_M0
CONFIG PROHIBIT = N4 ; # PSOC_FPGA_M1
CONFIG PROHIBIT = R2 ; # PSOC_FPGA_M2
/boards/avnet_s3aeval/syn/light52_s3aeval/light52_s3aeval.xise
0,0 → 1,424
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="../../Avnet_Sp3A_Eval.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../vhdl/s3aeval_soc.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../../vhdl/light52_alu.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../../vhdl/light52_cpu.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../../../vhdl/light52_mcu.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../../vhdl/light52_muldiv.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../../vhdl/light52_pkg.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../../vhdl/light52_timer.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../../vhdl/light52_uart.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../../vhdl/light52_ucode_pkg.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../../test/blinker/obj_code_pkg.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
</files>
 
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="../../vhdl/s3aeval_soc.vhdl" xil_pn:valueState="non-default"/>
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<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="s3aeval_soc" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="s3aeval_soc_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="s3aeval_soc_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
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<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
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<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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</properties>
 
<bindings/>
 
<libraries/>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
 
</project>
/boards/avnet_s3aeval/readme.txt
0,0 → 1,12
 
Support files common to all the demos that run on the Spartan-3A Evaluation Kit
from Avnet, and use the vhdl SoC.
 
An ISE WebPack 14 project file is included in the /syn/light52_s3aeval
directory. This project uses the object code from the 'Blinker' demo to
initialize the XCODE ROM.
Upon reset, you should see LEDs D2..D5 counting seconds.
 
A constraints file with all the pin definitions for the board is included
(Avnet_Sp3A_Eval.ucf) that can be used from Xilinx' ISE WebPack, in case the
supplied project file is not used.
/boards/avnet_s3aeval/vhdl/s3aeval_soc.vhdl
0,0 → 1,157
--##############################################################################
-- light52 MCU demo on Avnet's Spartan-3A Evaluation Kit board.
--##############################################################################
--
-- This is a minimal demo of the light52 core targetting Avnet's Spartan-3A
-- Evaluation Kit board for Xilinx Spartan-3A FPGAs.
-- This file is strictly for trial purposes and has not been tested.
--
-- This demo has been built from a generic template for designs targetting the
-- same development board. The entity defines all the inputs and outputs present
-- in the actual board, whether or not they are used in the design at hand.
--##############################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
-- Define the entity outputs as they are connected in the DE-1 development
-- board. Many of the outputs will be left unused in this demo.
entity s3aeval_soc is
port (
-- ***** Clocks
CLK_12MHZ : in std_logic;
CLK_16MHZ : in std_logic;
CLK_32KHZ : in std_logic;
 
-- ***** Parallel Flash 4MB
FLASH_A : out std_logic_vector(21 downto 0);
FLASH_D : inout std_logic_vector(15 downto 0);
FLASH_BYTEn : out std_logic;
FLASH_CEn : out std_logic;
FLASH_OEn : out std_logic;
FLASH_RESETn : out std_logic;
FLASH_RY_BYn : out std_logic;
FLASH_WEn : out std_logic;
-- ***** Serial flash
FPGA_MOSI : in std_logic;
FPGA_SPI_SELn : in std_logic;
SF_HOLDn : in std_logic;
SF_Wn : in std_logic;
SPI_CLK : in std_logic;
--FLASH_D00 : inout std_logic;
 
-- ***** User I/O
FPGA_RESET : in std_logic;
FPGA_PUSH_A : in std_logic;
FPGA_PUSH_B : in std_logic;
FPGA_PUSH_C : in std_logic;
LEDS : out std_logic_vector(3 downto 0);
 
-- ***** I2C
IIC_SCL : in std_logic;
IIC_SDA : in std_logic;
 
-- ***** PSoC
PSOC_P0_4 : in std_logic;
PSOC_P2_1 : in std_logic;
PSOC_P2_3 : in std_logic;
PSOC_P2_5 : in std_logic;
PSOC_P2_7 : in std_logic;
PSOC_P4_6 : in std_logic;
PSOC_P5_3 : in std_logic;
PSOC_P5_4 : in std_logic;
PSOC_P5_6 : in std_logic;
PSOC_P5_7 : in std_logic;
PSOC_P7_0 : in std_logic;
PSOC_P7_7 : in std_logic;
 
-- ***** RS-232
uart_rxd : in std_logic;
uart_txd : out std_logic;
 
-- ***** Digi Headers
DIGI1 : inout std_logic_vector(3 downto 0);
DIGI2 : inout std_logic_vector(3 downto 0);
 
-- ***** GPIO
BANK0_IO : inout std_logic_vector(32 downto 1);
BANK1_IO : inout std_logic_vector(1 downto 1);
BANK2_IO : inout std_logic_vector(2 downto 1)
);
end s3aeval_soc;
 
architecture minimal of s3aeval_soc is
 
-- light52 MCU signals ---------------------------------------------------------
signal p0_out : std_logic_vector(7 downto 0);
signal p1_out : std_logic_vector(7 downto 0);
signal p2_in : std_logic_vector(7 downto 0);
signal p3_in : std_logic_vector(7 downto 0);
signal external_irq : std_logic_vector(7 downto 0);
signal reset : std_logic;
signal clk : std_logic;
 
 
begin
 
-- The clock comes from the on-board oscillator. We need no speed so we
-- won't instantiate a DCM.
clk <= clk_16MHz;
 
-- SOC instantiation
mcu: entity work.light52_mcu
generic map (
-- Memory size is defined in package obj_code_pkg...
CODE_ROM_SIZE => work.obj_code_pkg.XCODE_SIZE,
XDATA_RAM_SIZE => work.obj_code_pkg.XDATA_SIZE,
-- ...as is the object code initialization constant.
OBJ_CODE => work.obj_code_pkg.object_code,
-- Leave BCD opcodes disabled.
IMPLEMENT_BCD_INSTRUCTIONS => true,
-- UART baud rate isn't programmable in run time.
UART_HARDWIRED => true,
-- We're using the 16MHz clock of the Avnet S3A board.
CLOCK_RATE => 16e6
)
port map (
clk => clk,
reset => reset,
txd => uart_txd,
rxd => uart_rxd,
external_irq => external_irq,
p0_out => p0_out,
p1_out => p1_out,
p2_in => p2_in,
p3_in => p3_in
);
 
-- The CPU reset input will be wired straight to the PSoC-controlled
-- capacitive button labelled 'reset'. This is a recipe for faulty resets
-- but it will do for the first quick tests.
reset <= FPGA_RESET;
p2_in <= "00000" & FPGA_PUSH_C & FPGA_PUSH_B & FPGA_PUSH_A;
p3_in <= p1_out;
LEDS <= p1_out(3 downto 0);
 
-- The parallel flash is not used so leave its interface inactive.
FLASH_A <= (others => '0');
FLASH_D <= (others => 'Z');
FLASH_BYTEn <= '1';
FLASH_CEn <= '1';
FLASH_OEn <= '1';
FLASH_RESETn <= '1';
FLASH_RY_BYn <= '1';
FLASH_WEn <= '1';
 
-- FIXME he board has some other peripheral devices which are not accounted
-- for; there will be plenty of warnings.
end minimal;

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