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https://opencores.org/ocsvn/light8080/light8080/trunk
Subversion Repositories light8080
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- This comparison shows the changes necessary to convert path
/light8080/trunk/verilog/syn/xilinx_s3
- from Rev 65 to Rev 66
- ↔ Reverse comparison
Rev 65 → Rev 66
/xilinx_s3.xise
38,6 → 38,10
<file xil_pn:name="l80soc.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="../../rtl/intr_ctrl.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
</files> |
|
<properties> |
/l80soc_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>xilinx_s3 Project Status (02/21/2012 - 11:58:43)</B></TD></TR> |
<TD ALIGN=CENTER COLSPAN='4'><B>xilinx_s3 Project Status (03/03/2012 - 19:50:25)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>xilinx_s3.ise</TD> |
20,7 → 20,7
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc3s200-4ft256</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs'>33 Warnings</A></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs'>26 Warnings</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.4</TD> |
51,43 → 51,43
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD> |
<TD ALIGN=RIGHT>211</TD> |
<TD ALIGN=RIGHT>233</TD> |
<TD ALIGN=RIGHT>3,840</TD> |
<TD ALIGN=RIGHT>5%</TD> |
<TD ALIGN=RIGHT>6%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD> |
<TD ALIGN=RIGHT>327</TD> |
<TD ALIGN=RIGHT>377</TD> |
<TD ALIGN=RIGHT>3,840</TD> |
<TD ALIGN=RIGHT>8%</TD> |
<TD ALIGN=RIGHT>9%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> |
<TD ALIGN=RIGHT>223</TD> |
<TD ALIGN=RIGHT>253</TD> |
<TD ALIGN=RIGHT>1,920</TD> |
<TD ALIGN=RIGHT>11%</TD> |
<TD ALIGN=RIGHT>13%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD> |
<TD ALIGN=RIGHT>223</TD> |
<TD ALIGN=RIGHT>223</TD> |
<TD ALIGN=RIGHT>253</TD> |
<TD ALIGN=RIGHT>253</TD> |
<TD ALIGN=RIGHT>100%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>223</TD> |
<TD ALIGN=RIGHT>253</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number of 4 input LUTs</B></TD> |
<TD ALIGN=RIGHT>328</TD> |
<TD ALIGN=RIGHT>378</TD> |
<TD ALIGN=RIGHT>3,840</TD> |
<TD ALIGN=RIGHT>8%</TD> |
<TD ALIGN=RIGHT>9%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> |
<TD ALIGN=RIGHT>311</TD> |
<TD ALIGN=RIGHT>361</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
105,9 → 105,9
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
<TD ALIGN=RIGHT>20</TD> |
<TD ALIGN=RIGHT>24</TD> |
<TD ALIGN=RIGHT>173</TD> |
<TD ALIGN=RIGHT>11%</TD> |
<TD ALIGN=RIGHT>13%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16s</TD> |
123,7 → 123,7
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> |
<TD ALIGN=RIGHT>3.29</TD> |
<TD ALIGN=RIGHT>3.36</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
160,12 → 160,12
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:54:55 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>31 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>6 Infos</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:21 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:29 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:40 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:01 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>24 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>9 Infos</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:06 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:13 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:23 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:43 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:25 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
174,5 → 174,5
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 02/21/2012 - 11:58:43</center> |
<br><center><b>Date Generated:</b> 03/03/2012 - 19:50:25</center> |
</BODY></HTML> |