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URL https://opencores.org/ocsvn/light8080/light8080/trunk

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    /light8080/trunk/verilog
    from Rev 65 to Rev 66
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Rev 65 → Rev 66

/bench/tb_l80soc.v
35,7 → 35,6
// the following define selects between CPU instruction trace and uart transmitted bytes
//`define CPU_TRACE 1
 
 
//---------------------------------------------------------------------------------------
// internal signals
reg clock; // global clock
44,6 → 43,8
// UUT interfaces
wire rxd, txd;
wire [7:0] p1dio, p2dio;
wire [3:0] extint;
reg sp1dio0;
 
//---------------------------------------------------------------------------------------
// test bench implementation
93,7 → 94,8
.txd(txd),
.rxd(rxd),
.p1dio(p1dio),
.p2dio(p2dio)
.p2dio(p2dio),
.extint(extint)
);
 
//------------------------------------------------------------------
100,6 → 102,24
// uart receive is not used in this test becnch
assign rxd = 1'b1;
 
// external interrupt 0 is connected to the p1dio[0] rising edge
assign extint[3:1] = 3'b0;
assign extint[0] = ((sp1dio0 == 1'b0) && (p1dio[0] == 1'b1)) ? 1'b1 : 1'b0;
 
// p1dio[0] rising edge detection
always @ (posedge reset or posedge clock)
begin
if (reset)
sp1dio0 <= 1'b0;
else if (p1dio[0] == 1'b1)
sp1dio0 <= 1'b1;
else
sp1dio0 <= 1'b0;
end
 
//------------------------------------------------------------------
// test bench output log selection - either simple CPU trace or UART
// transmit port log
`ifdef CPU_TRACE
// display executed instructions
reg [15:0] saddr;
/rtl/intr_ctrl.v
0,0 → 1,171
//---------------------------------------------------------------------------------------
// Project: light8080 SOC WiCores Solutions
//
// File name: intr_ctrl.v (March 02, 2012)
//
// Writer: Moti Litochevski
//
// Description:
// This file contains the light8080 SOC interrupt controller. The controller
// supports 4 external interrupt requests with fixed interrupt vector addresses.
// The interrupt vectors code is implemented in the "intr_vec.h" file included in
// the projects C directory.
// Note that the controller clears the interrupt request after the CPU read the
// interrupt vector.
//
// Revision History:
//
// Rev <revnumber> <Date> <owner>
// <comment>
//
//---------------------------------------------------------------------------------------
//
// Copyright (C) 2012 Moti Litochevski
//
// This source file may be used and distributed without restriction provided that this
// copyright statement is not removed from the file and that any derivative work
// contains the original copyright notice and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
// FITNESS FOR A PARTICULAR PURPOSE.
//
//---------------------------------------------------------------------------------------
 
module intr_ctrl
(
clock, reset,
ext_intr, cpu_intr,
cpu_inte, cpu_inta,
cpu_rd, cpu_inst,
intr_ena
);
//---------------------------------------------------------------------------------------
// module interfaces
// global signals
input clock; // global clock input
input reset; // global reset input
// external interrupt sources
// least significant bit has the highest priority, most significant bit has the lowest
// priority.
input [3:0] ext_intr; // active high
// CPU interface
output cpu_intr; // CPU interrupt request
input cpu_inte; // CPU interrupt enable - just to mask
input cpu_inta; // CPU interrupt acknowledge
input cpu_rd; // CPU read signal
output [7:0] cpu_inst; // interrupt calling instruction
 
// interrupt enable register
input [3:0] intr_ena; // set high to enable respective interrupt
 
//---------------------------------------------------------------------------------------
// 8080 assembly code constants
// call instruction opcode used to call interrupt routine
`define CALL_INST 8'hcd
// interrupt vectors fixed addresses - high address byte is 0
`define INT0_VEC 8'h08
`define INT1_VEC 8'h18
`define INT2_VEC 8'h28
`define INT3_VEC 8'h38
 
//---------------------------------------------------------------------------------------
// internal declarations
// registered output
reg [7:0] cpu_inst;
 
// internals
reg [1:0] intSq, intSel;
reg [3:0] act_int, int_clr;
reg [7:0] int_vec;
 
//---------------------------------------------------------------------------------------
// module implementation
// main interrupt controller control process
always @ (posedge reset or posedge clock)
begin
if (reset)
begin
intSq <= 2'b0;
intSel <= 2'b0;
cpu_inst <= 8'b0;
end
else
begin
// interrupt controller state machine
case (intSq)
2'd0: // idle state - wait for active interrupt
if ((act_int != 4'b0) && cpu_inte)
begin
// latch the index of the active interrupt according to priority
if (act_int[0]) intSel <= 2'd0;
else if (act_int[2]) intSel <= 2'd1;
else if (act_int[3]) intSel <= 2'd2;
else intSel <= 2'd3;
// switch to next state
intSq <= 2'd1;
end
default: // all other states increment the state register on inta read
if (cpu_inta && cpu_rd)
begin
// update state
intSq <= intSq + 1;
// update instruction opcode for each byte read during inta
case (intSq)
2'd1: cpu_inst <= `CALL_INST;
2'd2: cpu_inst <= int_vec;
default: cpu_inst <= 8'd0;
endcase
end
else if (!cpu_inta)
begin
intSq <= 2'd0;
cpu_inst <= 8'd0;
end
endcase
end
end
 
// assign interrupt vector address according to selected interrupt
always @ (intSel)
begin
case (intSel)
2'd0: int_vec <= `INT0_VEC;
2'd1: int_vec <= `INT1_VEC;
2'd2: int_vec <= `INT2_VEC;
2'd3: int_vec <= `INT3_VEC;
endcase
end
 
// latch active interrupt on rising edge
always @ (posedge reset or posedge clock)
begin
if (reset)
act_int <= 4'b0;
else
act_int <= (act_int & ~int_clr) | (ext_intr & intr_ena);
end
// CPU interrupt is asserted when at least one interrupt is active
assign cpu_intr = |act_int;
 
// clear serviced interrupt
always @ (cpu_inta or cpu_rd or intSq or intSel)
begin
if (cpu_inta && cpu_rd && (intSq == 2'd3))
begin
case (intSel)
2'd0: int_clr <= 4'b0001;
2'd1: int_clr <= 4'b0010;
2'd2: int_clr <= 4'b0100;
2'd3: int_clr <= 4'b1000;
endcase
end
else
int_clr <= 4'b0;
end
 
endmodule
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
/rtl/ram_image.v
21,274 → 21,274
initial
begin
ram[0] = 8'h21; ram[1] = 8'h00; ram[2] = 8'h0c; ram[3] = 8'hf9;
ram[4] = 8'hcd; ram[5] = 8'he3; ram[6] = 8'h02; ram[7] = 8'h7e;
ram[8] = 8'h6f; ram[9] = 8'h07; ram[10] = 8'h9f; ram[11] = 8'h67;
ram[12] = 8'hc9; ram[13] = 8'h7e; ram[14] = 8'h23; ram[15] = 8'h66;
ram[16] = 8'h6f; ram[17] = 8'hc9; ram[18] = 8'h7d; ram[19] = 8'h12;
ram[20] = 8'hc9; ram[21] = 8'h7d; ram[22] = 8'h12; ram[23] = 8'h13;
ram[24] = 8'h7c; ram[25] = 8'h12; ram[26] = 8'hc9; ram[27] = 8'h7d;
ram[28] = 8'hb3; ram[29] = 8'h6f; ram[30] = 8'h7c; ram[31] = 8'hb2;
ram[32] = 8'h67; ram[33] = 8'hc9; ram[34] = 8'h7d; ram[35] = 8'hab;
ram[36] = 8'h6f; ram[37] = 8'h7c; ram[38] = 8'haa; ram[39] = 8'h67;
ram[40] = 8'hc9; ram[41] = 8'h7d; ram[42] = 8'ha3; ram[43] = 8'h6f;
ram[44] = 8'h7c; ram[45] = 8'ha2; ram[46] = 8'h67; ram[47] = 8'hc9;
ram[48] = 8'hcd; ram[49] = 8'h56; ram[50] = 8'h00; ram[51] = 8'hc8;
ram[52] = 8'h2b; ram[53] = 8'hc9; ram[54] = 8'hcd; ram[55] = 8'h56;
ram[56] = 8'h00; ram[57] = 8'hc0; ram[58] = 8'h2b; ram[59] = 8'hc9;
ram[60] = 8'heb; ram[61] = 8'hcd; ram[62] = 8'h56; ram[63] = 8'h00;
ram[64] = 8'hd8; ram[65] = 8'h2b; ram[66] = 8'hc9; ram[67] = 8'hcd;
ram[68] = 8'h56; ram[69] = 8'h00; ram[70] = 8'hc8; ram[71] = 8'hd8;
ram[72] = 8'h2b; ram[73] = 8'hc9; ram[74] = 8'hcd; ram[75] = 8'h56;
ram[76] = 8'h00; ram[77] = 8'hd0; ram[78] = 8'h2b; ram[79] = 8'hc9;
ram[80] = 8'hcd; ram[81] = 8'h56; ram[82] = 8'h00; ram[83] = 8'hd8;
ram[84] = 8'h2b; ram[85] = 8'hc9; ram[86] = 8'h7b; ram[87] = 8'h95;
ram[88] = 8'h5f; ram[89] = 8'h7a; ram[90] = 8'h9c; ram[91] = 8'h21;
ram[92] = 8'h01; ram[93] = 8'h00; ram[94] = 8'hfa; ram[95] = 8'h63;
ram[96] = 8'h00; ram[97] = 8'hb3; ram[98] = 8'hc9; ram[99] = 8'hb3;
ram[100] = 8'h37; ram[101] = 8'hc9; ram[102] = 8'hcd; ram[103] = 8'h80;
ram[104] = 8'h00; ram[105] = 8'hd0; ram[106] = 8'h2b; ram[107] = 8'hc9;
ram[108] = 8'hcd; ram[109] = 8'h80; ram[110] = 8'h00; ram[111] = 8'hd8;
ram[112] = 8'h2b; ram[113] = 8'hc9; ram[114] = 8'heb; ram[115] = 8'hcd;
ram[116] = 8'h80; ram[117] = 8'h00; ram[118] = 8'hd8; ram[119] = 8'h2b;
ram[120] = 8'hc9; ram[121] = 8'hcd; ram[122] = 8'h80; ram[123] = 8'h00;
ram[124] = 8'hc8; ram[125] = 8'hd8; ram[126] = 8'h2b; ram[127] = 8'hc9;
ram[128] = 8'h7a; ram[129] = 8'hbc; ram[130] = 8'hc2; ram[131] = 8'h87;
ram[132] = 8'h00; ram[133] = 8'h7b; ram[134] = 8'hbd; ram[135] = 8'h21;
ram[136] = 8'h01; ram[137] = 8'h00; ram[138] = 8'hc9; ram[139] = 8'heb;
ram[140] = 8'h7c; ram[141] = 8'h17; ram[142] = 8'h7c; ram[143] = 8'h1f;
ram[144] = 8'h67; ram[145] = 8'h7d; ram[146] = 8'h1f; ram[147] = 8'h6f;
ram[148] = 8'h1d; ram[149] = 8'hc2; ram[150] = 8'h8c; ram[151] = 8'h00;
ram[152] = 8'hc9; ram[153] = 8'heb; ram[154] = 8'h29; ram[155] = 8'h1d;
ram[156] = 8'hc2; ram[157] = 8'h9a; ram[158] = 8'h00; ram[159] = 8'hc9;
ram[160] = 8'h7b; ram[161] = 8'h95; ram[162] = 8'h6f; ram[163] = 8'h7a;
ram[164] = 8'h9c; ram[165] = 8'h67; ram[166] = 8'hc9; ram[167] = 8'hcd;
ram[168] = 8'hac; ram[169] = 8'h00; ram[170] = 8'h23; ram[171] = 8'hc9;
ram[172] = 8'h7c; ram[173] = 8'h2f; ram[174] = 8'h67; ram[175] = 8'h7d;
ram[176] = 8'h2f; ram[177] = 8'h6f; ram[178] = 8'hc9; ram[179] = 8'h44;
ram[180] = 8'h4d; ram[181] = 8'h21; ram[182] = 8'h00; ram[183] = 8'h00;
ram[184] = 8'h79; ram[185] = 8'h0f; ram[186] = 8'hd2; ram[187] = 8'hbe;
ram[188] = 8'h00; ram[189] = 8'h19; ram[190] = 8'haf; ram[191] = 8'h78;
ram[192] = 8'h1f; ram[193] = 8'h47; ram[194] = 8'h79; ram[195] = 8'h1f;
ram[196] = 8'h4f; ram[197] = 8'hb0; ram[198] = 8'hc8; ram[199] = 8'haf;
ram[200] = 8'h7b; ram[201] = 8'h17; ram[202] = 8'h5f; ram[203] = 8'h7a;
ram[204] = 8'h17; ram[205] = 8'h57; ram[206] = 8'hb3; ram[207] = 8'hc8;
ram[208] = 8'hc3; ram[209] = 8'hb8; ram[210] = 8'h00; ram[211] = 8'h44;
ram[212] = 8'h4d; ram[213] = 8'h7a; ram[214] = 8'ha8; ram[215] = 8'hf5;
ram[216] = 8'h7a; ram[217] = 8'hb7; ram[218] = 8'hfc; ram[219] = 8'h14;
ram[220] = 8'h01; ram[221] = 8'h78; ram[222] = 8'hb7; ram[223] = 8'hfc;
ram[224] = 8'h1c; ram[225] = 8'h01; ram[226] = 8'h3e; ram[227] = 8'h10;
ram[228] = 8'hf5; ram[229] = 8'heb; ram[230] = 8'h11; ram[231] = 8'h00;
ram[232] = 8'h00; ram[233] = 8'h29; ram[234] = 8'hcd; ram[235] = 8'h24;
ram[236] = 8'h01; ram[237] = 8'hca; ram[238] = 8'h00; ram[239] = 8'h01;
ram[240] = 8'hcd; ram[241] = 8'h2c; ram[242] = 8'h01; ram[243] = 8'hfa;
ram[244] = 8'h00; ram[245] = 8'h01; ram[246] = 8'h7d; ram[247] = 8'hf6;
ram[248] = 8'h01; ram[249] = 8'h6f; ram[250] = 8'h7b; ram[251] = 8'h91;
ram[252] = 8'h5f; ram[253] = 8'h7a; ram[254] = 8'h98; ram[255] = 8'h57;
ram[256] = 8'hf1; ram[257] = 8'h3d; ram[258] = 8'hca; ram[259] = 8'h09;
ram[260] = 8'h01; ram[261] = 8'hf5; ram[262] = 8'hc3; ram[263] = 8'he9;
ram[264] = 8'h00; ram[265] = 8'hf1; ram[266] = 8'hf0; ram[267] = 8'hcd;
ram[268] = 8'h14; ram[269] = 8'h01; ram[270] = 8'heb; ram[271] = 8'hcd;
ram[272] = 8'h14; ram[273] = 8'h01; ram[274] = 8'heb; ram[275] = 8'hc9;
ram[276] = 8'h7a; ram[277] = 8'h2f; ram[278] = 8'h57; ram[279] = 8'h7b;
ram[280] = 8'h2f; ram[281] = 8'h5f; ram[282] = 8'h13; ram[283] = 8'hc9;
ram[284] = 8'h78; ram[285] = 8'h2f; ram[286] = 8'h47; ram[287] = 8'h79;
ram[288] = 8'h2f; ram[289] = 8'h4f; ram[290] = 8'h03; ram[291] = 8'hc9;
ram[292] = 8'h7b; ram[293] = 8'h17; ram[294] = 8'h5f; ram[295] = 8'h7a;
ram[296] = 8'h17; ram[297] = 8'h57; ram[298] = 8'hb3; ram[299] = 8'hc9;
ram[300] = 8'h7b; ram[301] = 8'h91; ram[302] = 8'h7a; ram[303] = 8'h98;
ram[304] = 8'hc9; ram[305] = 8'hdb; ram[306] = 8'h83; ram[307] = 8'hcf;
ram[308] = 8'he5; ram[309] = 8'h21; ram[310] = 8'h01; ram[311] = 8'h00;
ram[312] = 8'hd1; ram[313] = 8'hcd; ram[314] = 8'h29; ram[315] = 8'h00;
ram[316] = 8'h7c; ram[317] = 8'hb5; ram[318] = 8'hca; ram[319] = 8'h44;
ram[320] = 8'h01; ram[321] = 8'hc3; ram[322] = 8'h31; ram[323] = 8'h01;
ram[324] = 8'h21; ram[325] = 8'h02; ram[326] = 8'h00; ram[327] = 8'h39;
ram[328] = 8'hcd; ram[329] = 8'h07; ram[330] = 8'h00; ram[331] = 8'h7d;
ram[332] = 8'hd3; ram[333] = 8'h80; ram[334] = 8'hc9; ram[335] = 8'hdb;
ram[336] = 8'h83; ram[337] = 8'hcf; ram[338] = 8'he5; ram[339] = 8'h21;
ram[340] = 8'h10; ram[341] = 8'h00; ram[342] = 8'hd1; ram[343] = 8'hcd;
ram[344] = 8'h29; ram[345] = 8'h00; ram[346] = 8'h7c; ram[347] = 8'hb5;
ram[348] = 8'hca; ram[349] = 8'h6d; ram[350] = 8'h01; ram[351] = 8'hdb;
ram[352] = 8'h80; ram[353] = 8'hcf; ram[354] = 8'h7d; ram[355] = 8'h32;
ram[356] = 8'h9e; ram[357] = 8'h03; ram[358] = 8'h21; ram[359] = 8'h01;
ram[360] = 8'h00; ram[361] = 8'hc9; ram[362] = 8'hc3; ram[363] = 8'h71;
ram[364] = 8'h01; ram[365] = 8'h21; ram[366] = 8'h00; ram[367] = 8'h00;
ram[368] = 8'hc9; ram[369] = 8'hc9; ram[370] = 8'h21; ram[371] = 8'h0d;
ram[372] = 8'h00; ram[373] = 8'he5; ram[374] = 8'hcd; ram[375] = 8'h31;
ram[376] = 8'h01; ram[377] = 8'hc1; ram[378] = 8'h21; ram[379] = 8'h0a;
ram[380] = 8'h00; ram[381] = 8'he5; ram[382] = 8'hcd; ram[383] = 8'h31;
ram[384] = 8'h01; ram[385] = 8'hc1; ram[386] = 8'hc9; ram[387] = 8'h21;
ram[388] = 8'h02; ram[389] = 8'h00; ram[390] = 8'h39; ram[391] = 8'hcd;
ram[392] = 8'h0d; ram[393] = 8'h00; ram[394] = 8'hcd; ram[395] = 8'h07;
ram[396] = 8'h00; ram[397] = 8'he5; ram[398] = 8'h21; ram[399] = 8'h00;
ram[400] = 8'h00; ram[401] = 8'hd1; ram[402] = 8'hcd; ram[403] = 8'h36;
ram[404] = 8'h00; ram[405] = 8'h7c; ram[406] = 8'hb5; ram[407] = 8'hca;
ram[408] = 8'hb3; ram[409] = 8'h01; ram[410] = 8'h21; ram[411] = 8'h02;
ram[412] = 8'h00; ram[413] = 8'h39; ram[414] = 8'he5; ram[415] = 8'hcd;
ram[416] = 8'h0d; ram[417] = 8'h00; ram[418] = 8'h23; ram[419] = 8'hd1;
ram[420] = 8'hcd; ram[421] = 8'h15; ram[422] = 8'h00; ram[423] = 8'h2b;
ram[424] = 8'hcd; ram[425] = 8'h07; ram[426] = 8'h00; ram[427] = 8'he5;
ram[428] = 8'hcd; ram[429] = 8'h31; ram[430] = 8'h01; ram[431] = 8'hc1;
ram[432] = 8'hc3; ram[433] = 8'h83; ram[434] = 8'h01; ram[435] = 8'hc9;
ram[436] = 8'h21; ram[437] = 8'h02; ram[438] = 8'h00; ram[439] = 8'h39;
ram[440] = 8'hcd; ram[441] = 8'h0d; ram[442] = 8'h00; ram[443] = 8'he5;
ram[444] = 8'h21; ram[445] = 8'h00; ram[446] = 8'h00; ram[447] = 8'hd1;
ram[448] = 8'hcd; ram[449] = 8'h50; ram[450] = 8'h00; ram[451] = 8'h7c;
ram[452] = 8'hb5; ram[453] = 8'hca; ram[454] = 8'he3; ram[455] = 8'h01;
ram[456] = 8'h21; ram[457] = 8'h2d; ram[458] = 8'h00; ram[459] = 8'he5;
ram[460] = 8'hcd; ram[461] = 8'h31; ram[462] = 8'h01; ram[463] = 8'hc1;
ram[464] = 8'h21; ram[465] = 8'h02; ram[466] = 8'h00; ram[467] = 8'h39;
ram[468] = 8'he5; ram[469] = 8'h21; ram[470] = 8'h04; ram[471] = 8'h00;
ram[472] = 8'h39; ram[473] = 8'hcd; ram[474] = 8'h0d; ram[475] = 8'h00;
ram[476] = 8'hcd; ram[477] = 8'ha7; ram[478] = 8'h00; ram[479] = 8'hd1;
ram[480] = 8'hcd; ram[481] = 8'h15; ram[482] = 8'h00; ram[483] = 8'h21;
ram[484] = 8'h02; ram[485] = 8'h00; ram[486] = 8'h39; ram[487] = 8'hcd;
ram[488] = 8'h0d; ram[489] = 8'h00; ram[490] = 8'he5; ram[491] = 8'hcd;
ram[492] = 8'hf0; ram[493] = 8'h01; ram[494] = 8'hc1; ram[495] = 8'hc9;
ram[496] = 8'hc5; ram[497] = 8'h21; ram[498] = 8'h00; ram[499] = 8'h00;
ram[500] = 8'h39; ram[501] = 8'he5; ram[502] = 8'h21; ram[503] = 8'h06;
ram[504] = 8'h00; ram[505] = 8'h39; ram[506] = 8'hcd; ram[507] = 8'h0d;
ram[508] = 8'h00; ram[509] = 8'he5; ram[510] = 8'h21; ram[511] = 8'h0a;
ram[512] = 8'h00; ram[513] = 8'hd1; ram[514] = 8'hcd; ram[515] = 8'hd3;
ram[516] = 8'h00; ram[517] = 8'hd1; ram[518] = 8'hcd; ram[519] = 8'h15;
ram[520] = 8'h00; ram[521] = 8'h21; ram[522] = 8'h00; ram[523] = 8'h00;
ram[524] = 8'h39; ram[525] = 8'hcd; ram[526] = 8'h0d; ram[527] = 8'h00;
ram[528] = 8'h7c; ram[529] = 8'hb5; ram[530] = 8'hca; ram[531] = 8'h21;
ram[532] = 8'h02; ram[533] = 8'h21; ram[534] = 8'h00; ram[535] = 8'h00;
ram[536] = 8'h39; ram[537] = 8'hcd; ram[538] = 8'h0d; ram[539] = 8'h00;
ram[540] = 8'he5; ram[541] = 8'hcd; ram[542] = 8'hf0; ram[543] = 8'h01;
ram[544] = 8'hc1; ram[545] = 8'h21; ram[546] = 8'h30; ram[547] = 8'h00;
ram[548] = 8'he5; ram[549] = 8'h21; ram[550] = 8'h06; ram[551] = 8'h00;
ram[552] = 8'h39; ram[553] = 8'hcd; ram[554] = 8'h0d; ram[555] = 8'h00;
ram[556] = 8'he5; ram[557] = 8'h21; ram[558] = 8'h04; ram[559] = 8'h00;
ram[560] = 8'h39; ram[561] = 8'hcd; ram[562] = 8'h0d; ram[563] = 8'h00;
ram[564] = 8'he5; ram[565] = 8'h21; ram[566] = 8'h0a; ram[567] = 8'h00;
ram[568] = 8'hd1; ram[569] = 8'hcd; ram[570] = 8'hb3; ram[571] = 8'h00;
ram[572] = 8'hd1; ram[573] = 8'hcd; ram[574] = 8'ha0; ram[575] = 8'h00;
ram[576] = 8'hd1; ram[577] = 8'h19; ram[578] = 8'he5; ram[579] = 8'hcd;
ram[580] = 8'h31; ram[581] = 8'h01; ram[582] = 8'hc1; ram[583] = 8'hc1;
ram[584] = 8'hc9; ram[585] = 8'hc5; ram[586] = 8'h21; ram[587] = 8'h00;
ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'he5; ram[591] = 8'h21;
ram[592] = 8'h06; ram[593] = 8'h00; ram[594] = 8'h39; ram[595] = 8'hcd;
ram[596] = 8'h0d; ram[597] = 8'h00; ram[598] = 8'he5; ram[599] = 8'h21;
ram[600] = 8'h10; ram[601] = 8'h00; ram[602] = 8'hd1; ram[603] = 8'hcd;
ram[604] = 8'hd3; ram[605] = 8'h00; ram[606] = 8'hd1; ram[607] = 8'hcd;
ram[608] = 8'h15; ram[609] = 8'h00; ram[610] = 8'h21; ram[611] = 8'h00;
ram[612] = 8'h00; ram[613] = 8'h39; ram[614] = 8'hcd; ram[615] = 8'h0d;
ram[616] = 8'h00; ram[617] = 8'h7c; ram[618] = 8'hb5; ram[619] = 8'hca;
ram[620] = 8'h7a; ram[621] = 8'h02; ram[622] = 8'h21; ram[623] = 8'h00;
ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h0d;
ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'hcd; ram[631] = 8'h49;
ram[632] = 8'h02; ram[633] = 8'hc1; ram[634] = 8'h21; ram[635] = 8'h00;
ram[636] = 8'h00; ram[637] = 8'h39; ram[638] = 8'he5; ram[639] = 8'h21;
ram[640] = 8'h06; ram[641] = 8'h00; ram[642] = 8'h39; ram[643] = 8'hcd;
ram[644] = 8'h0d; ram[645] = 8'h00; ram[646] = 8'he5; ram[647] = 8'h21;
ram[648] = 8'h04; ram[649] = 8'h00; ram[650] = 8'h39; ram[651] = 8'hcd;
ram[652] = 8'h0d; ram[653] = 8'h00; ram[654] = 8'he5; ram[655] = 8'h21;
ram[656] = 8'h10; ram[657] = 8'h00; ram[658] = 8'hd1; ram[659] = 8'hcd;
ram[660] = 8'hb3; ram[661] = 8'h00; ram[662] = 8'hd1; ram[663] = 8'hcd;
ram[664] = 8'ha0; ram[665] = 8'h00; ram[666] = 8'hd1; ram[667] = 8'hcd;
ram[668] = 8'h15; ram[669] = 8'h00; ram[670] = 8'h21; ram[671] = 8'h00;
ram[672] = 8'h00; ram[673] = 8'h39; ram[674] = 8'hcd; ram[675] = 8'h0d;
ram[676] = 8'h00; ram[677] = 8'he5; ram[678] = 8'h21; ram[679] = 8'h09;
ram[680] = 8'h00; ram[681] = 8'hd1; ram[682] = 8'hcd; ram[683] = 8'h3c;
ram[684] = 8'h00; ram[685] = 8'h7c; ram[686] = 8'hb5; ram[687] = 8'hca;
ram[688] = 8'hcf; ram[689] = 8'h02; ram[690] = 8'h21; ram[691] = 8'h41;
ram[692] = 8'h00; ram[693] = 8'he5; ram[694] = 8'h21; ram[695] = 8'h02;
ram[696] = 8'h00; ram[697] = 8'h39; ram[698] = 8'hcd; ram[699] = 8'h0d;
ram[700] = 8'h00; ram[701] = 8'hd1; ram[702] = 8'h19; ram[703] = 8'he5;
ram[704] = 8'h21; ram[705] = 8'h0a; ram[706] = 8'h00; ram[707] = 8'hd1;
ram[708] = 8'hcd; ram[709] = 8'ha0; ram[710] = 8'h00; ram[711] = 8'he5;
ram[712] = 8'hcd; ram[713] = 8'h31; ram[714] = 8'h01; ram[715] = 8'hc1;
ram[716] = 8'hc3; ram[717] = 8'he1; ram[718] = 8'h02; ram[719] = 8'h21;
ram[720] = 8'h30; ram[721] = 8'h00; ram[722] = 8'he5; ram[723] = 8'h21;
ram[724] = 8'h02; ram[725] = 8'h00; ram[726] = 8'h39; ram[727] = 8'hcd;
ram[728] = 8'h0d; ram[729] = 8'h00; ram[730] = 8'hd1; ram[731] = 8'h19;
ram[732] = 8'he5; ram[733] = 8'hcd; ram[734] = 8'h31; ram[735] = 8'h01;
ram[736] = 8'hc1; ram[737] = 8'hc1; ram[738] = 8'hc9; ram[739] = 8'h21;
ram[740] = 8'hc3; ram[741] = 8'h00; ram[742] = 8'h7d; ram[743] = 8'hd3;
ram[744] = 8'h81; ram[745] = 8'h21; ram[746] = 8'h00; ram[747] = 8'h00;
ram[748] = 8'h7d; ram[749] = 8'hd3; ram[750] = 8'h82; ram[751] = 8'h21;
ram[752] = 8'h5c; ram[753] = 8'h03; ram[754] = 8'he5; ram[755] = 8'hcd;
ram[756] = 8'h83; ram[757] = 8'h01; ram[758] = 8'hc1; ram[759] = 8'hcd;
ram[760] = 8'h72; ram[761] = 8'h01; ram[762] = 8'h21; ram[763] = 8'h6b;
ram[764] = 8'h03; ram[765] = 8'he5; ram[766] = 8'hcd; ram[767] = 8'h83;
ram[768] = 8'h01; ram[769] = 8'hc1; ram[770] = 8'h21; ram[771] = 8'h9f;
ram[772] = 8'h03; ram[773] = 8'he5; ram[774] = 8'h21; ram[775] = 8'h01;
ram[776] = 8'h00; ram[777] = 8'h29; ram[778] = 8'hd1; ram[779] = 8'h19;
ram[780] = 8'hcd; ram[781] = 8'h0d; ram[782] = 8'h00; ram[783] = 8'he5;
ram[784] = 8'hcd; ram[785] = 8'hb4; ram[786] = 8'h01; ram[787] = 8'hc1;
ram[788] = 8'hcd; ram[789] = 8'h72; ram[790] = 8'h01; ram[791] = 8'h21;
ram[792] = 8'h77; ram[793] = 8'h03; ram[794] = 8'he5; ram[795] = 8'hcd;
ram[796] = 8'h83; ram[797] = 8'h01; ram[798] = 8'hc1; ram[799] = 8'h21;
ram[800] = 8'h9f; ram[801] = 8'h03; ram[802] = 8'he5; ram[803] = 8'h21;
ram[804] = 8'h00; ram[805] = 8'h00; ram[806] = 8'h29; ram[807] = 8'hd1;
ram[808] = 8'h19; ram[809] = 8'hcd; ram[810] = 8'h0d; ram[811] = 8'h00;
ram[812] = 8'he5; ram[813] = 8'hcd; ram[814] = 8'h49; ram[815] = 8'h02;
ram[816] = 8'hc1; ram[817] = 8'hcd; ram[818] = 8'h72; ram[819] = 8'h01;
ram[820] = 8'h21; ram[821] = 8'h85; ram[822] = 8'h03; ram[823] = 8'he5;
ram[824] = 8'hcd; ram[825] = 8'h83; ram[826] = 8'h01; ram[827] = 8'hc1;
ram[828] = 8'hcd; ram[829] = 8'h72; ram[830] = 8'h01; ram[831] = 8'h21;
ram[832] = 8'h01; ram[833] = 8'h00; ram[834] = 8'h7c; ram[835] = 8'hb5;
ram[836] = 8'hca; ram[837] = 8'h5b; ram[838] = 8'h03; ram[839] = 8'hcd;
ram[840] = 8'h4f; ram[841] = 8'h01; ram[842] = 8'h7c; ram[843] = 8'hb5;
ram[844] = 8'hca; ram[845] = 8'h58; ram[846] = 8'h03; ram[847] = 8'h3a;
ram[848] = 8'h9e; ram[849] = 8'h03; ram[850] = 8'hcf; ram[851] = 8'he5;
ram[852] = 8'hcd; ram[853] = 8'h31; ram[854] = 8'h01; ram[855] = 8'hc1;
ram[856] = 8'hc3; ram[857] = 8'h3f; ram[858] = 8'h03; ram[859] = 8'hc9;
ram[860] = 8'h48; ram[861] = 8'h65; ram[862] = 8'h6c; ram[863] = 8'h6c;
ram[864] = 8'h6f; ram[865] = 8'h20; ram[866] = 8'h57; ram[867] = 8'h6f;
ram[868] = 8'h72; ram[869] = 8'h6c; ram[870] = 8'h64; ram[871] = 8'h21;
ram[872] = 8'h21; ram[873] = 8'h21; ram[874] = 8'h00; ram[875] = 8'h44;
ram[876] = 8'h65; ram[877] = 8'h63; ram[878] = 8'h20; ram[879] = 8'h76;
ram[880] = 8'h61; ram[881] = 8'h6c; ram[882] = 8'h75; ram[883] = 8'h65;
ram[884] = 8'h3a; ram[885] = 8'h20; ram[886] = 8'h00; ram[887] = 8'h48;
ram[888] = 8'h65; ram[889] = 8'h78; ram[890] = 8'h20; ram[891] = 8'h76;
ram[892] = 8'h61; ram[893] = 8'h6c; ram[894] = 8'h75; ram[895] = 8'h65;
ram[896] = 8'h3a; ram[897] = 8'h20; ram[898] = 8'h30; ram[899] = 8'h78;
ram[900] = 8'h00; ram[901] = 8'h45; ram[902] = 8'h63; ram[903] = 8'h68;
ram[904] = 8'h6f; ram[905] = 8'h69; ram[906] = 8'h6e; ram[907] = 8'h67;
ram[908] = 8'h20; ram[909] = 8'h72; ram[910] = 8'h65; ram[911] = 8'h63;
ram[912] = 8'h65; ram[913] = 8'h69; ram[914] = 8'h76; ram[915] = 8'h65;
ram[916] = 8'h64; ram[917] = 8'h20; ram[918] = 8'h62; ram[919] = 8'h79;
ram[920] = 8'h74; ram[921] = 8'h65; ram[922] = 8'h73; ram[923] = 8'h3a;
ram[924] = 8'h20; ram[925] = 8'h00; ram[926] = 8'h00; ram[927] = 8'hd2;
ram[928] = 8'h04; ram[929] = 8'h2e; ram[930] = 8'h16; ram[931] = 8'h00;
ram[932] = 8'h00; ram[933] = 8'h00; ram[934] = 8'h00; ram[935] = 8'h00;
ram[936] = 8'h00; ram[937] = 8'h00; ram[938] = 8'h00; ram[939] = 8'h00;
ram[940] = 8'h00; ram[941] = 8'h00; ram[942] = 8'h00; ram[943] = 8'h00;
ram[944] = 8'h00; ram[945] = 8'h00; ram[946] = 8'h00; ram[947] = 8'h00;
ram[948] = 8'h00; ram[949] = 8'h00; ram[950] = 8'h00; ram[951] = 8'h00;
ram[952] = 8'h00; ram[953] = 8'h00; ram[954] = 8'h00; ram[955] = 8'h00;
ram[956] = 8'h00; ram[957] = 8'h00; ram[958] = 8'h00; ram[959] = 8'h00;
ram[960] = 8'h00; ram[961] = 8'h00; ram[962] = 8'h00; ram[963] = 8'h00;
ram[964] = 8'h00; ram[965] = 8'h00; ram[966] = 8'h00; ram[967] = 8'h00;
ram[968] = 8'h00; ram[969] = 8'h00; ram[970] = 8'h00; ram[971] = 8'h00;
ram[972] = 8'h00; ram[973] = 8'h00; ram[974] = 8'h00; ram[975] = 8'h00;
ram[976] = 8'h00; ram[977] = 8'h00; ram[978] = 8'h00; ram[979] = 8'h00;
ram[980] = 8'h00; ram[981] = 8'h00; ram[982] = 8'h00; ram[983] = 8'h00;
ram[984] = 8'h00; ram[985] = 8'h00; ram[986] = 8'h00; ram[987] = 8'h00;
ram[988] = 8'h00; ram[989] = 8'h00; ram[990] = 8'h00; ram[991] = 8'h00;
ram[992] = 8'h00; ram[993] = 8'h00; ram[994] = 8'h00; ram[995] = 8'h00;
ram[996] = 8'h00; ram[997] = 8'h00; ram[998] = 8'h00; ram[999] = 8'h00;
ram[1000] = 8'h00; ram[1001] = 8'h00; ram[1002] = 8'h00; ram[1003] = 8'h00;
ram[1004] = 8'h00; ram[1005] = 8'h00; ram[1006] = 8'h00; ram[1007] = 8'h00;
ram[1008] = 8'h00; ram[1009] = 8'h00; ram[1010] = 8'h00; ram[1011] = 8'h00;
ram[1012] = 8'h00; ram[1013] = 8'h00; ram[1014] = 8'h00; ram[1015] = 8'h00;
ram[1016] = 8'h00; ram[1017] = 8'h00; ram[1018] = 8'h00; ram[1019] = 8'h00;
ram[1020] = 8'h00; ram[1021] = 8'h00; ram[1022] = 8'h00; ram[1023] = 8'h00;
ram[1024] = 8'h00; ram[1025] = 8'h00; ram[1026] = 8'h00; ram[1027] = 8'h00;
ram[1028] = 8'h00; ram[1029] = 8'h00; ram[1030] = 8'h00; ram[1031] = 8'h00;
ram[1032] = 8'h00; ram[1033] = 8'h00; ram[1034] = 8'h00; ram[1035] = 8'h00;
ram[1036] = 8'h00; ram[1037] = 8'h00; ram[1038] = 8'h00; ram[1039] = 8'h00;
ram[1040] = 8'h00; ram[1041] = 8'h00; ram[1042] = 8'h00; ram[1043] = 8'h00;
ram[1044] = 8'h00; ram[1045] = 8'h00; ram[1046] = 8'h00; ram[1047] = 8'h00;
ram[1048] = 8'h00; ram[1049] = 8'h00; ram[1050] = 8'h00; ram[1051] = 8'h00;
ram[1052] = 8'h00; ram[1053] = 8'h00; ram[1054] = 8'h00; ram[1055] = 8'h00;
ram[1056] = 8'h00; ram[1057] = 8'h00; ram[1058] = 8'h00; ram[1059] = 8'h00;
ram[1060] = 8'h00; ram[1061] = 8'h00; ram[1062] = 8'h00; ram[1063] = 8'h00;
ram[1064] = 8'h00; ram[1065] = 8'h00; ram[1066] = 8'h00; ram[1067] = 8'h00;
ram[1068] = 8'h00; ram[1069] = 8'h00; ram[1070] = 8'h00; ram[1071] = 8'h00;
ram[1072] = 8'h00; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
ram[4] = 8'hcd; ram[5] = 8'h30; ram[6] = 8'h03; ram[7] = 8'h00;
ram[8] = 8'hf5; ram[9] = 8'hc5; ram[10] = 8'hd5; ram[11] = 8'he5;
ram[12] = 8'hcd; ram[13] = 8'h24; ram[14] = 8'h03; ram[15] = 8'he1;
ram[16] = 8'hd1; ram[17] = 8'hc1; ram[18] = 8'hf1; ram[19] = 8'hfb;
ram[20] = 8'hc9; ram[21] = 8'h00; ram[22] = 8'h00; ram[23] = 8'h00;
ram[24] = 8'hf5; ram[25] = 8'hc5; ram[26] = 8'hd5; ram[27] = 8'he5;
ram[28] = 8'he1; ram[29] = 8'hd1; ram[30] = 8'hc1; ram[31] = 8'hf1;
ram[32] = 8'hfb; ram[33] = 8'hc9; ram[34] = 8'h00; ram[35] = 8'h00;
ram[36] = 8'h00; ram[37] = 8'h00; ram[38] = 8'h00; ram[39] = 8'h00;
ram[40] = 8'hf5; ram[41] = 8'hc5; ram[42] = 8'hd5; ram[43] = 8'he5;
ram[44] = 8'he1; ram[45] = 8'hd1; ram[46] = 8'hc1; ram[47] = 8'hf1;
ram[48] = 8'hfb; ram[49] = 8'hc9; ram[50] = 8'h00; ram[51] = 8'h00;
ram[52] = 8'h00; ram[53] = 8'h00; ram[54] = 8'h00; ram[55] = 8'h00;
ram[56] = 8'hf5; ram[57] = 8'hc5; ram[58] = 8'hd5; ram[59] = 8'he5;
ram[60] = 8'he1; ram[61] = 8'hd1; ram[62] = 8'hc1; ram[63] = 8'hf1;
ram[64] = 8'hfb; ram[65] = 8'hc9; ram[66] = 8'h7e; ram[67] = 8'h6f;
ram[68] = 8'h07; ram[69] = 8'h9f; ram[70] = 8'h67; ram[71] = 8'hc9;
ram[72] = 8'h7e; ram[73] = 8'h23; ram[74] = 8'h66; ram[75] = 8'h6f;
ram[76] = 8'hc9; ram[77] = 8'h7d; ram[78] = 8'h12; ram[79] = 8'hc9;
ram[80] = 8'h7d; ram[81] = 8'h12; ram[82] = 8'h13; ram[83] = 8'h7c;
ram[84] = 8'h12; ram[85] = 8'hc9; ram[86] = 8'h7d; ram[87] = 8'hb3;
ram[88] = 8'h6f; ram[89] = 8'h7c; ram[90] = 8'hb2; ram[91] = 8'h67;
ram[92] = 8'hc9; ram[93] = 8'h7d; ram[94] = 8'hab; ram[95] = 8'h6f;
ram[96] = 8'h7c; ram[97] = 8'haa; ram[98] = 8'h67; ram[99] = 8'hc9;
ram[100] = 8'h7d; ram[101] = 8'ha3; ram[102] = 8'h6f; ram[103] = 8'h7c;
ram[104] = 8'ha2; ram[105] = 8'h67; ram[106] = 8'hc9; ram[107] = 8'hcd;
ram[108] = 8'h91; ram[109] = 8'h00; ram[110] = 8'hc8; ram[111] = 8'h2b;
ram[112] = 8'hc9; ram[113] = 8'hcd; ram[114] = 8'h91; ram[115] = 8'h00;
ram[116] = 8'hc0; ram[117] = 8'h2b; ram[118] = 8'hc9; ram[119] = 8'heb;
ram[120] = 8'hcd; ram[121] = 8'h91; ram[122] = 8'h00; ram[123] = 8'hd8;
ram[124] = 8'h2b; ram[125] = 8'hc9; ram[126] = 8'hcd; ram[127] = 8'h91;
ram[128] = 8'h00; ram[129] = 8'hc8; ram[130] = 8'hd8; ram[131] = 8'h2b;
ram[132] = 8'hc9; ram[133] = 8'hcd; ram[134] = 8'h91; ram[135] = 8'h00;
ram[136] = 8'hd0; ram[137] = 8'h2b; ram[138] = 8'hc9; ram[139] = 8'hcd;
ram[140] = 8'h91; ram[141] = 8'h00; ram[142] = 8'hd8; ram[143] = 8'h2b;
ram[144] = 8'hc9; ram[145] = 8'h7b; ram[146] = 8'h95; ram[147] = 8'h5f;
ram[148] = 8'h7a; ram[149] = 8'h9c; ram[150] = 8'h21; ram[151] = 8'h01;
ram[152] = 8'h00; ram[153] = 8'hfa; ram[154] = 8'h9e; ram[155] = 8'h00;
ram[156] = 8'hb3; ram[157] = 8'hc9; ram[158] = 8'hb3; ram[159] = 8'h37;
ram[160] = 8'hc9; ram[161] = 8'hcd; ram[162] = 8'hbb; ram[163] = 8'h00;
ram[164] = 8'hd0; ram[165] = 8'h2b; ram[166] = 8'hc9; ram[167] = 8'hcd;
ram[168] = 8'hbb; ram[169] = 8'h00; ram[170] = 8'hd8; ram[171] = 8'h2b;
ram[172] = 8'hc9; ram[173] = 8'heb; ram[174] = 8'hcd; ram[175] = 8'hbb;
ram[176] = 8'h00; ram[177] = 8'hd8; ram[178] = 8'h2b; ram[179] = 8'hc9;
ram[180] = 8'hcd; ram[181] = 8'hbb; ram[182] = 8'h00; ram[183] = 8'hc8;
ram[184] = 8'hd8; ram[185] = 8'h2b; ram[186] = 8'hc9; ram[187] = 8'h7a;
ram[188] = 8'hbc; ram[189] = 8'hc2; ram[190] = 8'hc2; ram[191] = 8'h00;
ram[192] = 8'h7b; ram[193] = 8'hbd; ram[194] = 8'h21; ram[195] = 8'h01;
ram[196] = 8'h00; ram[197] = 8'hc9; ram[198] = 8'heb; ram[199] = 8'h7c;
ram[200] = 8'h17; ram[201] = 8'h7c; ram[202] = 8'h1f; ram[203] = 8'h67;
ram[204] = 8'h7d; ram[205] = 8'h1f; ram[206] = 8'h6f; ram[207] = 8'h1d;
ram[208] = 8'hc2; ram[209] = 8'hc7; ram[210] = 8'h00; ram[211] = 8'hc9;
ram[212] = 8'heb; ram[213] = 8'h29; ram[214] = 8'h1d; ram[215] = 8'hc2;
ram[216] = 8'hd5; ram[217] = 8'h00; ram[218] = 8'hc9; ram[219] = 8'h7b;
ram[220] = 8'h95; ram[221] = 8'h6f; ram[222] = 8'h7a; ram[223] = 8'h9c;
ram[224] = 8'h67; ram[225] = 8'hc9; ram[226] = 8'hcd; ram[227] = 8'he7;
ram[228] = 8'h00; ram[229] = 8'h23; ram[230] = 8'hc9; ram[231] = 8'h7c;
ram[232] = 8'h2f; ram[233] = 8'h67; ram[234] = 8'h7d; ram[235] = 8'h2f;
ram[236] = 8'h6f; ram[237] = 8'hc9; ram[238] = 8'h44; ram[239] = 8'h4d;
ram[240] = 8'h21; ram[241] = 8'h00; ram[242] = 8'h00; ram[243] = 8'h79;
ram[244] = 8'h0f; ram[245] = 8'hd2; ram[246] = 8'hf9; ram[247] = 8'h00;
ram[248] = 8'h19; ram[249] = 8'haf; ram[250] = 8'h78; ram[251] = 8'h1f;
ram[252] = 8'h47; ram[253] = 8'h79; ram[254] = 8'h1f; ram[255] = 8'h4f;
ram[256] = 8'hb0; ram[257] = 8'hc8; ram[258] = 8'haf; ram[259] = 8'h7b;
ram[260] = 8'h17; ram[261] = 8'h5f; ram[262] = 8'h7a; ram[263] = 8'h17;
ram[264] = 8'h57; ram[265] = 8'hb3; ram[266] = 8'hc8; ram[267] = 8'hc3;
ram[268] = 8'hf3; ram[269] = 8'h00; ram[270] = 8'h44; ram[271] = 8'h4d;
ram[272] = 8'h7a; ram[273] = 8'ha8; ram[274] = 8'hf5; ram[275] = 8'h7a;
ram[276] = 8'hb7; ram[277] = 8'hfc; ram[278] = 8'h4f; ram[279] = 8'h01;
ram[280] = 8'h78; ram[281] = 8'hb7; ram[282] = 8'hfc; ram[283] = 8'h57;
ram[284] = 8'h01; ram[285] = 8'h3e; ram[286] = 8'h10; ram[287] = 8'hf5;
ram[288] = 8'heb; ram[289] = 8'h11; ram[290] = 8'h00; ram[291] = 8'h00;
ram[292] = 8'h29; ram[293] = 8'hcd; ram[294] = 8'h5f; ram[295] = 8'h01;
ram[296] = 8'hca; ram[297] = 8'h3b; ram[298] = 8'h01; ram[299] = 8'hcd;
ram[300] = 8'h67; ram[301] = 8'h01; ram[302] = 8'hfa; ram[303] = 8'h3b;
ram[304] = 8'h01; ram[305] = 8'h7d; ram[306] = 8'hf6; ram[307] = 8'h01;
ram[308] = 8'h6f; ram[309] = 8'h7b; ram[310] = 8'h91; ram[311] = 8'h5f;
ram[312] = 8'h7a; ram[313] = 8'h98; ram[314] = 8'h57; ram[315] = 8'hf1;
ram[316] = 8'h3d; ram[317] = 8'hca; ram[318] = 8'h44; ram[319] = 8'h01;
ram[320] = 8'hf5; ram[321] = 8'hc3; ram[322] = 8'h24; ram[323] = 8'h01;
ram[324] = 8'hf1; ram[325] = 8'hf0; ram[326] = 8'hcd; ram[327] = 8'h4f;
ram[328] = 8'h01; ram[329] = 8'heb; ram[330] = 8'hcd; ram[331] = 8'h4f;
ram[332] = 8'h01; ram[333] = 8'heb; ram[334] = 8'hc9; ram[335] = 8'h7a;
ram[336] = 8'h2f; ram[337] = 8'h57; ram[338] = 8'h7b; ram[339] = 8'h2f;
ram[340] = 8'h5f; ram[341] = 8'h13; ram[342] = 8'hc9; ram[343] = 8'h78;
ram[344] = 8'h2f; ram[345] = 8'h47; ram[346] = 8'h79; ram[347] = 8'h2f;
ram[348] = 8'h4f; ram[349] = 8'h03; ram[350] = 8'hc9; ram[351] = 8'h7b;
ram[352] = 8'h17; ram[353] = 8'h5f; ram[354] = 8'h7a; ram[355] = 8'h17;
ram[356] = 8'h57; ram[357] = 8'hb3; ram[358] = 8'hc9; ram[359] = 8'h7b;
ram[360] = 8'h91; ram[361] = 8'h7a; ram[362] = 8'h98; ram[363] = 8'hc9;
ram[364] = 8'hdb; ram[365] = 8'h83; ram[366] = 8'hcd; ram[367] = 8'h43;
ram[368] = 8'h00; ram[369] = 8'he5; ram[370] = 8'h21; ram[371] = 8'h01;
ram[372] = 8'h00; ram[373] = 8'hd1; ram[374] = 8'hcd; ram[375] = 8'h64;
ram[376] = 8'h00; ram[377] = 8'h7c; ram[378] = 8'hb5; ram[379] = 8'hca;
ram[380] = 8'h81; ram[381] = 8'h01; ram[382] = 8'hc3; ram[383] = 8'h6c;
ram[384] = 8'h01; ram[385] = 8'h21; ram[386] = 8'h02; ram[387] = 8'h00;
ram[388] = 8'h39; ram[389] = 8'hcd; ram[390] = 8'h42; ram[391] = 8'h00;
ram[392] = 8'h7d; ram[393] = 8'hd3; ram[394] = 8'h80; ram[395] = 8'hc9;
ram[396] = 8'hdb; ram[397] = 8'h83; ram[398] = 8'hcd; ram[399] = 8'h43;
ram[400] = 8'h00; ram[401] = 8'he5; ram[402] = 8'h21; ram[403] = 8'h10;
ram[404] = 8'h00; ram[405] = 8'hd1; ram[406] = 8'hcd; ram[407] = 8'h64;
ram[408] = 8'h00; ram[409] = 8'h7c; ram[410] = 8'hb5; ram[411] = 8'hca;
ram[412] = 8'hae; ram[413] = 8'h01; ram[414] = 8'hdb; ram[415] = 8'h80;
ram[416] = 8'hcd; ram[417] = 8'h43; ram[418] = 8'h00; ram[419] = 8'h7d;
ram[420] = 8'h32; ram[421] = 8'h2c; ram[422] = 8'h04; ram[423] = 8'h21;
ram[424] = 8'h01; ram[425] = 8'h00; ram[426] = 8'hc9; ram[427] = 8'hc3;
ram[428] = 8'hb2; ram[429] = 8'h01; ram[430] = 8'h21; ram[431] = 8'h00;
ram[432] = 8'h00; ram[433] = 8'hc9; ram[434] = 8'hc9; ram[435] = 8'h21;
ram[436] = 8'h0d; ram[437] = 8'h00; ram[438] = 8'he5; ram[439] = 8'hcd;
ram[440] = 8'h6c; ram[441] = 8'h01; ram[442] = 8'hc1; ram[443] = 8'h21;
ram[444] = 8'h0a; ram[445] = 8'h00; ram[446] = 8'he5; ram[447] = 8'hcd;
ram[448] = 8'h6c; ram[449] = 8'h01; ram[450] = 8'hc1; ram[451] = 8'hc9;
ram[452] = 8'h21; ram[453] = 8'h02; ram[454] = 8'h00; ram[455] = 8'h39;
ram[456] = 8'hcd; ram[457] = 8'h48; ram[458] = 8'h00; ram[459] = 8'hcd;
ram[460] = 8'h42; ram[461] = 8'h00; ram[462] = 8'he5; ram[463] = 8'h21;
ram[464] = 8'h00; ram[465] = 8'h00; ram[466] = 8'hd1; ram[467] = 8'hcd;
ram[468] = 8'h71; ram[469] = 8'h00; ram[470] = 8'h7c; ram[471] = 8'hb5;
ram[472] = 8'hca; ram[473] = 8'hf4; ram[474] = 8'h01; ram[475] = 8'h21;
ram[476] = 8'h02; ram[477] = 8'h00; ram[478] = 8'h39; ram[479] = 8'he5;
ram[480] = 8'hcd; ram[481] = 8'h48; ram[482] = 8'h00; ram[483] = 8'h23;
ram[484] = 8'hd1; ram[485] = 8'hcd; ram[486] = 8'h50; ram[487] = 8'h00;
ram[488] = 8'h2b; ram[489] = 8'hcd; ram[490] = 8'h42; ram[491] = 8'h00;
ram[492] = 8'he5; ram[493] = 8'hcd; ram[494] = 8'h6c; ram[495] = 8'h01;
ram[496] = 8'hc1; ram[497] = 8'hc3; ram[498] = 8'hc4; ram[499] = 8'h01;
ram[500] = 8'hc9; ram[501] = 8'h21; ram[502] = 8'h02; ram[503] = 8'h00;
ram[504] = 8'h39; ram[505] = 8'hcd; ram[506] = 8'h48; ram[507] = 8'h00;
ram[508] = 8'he5; ram[509] = 8'h21; ram[510] = 8'h00; ram[511] = 8'h00;
ram[512] = 8'hd1; ram[513] = 8'hcd; ram[514] = 8'h8b; ram[515] = 8'h00;
ram[516] = 8'h7c; ram[517] = 8'hb5; ram[518] = 8'hca; ram[519] = 8'h24;
ram[520] = 8'h02; ram[521] = 8'h21; ram[522] = 8'h2d; ram[523] = 8'h00;
ram[524] = 8'he5; ram[525] = 8'hcd; ram[526] = 8'h6c; ram[527] = 8'h01;
ram[528] = 8'hc1; ram[529] = 8'h21; ram[530] = 8'h02; ram[531] = 8'h00;
ram[532] = 8'h39; ram[533] = 8'he5; ram[534] = 8'h21; ram[535] = 8'h04;
ram[536] = 8'h00; ram[537] = 8'h39; ram[538] = 8'hcd; ram[539] = 8'h48;
ram[540] = 8'h00; ram[541] = 8'hcd; ram[542] = 8'he2; ram[543] = 8'h00;
ram[544] = 8'hd1; ram[545] = 8'hcd; ram[546] = 8'h50; ram[547] = 8'h00;
ram[548] = 8'h21; ram[549] = 8'h02; ram[550] = 8'h00; ram[551] = 8'h39;
ram[552] = 8'hcd; ram[553] = 8'h48; ram[554] = 8'h00; ram[555] = 8'he5;
ram[556] = 8'hcd; ram[557] = 8'h31; ram[558] = 8'h02; ram[559] = 8'hc1;
ram[560] = 8'hc9; ram[561] = 8'hc5; ram[562] = 8'h21; ram[563] = 8'h00;
ram[564] = 8'h00; ram[565] = 8'h39; ram[566] = 8'he5; ram[567] = 8'h21;
ram[568] = 8'h06; ram[569] = 8'h00; ram[570] = 8'h39; ram[571] = 8'hcd;
ram[572] = 8'h48; ram[573] = 8'h00; ram[574] = 8'he5; ram[575] = 8'h21;
ram[576] = 8'h0a; ram[577] = 8'h00; ram[578] = 8'hd1; ram[579] = 8'hcd;
ram[580] = 8'h0e; ram[581] = 8'h01; ram[582] = 8'hd1; ram[583] = 8'hcd;
ram[584] = 8'h50; ram[585] = 8'h00; ram[586] = 8'h21; ram[587] = 8'h00;
ram[588] = 8'h00; ram[589] = 8'h39; ram[590] = 8'hcd; ram[591] = 8'h48;
ram[592] = 8'h00; ram[593] = 8'h7c; ram[594] = 8'hb5; ram[595] = 8'hca;
ram[596] = 8'h62; ram[597] = 8'h02; ram[598] = 8'h21; ram[599] = 8'h00;
ram[600] = 8'h00; ram[601] = 8'h39; ram[602] = 8'hcd; ram[603] = 8'h48;
ram[604] = 8'h00; ram[605] = 8'he5; ram[606] = 8'hcd; ram[607] = 8'h31;
ram[608] = 8'h02; ram[609] = 8'hc1; ram[610] = 8'h21; ram[611] = 8'h30;
ram[612] = 8'h00; ram[613] = 8'he5; ram[614] = 8'h21; ram[615] = 8'h06;
ram[616] = 8'h00; ram[617] = 8'h39; ram[618] = 8'hcd; ram[619] = 8'h48;
ram[620] = 8'h00; ram[621] = 8'he5; ram[622] = 8'h21; ram[623] = 8'h04;
ram[624] = 8'h00; ram[625] = 8'h39; ram[626] = 8'hcd; ram[627] = 8'h48;
ram[628] = 8'h00; ram[629] = 8'he5; ram[630] = 8'h21; ram[631] = 8'h0a;
ram[632] = 8'h00; ram[633] = 8'hd1; ram[634] = 8'hcd; ram[635] = 8'hee;
ram[636] = 8'h00; ram[637] = 8'hd1; ram[638] = 8'hcd; ram[639] = 8'hdb;
ram[640] = 8'h00; ram[641] = 8'hd1; ram[642] = 8'h19; ram[643] = 8'he5;
ram[644] = 8'hcd; ram[645] = 8'h6c; ram[646] = 8'h01; ram[647] = 8'hc1;
ram[648] = 8'hc1; ram[649] = 8'hc9; ram[650] = 8'hc5; ram[651] = 8'h21;
ram[652] = 8'h00; ram[653] = 8'h00; ram[654] = 8'h39; ram[655] = 8'he5;
ram[656] = 8'h21; ram[657] = 8'h06; ram[658] = 8'h00; ram[659] = 8'h39;
ram[660] = 8'hcd; ram[661] = 8'h48; ram[662] = 8'h00; ram[663] = 8'he5;
ram[664] = 8'h21; ram[665] = 8'h10; ram[666] = 8'h00; ram[667] = 8'hd1;
ram[668] = 8'hcd; ram[669] = 8'h0e; ram[670] = 8'h01; ram[671] = 8'hd1;
ram[672] = 8'hcd; ram[673] = 8'h50; ram[674] = 8'h00; ram[675] = 8'h21;
ram[676] = 8'h00; ram[677] = 8'h00; ram[678] = 8'h39; ram[679] = 8'hcd;
ram[680] = 8'h48; ram[681] = 8'h00; ram[682] = 8'h7c; ram[683] = 8'hb5;
ram[684] = 8'hca; ram[685] = 8'hbb; ram[686] = 8'h02; ram[687] = 8'h21;
ram[688] = 8'h00; ram[689] = 8'h00; ram[690] = 8'h39; ram[691] = 8'hcd;
ram[692] = 8'h48; ram[693] = 8'h00; ram[694] = 8'he5; ram[695] = 8'hcd;
ram[696] = 8'h8a; ram[697] = 8'h02; ram[698] = 8'hc1; ram[699] = 8'h21;
ram[700] = 8'h00; ram[701] = 8'h00; ram[702] = 8'h39; ram[703] = 8'he5;
ram[704] = 8'h21; ram[705] = 8'h06; ram[706] = 8'h00; ram[707] = 8'h39;
ram[708] = 8'hcd; ram[709] = 8'h48; ram[710] = 8'h00; ram[711] = 8'he5;
ram[712] = 8'h21; ram[713] = 8'h04; ram[714] = 8'h00; ram[715] = 8'h39;
ram[716] = 8'hcd; ram[717] = 8'h48; ram[718] = 8'h00; ram[719] = 8'he5;
ram[720] = 8'h21; ram[721] = 8'h10; ram[722] = 8'h00; ram[723] = 8'hd1;
ram[724] = 8'hcd; ram[725] = 8'hee; ram[726] = 8'h00; ram[727] = 8'hd1;
ram[728] = 8'hcd; ram[729] = 8'hdb; ram[730] = 8'h00; ram[731] = 8'hd1;
ram[732] = 8'hcd; ram[733] = 8'h50; ram[734] = 8'h00; ram[735] = 8'h21;
ram[736] = 8'h00; ram[737] = 8'h00; ram[738] = 8'h39; ram[739] = 8'hcd;
ram[740] = 8'h48; ram[741] = 8'h00; ram[742] = 8'he5; ram[743] = 8'h21;
ram[744] = 8'h09; ram[745] = 8'h00; ram[746] = 8'hd1; ram[747] = 8'hcd;
ram[748] = 8'h77; ram[749] = 8'h00; ram[750] = 8'h7c; ram[751] = 8'hb5;
ram[752] = 8'hca; ram[753] = 8'h10; ram[754] = 8'h03; ram[755] = 8'h21;
ram[756] = 8'h41; ram[757] = 8'h00; ram[758] = 8'he5; ram[759] = 8'h21;
ram[760] = 8'h02; ram[761] = 8'h00; ram[762] = 8'h39; ram[763] = 8'hcd;
ram[764] = 8'h48; ram[765] = 8'h00; ram[766] = 8'hd1; ram[767] = 8'h19;
ram[768] = 8'he5; ram[769] = 8'h21; ram[770] = 8'h0a; ram[771] = 8'h00;
ram[772] = 8'hd1; ram[773] = 8'hcd; ram[774] = 8'hdb; ram[775] = 8'h00;
ram[776] = 8'he5; ram[777] = 8'hcd; ram[778] = 8'h6c; ram[779] = 8'h01;
ram[780] = 8'hc1; ram[781] = 8'hc3; ram[782] = 8'h22; ram[783] = 8'h03;
ram[784] = 8'h21; ram[785] = 8'h30; ram[786] = 8'h00; ram[787] = 8'he5;
ram[788] = 8'h21; ram[789] = 8'h02; ram[790] = 8'h00; ram[791] = 8'h39;
ram[792] = 8'hcd; ram[793] = 8'h48; ram[794] = 8'h00; ram[795] = 8'hd1;
ram[796] = 8'h19; ram[797] = 8'he5; ram[798] = 8'hcd; ram[799] = 8'h6c;
ram[800] = 8'h01; ram[801] = 8'hc1; ram[802] = 8'hc1; ram[803] = 8'hc9;
ram[804] = 8'h21; ram[805] = 8'hd0; ram[806] = 8'h03; ram[807] = 8'he5;
ram[808] = 8'hcd; ram[809] = 8'hc4; ram[810] = 8'h01; ram[811] = 8'hc1;
ram[812] = 8'hcd; ram[813] = 8'hb3; ram[814] = 8'h01; ram[815] = 8'hc9;
ram[816] = 8'h21; ram[817] = 8'h01; ram[818] = 8'h00; ram[819] = 8'h7d;
ram[820] = 8'hd3; ram[821] = 8'h81; ram[822] = 8'h21; ram[823] = 8'h00;
ram[824] = 8'h00; ram[825] = 8'h7d; ram[826] = 8'hd3; ram[827] = 8'h82;
ram[828] = 8'h21; ram[829] = 8'h00; ram[830] = 8'h00; ram[831] = 8'h7d;
ram[832] = 8'hd3; ram[833] = 8'h84; ram[834] = 8'h21; ram[835] = 8'hff;
ram[836] = 8'h00; ram[837] = 8'h7d; ram[838] = 8'hd3; ram[839] = 8'h85;
ram[840] = 8'h21; ram[841] = 8'h00; ram[842] = 8'h00; ram[843] = 8'h7d;
ram[844] = 8'hd3; ram[845] = 8'h86; ram[846] = 8'h21; ram[847] = 8'hff;
ram[848] = 8'h00; ram[849] = 8'h7d; ram[850] = 8'hd3; ram[851] = 8'h87;
ram[852] = 8'h21; ram[853] = 8'h01; ram[854] = 8'h00; ram[855] = 8'h7d;
ram[856] = 8'hd3; ram[857] = 8'h88; ram[858] = 8'hfb; ram[859] = 8'h21;
ram[860] = 8'hea; ram[861] = 8'h03; ram[862] = 8'he5; ram[863] = 8'hcd;
ram[864] = 8'hc4; ram[865] = 8'h01; ram[866] = 8'hc1; ram[867] = 8'hcd;
ram[868] = 8'hb3; ram[869] = 8'h01; ram[870] = 8'h21; ram[871] = 8'hf9;
ram[872] = 8'h03; ram[873] = 8'he5; ram[874] = 8'hcd; ram[875] = 8'hc4;
ram[876] = 8'h01; ram[877] = 8'hc1; ram[878] = 8'h21; ram[879] = 8'h2d;
ram[880] = 8'h04; ram[881] = 8'he5; ram[882] = 8'h21; ram[883] = 8'h01;
ram[884] = 8'h00; ram[885] = 8'h29; ram[886] = 8'hd1; ram[887] = 8'h19;
ram[888] = 8'hcd; ram[889] = 8'h48; ram[890] = 8'h00; ram[891] = 8'he5;
ram[892] = 8'hcd; ram[893] = 8'hf5; ram[894] = 8'h01; ram[895] = 8'hc1;
ram[896] = 8'hcd; ram[897] = 8'hb3; ram[898] = 8'h01; ram[899] = 8'h21;
ram[900] = 8'h05; ram[901] = 8'h04; ram[902] = 8'he5; ram[903] = 8'hcd;
ram[904] = 8'hc4; ram[905] = 8'h01; ram[906] = 8'hc1; ram[907] = 8'h21;
ram[908] = 8'h2d; ram[909] = 8'h04; ram[910] = 8'he5; ram[911] = 8'h21;
ram[912] = 8'h00; ram[913] = 8'h00; ram[914] = 8'h29; ram[915] = 8'hd1;
ram[916] = 8'h19; ram[917] = 8'hcd; ram[918] = 8'h48; ram[919] = 8'h00;
ram[920] = 8'he5; ram[921] = 8'hcd; ram[922] = 8'h8a; ram[923] = 8'h02;
ram[924] = 8'hc1; ram[925] = 8'hcd; ram[926] = 8'hb3; ram[927] = 8'h01;
ram[928] = 8'h21; ram[929] = 8'h01; ram[930] = 8'h00; ram[931] = 8'h7d;
ram[932] = 8'hd3; ram[933] = 8'h84; ram[934] = 8'h21; ram[935] = 8'h13;
ram[936] = 8'h04; ram[937] = 8'he5; ram[938] = 8'hcd; ram[939] = 8'hc4;
ram[940] = 8'h01; ram[941] = 8'hc1; ram[942] = 8'hcd; ram[943] = 8'hb3;
ram[944] = 8'h01; ram[945] = 8'h21; ram[946] = 8'h01; ram[947] = 8'h00;
ram[948] = 8'h7c; ram[949] = 8'hb5; ram[950] = 8'hca; ram[951] = 8'hcf;
ram[952] = 8'h03; ram[953] = 8'hcd; ram[954] = 8'h8c; ram[955] = 8'h01;
ram[956] = 8'h7c; ram[957] = 8'hb5; ram[958] = 8'hca; ram[959] = 8'hcc;
ram[960] = 8'h03; ram[961] = 8'h3a; ram[962] = 8'h2c; ram[963] = 8'h04;
ram[964] = 8'hcd; ram[965] = 8'h43; ram[966] = 8'h00; ram[967] = 8'he5;
ram[968] = 8'hcd; ram[969] = 8'h6c; ram[970] = 8'h01; ram[971] = 8'hc1;
ram[972] = 8'hc3; ram[973] = 8'hb1; ram[974] = 8'h03; ram[975] = 8'hc9;
ram[976] = 8'h49; ram[977] = 8'h6e; ram[978] = 8'h74; ram[979] = 8'h65;
ram[980] = 8'h72; ram[981] = 8'h72; ram[982] = 8'h75; ram[983] = 8'h70;
ram[984] = 8'h74; ram[985] = 8'h20; ram[986] = 8'h30; ram[987] = 8'h20;
ram[988] = 8'h77; ram[989] = 8'h61; ram[990] = 8'h73; ram[991] = 8'h20;
ram[992] = 8'h61; ram[993] = 8'h73; ram[994] = 8'h73; ram[995] = 8'h65;
ram[996] = 8'h72; ram[997] = 8'h74; ram[998] = 8'h65; ram[999] = 8'h64;
ram[1000] = 8'h2e; ram[1001] = 8'h00; ram[1002] = 8'h48; ram[1003] = 8'h65;
ram[1004] = 8'h6c; ram[1005] = 8'h6c; ram[1006] = 8'h6f; ram[1007] = 8'h20;
ram[1008] = 8'h57; ram[1009] = 8'h6f; ram[1010] = 8'h72; ram[1011] = 8'h6c;
ram[1012] = 8'h64; ram[1013] = 8'h21; ram[1014] = 8'h21; ram[1015] = 8'h21;
ram[1016] = 8'h00; ram[1017] = 8'h44; ram[1018] = 8'h65; ram[1019] = 8'h63;
ram[1020] = 8'h20; ram[1021] = 8'h76; ram[1022] = 8'h61; ram[1023] = 8'h6c;
ram[1024] = 8'h75; ram[1025] = 8'h65; ram[1026] = 8'h3a; ram[1027] = 8'h20;
ram[1028] = 8'h00; ram[1029] = 8'h48; ram[1030] = 8'h65; ram[1031] = 8'h78;
ram[1032] = 8'h20; ram[1033] = 8'h76; ram[1034] = 8'h61; ram[1035] = 8'h6c;
ram[1036] = 8'h75; ram[1037] = 8'h65; ram[1038] = 8'h3a; ram[1039] = 8'h20;
ram[1040] = 8'h30; ram[1041] = 8'h78; ram[1042] = 8'h00; ram[1043] = 8'h45;
ram[1044] = 8'h63; ram[1045] = 8'h68; ram[1046] = 8'h6f; ram[1047] = 8'h69;
ram[1048] = 8'h6e; ram[1049] = 8'h67; ram[1050] = 8'h20; ram[1051] = 8'h72;
ram[1052] = 8'h65; ram[1053] = 8'h63; ram[1054] = 8'h65; ram[1055] = 8'h69;
ram[1056] = 8'h76; ram[1057] = 8'h65; ram[1058] = 8'h64; ram[1059] = 8'h20;
ram[1060] = 8'h62; ram[1061] = 8'h79; ram[1062] = 8'h74; ram[1063] = 8'h65;
ram[1064] = 8'h73; ram[1065] = 8'h3a; ram[1066] = 8'h20; ram[1067] = 8'h00;
ram[1068] = 8'h00; ram[1069] = 8'hd2; ram[1070] = 8'h04; ram[1071] = 8'h2e;
ram[1072] = 8'h16; ram[1073] = 8'h00; ram[1074] = 8'h00; ram[1075] = 8'h00;
ram[1076] = 8'h00; ram[1077] = 8'h00; ram[1078] = 8'h00; ram[1079] = 8'h00;
ram[1080] = 8'h00; ram[1081] = 8'h00; ram[1082] = 8'h00; ram[1083] = 8'h00;
ram[1084] = 8'h00; ram[1085] = 8'h00; ram[1086] = 8'h00; ram[1087] = 8'h00;
/rtl/l80soc.v
32,7 → 32,8
(
clock, reset,
txd, rxd,
p1dio, p2dio
p1dio, p2dio,
extint
);
//---------------------------------------------------------------------------------------
// module interfaces
45,6 → 46,8
// digital IO ports
inout [7:0] p1dio; // port 1 digital IO
inout [7:0] p2dio; // port 2 digital IO
// external interrupt sources
input [3:0] extint; // external interrupt sources
 
//---------------------------------------------------------------------------------------
// io space registers addresses
58,6 → 61,8
`define P1_DIR_REG 8'h85 // port 1 direction register
`define P2_DATA_REG 8'h86 // port 2 data register
`define P2_DIR_REG 8'h87 // port 2 direction register
// interrupt controller register
`define INTR_EN_REG 8'h88 // interrupts enable register
 
//---------------------------------------------------------------------------------------
// internal declarations
65,14 → 70,14
 
// internals
wire [15:0] cpu_addr;
wire [7:0] cpu_din, cpu_dout, ram_dout;
wire cpu_io, cpu_rd, cpu_wr;
wire [7:0] txData;
wire txValid, txBusy, rxValid, lcd_clk;
wire [7:0] rxData;
wire [7:0] cpu_din, cpu_dout, ram_dout, intr_dout;
wire cpu_io, cpu_rd, cpu_wr, cpu_inta, cpu_inte, cpu_intr;
wire [7:0] txData, rxData;
wire txValid, txBusy, rxValid;
reg [15:0] uartbaud;
reg rxfull, scpu_io;
reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
reg [3:0] intr_ena;
 
//---------------------------------------------------------------------------------------
// module implementation
89,13 → 94,13
.fetch(/* nu */),
.data_in(cpu_din),
.data_out(cpu_dout),
.inta(/* nu */),
.inte(/* nu */),
.inta(cpu_inta),
.inte(cpu_inte),
.halt(/* nu */),
.intr(1'b0)
.intr(cpu_intr)
);
// cpu data input selection
assign cpu_din = scpu_io ? io_dout : ram_dout;
assign cpu_din = (cpu_inta) ? intr_dout : (scpu_io) ? io_dout : ram_dout;
 
// program and data Xilinx RAM memory
ram_image ram
118,6 → 123,7
p1dir <= 8'b0;
p2reg <= 8'b0;
p2dir <= 8'b0;
intr_ena <= 4'b0;
end
else
begin
130,6 → 136,7
if (cpu_addr[7:0] == `P1_DIR_REG) p1dir <= cpu_dout;
if (cpu_addr[7:0] == `P2_DATA_REG) p2reg <= cpu_dout;
if (cpu_addr[7:0] == `P2_DIR_REG) p2dir <= cpu_dout;
if (cpu_addr[7:0] == `INTR_EN_REG) intr_ena <= cpu_dout[3:0];
end
// receiver full flag
166,6 → 173,20
end
end
 
// interrupt controller
intr_ctrl intrc
(
.clock(clock),
.reset(reset),
.ext_intr(extint),
.cpu_intr(cpu_intr),
.cpu_inte(cpu_inte),
.cpu_inta(cpu_inta),
.cpu_rd(cpu_rd),
.cpu_inst(intr_dout),
.intr_ena(intr_ena)
);
 
// uart module mapped to the io space
uart uart
(
/sim/icarus/block.cfg
1,6 → 1,7
../../rtl/uart.v
../../rtl/ram_image.v
../../rtl/micro_rom.v
../../rtl/intr_ctrl.v
../../rtl/light8080.v
../../rtl/l80soc.v
../../bench/tb_l80soc.v
/syn/xilinx_s3/xilinx_s3.xise
38,6 → 38,10
<file xil_pn:name="l80soc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../rtl/intr_ctrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files>
 
<properties>
/syn/xilinx_s3/l80soc_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>xilinx_s3 Project Status (02/21/2012 - 11:58:43)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>xilinx_s3 Project Status (03/03/2012 - 19:50:25)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>xilinx_s3.ise</TD>
20,7 → 20,7
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s200-4ft256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs'>33 Warnings</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs'>26 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.4</TD>
51,43 → 51,43
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>211</TD>
<TD ALIGN=RIGHT>233</TD>
<TD ALIGN=RIGHT>3,840</TD>
<TD ALIGN=RIGHT>5%</TD>
<TD ALIGN=RIGHT>6%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>327</TD>
<TD ALIGN=RIGHT>377</TD>
<TD ALIGN=RIGHT>3,840</TD>
<TD ALIGN=RIGHT>8%</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>253</TD>
<TD ALIGN=RIGHT>1,920</TD>
<TD ALIGN=RIGHT>11%</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>253</TD>
<TD ALIGN=RIGHT>253</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>253</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number of 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>328</TD>
<TD ALIGN=RIGHT>378</TD>
<TD ALIGN=RIGHT>3,840</TD>
<TD ALIGN=RIGHT>8%</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>311</TD>
<TD ALIGN=RIGHT>361</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
105,9 → 105,9
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>173</TD>
<TD ALIGN=RIGHT>11%</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16s</TD>
123,7 → 123,7
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.29</TD>
<TD ALIGN=RIGHT>3.36</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
160,12 → 160,12
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:54:55 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>31 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>6 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:21 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:29 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:40 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:01 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>24 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>9 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:06 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:13 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:23 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:43 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:25 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
174,5 → 174,5
</TABLE>
 
 
<br><center><b>Date Generated:</b> 02/21/2012 - 11:58:43</center>
<br><center><b>Date Generated:</b> 03/03/2012 - 19:50:25</center>
</BODY></HTML>
/syn/altera_c2/l80soc.qsf
49,11 → 49,6
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
set_global_assignment -name SEARCH_PATH "c:\\altera\\81\\ip\\altera\\reed_solomon\\lib/"
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
62,4 → 57,10
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name FMAX_REQUIREMENT "15 ns"
set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
set_global_assignment -name VERILOG_FILE ../../rtl/intr_ctrl.v
set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/syn/altera_c2/l80soc.fit.rpt
1,5 → 1,5
Fitter report for l80soc
Tue Feb 21 12:01:11 2012
Sat Mar 03 19:54:03 2012
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
 
 
63,7 → 63,7
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
; Fitter Status ; Successful - Tue Feb 21 12:01:11 2012 ;
; Fitter Status ; Successful - Sat Mar 03 19:54:03 2012 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; l80soc ;
; Top-level Entity Name ; l80soc ;
70,11 → 70,11
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Total logic elements ; 596 / 8,256 ( 7 % ) ;
; Total combinational functions ; 452 / 8,256 ( 5 % ) ;
; Dedicated logic registers ; 339 / 8,256 ( 4 % ) ;
; Total registers ; 339 ;
; Total pins ; 20 / 138 ( 14 % ) ;
; Total logic elements ; 646 / 8,256 ( 8 % ) ;
; Total combinational functions ; 496 / 8,256 ( 6 % ) ;
; Dedicated logic registers ; 361 / 8,256 ( 4 % ) ;
; Total registers ; 361 ;
; Total pins ; 24 / 138 ( 17 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 47,616 / 165,888 ( 29 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
152,8 → 152,8
; Type ; Value ;
+-------------------------+--------------------+
; Placement ; ;
; -- Requested ; 0 / 854 ( 0.00 % ) ;
; -- Achieved ; 0 / 854 ( 0.00 % ) ;
; -- Requested ; 0 / 924 ( 0.00 % ) ;
; -- Achieved ; 0 / 924 ( 0.00 % ) ;
; ; ;
; Routing (by Connection) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
175,7 → 175,7
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top ; 854 ; 0 ; N/A ; Source File ;
; Top ; 924 ; 0 ; N/A ; Source File ;
+----------------+---------+-------------------+-------------------------+-------------------+
 
 
190,29 → 190,29
+---------------------------------------------+---------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------+
; Total logic elements ; 596 / 8,256 ( 7 % ) ;
; -- Combinational with no register ; 257 ;
; -- Register only ; 144 ;
; -- Combinational with a register ; 195 ;
; Total logic elements ; 646 / 8,256 ( 8 % ) ;
; -- Combinational with no register ; 285 ;
; -- Register only ; 150 ;
; -- Combinational with a register ; 211 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 275 ;
; -- 3 input functions ; 68 ;
; -- <=2 input functions ; 109 ;
; -- Register only ; 144 ;
; -- 4 input functions ; 325 ;
; -- 3 input functions ; 72 ;
; -- <=2 input functions ; 99 ;
; -- Register only ; 150 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 406 ;
; -- normal mode ; 450 ;
; -- arithmetic mode ; 46 ;
; ; ;
; Total registers* ; 339 / 8,646 ( 4 % ) ;
; -- Dedicated logic registers ; 339 / 8,256 ( 4 % ) ;
; Total registers* ; 361 / 8,646 ( 4 % ) ;
; -- Dedicated logic registers ; 361 / 8,256 ( 4 % ) ;
; -- I/O registers ; 0 / 390 ( 0 % ) ;
; ; ;
; Total LABs: partially or completely used ; 47 / 516 ( 9 % ) ;
; Total LABs: partially or completely used ; 53 / 516 ( 10 % ) ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 20 / 138 ( 14 % ) ;
; I/O pins ; 24 / 138 ( 17 % ) ;
; -- Clock pins ; 2 / 4 ( 50 % ) ;
; Global signals ; 2 ;
; M4Ks ; 12 / 36 ( 33 % ) ;
224,28 → 224,32
; JTAGs ; 0 / 1 ( 0 % ) ;
; ASMI blocks ; 0 / 1 ( 0 % ) ;
; CRC blocks ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 2% / 2% / 3% ;
; Peak interconnect usage (total/H/V) ; 6% / 6% / 7% ;
; Average interconnect usage (total/H/V) ; 2% / 3% / 2% ;
; Peak interconnect usage (total/H/V) ; 8% / 8% / 7% ;
; Maximum fan-out node ; clock~clkctrl ;
; Maximum fan-out ; 351 ;
; Maximum fan-out ; 373 ;
; Highest non-global fan-out signal ; reset ;
; Highest non-global fan-out ; 50 ;
; Total fan-out ; 2865 ;
; Average fan-out ; 3.16 ;
; Highest non-global fan-out ; 54 ;
; Total fan-out ; 3136 ;
; Average fan-out ; 3.18 ;
+---------------------------------------------+---------------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
 
 
 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clock ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; reset ; 24 ; 1 ; 0 ; 9 ; 1 ; 51 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; rxd ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clock ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; extint[0] ; 14 ; 1 ; 0 ; 14 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; extint[1] ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; extint[2] ; 145 ; 3 ; 34 ; 14 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; extint[3] ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; reset ; 24 ; 1 ; 0 ; 9 ; 1 ; 55 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; rxd ; 74 ; 4 ; 16 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
 
 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
253,7 → 257,7
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
; txd ; 61 ; 4 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
; txd ; 192 ; 2 ; 9 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
 
 
262,22 → 266,22
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
; p1dio[0] ; 75 ; 4 ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[0] ; - ;
; p1dio[1] ; 189 ; 2 ; 12 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[1] ; - ;
; p1dio[2] ; 74 ; 4 ; 16 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[2] ; - ;
; p1dio[3] ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[3] ; - ;
; p1dio[4] ; 35 ; 1 ; 0 ; 7 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[4] ; - ;
; p1dio[5] ; 70 ; 4 ; 14 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[5] ; - ;
; p1dio[6] ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[6] ; - ;
; p1dio[7] ; 187 ; 2 ; 14 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[7] ; - ;
; p2dio[0] ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[0] ; - ;
; p2dio[1] ; 60 ; 4 ; 3 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[1] ; - ;
; p2dio[2] ; 37 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[2] ; - ;
; p2dio[3] ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[3] ; - ;
; p2dio[4] ; 69 ; 4 ; 12 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[4] ; - ;
; p2dio[5] ; 67 ; 4 ; 9 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[5] ; - ;
; p2dio[6] ; 64 ; 4 ; 5 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[6] ; - ;
; p2dio[7] ; 72 ; 4 ; 16 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[7] ; - ;
; p1dio[0] ; 189 ; 2 ; 12 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[0] ; - ;
; p1dio[1] ; 187 ; 2 ; 14 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[1] ; - ;
; p1dio[2] ; 149 ; 3 ; 34 ; 16 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[2] ; - ;
; p1dio[3] ; 75 ; 4 ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[3] ; - ;
; p1dio[4] ; 171 ; 2 ; 28 ; 19 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[4] ; - ;
; p1dio[5] ; 182 ; 2 ; 18 ; 19 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[5] ; - ;
; p1dio[6] ; 150 ; 3 ; 34 ; 16 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[6] ; - ;
; p1dio[7] ; 180 ; 2 ; 18 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[7] ; - ;
; p2dio[0] ; 191 ; 2 ; 12 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[0] ; - ;
; p2dio[1] ; 188 ; 2 ; 12 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[1] ; - ;
; p2dio[2] ; 176 ; 2 ; 23 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[2] ; - ;
; p2dio[3] ; 185 ; 2 ; 14 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[3] ; - ;
; p2dio[4] ; 173 ; 2 ; 25 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[4] ; - ;
; p2dio[5] ; 179 ; 2 ; 18 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[5] ; - ;
; p2dio[6] ; 181 ; 2 ; 18 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[6] ; - ;
; p2dio[7] ; 175 ; 2 ; 23 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[7] ; - ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
 
 
286,10 → 290,10
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1 ; 8 / 32 ( 25 % ) ; 3.3V ; -- ;
; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;
; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
; 4 ; 12 / 36 ( 33 % ) ; 3.3V ; -- ;
; 1 ; 7 / 32 ( 22 % ) ; 3.3V ; -- ;
; 2 ; 14 / 35 ( 40 % ) ; 3.3V ; -- ;
; 3 ; 4 / 35 ( 11 % ) ; 3.3V ; -- ;
; 4 ; 2 / 36 ( 6 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
 
 
311,7 → 315,7
; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 14 ; 18 ; 1 ; extint[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
324,17 → 328,17
; 24 ; 28 ; 1 ; reset ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; 27 ; 30 ; 1 ; rxd ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 27 ; 30 ; 1 ; extint[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 28 ; 31 ; 1 ; extint[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 30 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 34 ; 36 ; 1 ; p2dio[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 35 ; 37 ; 1 ; p1dio[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 34 ; 36 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 35 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 37 ; 39 ; 1 ; p2dio[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
357,24 → 361,24
; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 60 ; 58 ; 4 ; p2dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 61 ; 59 ; 4 ; txd ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 64 ; 61 ; 4 ; p2dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 67 ; 69 ; 4 ; p2dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 68 ; 70 ; 4 ; p2dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 69 ; 71 ; 4 ; p2dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 70 ; 74 ; 4 ; p1dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 72 ; 75 ; 4 ; p2dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 74 ; 76 ; 4 ; p1dio[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 75 ; 77 ; 4 ; p1dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 76 ; 78 ; 4 ; p1dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 77 ; 79 ; 4 ; p1dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 74 ; 76 ; 4 ; rxd ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 75 ; 77 ; 4 ; p1dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
442,12 → 446,12
; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 145 ; 143 ; 3 ; extint[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 149 ; 151 ; 3 ; p1dio[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 150 ; 152 ; 3 ; p1dio[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
468,28 → 472,28
; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 171 ; 164 ; 2 ; p1dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 173 ; 165 ; 2 ; p2dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 175 ; 168 ; 2 ; p2dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 176 ; 169 ; 2 ; p2dio[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 179 ; 173 ; 2 ; p2dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 180 ; 174 ; 2 ; p1dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 181 ; 175 ; 2 ; p2dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 182 ; 176 ; 2 ; p1dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 185 ; 180 ; 2 ; p2dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 187 ; 181 ; 2 ; p1dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 189 ; 183 ; 2 ; p1dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 187 ; 181 ; 2 ; p1dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 188 ; 182 ; 2 ; p2dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 189 ; 183 ; 2 ; p1dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 191 ; 184 ; 2 ; p2dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 192 ; 185 ; 2 ; txd ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
552,88 → 556,100
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
; |l80soc ; 596 (90) ; 339 (58) ; 0 (0) ; 47616 ; 12 ; 0 ; 0 ; 0 ; 20 ; 0 ; 257 (32) ; 144 (37) ; 195 (15) ; |l80soc ; work ;
; |light8080:cpu| ; 422 (422) ; 218 (218) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 204 (204) ; 89 (89) ; 129 (129) ; |l80soc|light8080:cpu ; ;
; |micro_rom:rom| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom ; ;
; |l80soc ; 646 (101) ; 361 (62) ; 0 (0) ; 47616 ; 12 ; 0 ; 0 ; 0 ; 24 ; 0 ; 285 (39) ; 150 (39) ; 211 (15) ; |l80soc ; work ;
; |intr_ctrl:intrc| ; 27 (27) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 1 (1) ; 13 (13) ; |l80soc|intr_ctrl:intrc ; work ;
; |light8080:cpu| ; 435 (435) ; 222 (222) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 213 (213) ; 92 (92) ; 130 (130) ; |l80soc|light8080:cpu ; ;
; |micro_rom:rom| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom ; work ;
; |altsyncram:Ram0_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0 ; ;
; |altsyncram_ts61:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated ; ;
; |ram_image:ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram ; work ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram|altsyncram:ram_rtl_1 ; ;
; |altsyncram_9il1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated ; ;
; |uart:uart| ; 91 (91) ; 63 (63) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (21) ; 18 (18) ; 52 (52) ; |l80soc|uart:uart ; ;
; |uart:uart| ; 91 (91) ; 63 (63) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (20) ; 18 (18) ; 53 (53) ; |l80soc|uart:uart ; work ;
+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
+-----------------------------------------------------------------------------------+
; Delay Chain Summary ;
+----------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+----------+----------+---------------+---------------+-----------------------+-----+
; p1dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[2] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[4] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p1dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[0] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p2dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[2] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p2dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; txd ; Output ; -- ; -- ; -- ; -- ;
; clock ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; reset ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; rxd ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
+----------+----------+---------------+---------------+-----------------------+-----+
+------------------------------------------------------------------------------------+
; Delay Chain Summary ;
+-----------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+-----------+----------+---------------+---------------+-----------------------+-----+
; p1dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[2] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p1dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p1dio[6] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; p1dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[2] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; p2dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
; txd ; Output ; -- ; -- ; -- ; -- ;
; clock ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; reset ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; extint[1] ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; extint[3] ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;
; extint[2] ; Input ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; extint[0] ; Input ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;
; rxd ; Input ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;
+-----------+----------+---------------+---------------+-----------------------+-----+
 
 
+---------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; p1dio[0] ; ; ;
; - io_dout~3 ; 0 ; 6 ;
; p1dio[1] ; ; ;
; - io_dout~7 ; 0 ; 6 ;
; p1dio[2] ; ; ;
; - io_dout~9 ; 0 ; 6 ;
; p1dio[3] ; ; ;
; - io_dout~11 ; 0 ; 6 ;
; p1dio[4] ; ; ;
; - io_dout~14 ; 1 ; 6 ;
; p1dio[5] ; ; ;
; - io_dout~15 ; 0 ; 6 ;
; p1dio[6] ; ; ;
; - io_dout~17 ; 0 ; 6 ;
; p1dio[7] ; ; ;
; - io_dout~19 ; 0 ; 6 ;
; p2dio[0] ; ; ;
; - io_dout~2 ; 0 ; 6 ;
; p2dio[1] ; ; ;
; - io_dout~7 ; 1 ; 6 ;
; p2dio[2] ; ; ;
; - io_dout~9 ; 0 ; 6 ;
; p2dio[3] ; ; ;
; - io_dout~11 ; 0 ; 6 ;
; p2dio[4] ; ; ;
; - io_dout~13 ; 0 ; 6 ;
; p2dio[5] ; ; ;
; - io_dout~15 ; 0 ; 6 ;
; p2dio[6] ; ; ;
; - io_dout~17 ; 1 ; 6 ;
; p2dio[7] ; ; ;
; - io_dout~19 ; 0 ; 6 ;
; clock ; ; ;
; reset ; ; ;
; rxd ; ; ;
+---------------------+-------------------+---------+
+----------------------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+----------------------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+----------------------------------+-------------------+---------+
; p1dio[0] ; ; ;
; - io_dout~3 ; 1 ; 6 ;
; p1dio[1] ; ; ;
; - io_dout~7 ; 0 ; 6 ;
; p1dio[2] ; ; ;
; - io_dout~9 ; 0 ; 6 ;
; p1dio[3] ; ; ;
; - io_dout~11 ; 0 ; 6 ;
; p1dio[4] ; ; ;
; - io_dout~14 ; 1 ; 6 ;
; p1dio[5] ; ; ;
; - io_dout~15 ; 0 ; 6 ;
; p1dio[6] ; ; ;
; - io_dout~17 ; 0 ; 6 ;
; p1dio[7] ; ; ;
; - io_dout~19 ; 0 ; 6 ;
; p2dio[0] ; ; ;
; - io_dout~2 ; 0 ; 6 ;
; p2dio[1] ; ; ;
; - io_dout~7 ; 0 ; 6 ;
; p2dio[2] ; ; ;
; - io_dout~9 ; 0 ; 6 ;
; p2dio[3] ; ; ;
; - io_dout~11 ; 0 ; 6 ;
; p2dio[4] ; ; ;
; - io_dout~13 ; 1 ; 6 ;
; p2dio[5] ; ; ;
; - io_dout~15 ; 1 ; 6 ;
; p2dio[6] ; ; ;
; - io_dout~17 ; 0 ; 6 ;
; p2dio[7] ; ; ;
; - io_dout~19 ; 1 ; 6 ;
; clock ; ; ;
; reset ; ; ;
; extint[1] ; ; ;
; extint[3] ; ; ;
; extint[2] ; ; ;
; - intr_ctrl:intrc|act_int~5 ; 1 ; 6 ;
; extint[0] ; ; ;
; - intr_ctrl:intrc|act_int~7 ; 0 ; 6 ;
; rxd ; ; ;
; - uart:uart|sserIn~feeder ; 0 ; 6 ;
+----------------------------------+-------------------+---------+
 
 
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
641,67 → 657,72
+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
; clock ; PIN_23 ; 351 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
; comb~0 ; LCCOMB_X12_Y8_N22 ; 8 ; Write enable ; no ; -- ; -- ; -- ;
; io_dout[0]~5 ; LCCOMB_X13_Y6_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|Equal18~0 ; LCCOMB_X14_Y12_N0 ; 4 ; Sync. load ; no ; -- ; -- ; -- ;
; light8080:cpu|T1[2]~3 ; LCCOMB_X15_Y12_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|T2[0]~3 ; LCCOMB_X15_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|addr_low[1]~1 ; LCCOMB_X12_Y8_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|flag_reg[2]~8 ; LCCOMB_X15_Y8_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~209 ; LCCOMB_X14_Y9_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~211 ; LCCOMB_X14_Y9_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~213 ; LCCOMB_X12_Y13_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~215 ; LCCOMB_X16_Y11_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~217 ; LCCOMB_X13_Y10_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~219 ; LCCOMB_X16_Y11_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~221 ; LCCOMB_X14_Y9_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~223 ; LCCOMB_X13_Y10_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~225 ; LCCOMB_X16_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~227 ; LCCOMB_X14_Y9_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~229 ; LCCOMB_X14_Y9_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~231 ; LCCOMB_X16_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~233 ; LCCOMB_X13_Y11_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~235 ; LCCOMB_X13_Y11_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~237 ; LCCOMB_X16_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~239 ; LCCOMB_X16_Y11_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|uc_decode~0 ; LCCOMB_X16_Y9_N26 ; 21 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|uc_ret_addr[4]~1 ; LCCOMB_X16_Y7_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|ucode_field2[7] ; LCFF_X17_Y9_N17 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p1dir[0] ; LCFF_X14_Y7_N31 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[0]~1 ; LCCOMB_X14_Y7_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p1dir[1] ; LCFF_X14_Y7_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[2] ; LCFF_X14_Y7_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[3] ; LCFF_X14_Y7_N15 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[4] ; LCFF_X14_Y7_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[5] ; LCFF_X14_Y7_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[6] ; LCFF_X14_Y7_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[7] ; LCFF_X14_Y7_N27 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1reg[0]~0 ; LCCOMB_X14_Y7_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p2dir[0] ; LCFF_X13_Y7_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[0]~0 ; LCCOMB_X13_Y7_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p2dir[1] ; LCFF_X13_Y7_N13 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[2] ; LCFF_X13_Y7_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[3] ; LCFF_X13_Y7_N21 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[4] ; LCFF_X13_Y7_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[5] ; LCFF_X13_Y7_N29 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[6] ; LCFF_X13_Y7_N27 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[7] ; LCFF_X13_Y7_N25 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2reg[0]~0 ; LCCOMB_X12_Y7_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; reset ; PIN_24 ; 51 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
; reset ; PIN_24 ; 120 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;
; uart:uart|Equal5~10 ; LCCOMB_X9_Y6_N2 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|rxBaudCnt[3]~1 ; LCCOMB_X8_Y6_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxBitCnt[0]~12 ; LCCOMB_X9_Y6_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxBusy ; LCFF_X8_Y6_N29 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|rxData[0]~0 ; LCCOMB_X9_Y6_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxShiftReg[0]~0 ; LCCOMB_X9_Y6_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txBitCnt[0]~6 ; LCCOMB_X8_Y8_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txBusy ; LCFF_X9_Y8_N15 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|txShiftReg[3]~6 ; LCCOMB_X10_Y8_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txShiftReg~14 ; LCCOMB_X10_Y8_N10 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
; uartbaud[15]~1 ; LCCOMB_X10_Y7_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uartbaud[7]~0 ; LCCOMB_X10_Y7_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; clock ; PIN_23 ; 373 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
; comb~0 ; LCCOMB_X18_Y14_N0 ; 8 ; Write enable ; no ; -- ; -- ; -- ;
; intr_ctrl:intrc|Equal3~0 ; LCCOMB_X15_Y14_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; intr_ctrl:intrc|cpu_inst[4]~8 ; LCCOMB_X15_Y14_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
; intr_ctrl:intrc|intSel~15 ; LCCOMB_X15_Y14_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; intr_ena[0]~1 ; LCCOMB_X18_Y14_N8 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; io_dout[0]~5 ; LCCOMB_X17_Y16_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|Equal18~0 ; LCCOMB_X23_Y14_N8 ; 5 ; Sync. load ; no ; -- ; -- ; -- ;
; light8080:cpu|T1[6]~3 ; LCCOMB_X13_Y14_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|T2[2]~3 ; LCCOMB_X13_Y14_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|addr_low[1]~1 ; LCCOMB_X17_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|flag_reg[6]~12 ; LCCOMB_X21_Y14_N28 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|inta_reg ; LCFF_X14_Y14_N17 ; 41 ; Sync. clear ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~209 ; LCCOMB_X24_Y16_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~211 ; LCCOMB_X23_Y13_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~213 ; LCCOMB_X24_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~215 ; LCCOMB_X24_Y11_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~217 ; LCCOMB_X24_Y16_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~219 ; LCCOMB_X24_Y16_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~221 ; LCCOMB_X24_Y16_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~223 ; LCCOMB_X24_Y11_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~225 ; LCCOMB_X24_Y11_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~227 ; LCCOMB_X23_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~229 ; LCCOMB_X24_Y16_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~231 ; LCCOMB_X23_Y13_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~233 ; LCCOMB_X24_Y16_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~235 ; LCCOMB_X24_Y16_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~237 ; LCCOMB_X24_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|rbank~239 ; LCCOMB_X24_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|uc_decode~0 ; LCCOMB_X12_Y14_N20 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|uc_ret_addr[4]~1 ; LCCOMB_X13_Y14_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; light8080:cpu|ucode_field2[7] ; LCFF_X19_Y13_N1 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p1dir[0] ; LCFF_X18_Y14_N25 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[0]~0 ; LCCOMB_X18_Y14_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p1dir[1] ; LCFF_X18_Y16_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[2] ; LCFF_X18_Y14_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[3] ; LCFF_X18_Y14_N29 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[4] ; LCFF_X18_Y14_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[5] ; LCFF_X18_Y14_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[6] ; LCFF_X18_Y16_N17 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1dir[7] ; LCFF_X18_Y14_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p1reg[0]~0 ; LCCOMB_X18_Y16_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p2dir[0] ; LCFF_X19_Y16_N27 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[0]~0 ; LCCOMB_X19_Y16_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; p2dir[1] ; LCFF_X19_Y16_N9 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[2] ; LCFF_X19_Y16_N13 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[3] ; LCFF_X19_Y16_N17 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[4] ; LCFF_X19_Y16_N21 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[5] ; LCFF_X19_Y16_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[6] ; LCFF_X19_Y16_N25 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2dir[7] ; LCFF_X19_Y16_N29 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
; p2reg[0]~0 ; LCCOMB_X18_Y16_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; reset ; PIN_24 ; 55 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
; reset ; PIN_24 ; 138 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;
; uart:uart|Equal5~10 ; LCCOMB_X17_Y15_N10 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|rxBaudCnt[1]~1 ; LCCOMB_X17_Y13_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxBitCnt[1]~12 ; LCCOMB_X16_Y13_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxBusy ; LCFF_X17_Y13_N11 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|rxData[0]~0 ; LCCOMB_X16_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|rxShiftReg[0]~0 ; LCCOMB_X16_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txBitCnt[3]~6 ; LCCOMB_X15_Y15_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txBusy ; LCFF_X17_Y15_N27 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;
; uart:uart|txShiftReg[5]~4 ; LCCOMB_X17_Y15_N24 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
; uart:uart|txShiftReg~2 ; LCCOMB_X17_Y15_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
; uartbaud[15]~3 ; LCCOMB_X18_Y14_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
; uartbaud[7]~2 ; LCCOMB_X21_Y15_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
 
 
710,8 → 731,8
+-------+----------+---------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-------+----------+---------+----------------------+------------------+---------------------------+
; clock ; PIN_23 ; 351 ; Global Clock ; GCLK2 ; -- ;
; reset ; PIN_24 ; 120 ; Global Clock ; GCLK1 ; -- ;
; clock ; PIN_23 ; 373 ; Global Clock ; GCLK2 ; -- ;
; reset ; PIN_24 ; 138 ; Global Clock ; GCLK1 ; -- ;
+-------+----------+---------+----------------------+------------------+---------------------------+
 
 
720,24 → 741,24
+------------------------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+------------------------------------------------------------------------------------------------+---------+
; reset ; 50 ;
; reset ; 54 ;
; light8080:cpu|inta_reg ; 41 ;
; light8080:cpu|Mux10~1 ; 31 ;
; light8080:cpu|Mux11~1 ; 31 ;
; light8080:cpu|Mux8~1 ; 31 ;
; light8080:cpu|Mux9~1 ; 31 ;
; light8080:cpu|addr_low[0] ; 26 ;
; light8080:cpu|ucode_field2[4] ; 25 ;
; light8080:cpu|ucode_field2[4] ; 24 ;
; light8080:cpu|addr_low[1] ; 24 ;
; uart:uart|txBusy ; 24 ;
; light8080:cpu|addr_low[1] ; 23 ;
; light8080:cpu|addr_low[3] ; 23 ;
; light8080:cpu|addr_low[2] ; 23 ;
; light8080:cpu|addr_low[0] ; 23 ;
; light8080:cpu|uc_decode~0 ; 22 ;
; light8080:cpu|ucode_field2[0] ; 21 ;
; light8080:cpu|ucode_field2[1] ; 21 ;
; light8080:cpu|uc_decode~0 ; 21 ;
; light8080:cpu|addr_low[2] ; 21 ;
; light8080:cpu|DO[4]~1 ; 21 ;
; light8080:cpu|Mux20~3 ; 20 ;
; light8080:cpu|Mux27~1 ; 20 ;
; light8080:cpu|ucode_field2[2] ; 20 ;
; light8080:cpu|addr_low[3] ; 20 ;
; light8080:cpu|DO[4]~1 ; 20 ;
; light8080:cpu|Mux22~5 ; 19 ;
; light8080:cpu|Mux21~3 ; 19 ;
; light8080:cpu|rbank~207 ; 19 ;
747,40 → 768,40
; light8080:cpu|DO[2]~0 ; 19 ;
; light8080:cpu|Mux24~7 ; 18 ;
; light8080:cpu|Mux26~8 ; 18 ;
; light8080:cpu|ucode_field2[18] ; 17 ;
; light8080:cpu|ucode_field2[17] ; 17 ;
; light8080:cpu|ucode_field2[16] ; 17 ;
; light8080:cpu|ucode_field2[18] ; 18 ;
; light8080:cpu|ucode_field2[17] ; 18 ;
; light8080:cpu|ucode_field2[16] ; 18 ;
; light8080:cpu|ucode_field2[6] ; 17 ;
; light8080:cpu|ucode_field2[15] ; 17 ;
; light8080:cpu|ucode_field2[6] ; 17 ;
; light8080:cpu|Mux20~3 ; 17 ;
; uart:uart|Equal5~10 ; 17 ;
; light8080:cpu|addr_low[4] ; 17 ;
; light8080:cpu|addr_low[5] ; 17 ;
; light8080:cpu|addr_low[6] ; 17 ;
; light8080:cpu|addr_low[7] ; 17 ;
; light8080:cpu|we_rb~0 ; 16 ;
; uart:uart|rxBusy ; 13 ;
; light8080:cpu|Equal13~0 ; 13 ;
; light8080:cpu|ucode_field2[3] ; 12 ;
; uart:uart|baudCE16 ; 12 ;
; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a26 ; 11 ;
; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a26 ; 12 ;
; intr_ctrl:intrc|intSq[0] ; 11 ;
; intr_ctrl:intrc|always0~0 ; 11 ;
; intr_ctrl:intrc|intSq[1] ; 11 ;
; light8080:cpu|T1[2] ; 9 ;
; io_dout[0]~0 ; 9 ;
; light8080:cpu|T1[2] ; 9 ;
; light8080:cpu|Equal19~1 ; 9 ;
; light8080:cpu|ucode_field2[5] ; 9 ;
; light8080:cpu|T1[0] ; 9 ;
; uart:uart|rxShiftReg[0]~0 ; 8 ;
; uart:uart|rxData[0]~0 ; 8 ;
; light8080:cpu|T2[0]~3 ; 8 ;
+------------------------------------------------------------------------------------------------+---------+
 
 
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 512 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 16384 ; 512 ; 29 ; -- ; -- ; 14848 ; 4 ; db/l80soc.rom0_micro_rom_cd0ab125.hdl.mif ; M4K_X11_Y9, M4K_X11_Y5, M4K_X27_Y9, M4K_X27_Y7 ;
; ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 8 ; 4096 ; 8 ; yes ; no ; yes ; no ; 32768 ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 8 ; db/l80soc.ram0_ram_image_778cd75f.hdl.mif ; M4K_X11_Y11, M4K_X11_Y14, M4K_X11_Y13, M4K_X11_Y6, M4K_X11_Y7, M4K_X11_Y12, M4K_X11_Y8, M4K_X11_Y10 ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+--------------------------------------------------------------------------------------------------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+--------------------------------------------------------------------------------------------------------+
; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 512 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 16384 ; 512 ; 29 ; -- ; -- ; 14848 ; 4 ; db/l80soc.rom0_micro_rom_cd0ab125.hdl.mif ; M4K_X11_Y14, M4K_X11_Y15, M4K_X11_Y13, M4K_X11_Y12 ;
; ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 8 ; 4096 ; 8 ; yes ; no ; yes ; no ; 32768 ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 8 ; db/l80soc.ram0_ram_image_778cd75f.hdl.mif ; M4K_X27_Y17, M4K_X27_Y12, M4K_X27_Y13, M4K_X27_Y14, M4K_X27_Y11, M4K_X27_Y16, M4K_X11_Y16, M4K_X27_Y15 ;
+---------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+--------------------------------------------------------------------------------------------------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
 
 
789,14 → 810,14
+----------------------------+------------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------------+
; Block interconnects ; 1,076 / 26,052 ( 4 % ) ;
; C16 interconnects ; 8 / 1,156 ( < 1 % ) ;
; C4 interconnects ; 558 / 17,952 ( 3 % ) ;
; Direct links ; 135 / 26,052 ( < 1 % ) ;
; Block interconnects ; 1,081 / 26,052 ( 4 % ) ;
; C16 interconnects ; 4 / 1,156 ( < 1 % ) ;
; C4 interconnects ; 469 / 17,952 ( 3 % ) ;
; Direct links ; 175 / 26,052 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; Local interconnects ; 275 / 8,256 ( 3 % ) ;
; R24 interconnects ; 12 / 1,020 ( 1 % ) ;
; R4 interconnects ; 533 / 22,440 ( 2 % ) ;
; Local interconnects ; 306 / 8,256 ( 4 % ) ;
; R24 interconnects ; 23 / 1,020 ( 2 % ) ;
; R4 interconnects ; 621 / 22,440 ( 3 % ) ;
+----------------------------+------------------------+
 
 
803,24 → 824,24
+----------------------------------------------------------------------------+
; LAB Logic Elements ;
+---------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 12.68) ; Number of LABs (Total = 47) ;
; Number of Logic Elements (Average = 12.19) ; Number of LABs (Total = 53) ;
+---------------------------------------------+------------------------------+
; 1 ; 2 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 1 ; 5 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 2 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 3 ;
; 11 ; 3 ;
; 12 ; 1 ;
; 13 ; 2 ;
; 14 ; 1 ;
; 15 ; 4 ;
; 16 ; 24 ;
; 13 ; 1 ;
; 14 ; 3 ;
; 15 ; 3 ;
; 16 ; 27 ;
+---------------------------------------------+------------------------------+
 
 
827,13 → 848,13
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.98) ; Number of LABs (Total = 47) ;
; LAB-wide Signals (Average = 1.87) ; Number of LABs (Total = 53) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 13 ;
; 1 Clock ; 47 ;
; 1 Clock enable ; 13 ;
; 1 Sync. clear ; 4 ;
; 2 Clock enables ; 16 ;
; 1 Async. clear ; 17 ;
; 1 Clock ; 49 ;
; 1 Clock enable ; 17 ;
; 1 Sync. clear ; 2 ;
; 2 Clock enables ; 14 ;
+------------------------------------+------------------------------+
 
 
840,41 → 861,41
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 18.47) ; Number of LABs (Total = 47) ;
; Number of Signals Sourced (Average = 17.79) ; Number of LABs (Total = 53) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 1 ; 3 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 3 ;
; 12 ; 0 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 2 ;
; 13 ; 0 ;
; 14 ; 2 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 16 ; 1 ;
; 17 ; 2 ;
; 16 ; 3 ;
; 17 ; 4 ;
; 18 ; 4 ;
; 19 ; 3 ;
; 20 ; 3 ;
; 19 ; 1 ;
; 20 ; 1 ;
; 21 ; 2 ;
; 22 ; 4 ;
; 23 ; 3 ;
; 24 ; 3 ;
; 25 ; 3 ;
; 26 ; 1 ;
; 24 ; 7 ;
; 25 ; 2 ;
; 26 ; 3 ;
; 27 ; 1 ;
; 28 ; 2 ;
; 28 ; 0 ;
; 29 ; 1 ;
; 30 ; 0 ;
; 31 ; 0 ;
; 32 ; 1 ;
; 32 ; 2 ;
+----------------------------------------------+------------------------------+
 
 
881,25 → 902,27
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 9.00) ; Number of LABs (Total = 47) ;
; Number of Signals Sourced Out (Average = 8.58) ; Number of LABs (Total = 53) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 4 ;
; 5 ; 0 ;
; 1 ; 6 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 3 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 5 ;
; 8 ; 1 ;
; 9 ; 5 ;
; 10 ; 2 ;
; 11 ; 7 ;
; 12 ; 5 ;
; 13 ; 6 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 16 ; 3 ;
; 8 ; 6 ;
; 9 ; 4 ;
; 10 ; 4 ;
; 11 ; 3 ;
; 12 ; 3 ;
; 13 ; 2 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 6 ;
; 17 ; 0 ;
; 18 ; 1 ;
+-------------------------------------------------+------------------------------+
 
 
906,15 → 929,15
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 18.77) ; Number of LABs (Total = 47) ;
; Number of Distinct Inputs (Average = 16.68) ; Number of LABs (Total = 53) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 2 ; 0 ;
; 3 ; 3 ;
; 4 ; 4 ;
; 5 ; 3 ;
; 6 ; 1 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 2 ;
923,22 → 946,22
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 0 ;
; 17 ; 4 ;
; 18 ; 2 ;
; 19 ; 0 ;
; 20 ; 1 ;
; 21 ; 2 ;
; 22 ; 1 ;
; 23 ; 3 ;
; 15 ; 4 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 4 ;
; 19 ; 1 ;
; 20 ; 2 ;
; 21 ; 1 ;
; 22 ; 2 ;
; 23 ; 5 ;
; 24 ; 2 ;
; 25 ; 1 ;
; 26 ; 4 ;
; 27 ; 1 ;
; 28 ; 5 ;
; 29 ; 0 ;
; 30 ; 2 ;
; 25 ; 2 ;
; 26 ; 1 ;
; 27 ; 0 ;
; 28 ; 2 ;
; 29 ; 2 ;
; 30 ; 1 ;
; 31 ; 3 ;
+----------------------------------------------+------------------------------+
 
985,7 → 1008,7
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Tue Feb 21 12:01:04 2012
Info: Processing started: Sat Mar 03 19:53:56 2012
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off l80soc -c l80soc
Info: Selected device EP2C8Q208C8 for design "l80soc"
Info: Low junction temperature is 0 degrees C
1001,7 → 1024,7
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning: No exact pin location assignment(s) for 20 pins of 20 total pins
Critical Warning: No exact pin location assignment(s) for 24 pins of 24 total pins
Info: Pin p1dio[0] not assigned to an exact location on the device
Info: Pin p1dio[1] not assigned to an exact location on the device
Info: Pin p1dio[2] not assigned to an exact location on the device
1021,6 → 1044,10
Info: Pin txd not assigned to an exact location on the device
Info: Pin clock not assigned to an exact location on the device
Info: Pin reset not assigned to an exact location on the device
Info: Pin extint[1] not assigned to an exact location on the device
Info: Pin extint[3] not assigned to an exact location on the device
Info: Pin extint[2] not assigned to an exact location on the device
Info: Pin extint[0] not assigned to an exact location on the device
Info: Pin rxd not assigned to an exact location on the device
Info: Timing-driven compilation is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
1029,16 → 1056,16
Info: Automatically promoted node reset (placed in PIN 24 (CLK1, LVDSCLK0n, Input))
Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node light8080:cpu|inte_reg
Info: Destination node light8080:cpu|condition_reg
Info: Destination node light8080:cpu|inta_reg
Info: Destination node light8080:cpu|delayed_ei
Info: Destination node light8080:cpu|flag_reg[0]
Info: Destination node light8080:cpu|flag_reg[6]
Info: Destination node light8080:cpu|flag_reg[2]
Info: Destination node light8080:cpu|int_pending
Info: Destination node light8080:cpu|daa_res9[1]
Info: Destination node light8080:cpu|daa_res9[2]
Info: Destination node light8080:cpu|daa_res9[3]
Info: Destination node light8080:cpu|daa_res9[4]
Info: Destination node light8080:cpu|flag_reg[4]
Info: Destination node light8080:cpu|daa_res9[5]
Info: Non-global destination nodes limited to 10 nodes
Info: Starting register packing
Extra Info: Performing register packing on registers with non-logic cell location assignments
1050,7 → 1077,7
Info: Finished register packing
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 18 (unused VREF, 3.3V VCCIO, 1 input, 1 output, 16 bidirectional)
Info: Number of I/O pins in group: 22 (unused VREF, 3.3V VCCIO, 5 input, 1 output, 16 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
1064,22 → 1091,21
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is memory to register delay of 13.149 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16~porta_address_reg8'
Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X11_Y5; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16'
Info: 3: + IC(0.892 ns) + CELL(0.624 ns) = 5.277 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'light8080:cpu|Mux10~0'
Info: 4: + IC(0.160 ns) + CELL(0.651 ns) = 6.088 ns; Loc. = LAB_X12_Y9; Fanout = 31; COMB Node = 'light8080:cpu|Mux10~1'
Info: 5: + IC(1.157 ns) + CELL(0.370 ns) = 7.615 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'light8080:cpu|rbank~172'
Info: 6: + IC(1.173 ns) + CELL(0.366 ns) = 9.154 ns; Loc. = LAB_X13_Y13; Fanout = 1; COMB Node = 'light8080:cpu|rbank~173'
Info: 7: + IC(1.337 ns) + CELL(0.206 ns) = 10.697 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'light8080:cpu|rbank~174'
Info: 8: + IC(0.441 ns) + CELL(0.366 ns) = 11.504 ns; Loc. = LAB_X12_Y10; Fanout = 19; COMB Node = 'light8080:cpu|rbank~177'
Info: 9: + IC(0.887 ns) + CELL(0.650 ns) = 13.041 ns; Loc. = LAB_X13_Y12; Fanout = 1; COMB Node = 'light8080:cpu|T2~9'
Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 13.149 ns; Loc. = LAB_X13_Y12; Fanout = 3; REG Node = 'light8080:cpu|T2[2]'
Info: Total cell delay = 7.102 ns ( 54.01 % )
Info: Total interconnect delay = 6.047 ns ( 45.99 % )
Info: Estimated most critical path is memory to memory delay of 14.801 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y13; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16~porta_address_reg8'
Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X11_Y13; Fanout = 1; MEM Node = 'light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16'
Info: 3: + IC(2.001 ns) + CELL(0.624 ns) = 6.386 ns; Loc. = LAB_X24_Y15; Fanout = 1; COMB Node = 'light8080:cpu|Mux10~0'
Info: 4: + IC(0.160 ns) + CELL(0.651 ns) = 7.197 ns; Loc. = LAB_X24_Y15; Fanout = 31; COMB Node = 'light8080:cpu|Mux10~1'
Info: 5: + IC(1.158 ns) + CELL(0.370 ns) = 8.725 ns; Loc. = LAB_X24_Y14; Fanout = 1; COMB Node = 'light8080:cpu|rbank~182'
Info: 6: + IC(0.441 ns) + CELL(0.366 ns) = 9.532 ns; Loc. = LAB_X24_Y14; Fanout = 1; COMB Node = 'light8080:cpu|rbank~183'
Info: 7: + IC(1.697 ns) + CELL(0.206 ns) = 11.435 ns; Loc. = LAB_X26_Y15; Fanout = 1; COMB Node = 'light8080:cpu|rbank~184'
Info: 8: + IC(0.441 ns) + CELL(0.366 ns) = 12.242 ns; Loc. = LAB_X26_Y15; Fanout = 19; COMB Node = 'light8080:cpu|rbank~187'
Info: 9: + IC(2.383 ns) + CELL(0.176 ns) = 14.801 ns; Loc. = M4K_X11_Y16; Fanout = 0; MEM Node = 'ram_image:ram|altsyncram:ram_rtl_1|altsyncram_9il1:auto_generated|ram_block1a6~porta_address_reg10'
Info: Total cell delay = 6.520 ns ( 44.05 % )
Info: Total interconnect delay = 8.281 ns ( 55.95 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources
Info: Peak interconnect usage is 6% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9
Info: Peak interconnect usage is 7% of the available device resources in the region that extends from location X11_Y10 to location X22_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
1107,8 → 1133,8
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 208 megabytes
Info: Processing ended: Tue Feb 21 12:01:11 2012
Info: Peak virtual memory: 207 megabytes
Info: Processing ended: Sat Mar 03 19:54:03 2012
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:06
 

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