URL
https://opencores.org/ocsvn/light8080/light8080/trunk
Subversion Repositories light8080
Compare Revisions
- This comparison shows the changes necessary to convert path
/light8080
- from Rev 73 to Rev 74
- ↔ Reverse comparison
Rev 73 → Rev 74
/trunk/asm/readme.txt
File deleted
/trunk/asm/tasmtb.bat
File deleted
\ No newline at end of file
/trunk/asm/hexconv.pl
File deleted
/trunk/asm/tb0.asm
File deleted
/trunk/asm/tb1.asm
File deleted
\ No newline at end of file
/trunk/sw/tb/tb0/obj_code_pkg.vhdl
0,0 → 1,210
-- obj_code_pkg -- Object code in VHDL constant table for BRAM initialization. |
-- Generated automatically with script 'build_rom.py'. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.l80pkg.all; |
|
package obj_code_pkg is |
|
constant obj_code : obj_code_t(0 to 1566) := ( |
X"31", X"1d", X"06", X"3e", X"77", X"e6", X"00", X"ca", |
X"0d", X"00", X"cd", X"0a", X"05", X"d2", X"13", X"00", |
X"cd", X"0a", X"05", X"ea", X"19", X"00", X"cd", X"0a", |
X"05", X"f2", X"1f", X"00", X"cd", X"0a", X"05", X"c2", |
X"2e", X"00", X"da", X"2e", X"00", X"e2", X"2e", X"00", |
X"fa", X"2e", X"00", X"c3", X"31", X"00", X"cd", X"0a", |
X"05", X"c6", X"06", X"c2", X"39", X"00", X"cd", X"0a", |
X"05", X"da", X"42", X"00", X"e2", X"42", X"00", X"f2", |
X"45", X"00", X"cd", X"0a", X"05", X"c6", X"70", X"e2", |
X"4d", X"00", X"cd", X"0a", X"05", X"fa", X"56", X"00", |
X"ca", X"56", X"00", X"d2", X"59", X"00", X"cd", X"0a", |
X"05", X"c6", X"81", X"fa", X"61", X"00", X"cd", X"0a", |
X"05", X"ca", X"6a", X"00", X"da", X"6a", X"00", X"e2", |
X"6d", X"00", X"cd", X"0a", X"05", X"c6", X"fe", X"da", |
X"75", X"00", X"cd", X"0a", X"05", X"ca", X"7e", X"00", |
X"e2", X"7e", X"00", X"fa", X"81", X"00", X"cd", X"0a", |
X"05", X"fe", X"00", X"da", X"99", X"00", X"ca", X"99", |
X"00", X"fe", X"f5", X"da", X"99", X"00", X"c2", X"99", |
X"00", X"fe", X"ff", X"ca", X"99", X"00", X"da", X"9c", |
X"00", X"cd", X"0a", X"05", X"ce", X"0a", X"ce", X"0a", |
X"fe", X"0b", X"ca", X"a8", X"00", X"cd", X"0a", X"05", |
X"d6", X"0c", X"d6", X"0f", X"fe", X"f0", X"ca", X"b4", |
X"00", X"cd", X"0a", X"05", X"de", X"f1", X"de", X"0e", |
X"fe", X"f0", X"ca", X"c0", X"00", X"cd", X"0a", X"05", |
X"e6", X"55", X"dc", X"0a", X"05", X"cc", X"0a", X"05", |
X"fe", X"50", X"ca", X"d0", X"00", X"cd", X"0a", X"05", |
X"f6", X"3a", X"dc", X"0a", X"05", X"cc", X"0a", X"05", |
X"fe", X"7a", X"ca", X"e0", X"00", X"cd", X"0a", X"05", |
X"ee", X"0f", X"dc", X"0a", X"05", X"cc", X"0a", X"05", |
X"fe", X"75", X"ca", X"f0", X"00", X"cd", X"0a", X"05", |
X"e6", X"00", X"dc", X"0a", X"05", X"e4", X"0a", X"05", |
X"fc", X"0a", X"05", X"c4", X"0a", X"05", X"fe", X"00", |
X"ca", X"06", X"01", X"cd", X"0a", X"05", X"d6", X"77", |
X"d4", X"0a", X"05", X"ec", X"0a", X"05", X"f4", X"0a", |
X"05", X"cc", X"0a", X"05", X"fe", X"89", X"ca", X"1c", |
X"01", X"cd", X"0a", X"05", X"e6", X"ff", X"e4", X"29", |
X"01", X"fe", X"d9", X"ca", X"86", X"01", X"cd", X"0a", |
X"05", X"e8", X"c6", X"10", X"ec", X"35", X"01", X"c6", |
X"02", X"e0", X"cd", X"0a", X"05", X"e0", X"c6", X"20", |
X"fc", X"41", X"01", X"c6", X"04", X"e8", X"cd", X"0a", |
X"05", X"f0", X"c6", X"80", X"f4", X"4d", X"01", X"c6", |
X"80", X"f8", X"cd", X"0a", X"05", X"f8", X"c6", X"40", |
X"d4", X"59", X"01", X"c6", X"40", X"f0", X"cd", X"0a", |
X"05", X"d8", X"c6", X"8f", X"dc", X"65", X"01", X"d6", |
X"02", X"d0", X"cd", X"0a", X"05", X"d0", X"c6", X"f7", |
X"c4", X"71", X"01", X"c6", X"fe", X"d8", X"cd", X"0a", |
X"05", X"c8", X"c6", X"01", X"cc", X"7d", X"01", X"c6", |
X"d0", X"c0", X"cd", X"0a", X"05", X"c0", X"c6", X"47", |
X"fe", X"47", X"c8", X"cd", X"0a", X"05", X"3e", X"77", |
X"3c", X"47", X"04", X"48", X"0d", X"51", X"5a", X"63", |
X"6c", X"7d", X"3d", X"4f", X"59", X"6b", X"45", X"50", |
X"62", X"7c", X"57", X"14", X"6a", X"4d", X"0c", X"61", |
X"44", X"05", X"58", X"7b", X"5f", X"1c", X"43", X"60", |
X"24", X"4c", X"69", X"55", X"15", X"7a", X"67", X"25", |
X"54", X"42", X"68", X"2c", X"5d", X"1d", X"4b", X"79", |
X"6f", X"2d", X"65", X"5c", X"53", X"4a", X"41", X"78", |
X"fe", X"77", X"c4", X"0a", X"05", X"af", X"06", X"01", |
X"0e", X"03", X"16", X"07", X"1e", X"0f", X"26", X"1f", |
X"2e", X"3f", X"80", X"81", X"82", X"83", X"84", X"85", |
X"87", X"fe", X"f0", X"c4", X"0a", X"05", X"90", X"91", |
X"92", X"93", X"94", X"95", X"fe", X"78", X"c4", X"0a", |
X"05", X"97", X"c4", X"0a", X"05", X"3e", X"80", X"87", |
X"06", X"01", X"0e", X"02", X"16", X"03", X"1e", X"04", |
X"26", X"05", X"2e", X"06", X"88", X"06", X"80", X"80", |
X"80", X"89", X"80", X"80", X"8a", X"80", X"80", X"8b", |
X"80", X"80", X"8c", X"80", X"80", X"8d", X"80", X"80", |
X"8f", X"fe", X"37", X"c4", X"0a", X"05", X"3e", X"80", |
X"87", X"06", X"01", X"98", X"06", X"ff", X"80", X"99", |
X"80", X"9a", X"80", X"9b", X"80", X"9c", X"80", X"9d", |
X"fe", X"e0", X"c4", X"0a", X"05", X"3e", X"80", X"87", |
X"9f", X"fe", X"ff", X"c4", X"0a", X"05", X"3e", X"ff", |
X"06", X"fe", X"0e", X"fc", X"16", X"ef", X"1e", X"7f", |
X"26", X"f4", X"2e", X"bf", X"37", X"a7", X"dc", X"0a", |
X"05", X"a1", X"a2", X"a3", X"a4", X"a5", X"a7", X"fe", |
X"24", X"c4", X"0a", X"05", X"af", X"06", X"01", X"0e", |
X"02", X"16", X"04", X"1e", X"08", X"26", X"10", X"2e", |
X"20", X"37", X"b0", X"dc", X"0a", X"05", X"b1", X"b2", |
X"b3", X"b4", X"b5", X"b7", X"fe", X"3f", X"c4", X"0a", |
X"05", X"3e", X"00", X"26", X"8f", X"2e", X"4f", X"37", |
X"a8", X"dc", X"0a", X"05", X"a9", X"aa", X"ab", X"ac", |
X"ad", X"fe", X"cf", X"c4", X"0a", X"05", X"af", X"c4", |
X"0a", X"05", X"06", X"44", X"0e", X"45", X"16", X"46", |
X"1e", X"47", X"26", X"05", X"2e", X"16", X"70", X"06", |
X"00", X"46", X"3e", X"44", X"b8", X"c4", X"0a", X"05", |
X"72", X"16", X"00", X"56", X"3e", X"46", X"ba", X"c4", |
X"0a", X"05", X"73", X"1e", X"00", X"5e", X"3e", X"47", |
X"bb", X"c4", X"0a", X"05", X"74", X"26", X"05", X"2e", |
X"16", X"66", X"3e", X"05", X"bc", X"c4", X"0a", X"05", |
X"75", X"26", X"05", X"2e", X"16", X"6e", X"3e", X"16", |
X"bd", X"c4", X"0a", X"05", X"26", X"05", X"2e", X"16", |
X"3e", X"32", X"77", X"be", X"c4", X"0a", X"05", X"86", |
X"fe", X"64", X"c4", X"0a", X"05", X"af", X"7e", X"fe", |
X"32", X"c4", X"0a", X"05", X"26", X"05", X"2e", X"16", |
X"7e", X"96", X"c4", X"0a", X"05", X"3e", X"80", X"87", |
X"8e", X"fe", X"33", X"c4", X"0a", X"05", X"3e", X"80", |
X"87", X"9e", X"fe", X"cd", X"c4", X"0a", X"05", X"37", |
X"a6", X"dc", X"0a", X"05", X"c4", X"0a", X"05", X"3e", |
X"25", X"37", X"b6", X"dc", X"0a", X"05", X"fe", X"37", |
X"c4", X"0a", X"05", X"37", X"ae", X"dc", X"0a", X"05", |
X"fe", X"05", X"c4", X"0a", X"05", X"36", X"55", X"34", |
X"35", X"86", X"fe", X"5a", X"c4", X"0a", X"05", X"01", |
X"ff", X"12", X"11", X"ff", X"12", X"21", X"ff", X"12", |
X"03", X"13", X"23", X"3e", X"13", X"b8", X"c4", X"0a", |
X"05", X"ba", X"c4", X"0a", X"05", X"bc", X"c4", X"0a", |
X"05", X"3e", X"00", X"b9", X"c4", X"0a", X"05", X"bb", |
X"c4", X"0a", X"05", X"bd", X"c4", X"0a", X"05", X"0b", |
X"1b", X"2b", X"3e", X"12", X"b8", X"c4", X"0a", X"05", |
X"ba", X"c4", X"0a", X"05", X"bc", X"c4", X"0a", X"05", |
X"3e", X"ff", X"b9", X"c4", X"0a", X"05", X"bb", X"c4", |
X"0a", X"05", X"bd", X"c4", X"0a", X"05", X"32", X"16", |
X"05", X"af", X"3a", X"16", X"05", X"fe", X"ff", X"c4", |
X"0a", X"05", X"2a", X"14", X"05", X"22", X"16", X"05", |
X"3a", X"14", X"05", X"47", X"3a", X"16", X"05", X"b8", |
X"c4", X"0a", X"05", X"3a", X"15", X"05", X"47", X"3a", |
X"17", X"05", X"b8", X"c4", X"0a", X"05", X"3e", X"aa", |
X"32", X"16", X"05", X"44", X"4d", X"af", X"0a", X"fe", |
X"aa", X"c4", X"0a", X"05", X"3c", X"02", X"3a", X"16", |
X"05", X"fe", X"ab", X"c4", X"0a", X"05", X"3e", X"77", |
X"32", X"16", X"05", X"2a", X"14", X"05", X"11", X"00", |
X"00", X"eb", X"af", X"1a", X"fe", X"77", X"c4", X"0a", |
X"05", X"af", X"84", X"85", X"c4", X"0a", X"05", X"3e", |
X"cc", X"12", X"3a", X"16", X"05", X"fe", X"cc", X"12", |
X"3a", X"16", X"05", X"fe", X"cc", X"c4", X"0a", X"05", |
X"21", X"77", X"77", X"29", X"3e", X"ee", X"bc", X"c4", |
X"0a", X"05", X"bd", X"c4", X"0a", X"05", X"21", X"55", |
X"55", X"01", X"ff", X"ff", X"09", X"3e", X"55", X"d4", |
X"0a", X"05", X"bc", X"c4", X"0a", X"05", X"3e", X"54", |
X"bd", X"c4", X"0a", X"05", X"21", X"aa", X"aa", X"11", |
X"33", X"33", X"19", X"3e", X"dd", X"bc", X"c4", X"0a", |
X"05", X"bd", X"c4", X"0a", X"05", X"37", X"d4", X"0a", |
X"05", X"3f", X"dc", X"0a", X"05", X"3e", X"aa", X"2f", |
X"fe", X"55", X"c4", X"0a", X"05", X"b7", X"27", X"fe", |
X"55", X"c4", X"0a", X"05", X"3e", X"88", X"87", X"27", |
X"fe", X"76", X"c4", X"0a", X"05", X"af", X"3e", X"aa", |
X"27", X"d4", X"0a", X"05", X"fe", X"10", X"c4", X"0a", |
X"05", X"af", X"3e", X"9a", X"27", X"d4", X"0a", X"05", |
X"c4", X"0a", X"05", X"37", X"3e", X"42", X"07", X"dc", |
X"0a", X"05", X"07", X"d4", X"0a", X"05", X"fe", X"09", |
X"c4", X"0a", X"05", X"0f", X"d4", X"0a", X"05", X"0f", |
X"fe", X"42", X"c4", X"0a", X"05", X"17", X"17", X"d4", |
X"0a", X"05", X"fe", X"08", X"c4", X"0a", X"05", X"1f", |
X"1f", X"dc", X"0a", X"05", X"fe", X"02", X"c4", X"0a", |
X"05", X"01", X"34", X"12", X"11", X"aa", X"aa", X"21", |
X"55", X"55", X"af", X"c5", X"d5", X"e5", X"f5", X"01", |
X"00", X"00", X"11", X"00", X"00", X"21", X"00", X"00", |
X"3e", X"c0", X"c6", X"f0", X"f1", X"e1", X"d1", X"c1", |
X"dc", X"0a", X"05", X"c4", X"0a", X"05", X"e4", X"0a", |
X"05", X"fc", X"0a", X"05", X"3e", X"12", X"b8", X"c4", |
X"0a", X"05", X"3e", X"34", X"b9", X"c4", X"0a", X"05", |
X"3e", X"aa", X"ba", X"c4", X"0a", X"05", X"bb", X"c4", |
X"0a", X"05", X"3e", X"55", X"bc", X"c4", X"0a", X"05", |
X"bd", X"c4", X"0a", X"05", X"21", X"00", X"00", X"39", |
X"22", X"1b", X"05", X"31", X"1a", X"05", X"3b", X"3b", |
X"33", X"3b", X"3e", X"55", X"32", X"18", X"05", X"2f", |
X"32", X"19", X"05", X"c1", X"b8", X"c4", X"0a", X"05", |
X"2f", X"b9", X"c4", X"0a", X"05", X"21", X"1a", X"05", |
X"f9", X"21", X"33", X"77", X"3b", X"3b", X"e3", X"3a", |
X"19", X"05", X"fe", X"77", X"c4", X"0a", X"05", X"3a", |
X"18", X"05", X"fe", X"33", X"c4", X"0a", X"05", X"3e", |
X"55", X"bd", X"c4", X"0a", X"05", X"2f", X"bc", X"c4", |
X"0a", X"05", X"2a", X"1b", X"05", X"f9", X"21", X"0f", |
X"05", X"e9", X"3e", X"aa", X"d3", X"20", X"76", X"3e", |
X"55", X"d3", X"20", X"76", X"16", X"05", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00" |
); |
|
end package obj_code_pkg; |
/trunk/sw/tb/tb0/build.bat
0,0 → 1,26
@rem Build script for the TB0 test bench. |
@rem This script will assemble the program source and run the object code |
@rem conversion tool to build a vhdl package that can then be used to initalize |
@rem the test bench entity. |
@rem You need to edit this file with the path to your TASM installation. |
@rem Set the program name. |
@set PROG=tb0 |
@rem Edit to point to the directory you installed TASM in. |
@set TASM_DIR=..\..\..\local\tasm |
@rem Remove output from previous assembly. |
@del %PROG%.hex |
@del %PROG%.lst |
@rem Make sure TASM is able to find its table files (see TASM documentation). |
@set TASMTABS=%TASM_DIR% |
@rem Run assembler |
%TASM_DIR%\tasm -85 -a %PROG%.asm %PROG%.hex %PROG%.lst |
@rem Check TASM return value |
@if errorlevel 1 goto done |
@rem Build vhdl test bench file with object code embedded into it. |
python ..\..\..\tools\obj2hdl\src\obj2hdl.py ^ |
-f %PROG%.hex ^ |
-c obj_code ^ |
--package obj_code_pkg ^ |
--output obj_code_pkg.vhdl |
:done |
|
/trunk/sw/tb/tb0/tb0.asm
0,0 → 1,851
;*********************************************************************** |
; MICROCOSM ASSOCIATES 8080/8085 CPU DIAGNOSTIC VERSION 1.0 (C) 1980 |
;*********************************************************************** |
; |
;DONATED TO THE "SIG/M" CP/M USER'S GROUP BY: |
;KELLY SMITH, MICROCOSM ASSOCIATES |
;3055 WACO AVENUE |
;SIMI VALLEY, CALIFORNIA, 93065 |
;(805) 527-9321 (MODEM, CP/M-NET (TM)) |
;(805) 527-0518 (VERBAL) |
; |
;*********************************************************************** |
; Modified 2001/02/28 by Richard Cini for use in the Altair32 Emulator |
; Project |
; |
; Need to somehow connect this code to Windows so that failure messages |
; can be posted to Windows. Maybe just store error code in |
; Mem[0xffff]. Maybe trap NOP in the emulator code? |
; |
;*********************************************************************** |
; Modified 2006/11/16 by Scott Moore to work on CPU8080 FPGA core |
; |
;*********************************************************************** |
; Modified 2007/09/24 by Jose Ruiz for use in light8080 FPGA core |
; |
; 1.- Changed formatting for compatibility to CP/M's ASM |
; 2.- Commented out all Altair / MITS hardware related stuff |
; 3.- Set origin at 0H |
; |
; Modified again in 2008 to make it compatible with TASM assembler. |
; |
; Modified 2012/02/12 to add a few CY checks. |
; Flags go almost completely unchecked in this test. |
;*********************************************************************** |
|
; DS pseudo-directive; reserve space in bytes, without initializing it |
; (TASM does not have a DS directive) |
#define ds(n) \.org $+n |
|
; |
; Select controller defines |
; |
;selmain: equ 00H ; offset of main control register |
;sel1msk: equ 02H ; offset of select 1 mask |
;sel1cmp: equ 03H ; offset of select 1 compare |
;sel2msk: equ 04H ; offset of select 1 mask |
;sel2cmp: equ 05H ; offset of select 1 compare |
;sel3msk: equ 06H ; offset of select 1 mask |
;sel3cmp: equ 07H ; offset of select 1 compare |
;sel4msk: equ 08H ; offset of select 1 mask |
;sel4cmp: equ 09H ; offset of select 1 compare |
; |
; bits |
; |
;selenb: equ 01H ; enable select |
;selio: equ 02H ; I/O address or memory |
|
; |
; Note: select 1 is ROM, 2, is RAM, 3 is interrupt controller, 4 is serial I/O. |
; |
|
; |
; Where to place ROM and RAM for this test |
; |
;rombas: equ 0000H |
;rambas: equ rombas+4*1024 |
; |
; Interrupt controller defines |
; |
;intbas: equ 10H |
;intmsk: equ intbas+00H ; mask |
;intsts: equ intbas+01H ; status |
;intact: equ intbas+02H ; active interrupt |
;intpol: equ intbas+03H ; polarity select |
;intedg: equ intbas+04H ; edge/level select |
;intvec: equ intbas+05H ; vector base page |
; |
; Mits Serial I/O card |
; |
;siobas: equ 20H |
;sioctl: equ siobas+00H ; control register |
;siodat: equ siobas+01H ; data |
|
; |
; Set up selectors |
; |
|
; |
; ROM |
; |
; mvi a,rombas shr 8 ; enable select 1 to 4kb at base |
; out sel1cmp |
; mvi a,(0f000H shr 8) or selenb |
; out sel1msk |
; |
; RAM |
; |
; mvi a,rambas shr 8 ; enable select 2 to 1kb at base |
; out sel2cmp |
; mvi a,(0fc00H shr 8) or selenb |
; out sel2msk |
; |
; ROM and RAM set up, exit bootstrap mode |
; |
; mvi a,00H ; exit bootstrap mode |
; out selmain |
; |
; Serial I/O |
; |
; mvi a,siobas ; enable serial controller for 4 addresses |
; out sel4cmp |
; mvi a,0fcH or selio or selenb |
; out sel4msk |
|
;************************************************************ |
; 8080/8085 CPU TEST/DIAGNOSTIC |
;************************************************************ |
; |
;note: (1) program assumes "call",and "lxi sp" instructions work; |
; |
; (2) instructions not tested are "hlt","di","ei", |
; and "rst 0" thru "rst 7" |
; |
; |
; |
;test jump instructions and flags |
; |
.org 0H |
|
cpu: lxi sp,stack ;set the stack pointer |
mvi a,077H ;@ initialize A to remove X values from simulation |
ani 0 ;initialize a reg. and clear all flags |
jz j010 ;test "jz" |
call cpuer |
j010: jnc j020 ;test "jnc" |
call cpuer |
j020: jpe j030 ;test "jpe" |
call cpuer |
j030: jp j040 ;test "jp" |
call cpuer |
j040: jnz j050 ;test "jnz" |
jc j050 ;test "jc" |
jpo j050 ;test "jpo" |
jm j050 ;test "jm" |
jmp j060 ;test "jmp" (it's a little late,but what the hell; |
j050: call cpuer |
j060: adi 6 ;a=6,c=0,p=1,s=0,z=0 |
jnz j070 ;test "jnz" |
call cpuer |
j070: jc j080 ;test "jc" |
jpo j080 ;test "jpo" |
jp j090 ;test "jp" |
j080: call cpuer |
j090: adi 70H ;a=76h,c=0,p=0,s=0,z=0 |
jpo j100 ;test "jpo" |
call cpuer |
j100: jm j110 ;test "jm" |
jz j110 ;test "jz" |
jnc j120 ;test "jnc" |
j110: call cpuer |
j120: adi 81H ;a=f7h,c=0,p=0,s=1,z=0 |
jm j130 ;test "jm" |
call cpuer |
j130: jz j140 ;test "jz" |
jc j140 ;test "jc" |
jpo j150 ;test "jpo" |
j140: call cpuer |
j150: adi 0feH ;a=f5h,c=1,p=1,s=1,z=0 |
jc j160 ;test "jc" |
call cpuer |
j160: jz j170 ;test "jz" |
jpo j170 ;test "jpo" |
jm aimm ;test "jm" |
j170: call cpuer |
; |
; |
; |
;test accumulator immediate instructions |
; |
aimm: cpi 0 ;a=f5h,c=0,z=0 |
jc cpie ;test "cpi" for re-set carry |
jz cpie ;test "cpi" for re-set zero |
cpi 0f5H ;a=f5h,c=0,z=1 |
jc cpie ;test "cpi" for re-set carry ("adi") |
jnz cpie ;test "cpi" for re-set zero |
cpi 0ffH ;a=f5h,c=1,z=0 |
jz cpie ;test "cpi" for re-set zero |
jc acii ;test "cpi" for set carry |
cpie: call cpuer |
acii: aci 00aH ;a=f5h+0ah+carry(1)=0,c=1 |
aci 00aH ;a=0+0ah+carry(0)=0bh,c=0 |
cpi 00bH |
jz suii ;test "aci" |
call cpuer |
suii: sui 00cH ;a=ffh,c=0 |
sui 00fH ;a=f0h,c=1 |
cpi 0f0H |
jz sbii ;test "sui" |
call cpuer |
sbii: sbi 0f1H ;a=f0h-0f1h-carry(0)=ffh,c=1 |
sbi 0eH ;a=ffh-oeh-carry(1)=f0h,c=0 |
cpi 0f0H |
jz anii ;test "sbi" |
call cpuer |
anii: ani 055H ;a=f0h<and>55h=50h,c=0,p=1,s=0,z=0 |
cc cpuer |
cz cpuer |
cpi 050H |
jz orii ;test "ani" |
call cpuer |
orii: ori 03aH ;a=50h<or>3ah=7ah,c=0,p=0,s=0,z=0 |
cc cpuer |
cz cpuer |
cpi 07aH |
jz xrii ;test "ori" |
call cpuer |
xrii: xri 00fH ;a=7ah<xor>0fh=75h,c=0,p=0,s=0,z=0 |
cc cpuer |
cz cpuer |
cpi 075H |
jz c010 ;test "xri" |
call cpuer |
; |
; |
; |
;test calls and returns |
; |
c010: ani 0H ;a=0,c=0,p=1,s=0,z=1 |
cc cpuer ;test "cc" |
cpo cpuer ;test "cpo" |
cm cpuer ;test "cm" |
cnz cpuer ;test "cnz" |
cpi 0H |
jz c020 ;a=0,c=0,p=0,s=0,z=1 |
call cpuer |
c020: sui 077H ;a=89h,c=1,p=0,s=1,z=0 |
cnc cpuer ;test "cnc" |
cpe cpuer ;test "cpe" |
cp cpuer ;test "cp" |
cz cpuer ;test "cz" |
cpi 089H |
jz c030 ;test for "calls" taking branch |
call cpuer |
c030: ani 0ffH ;set flags back; |
cpo cpoi ;test "cpo" |
cpi 0d9H |
jz movi ;test "call" sequence success |
call cpuer |
cpoi: rpe ;test "rpe" |
adi 010H ;a=99h,c=0,p=0,s=1,z=0 |
cpe cpei ;test "cpe" |
adi 002H ;a=d9h,c=0,p=0,s=1,z=0 |
rpo ;test "rpo" |
call cpuer |
cpei: rpo ;test "rpo" |
adi 020H ;a=b9h,c=0,p=0,s=1,z=0 |
cm cmi ;test "cm" |
adi 004H ;a=d7h,c=0,p=1,s=1,z=0 |
rpe ;test "rpe" |
call cpuer |
cmi: rp ;test "rp" |
adi 080H ;a=39h,c=1,p=1,s=0,z=0 |
cp tcpi ;test "cp" |
adi 080H ;a=d3h,c=0,p=0,s=1,z=0 |
rm ;test "rm" |
call cpuer |
tcpi: rm ;test "rm" |
adi 040H ;a=79h,c=0,p=0,s=0,z=0 |
cnc cnci ;test "cnc" |
adi 040H ;a=53h,c=0,p=1,s=0,z=0 |
rp ;test "rp" |
call cpuer |
cnci: rc ;test "rc" |
adi 08fH ;a=08h,c=1,p=0,s=0,z=0 |
cc cci ;test "cc" |
sui 002H ;a=13h,c=0,p=0,s=0,z=0 |
rnc ;test "rnc" |
call cpuer |
cci: rnc ;test "rnc" |
adi 0f7H ;a=ffh,c=0,p=1,s=1,z=0 |
cnz cnzi ;test "cnz" |
adi 0feH ;a=15h,c=1,p=0,s=0,z=0 |
rc ;test "rc" |
call cpuer |
cnzi: rz ;test "rz" |
adi 001H ;a=00h,c=1,p=1,s=0,z=1 |
cz czi ;test "cz" |
adi 0d0H ;a=17h,c=1,p=1,s=0,z=0 |
rnz ;test "rnz" |
call cpuer |
czi: rnz ;test "rnz" |
adi 047H ;a=47h,c=0,p=1,s=0,z=0 |
cpi 047H ;a=47h,c=0,p=1,s=0,z=1 |
rz ;test "rz" |
call cpuer |
; |
; |
; |
;test "mov","inr",and "dcr" instructions |
; |
movi: mvi a,077H |
inr a |
mov b,a |
inr b |
mov c,b |
dcr c |
mov d,c |
mov e,d |
mov h,e |
mov l,h |
mov a,l ;test "mov" a,l,h,e,d,c,b,a |
dcr a |
mov c,a |
mov e,c |
mov l,e |
mov b,l |
mov d,b |
mov h,d |
mov a,h ;test "mov" a,h,d,b,l,e,c,a |
mov d,a |
inr d |
mov l,d |
mov c,l |
inr c |
mov h,c |
mov b,h |
dcr b |
mov e,b |
mov a,e ;test "mov" a,e,b,h,c,l,d,a |
mov e,a |
inr e |
mov b,e |
mov h,b |
inr h |
mov c,h |
mov l,c |
mov d,l |
dcr d |
mov a,d ;test "mov" a,d,l,c,h,b,e,a |
mov h,a |
dcr h |
mov d,h |
mov b,d |
mov l,b |
inr l |
mov e,l |
dcr e |
mov c,e |
mov a,c ;test "mov" a,c,e,l,b,d,h,a |
mov l,a |
dcr l |
mov h,l |
mov e,h |
mov d,e |
mov c,d |
mov b,c |
mov a,b |
cpi 077H |
cnz cpuer ;test "mov" a,b,c,d,e,h,l,a |
; |
; |
; |
;test arithmetic and logic instructions |
; |
xra a |
mvi b,001H |
mvi c,003H |
mvi d,007H |
mvi e,00fH |
mvi h,01fH |
mvi l,03fH |
add b |
add c |
add d |
add e |
add h |
add l |
add a |
cpi 0f0H |
cnz cpuer ;test "add" b,c,d,e,h,l,a |
sub b |
sub c |
sub d |
sub e |
sub h |
sub l |
cpi 078H |
cnz cpuer ;test "sub" b,c,d,e,h,l |
sub a |
cnz cpuer ;test "sub" a |
mvi a,080H |
add a |
mvi b,001H |
mvi c,002H |
mvi d,003H |
mvi e,004H |
mvi h,005H |
mvi l,006H |
adc b |
mvi b,080H |
add b |
add b |
adc c |
add b |
add b |
adc d |
add b |
add b |
adc e |
add b |
add b |
adc h |
add b |
add b |
adc l |
add b |
add b |
adc a |
cpi 037H |
cnz cpuer ;test "adc" b,c,d,e,h,l,a |
mvi a,080H |
add a |
mvi b,001H |
sbb b |
mvi b,0ffH |
add b |
sbb c |
add b |
sbb d |
add b |
sbb e |
add b |
sbb h |
add b |
sbb l |
cpi 0e0H |
cnz cpuer ;test "sbb" b,c,d,e,h,l |
mvi a,080H |
add a |
sbb a |
cpi 0ffH |
cnz cpuer ;test "sbb" a |
mvi a,0ffH |
mvi b,0feH |
mvi c,0fcH |
mvi d,0efH |
mvi e,07fH |
mvi h,0f4H |
mvi l,0bfH |
stc |
ana a |
cc cpuer |
ana c |
ana d |
ana e |
ana h |
ana l |
ana a |
cpi 024H |
cnz cpuer ;test "ana" b,c,d,e,h,l,a |
xra a |
mvi b,001H |
mvi c,002H |
mvi d,004H |
mvi e,008H |
mvi h,010H |
mvi l,020H |
stc |
ora b |
cc cpuer |
ora c |
ora d |
ora e |
ora h |
ora l |
ora a |
cpi 03fH |
cnz cpuer ;test "ora" b,c,d,e,h,l,a |
mvi a,0H |
mvi h,08fH |
mvi l,04fH |
stc |
xra b |
cc cpuer |
xra c |
xra d |
xra e |
xra h |
xra l |
cpi 0cfH |
cnz cpuer ;test "xra" b,c,d,e,h,l |
xra a |
cnz cpuer ;test "xra" a |
mvi b,044H |
mvi c,045H |
mvi d,046H |
mvi e,047H |
mvi h,temp0 / 0ffH ;high byte of test memory location |
mvi l,temp0 & 0ffH ;low byte of test memory location |
mov m,b |
mvi b,0H |
mov b,m |
mvi a,044H |
cmp b |
cnz cpuer ;test "mov" m,b and b,m |
mov m,d |
mvi d,0H |
mov d,m |
mvi a,046H |
cmp d |
cnz cpuer ;test "mov" m,d and d,m |
mov m,e |
mvi e,0H |
mov e,m |
mvi a,047H |
cmp e |
cnz cpuer ;test "mov" m,e and e,m |
mov m,h |
mvi h,temp0 / 0ffH |
mvi l,temp0 & 0ffH |
mov h,m |
mvi a,temp0 / 0ffH |
cmp h |
cnz cpuer ;test "mov" m,h and h,m |
mov m,l |
mvi h,temp0 / 0ffH |
mvi l,temp0 & 0ffH |
mov l,m |
mvi a,temp0 & 0ffH |
cmp l |
cnz cpuer ;test "mov" m,l and l,m |
mvi h,temp0 / 0ffH |
mvi l,temp0 & 0ffH |
mvi a,032H |
mov m,a |
cmp m |
cnz cpuer ;test "mov" m,a |
add m |
cpi 064H |
cnz cpuer ;test "add" m |
xra a |
mov a,m |
cpi 032H |
cnz cpuer ;test "mov" a,m |
mvi h,temp0 / 0ffH |
mvi l,temp0 & 0ffH |
mov a,m |
sub m |
cnz cpuer ;test "sub" m |
mvi a,080H |
add a |
adc m |
cpi 033H |
cnz cpuer ;test "adc" m |
mvi a,080H |
add a |
sbb m |
cpi 0cdH |
cnz cpuer ;test "sbb" m |
stc |
ana m |
cc cpuer |
cnz cpuer ;test "ana" m |
mvi a,025H |
stc |
ora m |
cc cpuer |
cpi 37H |
cnz cpuer ;test "ora" m |
stc |
xra m |
cc cpuer |
cpi 005H |
cnz cpuer ;test "xra" m |
mvi m,055H |
inr m |
dcr m |
add m |
cpi 05aH |
cnz cpuer ;test "inr","dcr",and "mvi" m |
lxi b,12ffH |
lxi d,12ffH |
lxi h,12ffH |
inx b |
inx d |
inx h |
mvi a,013H |
cmp b |
cnz cpuer ;test "lxi" and "inx" b |
cmp d |
cnz cpuer ;test "lxi" and "inx" d |
cmp h |
cnz cpuer ;test "lxi" and "inx" h |
mvi a,0H |
cmp c |
cnz cpuer ;test "lxi" and "inx" b |
cmp e |
cnz cpuer ;test "lxi" and "inx" d |
cmp l |
cnz cpuer ;test "lxi" and "inx" h |
dcx b |
dcx d |
dcx h |
mvi a,012H |
cmp b |
cnz cpuer ;test "dcx" b |
cmp d |
cnz cpuer ;test "dcx" d |
cmp h |
cnz cpuer ;test "dcx" h |
mvi a,0ffH |
cmp c |
cnz cpuer ;test "dcx" b |
cmp e |
cnz cpuer ;test "dcx" d |
cmp l |
cnz cpuer ;test "dcx" h |
sta temp0 |
xra a |
lda temp0 |
cpi 0ffH |
cnz cpuer ;test "lda" and "sta" |
lhld tempp |
shld temp0 |
lda tempp |
mov b,a |
lda temp0 |
cmp b |
cnz cpuer ;test "lhld" and "shld" |
lda tempp+1 |
mov b,a |
lda temp0+1 |
cmp b |
cnz cpuer ;test "lhld" and "shld" |
mvi a,0aaH |
sta temp0 |
mov b,h |
mov c,l |
xra a |
ldax b |
cpi 0aaH |
cnz cpuer ;test "ldax" b |
inr a |
stax b |
lda temp0 |
cpi 0abH |
cnz cpuer ;test "stax" b |
mvi a,077H |
sta temp0 |
lhld tempp |
lxi d,00000H |
xchg |
xra a |
ldax d |
cpi 077H |
cnz cpuer ;test "ldax" d and "xchg" |
xra a |
add h |
add l |
cnz cpuer ;test "xchg" |
mvi a,0ccH |
stax d |
lda temp0 |
cpi 0ccH |
stax d |
lda temp0 |
cpi 0ccH |
cnz cpuer ;test "stax" d |
lxi h,07777H |
dad h |
mvi a,0eeH |
cmp h |
cnz cpuer ;test "dad" h |
cmp l |
cnz cpuer ;test "dad" h |
lxi h,05555H |
lxi b,0ffffH |
dad b |
mvi a,055H |
cnc cpuer ;test "dad" b |
cmp h |
cnz cpuer ;test "dad" b |
mvi a,054H |
cmp l |
cnz cpuer ;test "dad" b |
lxi h,0aaaaH |
lxi d,03333H |
dad d |
mvi a,0ddH |
cmp h |
cnz cpuer ;test "dad" d |
cmp l |
cnz cpuer ;test "dad" b |
stc |
cnc cpuer ;test "stc" |
cmc |
cc cpuer ;test "cmc |
mvi a,0aaH |
cma |
cpi 055H |
cnz cpuer ;test "cma" |
ora a ;re-set auxiliary carry |
daa |
cpi 055H |
cnz cpuer ;test "daa" |
mvi a,088H |
add a |
daa |
cpi 076H |
cnz cpuer ;test "daa" |
xra a |
mvi a,0aaH |
daa |
cnc cpuer ;test "daa" |
cpi 010H |
cnz cpuer ;test "daa" |
xra a |
mvi a,09aH |
daa |
cnc cpuer ;test "daa" |
cnz cpuer ;test "daa" |
stc |
mvi a,042H |
rlc |
cc cpuer ;test "rlc" for re-set carry |
rlc |
cnc cpuer ;test "rlc" for set carry |
cpi 009H |
cnz cpuer ;test "rlc" for rotation |
rrc |
cnc cpuer ;test "rrc" for set carry |
rrc |
cpi 042H |
cnz cpuer ;test "rrc" for rotation |
ral |
ral |
cnc cpuer ;test "ral" for set carry |
cpi 008H |
cnz cpuer ;test "ral" for rotation |
rar |
rar |
cc cpuer ;test "rar" for re-set carry |
cpi 002H |
cnz cpuer ;test "rar" for rotation |
lxi b,01234H |
lxi d,0aaaaH |
lxi h,05555H |
xra a |
push b |
push d |
push h |
push psw |
lxi b,00000H |
lxi d,00000H |
lxi h,00000H |
mvi a,0c0H |
adi 0f0H |
pop psw |
pop h |
pop d |
pop b |
cc cpuer ;test "push psw" and "pop psw" |
cnz cpuer ;test "push psw" and "pop psw" |
cpo cpuer ;test "push psw" and "pop psw" |
cm cpuer ;test "push psw" and "pop psw" |
mvi a,012H |
cmp b |
cnz cpuer ;test "push b" and "pop b" |
mvi a,034H |
cmp c |
cnz cpuer ;test "push b" and "pop b" |
mvi a,0aaH |
cmp d |
cnz cpuer ;test "push d" and "pop d" |
cmp e |
cnz cpuer ;test "push d" and "pop d" |
mvi a,055H |
cmp h |
cnz cpuer ;test "push h" and "pop h" |
cmp l |
cnz cpuer ;test "push h" and "pop h" |
lxi h,00000H |
dad sp |
shld savstk ;save the "old" stack-pointer; |
lxi sp,temp4 |
dcx sp |
dcx sp |
inx sp |
dcx sp |
mvi a,055H |
sta temp2 |
cma |
sta temp3 |
pop b |
cmp b |
cnz cpuer ;test "lxi","dad","inx",and "dcx" sp |
cma |
cmp c |
cnz cpuer ;test "lxi","dad","inx", and "dcx" sp |
lxi h,temp4 |
sphl |
lxi h,07733H |
dcx sp |
dcx sp |
xthl |
lda temp3 |
cpi 077H |
cnz cpuer ;test "sphl" and "xthl" |
lda temp2 |
cpi 033H |
cnz cpuer ;test "sphl" and "xthl" |
mvi a,055H |
cmp l |
cnz cpuer ;test "sphl" and "xthl" |
cma |
cmp h |
cnz cpuer ;test "sphl" and "xthl" |
lhld savstk ;restore the "old" stack-pointer |
sphl |
lxi h,cpuok |
pchl ;test "pchl" |
|
cpuer: mvi a, 0aaH ; set exit code (failure) |
out 20h |
hlt ; stop here |
|
cpuok: mvi a, 55H ; |
out 20h |
hlt ; stop here - no trap |
|
|
; |
; Data area in program space |
; |
tempp: .dw temp0 ;pointer used to test "lhld","shld", |
; and "ldax" instructions |
; |
; Data area in variable space |
; |
temp0: ds(1) ;temporary storage for cpu test memory locations |
temp1: ds(1) ;temporary storage for cpu test memory locations |
temp2: ds(1) ;temporary storage for cpu test memory locations |
temp3: ds(1) ;temporary storage for cpu test memory locations |
temp4: ds(1) ;temporary storage for cpu test memory locations |
savstk: ds(2) ;temporary stack-pointer storage location |
|
ds(256) ;de-bug stack pointer storage area |
stack: .dw 0 |
|
.end |
|
/trunk/sw/tb/tb0/tb0.lst
0,0 → 1,859
0001 0000 ;*********************************************************************** |
0002 0000 ; MICROCOSM ASSOCIATES 8080/8085 CPU DIAGNOSTIC VERSION 1.0 (C) 1980 |
0003 0000 ;*********************************************************************** |
0004 0000 ; |
0005 0000 ;DONATED TO THE "SIG/M" CP/M USER'S GROUP BY: |
0006 0000 ;KELLY SMITH, MICROCOSM ASSOCIATES |
0007 0000 ;3055 WACO AVENUE |
0008 0000 ;SIMI VALLEY, CALIFORNIA, 93065 |
0009 0000 ;(805) 527-9321 (MODEM, CP/M-NET (TM)) |
0010 0000 ;(805) 527-0518 (VERBAL) |
0011 0000 ; |
0012 0000 ;*********************************************************************** |
0013 0000 ; Modified 2001/02/28 by Richard Cini for use in the Altair32 Emulator |
0014 0000 ; Project |
0015 0000 ; |
0016 0000 ; Need to somehow connect this code to Windows so that failure messages |
0017 0000 ; can be posted to Windows. Maybe just store error code in |
0018 0000 ; Mem[0xffff]. Maybe trap NOP in the emulator code? |
0019 0000 ; |
0020 0000 ;*********************************************************************** |
0021 0000 ; Modified 2006/11/16 by Scott Moore to work on CPU8080 FPGA core |
0022 0000 ; |
0023 0000 ;*********************************************************************** |
0024 0000 ; Modified 2007/09/24 by Jose Ruiz for use in light8080 FPGA core |
0025 0000 ; |
0026 0000 ; 1.- Changed formatting for compatibility to CP/M's ASM |
0027 0000 ; 2.- Commented out all Altair / MITS hardware related stuff |
0028 0000 ; 3.- Set origin at 0H |
0029 0000 ; |
0030 0000 ; Modified again in 2008 to make it compatible with TASM assembler. |
0031 0000 ; |
0032 0000 ; Modified 2012/02/12 to add a few CY checks. |
0033 0000 ; Flags go almost completely unchecked in this test. |
0034 0000 ;*********************************************************************** |
0035 0000 |
0036 0000 ; DS pseudo-directive; reserve space in bytes, without initializing it |
0037 0000 ; (TASM does not have a DS directive) |
0038 0000 #define ds(n) \.org $+n |
0039 0000 |
0040 0000 ; |
0041 0000 ; Select controller defines |
0042 0000 ; |
0043 0000 ;selmain: equ 00H ; offset of main control register |
0044 0000 ;sel1msk: equ 02H ; offset of select 1 mask |
0045 0000 ;sel1cmp: equ 03H ; offset of select 1 compare |
0046 0000 ;sel2msk: equ 04H ; offset of select 1 mask |
0047 0000 ;sel2cmp: equ 05H ; offset of select 1 compare |
0048 0000 ;sel3msk: equ 06H ; offset of select 1 mask |
0049 0000 ;sel3cmp: equ 07H ; offset of select 1 compare |
0050 0000 ;sel4msk: equ 08H ; offset of select 1 mask |
0051 0000 ;sel4cmp: equ 09H ; offset of select 1 compare |
0052 0000 ; |
0053 0000 ; bits |
0054 0000 ; |
0055 0000 ;selenb: equ 01H ; enable select |
0056 0000 ;selio: equ 02H ; I/O address or memory |
0057 0000 |
0058 0000 ; |
0059 0000 ; Note: select 1 is ROM, 2, is RAM, 3 is interrupt controller, 4 is serial I/O. |
0060 0000 ; |
0061 0000 |
0062 0000 ; |
0063 0000 ; Where to place ROM and RAM for this test |
0064 0000 ; |
0065 0000 ;rombas: equ 0000H |
0066 0000 ;rambas: equ rombas+4*1024 |
0067 0000 ; |
0068 0000 ; Interrupt controller defines |
0069 0000 ; |
0070 0000 ;intbas: equ 10H |
0071 0000 ;intmsk: equ intbas+00H ; mask |
0072 0000 ;intsts: equ intbas+01H ; status |
0073 0000 ;intact: equ intbas+02H ; active interrupt |
0074 0000 ;intpol: equ intbas+03H ; polarity select |
0075 0000 ;intedg: equ intbas+04H ; edge/level select |
0076 0000 ;intvec: equ intbas+05H ; vector base page |
0077 0000 ; |
0078 0000 ; Mits Serial I/O card |
0079 0000 ; |
0080 0000 ;siobas: equ 20H |
0081 0000 ;sioctl: equ siobas+00H ; control register |
0082 0000 ;siodat: equ siobas+01H ; data |
0083 0000 |
0084 0000 ; |
0085 0000 ; Set up selectors |
0086 0000 ; |
0087 0000 |
0088 0000 ; |
0089 0000 ; ROM |
0090 0000 ; |
0091 0000 ; mvi a,rombas shr 8 ; enable select 1 to 4kb at base |
0092 0000 ; out sel1cmp |
0093 0000 ; mvi a,(0f000H shr 8) or selenb |
0094 0000 ; out sel1msk |
0095 0000 ; |
0096 0000 ; RAM |
0097 0000 ; |
0098 0000 ; mvi a,rambas shr 8 ; enable select 2 to 1kb at base |
0099 0000 ; out sel2cmp |
0100 0000 ; mvi a,(0fc00H shr 8) or selenb |
0101 0000 ; out sel2msk |
0102 0000 ; |
0103 0000 ; ROM and RAM set up, exit bootstrap mode |
0104 0000 ; |
0105 0000 ; mvi a,00H ; exit bootstrap mode |
0106 0000 ; out selmain |
0107 0000 ; |
0108 0000 ; Serial I/O |
0109 0000 ; |
0110 0000 ; mvi a,siobas ; enable serial controller for 4 addresses |
0111 0000 ; out sel4cmp |
0112 0000 ; mvi a,0fcH or selio or selenb |
0113 0000 ; out sel4msk |
0114 0000 |
0115 0000 ;************************************************************ |
0116 0000 ; 8080/8085 CPU TEST/DIAGNOSTIC |
0117 0000 ;************************************************************ |
0118 0000 ; |
0119 0000 ;note: (1) program assumes "call",and "lxi sp" instructions work; |
0120 0000 ; |
0121 0000 ; (2) instructions not tested are "hlt","di","ei", |
0122 0000 ; and "rst 0" thru "rst 7" |
0123 0000 ; |
0124 0000 ; |
0125 0000 ; |
0126 0000 ;test jump instructions and flags |
0127 0000 ; |
0128 0000 .org 0H |
0129 0000 |
0130 0000 31 1D 06 cpu: lxi sp,stack ;set the stack pointer |
0131 0003 3E 77 mvi a,077H ;@ initialize A to remove X values from simulation |
0132 0005 E6 00 ani 0 ;initialize a reg. and clear all flags |
0133 0007 CA 0D 00 jz j010 ;test "jz" |
0134 000A CD 0A 05 call cpuer |
0135 000D D2 13 00 j010: jnc j020 ;test "jnc" |
0136 0010 CD 0A 05 call cpuer |
0137 0013 EA 19 00 j020: jpe j030 ;test "jpe" |
0138 0016 CD 0A 05 call cpuer |
0139 0019 F2 1F 00 j030: jp j040 ;test "jp" |
0140 001C CD 0A 05 call cpuer |
0141 001F C2 2E 00 j040: jnz j050 ;test "jnz" |
0142 0022 DA 2E 00 jc j050 ;test "jc" |
0143 0025 E2 2E 00 jpo j050 ;test "jpo" |
0144 0028 FA 2E 00 jm j050 ;test "jm" |
0145 002B C3 31 00 jmp j060 ;test "jmp" (it's a little late,but what the hell; |
0146 002E CD 0A 05 j050: call cpuer |
0147 0031 C6 06 j060: adi 6 ;a=6,c=0,p=1,s=0,z=0 |
0148 0033 C2 39 00 jnz j070 ;test "jnz" |
0149 0036 CD 0A 05 call cpuer |
0150 0039 DA 42 00 j070: jc j080 ;test "jc" |
0151 003C E2 42 00 jpo j080 ;test "jpo" |
0152 003F F2 45 00 jp j090 ;test "jp" |
0153 0042 CD 0A 05 j080: call cpuer |
0154 0045 C6 70 j090: adi 70H ;a=76h,c=0,p=0,s=0,z=0 |
0155 0047 E2 4D 00 jpo j100 ;test "jpo" |
0156 004A CD 0A 05 call cpuer |
0157 004D FA 56 00 j100: jm j110 ;test "jm" |
0158 0050 CA 56 00 jz j110 ;test "jz" |
0159 0053 D2 59 00 jnc j120 ;test "jnc" |
0160 0056 CD 0A 05 j110: call cpuer |
0161 0059 C6 81 j120: adi 81H ;a=f7h,c=0,p=0,s=1,z=0 |
0162 005B FA 61 00 jm j130 ;test "jm" |
0163 005E CD 0A 05 call cpuer |
0164 0061 CA 6A 00 j130: jz j140 ;test "jz" |
0165 0064 DA 6A 00 jc j140 ;test "jc" |
0166 0067 E2 6D 00 jpo j150 ;test "jpo" |
0167 006A CD 0A 05 j140: call cpuer |
0168 006D C6 FE j150: adi 0feH ;a=f5h,c=1,p=1,s=1,z=0 |
0169 006F DA 75 00 jc j160 ;test "jc" |
0170 0072 CD 0A 05 call cpuer |
0171 0075 CA 7E 00 j160: jz j170 ;test "jz" |
0172 0078 E2 7E 00 jpo j170 ;test "jpo" |
0173 007B FA 81 00 jm aimm ;test "jm" |
0174 007E CD 0A 05 j170: call cpuer |
0175 0081 ; |
0176 0081 ; |
0177 0081 ; |
0178 0081 ;test accumulator immediate instructions |
0179 0081 ; |
0180 0081 FE 00 aimm: cpi 0 ;a=f5h,c=0,z=0 |
0181 0083 DA 99 00 jc cpie ;test "cpi" for re-set carry |
0182 0086 CA 99 00 jz cpie ;test "cpi" for re-set zero |
0183 0089 FE F5 cpi 0f5H ;a=f5h,c=0,z=1 |
0184 008B DA 99 00 jc cpie ;test "cpi" for re-set carry ("adi") |
0185 008E C2 99 00 jnz cpie ;test "cpi" for re-set zero |
0186 0091 FE FF cpi 0ffH ;a=f5h,c=1,z=0 |
0187 0093 CA 99 00 jz cpie ;test "cpi" for re-set zero |
0188 0096 DA 9C 00 jc acii ;test "cpi" for set carry |
0189 0099 CD 0A 05 cpie: call cpuer |
0190 009C CE 0A acii: aci 00aH ;a=f5h+0ah+carry(1)=0,c=1 |
0191 009E CE 0A aci 00aH ;a=0+0ah+carry(0)=0bh,c=0 |
0192 00A0 FE 0B cpi 00bH |
0193 00A2 CA A8 00 jz suii ;test "aci" |
0194 00A5 CD 0A 05 call cpuer |
0195 00A8 D6 0C suii: sui 00cH ;a=ffh,c=0 |
0196 00AA D6 0F sui 00fH ;a=f0h,c=1 |
0197 00AC FE F0 cpi 0f0H |
0198 00AE CA B4 00 jz sbii ;test "sui" |
0199 00B1 CD 0A 05 call cpuer |
0200 00B4 DE F1 sbii: sbi 0f1H ;a=f0h-0f1h-carry(0)=ffh,c=1 |
0201 00B6 DE 0E sbi 0eH ;a=ffh-oeh-carry(1)=f0h,c=0 |
0202 00B8 FE F0 cpi 0f0H |
0203 00BA CA C0 00 jz anii ;test "sbi" |
0204 00BD CD 0A 05 call cpuer |
0205 00C0 E6 55 anii: ani 055H ;a=f0h<and>55h=50h,c=0,p=1,s=0,z=0 |
0206 00C2 DC 0A 05 cc cpuer |
0207 00C5 CC 0A 05 cz cpuer |
0208 00C8 FE 50 cpi 050H |
0209 00CA CA D0 00 jz orii ;test "ani" |
0210 00CD CD 0A 05 call cpuer |
0211 00D0 F6 3A orii: ori 03aH ;a=50h<or>3ah=7ah,c=0,p=0,s=0,z=0 |
0212 00D2 DC 0A 05 cc cpuer |
0213 00D5 CC 0A 05 cz cpuer |
0214 00D8 FE 7A cpi 07aH |
0215 00DA CA E0 00 jz xrii ;test "ori" |
0216 00DD CD 0A 05 call cpuer |
0217 00E0 EE 0F xrii: xri 00fH ;a=7ah<xor>0fh=75h,c=0,p=0,s=0,z=0 |
0218 00E2 DC 0A 05 cc cpuer |
0219 00E5 CC 0A 05 cz cpuer |
0220 00E8 FE 75 cpi 075H |
0221 00EA CA F0 00 jz c010 ;test "xri" |
0222 00ED CD 0A 05 call cpuer |
0223 00F0 ; |
0224 00F0 ; |
0225 00F0 ; |
0226 00F0 ;test calls and returns |
0227 00F0 ; |
0228 00F0 E6 00 c010: ani 0H ;a=0,c=0,p=1,s=0,z=1 |
0229 00F2 DC 0A 05 cc cpuer ;test "cc" |
0230 00F5 E4 0A 05 cpo cpuer ;test "cpo" |
0231 00F8 FC 0A 05 cm cpuer ;test "cm" |
0232 00FB C4 0A 05 cnz cpuer ;test "cnz" |
0233 00FE FE 00 cpi 0H |
0234 0100 CA 06 01 jz c020 ;a=0,c=0,p=0,s=0,z=1 |
0235 0103 CD 0A 05 call cpuer |
0236 0106 D6 77 c020: sui 077H ;a=89h,c=1,p=0,s=1,z=0 |
0237 0108 D4 0A 05 cnc cpuer ;test "cnc" |
0238 010B EC 0A 05 cpe cpuer ;test "cpe" |
0239 010E F4 0A 05 cp cpuer ;test "cp" |
0240 0111 CC 0A 05 cz cpuer ;test "cz" |
0241 0114 FE 89 cpi 089H |
0242 0116 CA 1C 01 jz c030 ;test for "calls" taking branch |
0243 0119 CD 0A 05 call cpuer |
0244 011C E6 FF c030: ani 0ffH ;set flags back; |
0245 011E E4 29 01 cpo cpoi ;test "cpo" |
0246 0121 FE D9 cpi 0d9H |
0247 0123 CA 86 01 jz movi ;test "call" sequence success |
0248 0126 CD 0A 05 call cpuer |
0249 0129 E8 cpoi: rpe ;test "rpe" |
0250 012A C6 10 adi 010H ;a=99h,c=0,p=0,s=1,z=0 |
0251 012C EC 35 01 cpe cpei ;test "cpe" |
0252 012F C6 02 adi 002H ;a=d9h,c=0,p=0,s=1,z=0 |
0253 0131 E0 rpo ;test "rpo" |
0254 0132 CD 0A 05 call cpuer |
0255 0135 E0 cpei: rpo ;test "rpo" |
0256 0136 C6 20 adi 020H ;a=b9h,c=0,p=0,s=1,z=0 |
0257 0138 FC 41 01 cm cmi ;test "cm" |
0258 013B C6 04 adi 004H ;a=d7h,c=0,p=1,s=1,z=0 |
0259 013D E8 rpe ;test "rpe" |
0260 013E CD 0A 05 call cpuer |
0261 0141 F0 cmi: rp ;test "rp" |
0262 0142 C6 80 adi 080H ;a=39h,c=1,p=1,s=0,z=0 |
0263 0144 F4 4D 01 cp tcpi ;test "cp" |
0264 0147 C6 80 adi 080H ;a=d3h,c=0,p=0,s=1,z=0 |
0265 0149 F8 rm ;test "rm" |
0266 014A CD 0A 05 call cpuer |
0267 014D F8 tcpi: rm ;test "rm" |
0268 014E C6 40 adi 040H ;a=79h,c=0,p=0,s=0,z=0 |
0269 0150 D4 59 01 cnc cnci ;test "cnc" |
0270 0153 C6 40 adi 040H ;a=53h,c=0,p=1,s=0,z=0 |
0271 0155 F0 rp ;test "rp" |
0272 0156 CD 0A 05 call cpuer |
0273 0159 D8 cnci: rc ;test "rc" |
0274 015A C6 8F adi 08fH ;a=08h,c=1,p=0,s=0,z=0 |
0275 015C DC 65 01 cc cci ;test "cc" |
0276 015F D6 02 sui 002H ;a=13h,c=0,p=0,s=0,z=0 |
0277 0161 D0 rnc ;test "rnc" |
0278 0162 CD 0A 05 call cpuer |
0279 0165 D0 cci: rnc ;test "rnc" |
0280 0166 C6 F7 adi 0f7H ;a=ffh,c=0,p=1,s=1,z=0 |
0281 0168 C4 71 01 cnz cnzi ;test "cnz" |
0282 016B C6 FE adi 0feH ;a=15h,c=1,p=0,s=0,z=0 |
0283 016D D8 rc ;test "rc" |
0284 016E CD 0A 05 call cpuer |
0285 0171 C8 cnzi: rz ;test "rz" |
0286 0172 C6 01 adi 001H ;a=00h,c=1,p=1,s=0,z=1 |
0287 0174 CC 7D 01 cz czi ;test "cz" |
0288 0177 C6 D0 adi 0d0H ;a=17h,c=1,p=1,s=0,z=0 |
0289 0179 C0 rnz ;test "rnz" |
0290 017A CD 0A 05 call cpuer |
0291 017D C0 czi: rnz ;test "rnz" |
0292 017E C6 47 adi 047H ;a=47h,c=0,p=1,s=0,z=0 |
0293 0180 FE 47 cpi 047H ;a=47h,c=0,p=1,s=0,z=1 |
0294 0182 C8 rz ;test "rz" |
0295 0183 CD 0A 05 call cpuer |
0296 0186 ; |
0297 0186 ; |
0298 0186 ; |
0299 0186 ;test "mov","inr",and "dcr" instructions |
0300 0186 ; |
0301 0186 3E 77 movi: mvi a,077H |
0302 0188 3C inr a |
0303 0189 47 mov b,a |
0304 018A 04 inr b |
0305 018B 48 mov c,b |
0306 018C 0D dcr c |
0307 018D 51 mov d,c |
0308 018E 5A mov e,d |
0309 018F 63 mov h,e |
0310 0190 6C mov l,h |
0311 0191 7D mov a,l ;test "mov" a,l,h,e,d,c,b,a |
0312 0192 3D dcr a |
0313 0193 4F mov c,a |
0314 0194 59 mov e,c |
0315 0195 6B mov l,e |
0316 0196 45 mov b,l |
0317 0197 50 mov d,b |
0318 0198 62 mov h,d |
0319 0199 7C mov a,h ;test "mov" a,h,d,b,l,e,c,a |
0320 019A 57 mov d,a |
0321 019B 14 inr d |
0322 019C 6A mov l,d |
0323 019D 4D mov c,l |
0324 019E 0C inr c |
0325 019F 61 mov h,c |
0326 01A0 44 mov b,h |
0327 01A1 05 dcr b |
0328 01A2 58 mov e,b |
0329 01A3 7B mov a,e ;test "mov" a,e,b,h,c,l,d,a |
0330 01A4 5F mov e,a |
0331 01A5 1C inr e |
0332 01A6 43 mov b,e |
0333 01A7 60 mov h,b |
0334 01A8 24 inr h |
0335 01A9 4C mov c,h |
0336 01AA 69 mov l,c |
0337 01AB 55 mov d,l |
0338 01AC 15 dcr d |
0339 01AD 7A mov a,d ;test "mov" a,d,l,c,h,b,e,a |
0340 01AE 67 mov h,a |
0341 01AF 25 dcr h |
0342 01B0 54 mov d,h |
0343 01B1 42 mov b,d |
0344 01B2 68 mov l,b |
0345 01B3 2C inr l |
0346 01B4 5D mov e,l |
0347 01B5 1D dcr e |
0348 01B6 4B mov c,e |
0349 01B7 79 mov a,c ;test "mov" a,c,e,l,b,d,h,a |
0350 01B8 6F mov l,a |
0351 01B9 2D dcr l |
0352 01BA 65 mov h,l |
0353 01BB 5C mov e,h |
0354 01BC 53 mov d,e |
0355 01BD 4A mov c,d |
0356 01BE 41 mov b,c |
0357 01BF 78 mov a,b |
0358 01C0 FE 77 cpi 077H |
0359 01C2 C4 0A 05 cnz cpuer ;test "mov" a,b,c,d,e,h,l,a |
0360 01C5 ; |
0361 01C5 ; |
0362 01C5 ; |
0363 01C5 ;test arithmetic and logic instructions |
0364 01C5 ; |
0365 01C5 AF xra a |
0366 01C6 06 01 mvi b,001H |
0367 01C8 0E 03 mvi c,003H |
0368 01CA 16 07 mvi d,007H |
0369 01CC 1E 0F mvi e,00fH |
0370 01CE 26 1F mvi h,01fH |
0371 01D0 2E 3F mvi l,03fH |
0372 01D2 80 add b |
0373 01D3 81 add c |
0374 01D4 82 add d |
0375 01D5 83 add e |
0376 01D6 84 add h |
0377 01D7 85 add l |
0378 01D8 87 add a |
0379 01D9 FE F0 cpi 0f0H |
0380 01DB C4 0A 05 cnz cpuer ;test "add" b,c,d,e,h,l,a |
0381 01DE 90 sub b |
0382 01DF 91 sub c |
0383 01E0 92 sub d |
0384 01E1 93 sub e |
0385 01E2 94 sub h |
0386 01E3 95 sub l |
0387 01E4 FE 78 cpi 078H |
0388 01E6 C4 0A 05 cnz cpuer ;test "sub" b,c,d,e,h,l |
0389 01E9 97 sub a |
0390 01EA C4 0A 05 cnz cpuer ;test "sub" a |
0391 01ED 3E 80 mvi a,080H |
0392 01EF 87 add a |
0393 01F0 06 01 mvi b,001H |
0394 01F2 0E 02 mvi c,002H |
0395 01F4 16 03 mvi d,003H |
0396 01F6 1E 04 mvi e,004H |
0397 01F8 26 05 mvi h,005H |
0398 01FA 2E 06 mvi l,006H |
0399 01FC 88 adc b |
0400 01FD 06 80 mvi b,080H |
0401 01FF 80 add b |
0402 0200 80 add b |
0403 0201 89 adc c |
0404 0202 80 add b |
0405 0203 80 add b |
0406 0204 8A adc d |
0407 0205 80 add b |
0408 0206 80 add b |
0409 0207 8B adc e |
0410 0208 80 add b |
0411 0209 80 add b |
0412 020A 8C adc h |
0413 020B 80 add b |
0414 020C 80 add b |
0415 020D 8D adc l |
0416 020E 80 add b |
0417 020F 80 add b |
0418 0210 8F adc a |
0419 0211 FE 37 cpi 037H |
0420 0213 C4 0A 05 cnz cpuer ;test "adc" b,c,d,e,h,l,a |
0421 0216 3E 80 mvi a,080H |
0422 0218 87 add a |
0423 0219 06 01 mvi b,001H |
0424 021B 98 sbb b |
0425 021C 06 FF mvi b,0ffH |
0426 021E 80 add b |
0427 021F 99 sbb c |
0428 0220 80 add b |
0429 0221 9A sbb d |
0430 0222 80 add b |
0431 0223 9B sbb e |
0432 0224 80 add b |
0433 0225 9C sbb h |
0434 0226 80 add b |
0435 0227 9D sbb l |
0436 0228 FE E0 cpi 0e0H |
0437 022A C4 0A 05 cnz cpuer ;test "sbb" b,c,d,e,h,l |
0438 022D 3E 80 mvi a,080H |
0439 022F 87 add a |
0440 0230 9F sbb a |
0441 0231 FE FF cpi 0ffH |
0442 0233 C4 0A 05 cnz cpuer ;test "sbb" a |
0443 0236 3E FF mvi a,0ffH |
0444 0238 06 FE mvi b,0feH |
0445 023A 0E FC mvi c,0fcH |
0446 023C 16 EF mvi d,0efH |
0447 023E 1E 7F mvi e,07fH |
0448 0240 26 F4 mvi h,0f4H |
0449 0242 2E BF mvi l,0bfH |
0450 0244 37 stc |
0451 0245 A7 ana a |
0452 0246 DC 0A 05 cc cpuer |
0453 0249 A1 ana c |
0454 024A A2 ana d |
0455 024B A3 ana e |
0456 024C A4 ana h |
0457 024D A5 ana l |
0458 024E A7 ana a |
0459 024F FE 24 cpi 024H |
0460 0251 C4 0A 05 cnz cpuer ;test "ana" b,c,d,e,h,l,a |
0461 0254 AF xra a |
0462 0255 06 01 mvi b,001H |
0463 0257 0E 02 mvi c,002H |
0464 0259 16 04 mvi d,004H |
0465 025B 1E 08 mvi e,008H |
0466 025D 26 10 mvi h,010H |
0467 025F 2E 20 mvi l,020H |
0468 0261 37 stc |
0469 0262 B0 ora b |
0470 0263 DC 0A 05 cc cpuer |
0471 0266 B1 ora c |
0472 0267 B2 ora d |
0473 0268 B3 ora e |
0474 0269 B4 ora h |
0475 026A B5 ora l |
0476 026B B7 ora a |
0477 026C FE 3F cpi 03fH |
0478 026E C4 0A 05 cnz cpuer ;test "ora" b,c,d,e,h,l,a |
0479 0271 3E 00 mvi a,0H |
0480 0273 26 8F mvi h,08fH |
0481 0275 2E 4F mvi l,04fH |
0482 0277 37 stc |
0483 0278 A8 xra b |
0484 0279 DC 0A 05 cc cpuer |
0485 027C A9 xra c |
0486 027D AA xra d |
0487 027E AB xra e |
0488 027F AC xra h |
0489 0280 AD xra l |
0490 0281 FE CF cpi 0cfH |
0491 0283 C4 0A 05 cnz cpuer ;test "xra" b,c,d,e,h,l |
0492 0286 AF xra a |
0493 0287 C4 0A 05 cnz cpuer ;test "xra" a |
0494 028A 06 44 mvi b,044H |
0495 028C 0E 45 mvi c,045H |
0496 028E 16 46 mvi d,046H |
0497 0290 1E 47 mvi e,047H |
0498 0292 26 05 mvi h,temp0 / 0ffH ;high byte of test memory location |
0499 0294 2E 16 mvi l,temp0 & 0ffH ;low byte of test memory location |
0500 0296 70 mov m,b |
0501 0297 06 00 mvi b,0H |
0502 0299 46 mov b,m |
0503 029A 3E 44 mvi a,044H |
0504 029C B8 cmp b |
0505 029D C4 0A 05 cnz cpuer ;test "mov" m,b and b,m |
0506 02A0 72 mov m,d |
0507 02A1 16 00 mvi d,0H |
0508 02A3 56 mov d,m |
0509 02A4 3E 46 mvi a,046H |
0510 02A6 BA cmp d |
0511 02A7 C4 0A 05 cnz cpuer ;test "mov" m,d and d,m |
0512 02AA 73 mov m,e |
0513 02AB 1E 00 mvi e,0H |
0514 02AD 5E mov e,m |
0515 02AE 3E 47 mvi a,047H |
0516 02B0 BB cmp e |
0517 02B1 C4 0A 05 cnz cpuer ;test "mov" m,e and e,m |
0518 02B4 74 mov m,h |
0519 02B5 26 05 mvi h,temp0 / 0ffH |
0520 02B7 2E 16 mvi l,temp0 & 0ffH |
0521 02B9 66 mov h,m |
0522 02BA 3E 05 mvi a,temp0 / 0ffH |
0523 02BC BC cmp h |
0524 02BD C4 0A 05 cnz cpuer ;test "mov" m,h and h,m |
0525 02C0 75 mov m,l |
0526 02C1 26 05 mvi h,temp0 / 0ffH |
0527 02C3 2E 16 mvi l,temp0 & 0ffH |
0528 02C5 6E mov l,m |
0529 02C6 3E 16 mvi a,temp0 & 0ffH |
0530 02C8 BD cmp l |
0531 02C9 C4 0A 05 cnz cpuer ;test "mov" m,l and l,m |
0532 02CC 26 05 mvi h,temp0 / 0ffH |
0533 02CE 2E 16 mvi l,temp0 & 0ffH |
0534 02D0 3E 32 mvi a,032H |
0535 02D2 77 mov m,a |
0536 02D3 BE cmp m |
0537 02D4 C4 0A 05 cnz cpuer ;test "mov" m,a |
0538 02D7 86 add m |
0539 02D8 FE 64 cpi 064H |
0540 02DA C4 0A 05 cnz cpuer ;test "add" m |
0541 02DD AF xra a |
0542 02DE 7E mov a,m |
0543 02DF FE 32 cpi 032H |
0544 02E1 C4 0A 05 cnz cpuer ;test "mov" a,m |
0545 02E4 26 05 mvi h,temp0 / 0ffH |
0546 02E6 2E 16 mvi l,temp0 & 0ffH |
0547 02E8 7E mov a,m |
0548 02E9 96 sub m |
0549 02EA C4 0A 05 cnz cpuer ;test "sub" m |
0550 02ED 3E 80 mvi a,080H |
0551 02EF 87 add a |
0552 02F0 8E adc m |
0553 02F1 FE 33 cpi 033H |
0554 02F3 C4 0A 05 cnz cpuer ;test "adc" m |
0555 02F6 3E 80 mvi a,080H |
0556 02F8 87 add a |
0557 02F9 9E sbb m |
0558 02FA FE CD cpi 0cdH |
0559 02FC C4 0A 05 cnz cpuer ;test "sbb" m |
0560 02FF 37 stc |
0561 0300 A6 ana m |
0562 0301 DC 0A 05 cc cpuer |
0563 0304 C4 0A 05 cnz cpuer ;test "ana" m |
0564 0307 3E 25 mvi a,025H |
0565 0309 37 stc |
0566 030A B6 ora m |
0567 030B DC 0A 05 cc cpuer |
0568 030E FE 37 cpi 37H |
0569 0310 C4 0A 05 cnz cpuer ;test "ora" m |
0570 0313 37 stc |
0571 0314 AE xra m |
0572 0315 DC 0A 05 cc cpuer |
0573 0318 FE 05 cpi 005H |
0574 031A C4 0A 05 cnz cpuer ;test "xra" m |
0575 031D 36 55 mvi m,055H |
0576 031F 34 inr m |
0577 0320 35 dcr m |
0578 0321 86 add m |
0579 0322 FE 5A cpi 05aH |
0580 0324 C4 0A 05 cnz cpuer ;test "inr","dcr",and "mvi" m |
0581 0327 01 FF 12 lxi b,12ffH |
0582 032A 11 FF 12 lxi d,12ffH |
0583 032D 21 FF 12 lxi h,12ffH |
0584 0330 03 inx b |
0585 0331 13 inx d |
0586 0332 23 inx h |
0587 0333 3E 13 mvi a,013H |
0588 0335 B8 cmp b |
0589 0336 C4 0A 05 cnz cpuer ;test "lxi" and "inx" b |
0590 0339 BA cmp d |
0591 033A C4 0A 05 cnz cpuer ;test "lxi" and "inx" d |
0592 033D BC cmp h |
0593 033E C4 0A 05 cnz cpuer ;test "lxi" and "inx" h |
0594 0341 3E 00 mvi a,0H |
0595 0343 B9 cmp c |
0596 0344 C4 0A 05 cnz cpuer ;test "lxi" and "inx" b |
0597 0347 BB cmp e |
0598 0348 C4 0A 05 cnz cpuer ;test "lxi" and "inx" d |
0599 034B BD cmp l |
0600 034C C4 0A 05 cnz cpuer ;test "lxi" and "inx" h |
0601 034F 0B dcx b |
0602 0350 1B dcx d |
0603 0351 2B dcx h |
0604 0352 3E 12 mvi a,012H |
0605 0354 B8 cmp b |
0606 0355 C4 0A 05 cnz cpuer ;test "dcx" b |
0607 0358 BA cmp d |
0608 0359 C4 0A 05 cnz cpuer ;test "dcx" d |
0609 035C BC cmp h |
0610 035D C4 0A 05 cnz cpuer ;test "dcx" h |
0611 0360 3E FF mvi a,0ffH |
0612 0362 B9 cmp c |
0613 0363 C4 0A 05 cnz cpuer ;test "dcx" b |
0614 0366 BB cmp e |
0615 0367 C4 0A 05 cnz cpuer ;test "dcx" d |
0616 036A BD cmp l |
0617 036B C4 0A 05 cnz cpuer ;test "dcx" h |
0618 036E 32 16 05 sta temp0 |
0619 0371 AF xra a |
0620 0372 3A 16 05 lda temp0 |
0621 0375 FE FF cpi 0ffH |
0622 0377 C4 0A 05 cnz cpuer ;test "lda" and "sta" |
0623 037A 2A 14 05 lhld tempp |
0624 037D 22 16 05 shld temp0 |
0625 0380 3A 14 05 lda tempp |
0626 0383 47 mov b,a |
0627 0384 3A 16 05 lda temp0 |
0628 0387 B8 cmp b |
0629 0388 C4 0A 05 cnz cpuer ;test "lhld" and "shld" |
0630 038B 3A 15 05 lda tempp+1 |
0631 038E 47 mov b,a |
0632 038F 3A 17 05 lda temp0+1 |
0633 0392 B8 cmp b |
0634 0393 C4 0A 05 cnz cpuer ;test "lhld" and "shld" |
0635 0396 3E AA mvi a,0aaH |
0636 0398 32 16 05 sta temp0 |
0637 039B 44 mov b,h |
0638 039C 4D mov c,l |
0639 039D AF xra a |
0640 039E 0A ldax b |
0641 039F FE AA cpi 0aaH |
0642 03A1 C4 0A 05 cnz cpuer ;test "ldax" b |
0643 03A4 3C inr a |
0644 03A5 02 stax b |
0645 03A6 3A 16 05 lda temp0 |
0646 03A9 FE AB cpi 0abH |
0647 03AB C4 0A 05 cnz cpuer ;test "stax" b |
0648 03AE 3E 77 mvi a,077H |
0649 03B0 32 16 05 sta temp0 |
0650 03B3 2A 14 05 lhld tempp |
0651 03B6 11 00 00 lxi d,00000H |
0652 03B9 EB xchg |
0653 03BA AF xra a |
0654 03BB 1A ldax d |
0655 03BC FE 77 cpi 077H |
0656 03BE C4 0A 05 cnz cpuer ;test "ldax" d and "xchg" |
0657 03C1 AF xra a |
0658 03C2 84 add h |
0659 03C3 85 add l |
0660 03C4 C4 0A 05 cnz cpuer ;test "xchg" |
0661 03C7 3E CC mvi a,0ccH |
0662 03C9 12 stax d |
0663 03CA 3A 16 05 lda temp0 |
0664 03CD FE CC cpi 0ccH |
0665 03CF 12 stax d |
0666 03D0 3A 16 05 lda temp0 |
0667 03D3 FE CC cpi 0ccH |
0668 03D5 C4 0A 05 cnz cpuer ;test "stax" d |
0669 03D8 21 77 77 lxi h,07777H |
0670 03DB 29 dad h |
0671 03DC 3E EE mvi a,0eeH |
0672 03DE BC cmp h |
0673 03DF C4 0A 05 cnz cpuer ;test "dad" h |
0674 03E2 BD cmp l |
0675 03E3 C4 0A 05 cnz cpuer ;test "dad" h |
0676 03E6 21 55 55 lxi h,05555H |
0677 03E9 01 FF FF lxi b,0ffffH |
0678 03EC 09 dad b |
0679 03ED 3E 55 mvi a,055H |
0680 03EF D4 0A 05 cnc cpuer ;test "dad" b |
0681 03F2 BC cmp h |
0682 03F3 C4 0A 05 cnz cpuer ;test "dad" b |
0683 03F6 3E 54 mvi a,054H |
0684 03F8 BD cmp l |
0685 03F9 C4 0A 05 cnz cpuer ;test "dad" b |
0686 03FC 21 AA AA lxi h,0aaaaH |
0687 03FF 11 33 33 lxi d,03333H |
0688 0402 19 dad d |
0689 0403 3E DD mvi a,0ddH |
0690 0405 BC cmp h |
0691 0406 C4 0A 05 cnz cpuer ;test "dad" d |
0692 0409 BD cmp l |
0693 040A C4 0A 05 cnz cpuer ;test "dad" b |
0694 040D 37 stc |
0695 040E D4 0A 05 cnc cpuer ;test "stc" |
0696 0411 3F cmc |
0697 0412 DC 0A 05 cc cpuer ;test "cmc |
0698 0415 3E AA mvi a,0aaH |
0699 0417 2F cma |
0700 0418 FE 55 cpi 055H |
0701 041A C4 0A 05 cnz cpuer ;test "cma" |
0702 041D B7 ora a ;re-set auxiliary carry |
0703 041E 27 daa |
0704 041F FE 55 cpi 055H |
0705 0421 C4 0A 05 cnz cpuer ;test "daa" |
0706 0424 3E 88 mvi a,088H |
0707 0426 87 add a |
0708 0427 27 daa |
0709 0428 FE 76 cpi 076H |
0710 042A C4 0A 05 cnz cpuer ;test "daa" |
0711 042D AF xra a |
0712 042E 3E AA mvi a,0aaH |
0713 0430 27 daa |
0714 0431 D4 0A 05 cnc cpuer ;test "daa" |
0715 0434 FE 10 cpi 010H |
0716 0436 C4 0A 05 cnz cpuer ;test "daa" |
0717 0439 AF xra a |
0718 043A 3E 9A mvi a,09aH |
0719 043C 27 daa |
0720 043D D4 0A 05 cnc cpuer ;test "daa" |
0721 0440 C4 0A 05 cnz cpuer ;test "daa" |
0722 0443 37 stc |
0723 0444 3E 42 mvi a,042H |
0724 0446 07 rlc |
0725 0447 DC 0A 05 cc cpuer ;test "rlc" for re-set carry |
0726 044A 07 rlc |
0727 044B D4 0A 05 cnc cpuer ;test "rlc" for set carry |
0728 044E FE 09 cpi 009H |
0729 0450 C4 0A 05 cnz cpuer ;test "rlc" for rotation |
0730 0453 0F rrc |
0731 0454 D4 0A 05 cnc cpuer ;test "rrc" for set carry |
0732 0457 0F rrc |
0733 0458 FE 42 cpi 042H |
0734 045A C4 0A 05 cnz cpuer ;test "rrc" for rotation |
0735 045D 17 ral |
0736 045E 17 ral |
0737 045F D4 0A 05 cnc cpuer ;test "ral" for set carry |
0738 0462 FE 08 cpi 008H |
0739 0464 C4 0A 05 cnz cpuer ;test "ral" for rotation |
0740 0467 1F rar |
0741 0468 1F rar |
0742 0469 DC 0A 05 cc cpuer ;test "rar" for re-set carry |
0743 046C FE 02 cpi 002H |
0744 046E C4 0A 05 cnz cpuer ;test "rar" for rotation |
0745 0471 01 34 12 lxi b,01234H |
0746 0474 11 AA AA lxi d,0aaaaH |
0747 0477 21 55 55 lxi h,05555H |
0748 047A AF xra a |
0749 047B C5 push b |
0750 047C D5 push d |
0751 047D E5 push h |
0752 047E F5 push psw |
0753 047F 01 00 00 lxi b,00000H |
0754 0482 11 00 00 lxi d,00000H |
0755 0485 21 00 00 lxi h,00000H |
0756 0488 3E C0 mvi a,0c0H |
0757 048A C6 F0 adi 0f0H |
0758 048C F1 pop psw |
0759 048D E1 pop h |
0760 048E D1 pop d |
0761 048F C1 pop b |
0762 0490 DC 0A 05 cc cpuer ;test "push psw" and "pop psw" |
0763 0493 C4 0A 05 cnz cpuer ;test "push psw" and "pop psw" |
0764 0496 E4 0A 05 cpo cpuer ;test "push psw" and "pop psw" |
0765 0499 FC 0A 05 cm cpuer ;test "push psw" and "pop psw" |
0766 049C 3E 12 mvi a,012H |
0767 049E B8 cmp b |
0768 049F C4 0A 05 cnz cpuer ;test "push b" and "pop b" |
0769 04A2 3E 34 mvi a,034H |
0770 04A4 B9 cmp c |
0771 04A5 C4 0A 05 cnz cpuer ;test "push b" and "pop b" |
0772 04A8 3E AA mvi a,0aaH |
0773 04AA BA cmp d |
0774 04AB C4 0A 05 cnz cpuer ;test "push d" and "pop d" |
0775 04AE BB cmp e |
0776 04AF C4 0A 05 cnz cpuer ;test "push d" and "pop d" |
0777 04B2 3E 55 mvi a,055H |
0778 04B4 BC cmp h |
0779 04B5 C4 0A 05 cnz cpuer ;test "push h" and "pop h" |
0780 04B8 BD cmp l |
0781 04B9 C4 0A 05 cnz cpuer ;test "push h" and "pop h" |
0782 04BC 21 00 00 lxi h,00000H |
0783 04BF 39 dad sp |
0784 04C0 22 1B 05 shld savstk ;save the "old" stack-pointer; |
0785 04C3 31 1A 05 lxi sp,temp4 |
0786 04C6 3B dcx sp |
0787 04C7 3B dcx sp |
0788 04C8 33 inx sp |
0789 04C9 3B dcx sp |
0790 04CA 3E 55 mvi a,055H |
0791 04CC 32 18 05 sta temp2 |
0792 04CF 2F cma |
0793 04D0 32 19 05 sta temp3 |
0794 04D3 C1 pop b |
0795 04D4 B8 cmp b |
0796 04D5 C4 0A 05 cnz cpuer ;test "lxi","dad","inx",and "dcx" sp |
0797 04D8 2F cma |
0798 04D9 B9 cmp c |
0799 04DA C4 0A 05 cnz cpuer ;test "lxi","dad","inx", and "dcx" sp |
0800 04DD 21 1A 05 lxi h,temp4 |
0801 04E0 F9 sphl |
0802 04E1 21 33 77 lxi h,07733H |
0803 04E4 3B dcx sp |
0804 04E5 3B dcx sp |
0805 04E6 E3 xthl |
0806 04E7 3A 19 05 lda temp3 |
0807 04EA FE 77 cpi 077H |
0808 04EC C4 0A 05 cnz cpuer ;test "sphl" and "xthl" |
0809 04EF 3A 18 05 lda temp2 |
0810 04F2 FE 33 cpi 033H |
0811 04F4 C4 0A 05 cnz cpuer ;test "sphl" and "xthl" |
0812 04F7 3E 55 mvi a,055H |
0813 04F9 BD cmp l |
0814 04FA C4 0A 05 cnz cpuer ;test "sphl" and "xthl" |
0815 04FD 2F cma |
0816 04FE BC cmp h |
0817 04FF C4 0A 05 cnz cpuer ;test "sphl" and "xthl" |
0818 0502 2A 1B 05 lhld savstk ;restore the "old" stack-pointer |
0819 0505 F9 sphl |
0820 0506 21 0F 05 lxi h,cpuok |
0821 0509 E9 pchl ;test "pchl" |
0822 050A |
0823 050A 3E AA cpuer: mvi a, 0aaH ; set exit code (failure) |
0824 050C D3 20 out 20h |
0825 050E 76 hlt ; stop here |
0826 050F |
0827 050F 3E 55 cpuok: mvi a, 55H ; |
0828 0511 D3 20 out 20h |
0829 0513 76 hlt ; stop here - no trap |
0830 0514 |
0831 0514 |
0832 0514 ; |
0833 0514 ; Data area in program space |
0834 0514 ; |
0835 0514 16 05 tempp: .dw temp0 ;pointer used to test "lhld","shld", |
0836 0516 ; and "ldax" instructions |
0837 0516 ; |
0838 0516 ; Data area in variable space |
0839 0516 ; |
0840 0516 temp0: ds(1) ;temporary storage for cpu test memory locations |
0840 0517 |
0841 0517 temp1: ds(1) ;temporary storage for cpu test memory locations |
0841 0518 |
0842 0518 temp2: ds(1) ;temporary storage for cpu test memory locations |
0842 0519 |
0843 0519 temp3: ds(1) ;temporary storage for cpu test memory locations |
0843 051A |
0844 051A temp4: ds(1) ;temporary storage for cpu test memory locations |
0844 051B |
0845 051B savstk: ds(2) ;temporary stack-pointer storage location |
0845 051D |
0846 051D |
0847 051D ds(256) ;de-bug stack pointer storage area |
0847 061D |
0848 061D 00 00 stack: .dw 0 |
0849 061F |
0850 061F .end |
0851 061F |
tasm: Number of errors = 0 |
/trunk/sw/tb/tb0/tb0.hex
0,0 → 1,57
:18000000311D063E77E600CA0D00CD0A05D21300CD0A05EA1900CD0AAB |
:1800180005F21F00CD0A05C22E00DA2E00E22E00FA2E00C33100CD0AE3 |
:1800300005C606C23900CD0A05DA4200E24200F24500CD0A05C670E2A5 |
:180048004D00CD0A05FA5600CA5600D25900CD0A05C681FA6100CD0A87 |
:1800600005CA6A00DA6A00E26D00CD0A05C6FEDA7500CD0A05CA7E00A9 |
:18007800E27E00FA8100CD0A05FE00DA9900CA9900FEF5DA9900C29924 |
:1800900000FEFFCA9900DA9C00CD0A05CE0ACE0AFE0BCAA800CD0A059F |
:1800A800D60CD60FFEF0CAB400CD0A05DEF1DE0EFEF0CAC000CD0A0522 |
:1800C000E655DC0A05CC0A05FE50CAD000CD0A05F63ADC0A05CC0A056D |
:1800D800FE7ACAE000CD0A05EE0FDC0A05CC0A05FE75CAF000CD0A0546 |
:1800F000E600DC0A05E40A05FC0A05C40A05FE00CA0601CD0A05D6775E |
:18010800D40A05EC0A05F40A05CC0A05FE89CA1C01CD0A05E6FFE429E7 |
:1801200001FED9CA8601CD0A05E8C610EC3501C602E0CD0A05E0C62098 |
:18013800FC4101C604E8CD0A05F0C680F44D01C680F8CD0A05F8C64053 |
:18015000D45901C640F0CD0A05D8C68FDC6501D602D0CD0A05D0C6F717 |
:18016800C47101C6FED8CD0A05C8C601CC7D01C6D0C0CD0A05C0C647F9 |
:18018000FE47C8CD0A053E773C4704480D515A636C7D3D4F596B455011 |
:18019800627C57146A4D0C614405587B5F1C4360244C6955157A67255F |
:1801B0005442682C5D1D4B796F2D655C534A4178FE77C40A05AF06011E |
:1801C8000E0316071E0F261F2E3F80818283848587FEF0C40A0590919A |
:1801E00092939495FE78C40A0597C40A053E808706010E0216031E046F |
:1801F80026052E0688068080808980808A80808B80808C80808D8080CB |
:180210008FFE37C40A053E808706019806FF8099809A809B809C809DCF |
:18022800FEE0C40A053E80879FFEFFC40A053EFF06FE0EFC16EF1E7F6C |
:1802400026F42EBF37A7DC0A05A1A2A3A4A5A7FE24C40A05AF06010E47 |
:180258000216041E0826102E2037B0DC0A05B1B2B3B4B5B7FE3FC40AB5 |
:18027000053E00268F2E4F37A8DC0A05A9AAABACADFECFC40A05AFC4CD |
:180288000A0506440E4516461E4726052E16700600463E44B8C40A05B9 |
:1802A000721600563E46BAC40A05731E005E3E47BBC40A057426052E88 |
:1802B80016663E05BCC40A057526052E166E3E16BDC40A0526052E163B |
:1802D0003E3277BEC40A0586FE64C40A05AF7EFE32C40A0526052E1644 |
:1802E8007E96C40A053E80878EFE33C40A053E80879EFECDC40A053788 |
:18030000A6DC0A05C40A053E2537B6DC0A05FE37C40A0537AEDC0A056E |
:18031800FE05C40A053655343586FE5AC40A0501FF1211FF1221FF12EC |
:180330000313233E13B8C40A05BAC40A05BCC40A053E00B9C40A05BBFF |
:18034800C40A05BDC40A050B1B2B3E12B8C40A05BAC40A05BCC40A05F2 |
:180360003EFFB9C40A05BBC40A05BDC40A05321605AF3A1605FEFFC48C |
:180378000A052A14052216053A1405473A1605B8C40A053A1505473A8F |
:180390001705B8C40A053EAA321605444DAF0AFEAAC40A053C023A1626 |
:1803A80005FEABC40A053E773216052A1405110000EBAF1AFE77C40A6F |
:1803C00005AF8485C40A053ECC123A1605FECC123A1605FECCC40A0556 |
:1803D800217777293EEEBCC40A05BDC40A0521555501FFFF093E55D450 |
:1803F0000A05BCC40A053E54BDC40A0521AAAA113333193EDDBCC40A8B |
:1804080005BDC40A0537D40A053FDC0A053EAA2FFE55C40A05B727FEEA |
:1804200055C40A053E888727FE76C40A05AF3EAA27D40A05FE10C40A64 |
:1804380005AF3E9A27D40A05C40A05373E4207DC0A0507D40A05FE09A9 |
:18045000C40A050FD40A050FFE42C40A051717D40A05FE08C40A051FA4 |
:180468001FDC0A05FE02C40A0501341211AAAA215555AFC5D5E5F50104 |
:1804800000001100002100003EC0C6F0F1E1D1C1DC0A05C40A05E40A6E |
:1804980005FC0A053E12B8C40A053E34B9C40A053EAABAC40A05BBC46F |
:1804B0000A053E55BCC40A05BDC40A0521000039221B05311A053B3B11 |
:1804C800333B3E553218052F321905C1B8C40A052FB9C40A05211A0506 |
:1804E000F92133773B3BE33A1905FE77C40A053A1805FE33C40A053EAE |
:1804F80055BDC40A052FBCC40A052A1B05F9210F05E93EAAD320763E59 |
:0605100055D3207616050C |
:02061D000000DB |
:00000001FF |
/trunk/sw/tb/tb1/obj_code_pkg.vhdl
0,0 → 1,54
-- obj_code_pkg -- Object code in VHDL constant table for BRAM initialization. |
-- Generated automatically with script 'build_rom.py'. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.l80pkg.all; |
|
package obj_code_pkg is |
|
constant obj_code : obj_code_t(0 to 313) := ( |
X"c3", X"60", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c6", X"01", X"fb", X"c9", X"00", X"00", X"00", X"00", |
X"3c", X"fb", X"c9", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"3c", X"00", X"00", X"00", X"ef", X"00", X"00", X"00", |
X"23", X"00", X"00", X"00", X"3e", X"42", X"00", X"00", |
X"21", X"34", X"12", X"00", X"c3", X"2f", X"01", X"00", |
X"cd", X"34", X"01", X"00", X"cd", X"37", X"01", X"00", |
X"31", X"7a", X"01", X"3e", X"13", X"e7", X"fe", X"14", |
X"c2", X"2a", X"01", X"3e", X"00", X"d3", X"10", X"fb", |
X"3e", X"14", X"d3", X"11", X"3e", X"27", X"00", X"00", |
X"00", X"00", X"fe", X"28", X"c2", X"2a", X"01", X"3e", |
X"01", X"d3", X"10", X"fb", X"3e", X"14", X"d3", X"11", |
X"3e", X"20", X"00", X"00", X"00", X"00", X"fe", X"21", |
X"c2", X"2a", X"01", X"21", X"ff", X"13", X"3e", X"02", |
X"d3", X"10", X"fb", X"3e", X"04", X"d3", X"11", X"00", |
X"00", X"7d", X"fe", X"00", X"c2", X"2a", X"01", X"7c", |
X"fe", X"14", X"c2", X"2a", X"01", X"3e", X"03", X"d3", |
X"10", X"fb", X"3e", X"04", X"d3", X"11", X"00", X"00", |
X"fe", X"42", X"c2", X"2a", X"01", X"3e", X"04", X"d3", |
X"10", X"fb", X"3e", X"04", X"d3", X"11", X"00", X"00", |
X"7c", X"fe", X"12", X"c2", X"2a", X"01", X"7d", X"fe", |
X"34", X"c2", X"2a", X"01", X"3e", X"05", X"d3", X"10", |
X"fb", X"3e", X"04", X"d3", X"11", X"00", X"00", X"fe", |
X"79", X"c2", X"2a", X"01", X"3e", X"06", X"d3", X"10", |
X"fb", X"3e", X"04", X"d3", X"11", X"3c", X"00", X"fe", |
X"05", X"c2", X"2a", X"01", X"78", X"fe", X"19", X"c2", |
X"2a", X"01", X"f3", X"3e", X"07", X"d3", X"10", X"3e", |
X"04", X"d3", X"11", X"00", X"00", X"00", X"3e", X"50", |
X"d3", X"12", X"3e", X"01", X"d3", X"10", X"fb", X"3e", |
X"14", X"d3", X"11", X"3e", X"27", X"00", X"00", X"3c", |
X"00", X"00", X"3c", X"00", X"00", X"00", X"00", X"00", |
X"fe", X"2b", X"c2", X"2a", X"01", X"3e", X"55", X"d3", |
X"20", X"76", X"3e", X"aa", X"d3", X"20", X"76", X"3e", |
X"79", X"c3", X"df", X"00", X"06", X"19", X"c9", X"c3", |
X"2a", X"01" |
); |
|
end package obj_code_pkg; |
/trunk/sw/tb/tb1/build.bat
0,0 → 1,26
@rem Build script for the TB1 test bench. |
@rem This script will assemble the program source and run the object code |
@rem conversion tool to build a vhdl package that can then be used to initalize |
@rem the test bench entity. |
@rem You need to edit this file with the path to your TASM installation. |
@rem Set the program name. |
@set PROG=tb1 |
@rem Edit to point to the directory you installed TASM in. |
@set TASM_DIR=..\..\..\local\tasm |
@rem Remove output from previous assembly. |
@del %PROG%.hex |
@del %PROG%.lst |
@rem Make sure TASM is able to find its table files (see TASM documentation). |
@set TASMTABS=%TASM_DIR% |
@rem Run assembler |
%TASM_DIR%\tasm -85 -a %PROG%.asm %PROG%.hex %PROG%.lst |
@rem Check TASM return value |
@if errorlevel 1 goto done |
@rem Build vhdl test bench file with object code embedded into it. |
python ..\..\..\tools\obj2hdl\src\obj2hdl.py ^ |
-f %PROG%.hex ^ |
-c obj_code ^ |
--package obj_code_pkg ^ |
--output obj_code_pkg.vhdl |
:done |
|
/trunk/sw/tb/tb1/tb1.asm
0,0 → 1,247
;******************************************************************************* |
; tb1.asm -- light8080 core test bench 1: interrupt & halt test |
;******************************************************************************* |
; Should be used with test bench template vhdl\test\tb_template.vhdl |
; Assembler format compatible with TASM for DOS and Linux. |
;******************************************************************************* |
; This program will test a few different interrupt vectors and the interrupt |
; enable/disable flag, but not exhaustively. |
; Besides, it will not test long intr assertions (more than 1 cycle). |
;******************************************************************************* |
|
; DS pseudo-directive; reserve space in bytes, without initializing it |
#define ds(n) \.org $+n |
|
; OUTing some value here will trigger intr in the n-th cycle from the end of |
; the 'out' instruction. For example, writing a 0 will trigger intr in the 1st |
; cycle of the following instruction, and so on. |
intr_trigger: .equ 11h |
; The value OUTput to this address will be used as the 'interrupt source' when |
; the intr line is asserted. In the inta acknowledge cycle, the simulated |
; interrupt logic will feed the CPU the instruction at memory address |
; 40h+source*4. See vhdl\test\tb_template.vhdl for details. |
intr_source: .equ 10h |
; The value OUTput to this port is the number of cycles the intr signal will |
; remain high after being asserted. By default this is 1 cycle. |
intr_width: .equ 12h |
; OUTing something here will stop the simulation. A 0x055 will signal a |
; success, a 0x0aa a failure. |
test_outcome: .equ 20h |
|
;******************************************************************************* |
|
.org 0H |
jmp start ; skip the rst address area |
|
; used to test that RST works |
.org 20H |
adi 1H |
ei |
ret |
|
; used to test the RST instruction as intr vector |
.org 28H |
inr a |
ei |
ret |
|
;***** simulated interrupt vectors in area 0040h-005fh ***************** |
|
.org 40h+(0*4) ; simulated interrupt vector 0 |
inr a |
.org 40h+(1*4) ; simulated interrupt vector 1 |
rst 5 |
.org 40h+(2*4) ; simulated interrupt vector 2 |
inx h |
.org 40h+(3*4) ; simulated interrupt vector 3 |
mvi a,42h |
.org 40h+(4*4) ; simulated interrupt vector 4 |
lxi h,1234h |
.org 40h+(5*4) ; simulated interrupt vector 5 |
jmp test_jump |
.org 40h+(6*4) ; simulated interrupt vector 6 |
call test_call |
.org 40h+(7*4) ; simulated interrupt vector 7 |
call shouldnt_trigger |
|
|
;***** program entry point ********************************************* |
|
start: .org 60H |
lxi sp,stack |
|
; first of all, make sure the RST instruction works, we have a valid |
; simulated stack, etc. |
mvi a,13h |
rst 4 ; this should add 1 to ACC |
cpi 14h |
jnz fail |
|
; now we'll try a few different interrupt vectors (single byte and |
; multi-byte). Since interrupts are disabled upon acknowledge, we have |
; to reenable them after every test. |
|
; try single-byte interrupt vector: INR A |
mvi a,0 |
out intr_source |
ei |
mvi a,014h |
out intr_trigger |
mvi a,027h |
nop ; the interrupt will hit in this nop area |
nop |
nop |
nop |
cpi 028h |
jnz fail |
|
; another single-byte vector: RST 5 |
mvi a,1 |
out intr_source |
ei |
mvi a,014h |
out intr_trigger ; the interrupt vector will do a rst 5, and |
mvi a,020h ; the rst routine will add 1 to the ACC |
nop ; and reenable interrupts |
nop |
nop |
nop |
cpi 021h |
jnz fail |
|
; another single-byte code: INX H |
lxi h,13ffh |
mvi a,2 |
out intr_source |
ei |
mvi a,4 |
out intr_trigger |
nop |
nop |
mov a,l |
cpi 0H |
jnz fail |
mov a,h |
cpi 14h |
jnz fail |
|
; a two-byte instruction: mvi a, 42h |
mvi a,3 |
out intr_source |
ei |
mvi a,4 |
out intr_trigger |
nop |
nop |
cpi 42h |
jnz fail |
|
; a three-byte instruction: lxi h,1234h |
mvi a,4 |
out intr_source |
ei |
mvi a,4 |
out intr_trigger |
nop |
nop |
mov a,h |
cpi 12h |
jnz fail |
mov a,l |
cpi 34h |
jnz fail |
|
; a 3-byte jump: jmp test_jump |
; if this fails, the test will probably derail |
mvi a,5 |
out intr_source |
ei |
mvi a,4 |
out intr_trigger |
nop |
nop |
comeback: |
cpi 79h |
jnz fail |
|
; a 3-byte call: call test_call |
; if this fails, the test will probably derail |
mvi a,6 |
out intr_source |
ei |
mvi a,4 |
out intr_trigger |
inr a |
; the interrupt will come back here, hopefully |
nop |
cpi 05h |
jnz fail |
mov a,b |
cpi 19h |
jnz fail |
|
; now, with interrupts disabled, make sure interrupts are ignored |
di |
mvi a,07h ; source 7 catches any unwanted interrupts |
out intr_source |
mvi a,04h |
out intr_trigger |
nop |
nop |
nop |
|
; Ok. So far we have tested only 1-cycle intr assertions. Now we'll |
; see what happens when we leave intr asserted for a long time (as would |
; happen intr was used for single-step debugging, for instance) |
|
; try single-byte interrupt vector (INR A) |
mvi a, 80 |
out intr_width |
mvi a,1 |
out intr_source |
ei |
mvi a,014h |
out intr_trigger |
mvi a,027h |
nop ; the interrupts will hit in this nop area |
nop |
inr a |
nop |
nop |
inr a |
nop |
nop |
nop |
nop |
nop |
cpi 02bh |
jnz fail |
|
|
; finished, run into the success outcome code |
|
success: |
mvi a,55h |
out test_outcome |
hlt |
fail: mvi a,0aah |
out test_outcome |
hlt |
|
test_jump: |
mvi a,79h |
jmp comeback |
|
test_call: |
mvi b,19h |
ret |
|
; called when an interrupt has been acknowledged that shouldn't have |
shouldnt_trigger: |
jmp fail |
|
; data space |
ds(64) |
stack: ds(2) |
.end |
|
/trunk/sw/tb/tb1/tb1.lst
0,0 → 1,249
0001 0000 ;******************************************************************************* |
0002 0000 ; tb1.asm -- light8080 core test bench 1: interrupt & halt test |
0003 0000 ;******************************************************************************* |
0004 0000 ; Should be used with test bench template vhdl\test\tb_template.vhdl |
0005 0000 ; Assembler format compatible with TASM for DOS and Linux. |
0006 0000 ;******************************************************************************* |
0007 0000 ; This program will test a few different interrupt vectors and the interrupt |
0008 0000 ; enable/disable flag, but not exhaustively. |
0009 0000 ; Besides, it will not test long intr assertions (more than 1 cycle). |
0010 0000 ;******************************************************************************* |
0011 0000 |
0012 0000 ; DS pseudo-directive; reserve space in bytes, without initializing it |
0013 0000 #define ds(n) \.org $+n |
0014 0000 |
0015 0000 ; OUTing some value here will trigger intr in the n-th cycle from the end of |
0016 0000 ; the 'out' instruction. For example, writing a 0 will trigger intr in the 1st |
0017 0000 ; cycle of the following instruction, and so on. |
0018 0000 intr_trigger: .equ 11h |
0019 0000 ; The value OUTput to this address will be used as the 'interrupt source' when |
0020 0000 ; the intr line is asserted. In the inta acknowledge cycle, the simulated |
0021 0000 ; interrupt logic will feed the CPU the instruction at memory address |
0022 0000 ; 40h+source*4. See vhdl\test\tb_template.vhdl for details. |
0023 0000 intr_source: .equ 10h |
0024 0000 ; The value OUTput to this port is the number of cycles the intr signal will |
0025 0000 ; remain high after being asserted. By default this is 1 cycle. |
0026 0000 intr_width: .equ 12h |
0027 0000 ; OUTing something here will stop the simulation. A 0x055 will signal a |
0028 0000 ; success, a 0x0aa a failure. |
0029 0000 test_outcome: .equ 20h |
0030 0000 |
0031 0000 ;******************************************************************************* |
0032 0000 |
0033 0000 .org 0H |
0034 0000 C3 60 00 jmp start ; skip the rst address area |
0035 0003 |
0036 0003 ; used to test that RST works |
0037 0020 .org 20H |
0038 0020 C6 01 adi 1H |
0039 0022 FB ei |
0040 0023 C9 ret |
0041 0024 |
0042 0024 ; used to test the RST instruction as intr vector |
0043 0028 .org 28H |
0044 0028 3C inr a |
0045 0029 FB ei |
0046 002A C9 ret |
0047 002B |
0048 002B ;***** simulated interrupt vectors in area 0040h-005fh ***************** |
0049 002B |
0050 0040 .org 40h+(0*4) ; simulated interrupt vector 0 |
0051 0040 3C inr a |
0052 0044 .org 40h+(1*4) ; simulated interrupt vector 1 |
0053 0044 EF rst 5 |
0054 0048 .org 40h+(2*4) ; simulated interrupt vector 2 |
0055 0048 23 inx h |
0056 004C .org 40h+(3*4) ; simulated interrupt vector 3 |
0057 004C 3E 42 mvi a,42h |
0058 0050 .org 40h+(4*4) ; simulated interrupt vector 4 |
0059 0050 21 34 12 lxi h,1234h |
0060 0054 .org 40h+(5*4) ; simulated interrupt vector 5 |
0061 0054 C3 2F 01 jmp test_jump |
0062 0058 .org 40h+(6*4) ; simulated interrupt vector 6 |
0063 0058 CD 34 01 call test_call |
0064 005C .org 40h+(7*4) ; simulated interrupt vector 7 |
0065 005C CD 37 01 call shouldnt_trigger |
0066 005F |
0067 005F |
0068 005F ;***** program entry point ********************************************* |
0069 005F |
0070 0060 start: .org 60H |
0071 0060 31 7A 01 lxi sp,stack |
0072 0063 |
0073 0063 ; first of all, make sure the RST instruction works, we have a valid |
0074 0063 ; simulated stack, etc. |
0075 0063 3E 13 mvi a,13h |
0076 0065 E7 rst 4 ; this should add 1 to ACC |
0077 0066 FE 14 cpi 14h |
0078 0068 C2 2A 01 jnz fail |
0079 006B |
0080 006B ; now we'll try a few different interrupt vectors (single byte and |
0081 006B ; multi-byte). Since interrupts are disabled upon acknowledge, we have |
0082 006B ; to reenable them after every test. |
0083 006B |
0084 006B ; try single-byte interrupt vector: INR A |
0085 006B 3E 00 mvi a,0 |
0086 006D D3 10 out intr_source |
0087 006F FB ei |
0088 0070 3E 14 mvi a,014h |
0089 0072 D3 11 out intr_trigger |
0090 0074 3E 27 mvi a,027h |
0091 0076 00 nop ; the interrupt will hit in this nop area |
0092 0077 00 nop |
0093 0078 00 nop |
0094 0079 00 nop |
0095 007A FE 28 cpi 028h |
0096 007C C2 2A 01 jnz fail |
0097 007F |
0098 007F ; another single-byte vector: RST 5 |
0099 007F 3E 01 mvi a,1 |
0100 0081 D3 10 out intr_source |
0101 0083 FB ei |
0102 0084 3E 14 mvi a,014h |
0103 0086 D3 11 out intr_trigger ; the interrupt vector will do a rst 5, and |
0104 0088 3E 20 mvi a,020h ; the rst routine will add 1 to the ACC |
0105 008A 00 nop ; and reenable interrupts |
0106 008B 00 nop |
0107 008C 00 nop |
0108 008D 00 nop |
0109 008E FE 21 cpi 021h |
0110 0090 C2 2A 01 jnz fail |
0111 0093 |
0112 0093 ; another single-byte code: INX H |
0113 0093 21 FF 13 lxi h,13ffh |
0114 0096 3E 02 mvi a,2 |
0115 0098 D3 10 out intr_source |
0116 009A FB ei |
0117 009B 3E 04 mvi a,4 |
0118 009D D3 11 out intr_trigger |
0119 009F 00 nop |
0120 00A0 00 nop |
0121 00A1 7D mov a,l |
0122 00A2 FE 00 cpi 0H |
0123 00A4 C2 2A 01 jnz fail |
0124 00A7 7C mov a,h |
0125 00A8 FE 14 cpi 14h |
0126 00AA C2 2A 01 jnz fail |
0127 00AD |
0128 00AD ; a two-byte instruction: mvi a, 42h |
0129 00AD 3E 03 mvi a,3 |
0130 00AF D3 10 out intr_source |
0131 00B1 FB ei |
0132 00B2 3E 04 mvi a,4 |
0133 00B4 D3 11 out intr_trigger |
0134 00B6 00 nop |
0135 00B7 00 nop |
0136 00B8 FE 42 cpi 42h |
0137 00BA C2 2A 01 jnz fail |
0138 00BD |
0139 00BD ; a three-byte instruction: lxi h,1234h |
0140 00BD 3E 04 mvi a,4 |
0141 00BF D3 10 out intr_source |
0142 00C1 FB ei |
0143 00C2 3E 04 mvi a,4 |
0144 00C4 D3 11 out intr_trigger |
0145 00C6 00 nop |
0146 00C7 00 nop |
0147 00C8 7C mov a,h |
0148 00C9 FE 12 cpi 12h |
0149 00CB C2 2A 01 jnz fail |
0150 00CE 7D mov a,l |
0151 00CF FE 34 cpi 34h |
0152 00D1 C2 2A 01 jnz fail |
0153 00D4 |
0154 00D4 ; a 3-byte jump: jmp test_jump |
0155 00D4 ; if this fails, the test will probably derail |
0156 00D4 3E 05 mvi a,5 |
0157 00D6 D3 10 out intr_source |
0158 00D8 FB ei |
0159 00D9 3E 04 mvi a,4 |
0160 00DB D3 11 out intr_trigger |
0161 00DD 00 nop |
0162 00DE 00 nop |
0163 00DF comeback: |
0164 00DF FE 79 cpi 79h |
0165 00E1 C2 2A 01 jnz fail |
0166 00E4 |
0167 00E4 ; a 3-byte call: call test_call |
0168 00E4 ; if this fails, the test will probably derail |
0169 00E4 3E 06 mvi a,6 |
0170 00E6 D3 10 out intr_source |
0171 00E8 FB ei |
0172 00E9 3E 04 mvi a,4 |
0173 00EB D3 11 out intr_trigger |
0174 00ED 3C inr a |
0175 00EE ; the interrupt will come back here, hopefully |
0176 00EE 00 nop |
0177 00EF FE 05 cpi 05h |
0178 00F1 C2 2A 01 jnz fail |
0179 00F4 78 mov a,b |
0180 00F5 FE 19 cpi 19h |
0181 00F7 C2 2A 01 jnz fail |
0182 00FA |
0183 00FA ; now, with interrupts disabled, make sure interrupts are ignored |
0184 00FA F3 di |
0185 00FB 3E 07 mvi a,07h ; source 7 catches any unwanted interrupts |
0186 00FD D3 10 out intr_source |
0187 00FF 3E 04 mvi a,04h |
0188 0101 D3 11 out intr_trigger |
0189 0103 00 nop |
0190 0104 00 nop |
0191 0105 00 nop |
0192 0106 |
0193 0106 ; Ok. So far we have tested only 1-cycle intr assertions. Now we'll |
0194 0106 ; see what happens when we leave intr asserted for a long time (as would |
0195 0106 ; happen intr was used for single-step debugging, for instance) |
0196 0106 |
0197 0106 ; try single-byte interrupt vector (INR A) |
0198 0106 3E 50 mvi a, 80 |
0199 0108 D3 12 out intr_width |
0200 010A 3E 01 mvi a,1 |
0201 010C D3 10 out intr_source |
0202 010E FB ei |
0203 010F 3E 14 mvi a,014h |
0204 0111 D3 11 out intr_trigger |
0205 0113 3E 27 mvi a,027h |
0206 0115 00 nop ; the interrupts will hit in this nop area |
0207 0116 00 nop |
0208 0117 3C inr a |
0209 0118 00 nop |
0210 0119 00 nop |
0211 011A 3C inr a |
0212 011B 00 nop |
0213 011C 00 nop |
0214 011D 00 nop |
0215 011E 00 nop |
0216 011F 00 nop |
0217 0120 FE 2B cpi 02bh |
0218 0122 C2 2A 01 jnz fail |
0219 0125 |
0220 0125 |
0221 0125 ; finished, run into the success outcome code |
0222 0125 |
0223 0125 success: |
0224 0125 3E 55 mvi a,55h |
0225 0127 D3 20 out test_outcome |
0226 0129 76 hlt |
0227 012A 3E AA fail: mvi a,0aah |
0228 012C D3 20 out test_outcome |
0229 012E 76 hlt |
0230 012F |
0231 012F test_jump: |
0232 012F 3E 79 mvi a,79h |
0233 0131 C3 DF 00 jmp comeback |
0234 0134 |
0235 0134 test_call: |
0236 0134 06 19 mvi b,19h |
0237 0136 C9 ret |
0238 0137 |
0239 0137 ; called when an interrupt has been acknowledged that shouldn't have |
0240 0137 shouldnt_trigger: |
0241 0137 C3 2A 01 jmp fail |
0242 013A |
0243 013A ; data space |
0244 013A ds(64) |
0244 017A |
0245 017A stack: ds(2) |
0245 017C |
0246 017C .end |
0247 017C tasm: Number of errors = 0 |
/trunk/sw/tb/tb1/tb1.hex
0,0 → 1,22
:03000000C36000DA |
:04002000C601FBC951 |
:030028003CFBC9D5 |
:010040003C83 |
:01004400EFCC |
:010048002394 |
:02004C003E4232 |
:0300500021341246 |
:03005400C32F01B6 |
:03005800CD3401A3 |
:03005C00CD37019C |
:18006000317A013E13E7FE14C22A013E00D310FB3E14D3113E270000EE |
:180078000000FE28C22A013E01D310FB3E14D3113E2000000000FE218D |
:18009000C22A0121FF133E02D310FB3E04D31100007DFE00C22A017C10 |
:1800A800FE14C22A013E03D310FB3E04D3110000FE42C22A013E04D3BA |
:1800C00010FB3E04D31100007CFE12C22A017DFE34C22A013E05D310BC |
:1800D800FB3E04D3110000FE79C22A013E06D310FB3E04D3113C00FE09 |
:1800F00005C22A0178FE19C22A01F33E07D3103E04D3110000003E50BB |
:18010800D3123E01D310FB3E14D3113E2700003C00003C0000000000CA |
:18012000FE2BC22A013E55D320763EAAD320763E79C3DF000619C9C360 |
:020138002A019A |
:00000001FF |
/trunk/sw/tb/soc_tb/obj_code_pkg.vhdl
0,0 → 1,61
-- obj_code_pkg -- Object code in VHDL constant table for BRAM initialization. |
-- Generated automatically with script 'build_rom.py'. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.l80pkg.all; |
|
package obj_code_pkg is |
|
constant obj_code : obj_code_t(0 to 372) := ( |
X"c3", X"60", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c3", X"12", X"01", X"00", X"00", X"00", X"00", X"00", |
X"fb", X"c9", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c3", X"1e", X"01", X"00", X"00", X"00", X"00", X"00", |
X"fb", X"c9", X"00", X"00", X"00", X"00", X"00", X"00", |
X"fb", X"c9", X"00", X"00", X"00", X"00", X"00", X"00", |
X"fb", X"c9", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c3", X"2a", X"01", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"31", X"da", X"01", X"21", X"74", X"01", X"22", X"75", |
X"01", X"21", X"7a", X"01", X"22", X"77", X"01", X"3e", |
X"00", X"32", X"79", X"01", X"3e", X"00", X"d3", X"86", |
X"3e", X"0b", X"d3", X"88", X"fb", X"21", X"02", X"01", |
X"cd", X"66", X"01", X"3e", X"01", X"32", X"73", X"01", |
X"3e", X"01", X"d3", X"86", X"3a", X"73", X"01", X"fe", |
X"04", X"ca", X"9c", X"00", X"fe", X"01", X"c2", X"fb", |
X"00", X"c3", X"8c", X"00", X"3e", X"00", X"d3", X"86", |
X"3e", X"01", X"32", X"73", X"01", X"3e", X"02", X"d3", |
X"86", X"3a", X"73", X"01", X"fe", X"02", X"ca", X"b9", |
X"00", X"fe", X"01", X"c2", X"fb", X"00", X"c3", X"a9", |
X"00", X"af", X"d3", X"86", X"3e", X"01", X"32", X"73", |
X"01", X"3e", X"03", X"d3", X"86", X"3a", X"73", X"01", |
X"fe", X"05", X"ca", X"d5", X"00", X"fe", X"01", X"c2", |
X"fb", X"00", X"c3", X"c5", X"00", X"af", X"d3", X"86", |
X"3a", X"79", X"01", X"fe", X"0f", X"c2", X"d8", X"00", |
X"21", X"7a", X"01", X"11", X"02", X"01", X"1a", X"fe", |
X"24", X"ca", X"f5", X"00", X"be", X"c2", X"fb", X"00", |
X"23", X"13", X"c3", X"e6", X"00", X"3e", X"80", X"d3", |
X"86", X"f3", X"76", X"3e", X"40", X"d3", X"86", X"c3", |
X"f9", X"00", X"0a", X"0d", X"0a", X"48", X"65", X"6c", |
X"6c", X"6f", X"20", X"57", X"6f", X"72", X"6c", X"64", |
X"21", X"24", X"f5", X"3a", X"73", X"01", X"07", X"07", |
X"32", X"73", X"01", X"f1", X"fb", X"c9", X"f5", X"3a", |
X"73", X"01", X"c6", X"01", X"32", X"73", X"01", X"f1", |
X"fb", X"c9", X"e5", X"f5", X"db", X"81", X"e6", X"20", |
X"ca", X"48", X"01", X"3e", X"20", X"d3", X"81", X"db", |
X"80", X"2a", X"77", X"01", X"77", X"23", X"22", X"77", |
X"01", X"3a", X"79", X"01", X"3c", X"32", X"79", X"01", |
X"db", X"81", X"e6", X"10", X"ca", X"62", X"01", X"3e", |
X"10", X"d3", X"81", X"2a", X"75", X"01", X"7e", X"fe", |
X"24", X"ca", X"62", X"01", X"23", X"22", X"75", X"01", |
X"d3", X"80", X"f1", X"e1", X"fb", X"c9", X"7e", X"23", |
X"22", X"75", X"01", X"fe", X"24", X"ca", X"72", X"01", |
X"d3", X"80", X"c9", X"00", X"24" |
); |
|
end package obj_code_pkg; |
/trunk/sw/tb/soc_tb/build.bat
0,0 → 1,26
@rem Build script for the SoC basic test bench 'soc_tb'. |
@rem This script will assemble the program source and run the object code |
@rem conversion tool to build a vhdl package that can then be used to initalize |
@rem the SoC entity. |
@rem You need to edit this file with the path to your TASM installation. |
@rem Set the program name. |
@set PROG=soc_tb |
@rem Edit to point to the directory you installed TASM in. |
@set TASM_DIR=..\..\local\tasm |
@rem Remove output from previous assembly. |
@del %PROG%.hex |
@del %PROG%.lst |
@rem Make sure TASM is able to find its table files (see TASM documentation). |
@set TASMTABS=%TASM_DIR% |
@rem Run assembler |
%TASM_DIR%\tasm -85 -a %PROG%.asm %PROG%.hex %PROG%.lst |
@rem Check TASM return value |
@if errorlevel 1 goto done |
@rem Build vhdl test bench file with object code embedded into it. |
python ..\..\tools\obj2hdl\src\obj2hdl.py ^ |
-f %PROG%.hex ^ |
-c obj_code ^ |
--package obj_code_pkg ^ |
--output obj_code_pkg.vhdl |
:done |
|
/trunk/sw/tb/soc_tb/soc_tb.asm
0,0 → 1,288
;******************************************************************************* |
; soc_tb.asm -- light8080 SoC basic test bench. |
;******************************************************************************* |
; Should be used with SoC core test bench entity vhdl\test\l80soc_tb.vhdl. |
; Assembler format compatible with TASM for DOS and Linux. |
;******************************************************************************* |
; This program will send a few bytes over a looped-back UART, using the UART |
; interrupt capability and verifying that received and transmitted data match. |
; It will then try one of the external interrupts, connected to one of the |
; general purpose outputs. |
; This minimal test bench relies on an already tested CPU core to do a |
; This program does not deserve to even be called a 'test' but if if works it |
; will at least rule out many obvious bug in the SoC core. |
;******************************************************************************* |
|
; DS pseudo-directive; reserve space in bytes, without initializing it |
#define ds(n) \.org $+n |
|
MASK_RX_IRQ: .equ 20h |
MASK_TX_IRQ: .equ 10h |
MASK_RX_RDY: .equ 02h |
MASK_TX_RDY: .equ 01h |
|
UART_DATA: .equ 80h |
UART_STATUS: .equ 81h |
UART_BAUDL: .equ 82h |
UART_BAUDH: .equ 83h |
IRQ_ENABLE: .equ 88h |
|
P1IN: .equ 84h |
P2OUT: .equ 86h |
|
|
;******************************************************************************* |
|
.org 0H ; Reset entry point |
jmp start ; Skip the rst address area |
|
;***** Interrupt vectors in area 0008h-0038h ***************** |
|
.org 0h+(1*8) ; interrupt vector 1 (IRQ0) |
jmp isr0 |
.org 0h+(2*8) ; interrupt vector 2 |
ei |
ret |
.org 0h+(3*8) ; interrupt vector 3 (IRQ1) |
jmp isr1 |
.org 0h+(4*8) ; interrupt vector 4 |
ei |
ret |
.org 0h+(5*8) ; interrupt vector 5 (IRQ2) |
ei |
ret |
.org 0h+(6*8) ; interrupt vector 6 |
ei |
ret |
|
.org 0h+(7*8) ; interrupt vector 7 (IRQ3, UART) |
int38h: jmp irq_uart ; UART interrupt |
|
;***** program entry point ******************************************* |
|
start: .org 60H |
lxi sp,stack |
|
; Initialize UART RX and TX buffers |
lxi h,void_buffer |
shld ptr_tx |
lxi h,rx_buffer |
shld ptr_rx |
mvi a,00h |
sta len_rx |
|
; Clear all P2 output lines (used to simulate external interrupts) |
mvi a,00h |
out P2OUT |
|
; Set up interrupts |
mvi a,0bh ; Enable UART irq plus IRQ0 and IRQ1... |
out IRQ_ENABLE |
ei ; ...and enable interrupts in the CPU |
|
; print hello message to console |
lxi h,msg_hello |
call print_string |
; Ok, now the message is being transferred through the looped back |
; UART, using the UART interrupts, which have the lowest priority. |
; We have plenty of time to make a few tests on the external interrupt |
; lines before the message transmission is finished. |
|
; The irq routines will leave some data at 'irq_data, each routine a |
; different value and all non-zero. This is how we know what irq |
; routines have executed and in which order. |
|
; Test IRQ0 alone |
mvi a,01h ; Initialize irq data |
sta irq_data |
mvi a,01h ; Trigger IRQ0 |
out P2OUT |
test_irq0: |
lda irq_data |
cpi 004h ; Do we see the IRQ test data? |
jz done_irq0 ; If we do, proceed to next test |
cpi 001h ; Do we see some other IRQ test data instead? |
jnz test_fail ; If we do, there's trouble with the irqs |
jmp test_irq0 ; Keep waiting for some IRQ test data |
done_irq0: |
mvi a,00h ; Deassert all interrupt lines |
out P2OUT |
|
; Test IRQ1 alone |
mvi a,01h ; Initialize irq data |
sta irq_data |
mvi a,02h ; Trigger IRQ1 |
out P2OUT |
test_irq1: |
lda irq_data |
cpi 002h ; Do we see the IRQ test data? |
jz done_irq1 ; If we do, proceed to next test |
cpi 001h ; Do we see some other IRQ test data instead? |
jnz test_fail ; If we do, there's trouble with the irqs |
jmp test_irq1 ; Keep waiting for some IRQ test data |
done_irq1: |
xra a ; Deassert all interrupt lines |
out P2OUT |
|
; Test IRQ0 and IRQ1 simultaneously |
mvi a,01h ; Initialize irq data |
sta irq_data |
mvi a,03h ; Trigger IRQ0 and IRQ1 |
out P2OUT |
|
; Sequence IRQ0->IRQ1 will result in (1 << 2) + 1 = 5 |
; Sequence IRQ1->IRQ0 would result in (1 + 1) << 2 = 6 |
; We expect IRQ0->IRQ1, since IRQ0 has higher priority |
test_irq01: |
lda irq_data |
cpi 005h ; Do we see the IRQ0->IRQ1 test data? |
jz done_irq01 ; If we do, proceed to next test |
cpi 001h ; Do we see some other IRQ test data instead? |
jnz test_fail ; If we do, there's trouble with the irqs |
jmp test_irq01 ; Keep waiting for some IRQ test data |
done_irq01: |
xra a ; Deassert all interrupt lines |
out P2OUT |
|
; Ok, the external interrupts have been tested (well, 'tested'). Now |
; wait for the UART looped-back transmission to end and compare |
; the data. |
|
; Wait until the number of UART received characters equals the length |
; of the test message. |
wait_for_message: |
lda len_rx |
cpi msg_len |
jnz wait_for_message |
|
; Compare the TX and RX strings |
lxi h,rx_buffer |
lxi d,msg_hello |
compare_loop: |
ldax d |
cpi '$' |
jz test_ok |
cmp m |
jnz test_fail |
inx h |
inx d |
jmp compare_loop |
|
|
|
|
|
test_ok: |
mvi a,80h ; Raise 'success' output flag... |
out P2OUT |
done: di ; ...and block here. |
hlt |
|
test_fail: |
mvi a,40h ; Raise 'failure' flag... |
out P2OUT |
jmp done ; ...and block. |
|
|
|
msg_hello: .text "\n\r\nHello World!$" |
msg_end: .equ $ |
; compute message length (-1 for the '$' that does not get TX'd) |
msg_len: .equ msg_end - msg_hello - 1 |
|
; IRQ0 routine will shift irq_data left twice |
isr0: push psw |
lda irq_data |
rlc |
rlc |
sta irq_data |
pop psw |
ei |
ret |
|
; IRQ1 routine will increment irq_data |
isr1: push psw |
lda irq_data |
adi 1 |
sta irq_data |
pop psw |
ei |
ret |
|
;irq_uart: UART interrupt processing |
irq_uart: |
push h |
push psw |
|
; Deal with RX interrupt (if any) first and then the TX interrupt. |
in UART_STATUS ; Is there new data in the RX register? |
ani MASK_RX_IRQ |
jz irq_uart_rx_done ; If there isn't, process TX interrupt. |
|
; Process UART RX interrupt |
irq_uart_rx: |
mvi a,MASK_RX_IRQ ; Clear IRQ flag. |
out UART_STATUS |
in UART_DATA ; Get RX byte... |
lhld ptr_rx ; ...and store it in the rx buffer. |
mov m,a |
inx h |
shld ptr_rx ; Update the rx buffer pointer. |
lda len_rx ; Update RX buffer length |
inr a |
sta len_rx |
|
; Note there's no check for RX buffer overrun! we shouldn't need it |
; here, a runaway condition would be readily apparent in the |
; simulation, anyway. |
|
irq_uart_rx_done: |
; Ok, RX is done. Now deal with TX irq, if any |
in UART_STATUS ; Is the TX buffer re new data in the RX register? |
ani MASK_TX_IRQ |
jz irq_uart_end ; If there isn't, we're done. |
|
; process UART TX interrupt |
irq_uart_tx: |
mvi a,MASK_TX_IRQ ; Clear IRQ flag. |
out UART_STATUS |
lhld ptr_tx ; Get next byte from the TX buffer |
mov a,m |
cpi '$' ; Did we reach the end of the buffer? |
jz irq_uart_tx_done ; If we did, we're done here... |
inx h ; ...otherwise increment the TX pointer... |
shld ptr_tx |
out UART_DATA ; ...and transmit the data byte. |
|
irq_uart_tx_done: |
|
irq_uart_end: |
pop psw ; Done, quit. |
pop h |
ei |
ret |
|
;print_string: print $-terminated string at HL |
print_string: |
; We don't check if there's a transmission going on |
mov a,m ; Get first character from string... |
inx h ; ...and move updated string pointer to TX |
shld ptr_tx ; buffer pointer. |
cpi '$' ; Kickstart transmission by sending 1st byte... |
jz print_string_end; ...unless its the end of string marker. |
out UART_DATA ; |
print_string_end: |
ret |
|
|
; data space, placed immediately after object code in memory |
irq_data: ds(1) |
void_buffer: .text "$" |
ptr_tx: ds(2) |
ptr_rx: ds(2) |
len_rx: ds(1) |
rx_buffer: ds(32) |
ds(64) |
stack: ds(2) |
.end |
|
/trunk/sw/tb/soc_tb/soc_tb.lst
0,0 → 1,295
0001 0000 ;******************************************************************************* |
0002 0000 ; soc_tb.asm -- light8080 SoC basic test bench. |
0003 0000 ;******************************************************************************* |
0004 0000 ; Should be used with SoC core test bench entity vhdl\test\l80soc_tb.vhdl. |
0005 0000 ; Assembler format compatible with TASM for DOS and Linux. |
0006 0000 ;******************************************************************************* |
0007 0000 ; This program will send a few bytes over a looped-back UART, using the UART |
0008 0000 ; interrupt capability and verifying that received and transmitted data match. |
0009 0000 ; It will then try one of the external interrupts, connected to one of the |
0010 0000 ; general purpose outputs. |
0011 0000 ; This minimal test bench relies on an already tested CPU core to do a |
0012 0000 ; This program does not deserve to even be called a 'test' but if if works it |
0013 0000 ; will at least rule out many obvious bug in the SoC core. |
0014 0000 ;******************************************************************************* |
0015 0000 |
0016 0000 ; DS pseudo-directive; reserve space in bytes, without initializing it |
0017 0000 #define ds(n) \.org $+n |
0018 0000 |
0019 0000 MASK_RX_IRQ: .equ 20h |
0020 0000 MASK_TX_IRQ: .equ 10h |
0021 0000 MASK_RX_RDY: .equ 02h |
0022 0000 MASK_TX_RDY: .equ 01h |
0023 0000 |
0024 0000 UART_DATA: .equ 80h |
0025 0000 UART_STATUS: .equ 81h |
0026 0000 UART_BAUDL: .equ 82h |
0027 0000 UART_BAUDH: .equ 83h |
0028 0000 IRQ_ENABLE: .equ 88h |
0029 0000 |
0030 0000 P1IN: .equ 84h |
0031 0000 P2OUT: .equ 86h |
0032 0000 |
0033 0000 |
0034 0000 ;******************************************************************************* |
0035 0000 |
0036 0000 .org 0H ; Reset entry point |
0037 0000 C3 60 00 jmp start ; Skip the rst address area |
0038 0003 |
0039 0003 ;***** Interrupt vectors in area 0008h-0038h ***************** |
0040 0003 |
0041 0008 .org 0h+(1*8) ; interrupt vector 1 (IRQ0) |
0042 0008 C3 12 01 jmp isr0 |
0043 0010 .org 0h+(2*8) ; interrupt vector 2 |
0044 0010 FB ei |
0045 0011 C9 ret |
0046 0018 .org 0h+(3*8) ; interrupt vector 3 (IRQ1) |
0047 0018 C3 1E 01 jmp isr1 |
0048 0020 .org 0h+(4*8) ; interrupt vector 4 |
0049 0020 FB ei |
0050 0021 C9 ret |
0051 0028 .org 0h+(5*8) ; interrupt vector 5 (IRQ2) |
0052 0028 FB ei |
0053 0029 C9 ret |
0054 0030 .org 0h+(6*8) ; interrupt vector 6 |
0055 0030 FB ei |
0056 0031 C9 ret |
0057 0032 |
0058 0038 .org 0h+(7*8) ; interrupt vector 7 (IRQ3, UART) |
0059 0038 C3 2A 01 int38h: jmp irq_uart ; UART interrupt |
0060 003B |
0061 003B ;***** program entry point ******************************************* |
0062 003B |
0063 0060 start: .org 60H |
0064 0060 31 DA 01 lxi sp,stack |
0065 0063 |
0066 0063 ; Initialize UART RX and TX buffers |
0067 0063 21 74 01 lxi h,void_buffer |
0068 0066 22 75 01 shld ptr_tx |
0069 0069 21 7A 01 lxi h,rx_buffer |
0070 006C 22 77 01 shld ptr_rx |
0071 006F 3E 00 mvi a,00h |
0072 0071 32 79 01 sta len_rx |
0073 0074 |
0074 0074 ; Clear all P2 output lines (used to simulate external interrupts) |
0075 0074 3E 00 mvi a,00h |
0076 0076 D3 86 out P2OUT |
0077 0078 |
0078 0078 ; Set up interrupts |
0079 0078 3E 0B mvi a,0bh ; Enable UART irq plus IRQ0 and IRQ1... |
0080 007A D3 88 out IRQ_ENABLE |
0081 007C FB ei ; ...and enable interrupts in the CPU |
0082 007D |
0083 007D ; print hello message to console |
0084 007D 21 02 01 lxi h,msg_hello |
0085 0080 CD 66 01 call print_string |
0086 0083 ; Ok, now the message is being transferred through the looped back |
0087 0083 ; UART, using the UART interrupts, which have the lowest priority. |
0088 0083 ; We have plenty of time to make a few tests on the external interrupt |
0089 0083 ; lines before the message transmission is finished. |
0090 0083 |
0091 0083 ; The irq routines will leave some data at 'irq_data, each routine a |
0092 0083 ; different value and all non-zero. This is how we know what irq |
0093 0083 ; routines have executed and in which order. |
0094 0083 |
0095 0083 ; Test IRQ0 alone |
0096 0083 3E 01 mvi a,01h ; Initialize irq data |
0097 0085 32 73 01 sta irq_data |
0098 0088 3E 01 mvi a,01h ; Trigger IRQ0 |
0099 008A D3 86 out P2OUT |
0100 008C test_irq0: |
0101 008C 3A 73 01 lda irq_data |
0102 008F FE 04 cpi 004h ; Do we see the IRQ test data? |
0103 0091 CA 9C 00 jz done_irq0 ; If we do, proceed to next test |
0104 0094 FE 01 cpi 001h ; Do we see some other IRQ test data instead? |
0105 0096 C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs |
0106 0099 C3 8C 00 jmp test_irq0 ; Keep waiting for some IRQ test data |
0107 009C done_irq0: |
0108 009C 3E 00 mvi a,00h ; Deassert all interrupt lines |
0109 009E D3 86 out P2OUT |
0110 00A0 |
0111 00A0 ; Test IRQ1 alone |
0112 00A0 3E 01 mvi a,01h ; Initialize irq data |
0113 00A2 32 73 01 sta irq_data |
0114 00A5 3E 02 mvi a,02h ; Trigger IRQ1 |
0115 00A7 D3 86 out P2OUT |
0116 00A9 test_irq1: |
0117 00A9 3A 73 01 lda irq_data |
0118 00AC FE 02 cpi 002h ; Do we see the IRQ test data? |
0119 00AE CA B9 00 jz done_irq1 ; If we do, proceed to next test |
0120 00B1 FE 01 cpi 001h ; Do we see some other IRQ test data instead? |
0121 00B3 C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs |
0122 00B6 C3 A9 00 jmp test_irq1 ; Keep waiting for some IRQ test data |
0123 00B9 done_irq1: |
0124 00B9 AF xra a ; Deassert all interrupt lines |
0125 00BA D3 86 out P2OUT |
0126 00BC |
0127 00BC ; Test IRQ0 and IRQ1 simultaneously |
0128 00BC 3E 01 mvi a,01h ; Initialize irq data |
0129 00BE 32 73 01 sta irq_data |
0130 00C1 3E 03 mvi a,03h ; Trigger IRQ0 and IRQ1 |
0131 00C3 D3 86 out P2OUT |
0132 00C5 |
0133 00C5 ; Sequence IRQ0->IRQ1 will result in (1 << 2) + 1 = 5 |
0134 00C5 ; Sequence IRQ1->IRQ0 would result in (1 + 1) << 2 = 6 |
0135 00C5 ; We expect IRQ0->IRQ1, since IRQ0 has higher priority |
0136 00C5 test_irq01: |
0137 00C5 3A 73 01 lda irq_data |
0138 00C8 FE 05 cpi 005h ; Do we see the IRQ0->IRQ1 test data? |
0139 00CA CA D5 00 jz done_irq01 ; If we do, proceed to next test |
0140 00CD FE 01 cpi 001h ; Do we see some other IRQ test data instead? |
0141 00CF C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs |
0142 00D2 C3 C5 00 jmp test_irq01 ; Keep waiting for some IRQ test data |
0143 00D5 done_irq01: |
0144 00D5 AF xra a ; Deassert all interrupt lines |
0145 00D6 D3 86 out P2OUT |
0146 00D8 |
0147 00D8 ; Ok, the external interrupts have been tested (well, 'tested'). Now |
0148 00D8 ; wait for the UART looped-back transmission to end and compare |
0149 00D8 ; the data. |
0150 00D8 |
0151 00D8 ; Wait until the number of UART received characters equals the length |
0152 00D8 ; of the test message. |
0153 00D8 wait_for_message: |
0154 00D8 3A 79 01 lda len_rx |
0155 00DB FE 0F cpi msg_len |
0156 00DD C2 D8 00 jnz wait_for_message |
0157 00E0 |
0158 00E0 ; Compare the TX and RX strings |
0159 00E0 21 7A 01 lxi h,rx_buffer |
0160 00E3 11 02 01 lxi d,msg_hello |
0161 00E6 compare_loop: |
0162 00E6 1A ldax d |
0163 00E7 FE 24 cpi '$' |
0164 00E9 CA F5 00 jz test_ok |
0165 00EC BE cmp m |
0166 00ED C2 FB 00 jnz test_fail |
0167 00F0 23 inx h |
0168 00F1 13 inx d |
0169 00F2 C3 E6 00 jmp compare_loop |
0170 00F5 |
0171 00F5 |
0172 00F5 |
0173 00F5 |
0174 00F5 |
0175 00F5 test_ok: |
0176 00F5 3E 80 mvi a,80h ; Raise 'success' output flag... |
0177 00F7 D3 86 out P2OUT |
0178 00F9 F3 done: di ; ...and block here. |
0179 00FA 76 hlt |
0180 00FB |
0181 00FB test_fail: |
0182 00FB 3E 40 mvi a,40h ; Raise 'failure' flag... |
0183 00FD D3 86 out P2OUT |
0184 00FF C3 F9 00 jmp done ; ...and block. |
0185 0102 |
0186 0102 |
0187 0102 |
0188 0102 0A 0D 0A 48 msg_hello: .text "\n\r\nHello World!$" |
0188 0106 65 6C 6C 6F |
0188 010A 20 57 6F 72 |
0188 010E 6C 64 21 24 |
0189 0112 msg_end: .equ $ |
0190 0112 msg_len: .equ msg_end - msg_hello - 1 |
0191 0112 |
0192 0112 F5 isr0: push psw |
0193 0113 3A 73 01 lda irq_data |
0194 0116 07 rlc |
0195 0117 07 rlc |
0196 0118 32 73 01 sta irq_data |
0197 011B F1 pop psw |
0198 011C FB ei |
0199 011D C9 ret |
0200 011E |
0201 011E F5 isr1: push psw |
0202 011F 3A 73 01 lda irq_data |
0203 0122 C6 01 adi 1 |
0204 0124 32 73 01 sta irq_data |
0205 0127 F1 pop psw |
0206 0128 FB ei |
0207 0129 C9 ret |
0208 012A |
0209 012A ;irq_uart: UART interrupt processing |
0210 012A irq_uart: |
0211 012A E5 push h |
0212 012B F5 push psw |
0213 012C |
0214 012C ; Deal with RX interrupt (if any) first and then the TX interrupt. |
0215 012C DB 81 in UART_STATUS ; Is there new data in the RX register? |
0216 012E E6 20 ani MASK_RX_IRQ |
0217 0130 CA 48 01 jz irq_uart_rx_done ; If there isn't, process TX interrupt. |
0218 0133 |
0219 0133 ; Process UART RX interrupt |
0220 0133 irq_uart_rx: |
0221 0133 3E 20 mvi a,MASK_RX_IRQ ; Clear IRQ flag. |
0222 0135 D3 81 out UART_STATUS |
0223 0137 DB 80 in UART_DATA ; Get RX byte... |
0224 0139 2A 77 01 lhld ptr_rx ; ...and store it in the rx buffer. |
0225 013C 77 mov m,a |
0226 013D 23 inx h |
0227 013E 22 77 01 shld ptr_rx ; Update the rx buffer pointer. |
0228 0141 3A 79 01 lda len_rx ; Update RX buffer length |
0229 0144 3C inr a |
0230 0145 32 79 01 sta len_rx |
0231 0148 |
0232 0148 ; Note there's no check for RX buffer overrun! we shouldn't need it |
0233 0148 ; here, a runaway condition would be readily apparent in the |
0234 0148 ; simulation, anyway. |
0235 0148 |
0236 0148 irq_uart_rx_done: |
0237 0148 ; Ok, RX is done. Now deal with TX irq, if any |
0238 0148 DB 81 in UART_STATUS ; Is the TX buffer re new data in the RX register? |
0239 014A E6 10 ani MASK_TX_IRQ |
0240 014C CA 62 01 jz irq_uart_end ; If there isn't, we're done. |
0241 014F |
0242 014F ; process UART TX interrupt |
0243 014F irq_uart_tx: |
0244 014F 3E 10 mvi a,MASK_TX_IRQ ; Clear IRQ flag. |
0245 0151 D3 81 out UART_STATUS |
0246 0153 2A 75 01 lhld ptr_tx ; Get next byte from the TX buffer |
0247 0156 7E mov a,m |
0248 0157 FE 24 cpi '$' ; Did we reach the end of the buffer? |
0249 0159 CA 62 01 jz irq_uart_tx_done ; If we did, we're done here... |
0250 015C 23 inx h ; ...otherwise increment the TX pointer... |
0251 015D 22 75 01 shld ptr_tx |
0252 0160 D3 80 out UART_DATA ; ...and transmit the data byte. |
0253 0162 |
0254 0162 irq_uart_tx_done: |
0255 0162 |
0256 0162 irq_uart_end: |
0257 0162 F1 pop psw ; Done, quit. |
0258 0163 E1 pop h |
0259 0164 FB ei |
0260 0165 C9 ret |
0261 0166 |
0262 0166 ;print_string: print $-terminated string at HL |
0263 0166 print_string: |
0264 0166 ; We don't check if there's a transmission going on |
0265 0166 7E mov a,m ; Get first character from string... |
0266 0167 23 inx h ; ...and move updated string pointer to TX |
0267 0168 22 75 01 shld ptr_tx ; buffer pointer. |
0268 016B FE 24 cpi '$' ; Kickstart transmission by sending 1st byte... |
0269 016D CA 72 01 jz print_string_end; ...unless its the end of string marker. |
0270 0170 D3 80 out UART_DATA ; |
0271 0172 print_string_end: |
0272 0172 C9 ret |
0273 0173 |
0274 0173 |
0275 0173 ; data space, placed immediately after object code in memory |
0276 0173 irq_data: ds(1) |
0276 0174 |
0277 0174 24 void_buffer: .text "$" |
0278 0175 ptr_tx: ds(2) |
0278 0177 |
0279 0177 ptr_rx: ds(2) |
0279 0179 |
0280 0179 len_rx: ds(1) |
0280 017A |
0281 017A rx_buffer: ds(32) |
0281 019A |
0282 019A ds(64) |
0282 01DA |
0283 01DA stack: ds(2) |
0283 01DC |
0284 01DC .end |
0285 01DC tasm: Number of errors = 0 |
/trunk/sw/tb/soc_tb/soc_tb.hex
0,0 → 1,22
:03000000C36000DA |
:03000800C312011F |
:02001000FBC92A |
:03001800C31E0103 |
:02002000FBC91A |
:02002800FBC912 |
:02003000FBC90A |
:03003800C32A01D7 |
:1800600031DA01217401227501217A012277013E003279013E00D38697 |
:180078003E0BD388FB210201CD66013E013273013E01D3863A7301FE50 |
:1800900004CA9C00FE01C2FB00C38C003E00D3863E013273013E02D354 |
:1800A800863A7301FE02CAB900FE01C2FB00C3A900AFD3863E01327375 |
:1800C000013E03D3863A7301FE05CAD500FE01C2FB00C3C500AFD386F1 |
:1800D8003A7901FE0FC2D800217A011102011AFE24CAF500BEC2FB008F |
:1800F0002313C3E6003E80D386F3763E40D386C3F9000A0D0A48656CCC |
:180108006C6F20576F726C642124F53A73010707327301F1FBC9F53A5C |
:180120007301C601327301F1FBC9E5F5DB81E620CA48013E20D381DB55 |
:18013800802A770177232277013A79013C327901DB81E610CA62013E00 |
:1801500010D3812A75017EFE24CA620123227501D380F1E1FBC97E2381 |
:0B016800227501FE24CA7201D380C979 |
:010174002466 |
:00000001FF |
/trunk/sw/tb/readme.txt
0,0 → 1,23
The batch script tasmtb.bat will assemble the test bench source and then build a |
VHDL test bench from the template tb_template.vhdl, with the assembled program |
encoded in a simulated ROM. |
|
For example, to build the test bench 0 do: |
|
tasmtb tb0 |
|
The script assumes you have installed TASM in local/TASM. You may need to edit |
the path to TASM in the script. |
Besides, it uses the perl script hexconv.pl, so you need to have Perl installed |
too. You can find them here: |
|
Telemark cross assembler (TASM): |
http://home.comcast.net/~tasm/ |
|
Perl for windows (ActivePerl): |
http://www.activestate.com/activeperl/ |
|
There are other versions of Perl for windows, this is the one I worked with. |
|
See more details about these test benches in the design notes and in the |
sources. |
/trunk/sw/demos/hello/obj_code_pkg.vhdl
0,0 → 1,44
-- obj_code_pkg -- Object code in VHDL constant table for BRAM initialization. |
-- Generated automatically with script 'build_rom.py'. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.l80pkg.all; |
|
package obj_code_pkg is |
|
constant obj_code : obj_code_t(0 to 235) := ( |
X"c3", X"60", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"c3", X"a7", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", |
X"31", X"50", X"01", X"21", X"eb", X"00", X"22", X"ec", |
X"00", X"21", X"f0", X"00", X"22", X"ee", X"00", X"3e", |
X"14", X"d3", X"83", X"3e", X"58", X"d3", X"82", X"3e", |
X"00", X"d3", X"86", X"3e", X"08", X"d3", X"88", X"fb", |
X"21", X"96", X"00", X"cd", X"de", X"00", X"db", X"84", |
X"4f", X"07", X"07", X"81", X"d3", X"86", X"c3", X"86", |
X"00", X"f3", X"76", X"c3", X"93", X"00", X"0a", X"0d", |
X"0a", X"48", X"65", X"6c", X"6c", X"6f", X"20", X"57", |
X"6f", X"72", X"6c", X"64", X"21", X"24", X"00", X"e5", |
X"f5", X"db", X"81", X"e6", X"20", X"ca", X"c0", X"00", |
X"3e", X"20", X"d3", X"81", X"db", X"80", X"d3", X"86", |
X"2a", X"ee", X"00", X"77", X"23", X"22", X"ee", X"00", |
X"db", X"81", X"e6", X"10", X"ca", X"da", X"00", X"3e", |
X"10", X"d3", X"81", X"2a", X"ec", X"00", X"7e", X"fe", |
X"24", X"ca", X"da", X"00", X"23", X"22", X"ec", X"00", |
X"d3", X"80", X"f1", X"e1", X"fb", X"c9", X"7e", X"23", |
X"22", X"ec", X"00", X"fe", X"24", X"ca", X"ea", X"00", |
X"d3", X"80", X"c9", X"24" |
); |
|
end package obj_code_pkg; |
/trunk/sw/demos/hello/hello.asm
0,0 → 1,177
;******************************************************************************* |
; tb1.asm -- light8080 core basic demo: 'Hello World!" |
;******************************************************************************* |
; Should be used with SoC vhdl\soc\l80soc.vhdl |
; Assembler format compatible with TASM for DOS and Linux. |
;******************************************************************************* |
; This program will print a Hello message to a 9600/8/N/1 serial port, then |
; will loop forever copying the input port P1 to the output port P2. |
; This demo is meant to be used as a starting point for those wanting to play |
; with the l80soc core -- which in turn is little more than an usage example |
; for the light8080 cpu core. |
; See the readme file for instructions for setting up a project with this |
; program on Digilentic's DE-1 development board. |
;******************************************************************************* |
|
; DS pseudo-directive; reserve space in bytes, without initializing it |
#define ds(n) \.org $+n |
|
MASK_RX_IRQ: .equ 20h |
MASK_TX_IRQ: .equ 10h |
MASK_RX_RDY: .equ 02h |
MASK_TX_RDY: .equ 01h |
|
UART_DATA: .equ 80h |
UART_STATUS: .equ 81h |
UART_BAUDL: .equ 82h |
UART_BAUDH: .equ 83h |
IRQ_ENABLE: .equ 88h |
|
P1IN: .equ 84h |
P2OUT: .equ 86h |
|
|
;******************************************************************************* |
|
.org 0H ; Reset entry point |
jmp start ; Skip the rst address area |
|
;***** Interrupt vectors in area 0008h-0038h ***************** |
|
.org 0h+(1*8) ; interrupt vector 1 |
ret |
.org 0h+(2*8) ; interrupt vector 2 |
ret |
.org 0h+(3*8) ; interrupt vector 3 |
ret |
.org 0h+(4*8) ; interrupt vector 4 |
ret |
.org 0h+(5*8) ; interrupt vector 5 |
ret |
.org 0h+(6*8) ; interrupt vector 6 |
ret |
|
.org 0h+(7*8) ; interrupt vector 7 |
int38h: jmp irq_uart ; UART interrupt |
|
;***** program entry point ******************************************* |
|
start: .org 60H |
lxi sp,stack |
|
; Initialize UART RX and TX buffers |
lxi h,void_buffer |
shld ptr_tx |
lxi h,rx_buffer |
shld ptr_rx |
; Set up UART baud rate to 9600 bauds @ 50MHz: |
; (50E6 / 9600) = 5208d = 1458h |
mvi a,14h |
out UART_BAUDH |
mvi a,58h |
out UART_BAUDL |
|
; Clear P2 port |
mvi a,00h |
out P2OUT |
|
; Set up interrupts |
mvi a,08h ; Enable UART irq... |
out IRQ_ENABLE |
ei ; ...and enable interrupts in the CPU |
|
; print hello message to console |
lxi h,msg_hello |
call print_string |
|
forever: |
in P1IN |
mov c,a |
rlc |
rlc |
add c |
out P2OUT |
jmp forever |
|
di |
hlt |
done: jmp done |
|
msg_hello: .text "\n\r\nHello World!$\000" |
|
;irq_uart: UART interrupt processing |
irq_uart: |
push h |
push psw |
|
; Deal with RX interrupt (if any) first and then the TX interrupt. |
in UART_STATUS ; Is there new data in the RX register? |
ani MASK_RX_IRQ |
jz irq_uart_rx_done ; If there isn't, process TX interrupt. |
|
; Process UART RX interrupt |
irq_uart_rx: |
mvi a,MASK_RX_IRQ ; Clear IRQ flag. |
out UART_STATUS |
in UART_DATA ; Get RX byte... |
out P2OUT ; ...display it in the output port... |
lhld ptr_rx ; ...and store it in the rx buffer. |
mov m,a |
inx h |
shld ptr_rx ; Update the rx buffer pointer. |
; Note there's no check for RX buffer overrun! |
|
irq_uart_rx_done: |
; Ok, RX is done. Now deal with TX irq, if any |
in UART_STATUS ; Is the TX buffer re new data in the RX register? |
ani MASK_TX_IRQ |
jz irq_uart_end ; If there isn't, we're done. |
|
; process UART TX interrupt |
irq_uart_tx: |
mvi a,MASK_TX_IRQ ; Clear IRQ flag. |
out UART_STATUS |
lhld ptr_tx ; Get next byte from the TX buffer |
mov a,m |
cpi '$' ; Did we reach the end of the buffer? |
jz irq_uart_tx_done ; If we did, we're done here... |
inx h ; ...otherwise increment the TX pointer... |
shld ptr_tx |
out UART_DATA ; ...and transmit the data byte. |
|
irq_uart_tx_done: |
|
irq_uart_end: |
pop psw ; Done, quit. |
pop h |
ei |
ret |
; Note there's no check for RX buffer overrun! we shouldn't need it |
; in this program, anyway. |
|
|
;print_string: print $-terminated string at HL |
; Returns as soon as the transmission has started; transmission proceeds in |
; 'background' through the UART interrupt service routine. |
print_string: |
; We don't check if there's a transmission going on, we just start |
; transmitting. Not suitable for real use! |
mov a,m ; Get first character from string... |
inx h ; ...and move updated string pointer to TX |
shld ptr_tx ; buffer pointer. |
cpi '$' ; Kickstart transmission by sending 1st byte... |
jz print_string_end; ...unless its the end of string marker. |
out UART_DATA ; |
print_string_end: |
ret |
|
|
; data space, placed immediately after object code in memory |
void_buffer: .text "$" |
ptr_tx: ds(2) |
ptr_rx: ds(2) |
rx_buffer: ds(32) |
ds(64) |
stack: ds(2) |
.end |
|
/trunk/sw/demos/hello/hello.lst
0,0 → 1,186
0001 0000 ;******************************************************************************* |
0002 0000 ; tb1.asm -- light8080 core basic demo: 'Hello World!" |
0003 0000 ;******************************************************************************* |
0004 0000 ; Should be used with SoC vhdl\soc\l80soc.vhdl |
0005 0000 ; Assembler format compatible with TASM for DOS and Linux. |
0006 0000 ;******************************************************************************* |
0007 0000 ; This program will print a Hello message to a 19200/8/N/1 serial port, then |
0008 0000 ; will loop forever copying the input port P1 to the output port P2. |
0009 0000 ; This demo is meant to be used as a starting point for those wanting to play |
0010 0000 ; with the l80soc core -- which in turn is little more than an usage example |
0011 0000 ; for the light8080 cpu core. |
0012 0000 ; See the readme file for instructions for setting up a project with this |
0013 0000 ; program on Digilentic's DE-1 development board. |
0014 0000 ;******************************************************************************* |
0015 0000 |
0016 0000 ; DS pseudo-directive; reserve space in bytes, without initializing it |
0017 0000 #define ds(n) \.org $+n |
0018 0000 |
0019 0000 MASK_RX_IRQ: .equ 20h |
0020 0000 MASK_TX_IRQ: .equ 10h |
0021 0000 MASK_RX_RDY: .equ 02h |
0022 0000 MASK_TX_RDY: .equ 01h |
0023 0000 |
0024 0000 UART_DATA: .equ 80h |
0025 0000 UART_STATUS: .equ 81h |
0026 0000 UART_BAUDL: .equ 82h |
0027 0000 UART_BAUDH: .equ 83h |
0028 0000 IRQ_ENABLE: .equ 88h |
0029 0000 |
0030 0000 P1IN: .equ 84h |
0031 0000 P2OUT: .equ 86h |
0032 0000 |
0033 0000 |
0034 0000 ;******************************************************************************* |
0035 0000 |
0036 0000 .org 0H ; Reset entry point |
0037 0000 C3 60 00 jmp start ; Skip the rst address area |
0038 0003 |
0039 0003 ;***** Interrupt vectors in area 0008h-0038h ***************** |
0040 0003 |
0041 0008 .org 0h+(1*8) ; interrupt vector 1 |
0042 0008 C9 ret |
0043 0010 .org 0h+(2*8) ; interrupt vector 2 |
0044 0010 C9 ret |
0045 0018 .org 0h+(3*8) ; interrupt vector 3 |
0046 0018 C9 ret |
0047 0020 .org 0h+(4*8) ; interrupt vector 4 |
0048 0020 C9 ret |
0049 0028 .org 0h+(5*8) ; interrupt vector 5 |
0050 0028 C9 ret |
0051 0030 .org 0h+(6*8) ; interrupt vector 6 |
0052 0030 C9 ret |
0053 0031 |
0054 0038 .org 0h+(7*8) ; interrupt vector 7 |
0055 0038 C3 A7 00 int38h: jmp irq_uart ; UART interrupt |
0056 003B |
0057 003B ;***** program entry point ******************************************* |
0058 003B |
0059 0060 start: .org 60H |
0060 0060 31 50 01 lxi sp,stack |
0061 0063 |
0062 0063 ; Initialize UART RX and TX buffers |
0063 0063 21 EB 00 lxi h,void_buffer |
0064 0066 22 EC 00 shld ptr_tx |
0065 0069 21 F0 00 lxi h,rx_buffer |
0066 006C 22 EE 00 shld ptr_rx |
0067 006F ; Set up UART baud rate to 9600 bauds @ 50MHz: |
0068 006F ; (50E6 / 16) / 9600 = 325d = 145h |
0069 006F 3E 14 mvi a,14h ; |
0070 0071 D3 83 out UART_BAUDH |
0071 0073 3E 58 mvi a,58h |
0072 0075 D3 82 out UART_BAUDL |
0073 0077 |
0074 0077 ; Clear P2 port |
0075 0077 3E 00 mvi a,00h |
0076 0079 D3 86 out P2OUT |
0077 007B |
0078 007B ; Set up interrupts |
0079 007B 3E 08 mvi a,08h ; Enable UART irq... |
0080 007D D3 88 out IRQ_ENABLE |
0081 007F FB ei ; ...and enable interrupts in the CPU |
0082 0080 |
0083 0080 ; print hello message to console |
0084 0080 21 96 00 lxi h,msg_hello |
0085 0083 CD DE 00 call print_string |
0086 0086 |
0087 0086 forever: |
0088 0086 DB 84 in P1IN |
0089 0088 4F mov c,a |
0090 0089 07 rlc |
0091 008A 07 rlc |
0092 008B 81 add c |
0093 008C D3 86 out P2OUT |
0094 008E C3 86 00 jmp forever |
0095 0091 |
0096 0091 F3 di |
0097 0092 76 hlt |
0098 0093 C3 93 00 done: jmp done |
0099 0096 |
0100 0096 0A 0D 0A 48 msg_hello: .text "\n\r\nHello World!$\000" |
0100 009A 65 6C 6C 6F |
0100 009E 20 57 6F 72 |
0100 00A2 6C 64 21 24 |
0100 00A6 00 |
0101 00A7 |
0102 00A7 ;irq_uart: UART interrupt processing |
0103 00A7 irq_uart: |
0104 00A7 E5 push h |
0105 00A8 F5 push psw |
0106 00A9 |
0107 00A9 ; Deal with RX interrupt (if any) first and then the TX interrupt. |
0108 00A9 DB 81 in UART_STATUS ; Is there new data in the RX register? |
0109 00AB E6 20 ani MASK_RX_IRQ |
0110 00AD CA C0 00 jz irq_uart_rx_done ; If there isn't, process TX interrupt. |
0111 00B0 |
0112 00B0 ; Process UART RX interrupt |
0113 00B0 irq_uart_rx: |
0114 00B0 3E 20 mvi a,MASK_RX_IRQ ; Clear IRQ flag. |
0115 00B2 D3 81 out UART_STATUS |
0116 00B4 DB 80 in UART_DATA ; Get RX byte... |
0117 00B6 D3 86 out P2OUT ; ...display it in the output port... |
0118 00B8 2A EE 00 lhld ptr_rx ; ...and store it in the rx buffer. |
0119 00BB 77 mov m,a |
0120 00BC 23 inx h |
0121 00BD 22 EE 00 shld ptr_rx ; Update the rx buffer pointer. |
0122 00C0 ; Note there's no check for RX buffer overrun! |
0123 00C0 |
0124 00C0 irq_uart_rx_done: |
0125 00C0 ; Ok, RX is done. Now deal with TX irq, if any |
0126 00C0 DB 81 in UART_STATUS ; Is the TX buffer re new data in the RX register? |
0127 00C2 E6 10 ani MASK_TX_IRQ |
0128 00C4 CA DA 00 jz irq_uart_end ; If there isn't, we're done. |
0129 00C7 |
0130 00C7 ; process UART TX interrupt |
0131 00C7 irq_uart_tx: |
0132 00C7 3E 10 mvi a,MASK_TX_IRQ ; Clear IRQ flag. |
0133 00C9 D3 81 out UART_STATUS |
0134 00CB 2A EC 00 lhld ptr_tx ; Get next byte from the TX buffer |
0135 00CE 7E mov a,m |
0136 00CF FE 24 cpi '$' ; Did we reach the end of the buffer? |
0137 00D1 CA DA 00 jz irq_uart_tx_done ; If we did, we're done here... |
0138 00D4 23 inx h ; ...otherwise increment the TX pointer... |
0139 00D5 22 EC 00 shld ptr_tx |
0140 00D8 D3 80 out UART_DATA ; ...and transmit the data byte. |
0141 00DA |
0142 00DA irq_uart_tx_done: |
0143 00DA |
0144 00DA irq_uart_end: |
0145 00DA F1 pop psw ; Done, quit. |
0146 00DB E1 pop h |
0147 00DC FB ei |
0148 00DD C9 ret |
0149 00DE ; Note there's no check for RX buffer overrun! we shouldn't need it |
0150 00DE ; in this program, anyway. |
0151 00DE |
0152 00DE |
0153 00DE ;print_string: print $-terminated string at HL |
0154 00DE ; Returns as soon as the transmission has started; transmission proceeds in |
0155 00DE ; 'background' through the UART interrupt service routine. |
0156 00DE print_string: |
0157 00DE ; We don't check if there's a transmission going on, we just start |
0158 00DE ; transmitting. Not suitable for real use! |
0159 00DE 7E mov a,m ; Get first character from string... |
0160 00DF 23 inx h ; ...and move updated string pointer to TX |
0161 00E0 22 EC 00 shld ptr_tx ; buffer pointer. |
0162 00E3 FE 24 cpi '$' ; Kickstart transmission by sending 1st byte... |
0163 00E5 CA EA 00 jz print_string_end; ...unless its the end of string marker. |
0164 00E8 D3 80 out UART_DATA ; |
0165 00EA print_string_end: |
0166 00EA C9 ret |
0167 00EB |
0168 00EB |
0169 00EB ; data space, placed immediately after object code in memory |
0170 00EB 24 void_buffer: .text "$" |
0171 00EC ptr_tx: ds(2) |
0171 00EE |
0172 00EE ptr_rx: ds(2) |
0172 00F0 |
0173 00F0 rx_buffer: ds(32) |
0173 0110 |
0174 0110 ds(64) |
0174 0150 |
0175 0150 stack: ds(2) |
0175 0152 |
0176 0152 .end |
0177 0152 tasm: Number of errors = 0 |
/trunk/sw/demos/hello/build.bat
0,0 → 1,26
@rem Build script for the SoC basic demo 'hello'. |
@rem This script will assemble the program source and run the object code |
@rem conversion tool to build a vhdl package that can then be used to initalize |
@rem the SoC entity. |
@rem You need to edit this file with the path to your TASM installation. |
@rem Set the program name. |
@set PROG=hello |
@rem Edit to point to the directory you installed TASM in. |
@set TASM_DIR=..\..\local\tasm |
@rem Remove output from previous assembly. |
@del %PROG%.hex |
@del %PROG%.lst |
@rem Make sure TASM is able to find its table files (see TASM documentation). |
@set TASMTABS=%TASM_DIR% |
@rem Run assembler |
%TASM_DIR%\tasm -85 -a %PROG%.asm %PROG%.hex %PROG%.lst |
@rem Check TASM return value |
@if errorlevel 1 goto done |
@rem Build vhdl test bench file with object code embedded into it. |
python ..\..\tools\obj2hdl\src\obj2hdl.py ^ |
-f %PROG%.hex ^ |
-c obj_code ^ |
--package obj_code_pkg ^ |
--output obj_code_pkg.vhdl |
:done |
|
/trunk/sw/demos/hello/hello.hex
0,0 → 1,15
:03000000C36000DA |
:01000800C92E |
:01001000C926 |
:01001800C91E |
:01002000C916 |
:01002800C90E |
:01003000C906 |
:03003800C3A7005B |
:1800600031500121EB0022EC0021F00022EE003E14D3833E58D3823EFA |
:1800780000D3863E08D388FB219600CDDE00DB844F070781D386C3863A |
:1800900000F376C393000A0D0A48656C6C6F20576F726C64212400E532 |
:1800A800F5DB81E620CAC0003E20D381DB80D3862AEE00772322EE0037 |
:1800C000DB81E610CADA003E10D3812AEC007EFE24CADA002322EC0005 |
:1400D800D380F1E1FBC97E2322EC00FE24CAEA00D380C92466 |
:00000001FF |
/trunk/sw/demos/c2sb/c2sb_soc.vhdl.bak
0,0 → 1,318
--############################################################################# |
-- Altair 4K Basic on DE-1 board demo |
--############################################################################# |
-- This is enough to run the Altair 4K Basic from internal FPGA RAM. |
-- The output signals of the DE-1 board are unused except for a reset button, |
-- a clock input and two seral pins (txd/rxd). it should be easy to port the |
-- Altair Basic demo to any other FPGA starter kit. |
-- |
-- The Altair Basic code is pre-loaded in an internal 4K RAM block. If the code |
-- becomes corrupted, there's no way to restore it other than reloading the |
-- FPGA -- a reset will not do. |
-- |
-- Note there are a few unused registers here and there. They are remnants of |
-- an unfinished CP/M-on-SD-card demo on which I based the Altair Basic demo. |
-- You may just ignore them. |
--############################################################################# |
-- PORT ADDRESSES: |
-- 00h : in status serial port |
-- 01h : in/out data serial port |
-- 23h : out HEX display, L (not used) |
-- 24h : out HEX display, H (not used) |
-- 40h : in switches (not used) |
-- 40h : out green leds (not used) |
-- |
-- Serial port status port: |
-- 01h : '1' => serial port RX busy |
-- 80h : '1' => serial port TX busy |
--############################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
use work.l80soc_pkg.all; |
use work.obj_code_pkg.all; |
|
-- Many of the board's i/o devices will go unused |
entity c2sb_4kbasic_cpu is |
port ( |
-- ***** Clocks |
clk_50MHz : in std_logic; |
|
-- ***** Flash 4MB |
flash_addr : out std_logic_vector(21 downto 0); |
flash_data : in std_logic_vector(7 downto 0); |
flash_oe_n : out std_logic; |
flash_we_n : out std_logic; |
flash_reset_n : out std_logic; |
|
-- ***** SRAM 256K x 16 |
sram_addr : out std_logic_vector(17 downto 0); |
sram_data : inout std_logic_vector(15 downto 0); |
sram_oe_n : out std_logic; |
sram_ub_n : out std_logic; |
sram_lb_n : out std_logic; |
sram_ce_n : out std_logic; |
sram_we_n : out std_logic; |
|
-- ***** RS-232 |
rxd : in std_logic; |
txd : out std_logic; |
|
-- ***** Switches and buttons |
switches : in std_logic_vector(9 downto 0); |
buttons : in std_logic_vector(3 downto 0); |
|
-- ***** Quad 7-seg displays |
hex0 : out std_logic_vector(0 to 6); |
hex1 : out std_logic_vector(0 to 6); |
hex2 : out std_logic_vector(0 to 6); |
hex3 : out std_logic_vector(0 to 6); |
|
-- ***** Leds |
red_leds : out std_logic_vector(9 downto 0); |
green_leds : out std_logic_vector(7 downto 0); |
|
-- ***** SD Card |
sd_data : in std_logic; |
sd_cs : out std_logic; |
sd_cmd : out std_logic; |
sd_clk : out std_logic |
); |
end c2sb_4kbasic_cpu; |
|
architecture minimal of c2sb_4kbasic_cpu is |
|
--############################################################################## |
-- light8080 SoC signals |
|
signal data_in : std_logic_vector(7 downto 0); |
signal vma : std_logic; |
signal rd : std_logic; |
signal wr : std_logic; |
signal io : std_logic; |
signal data_out : std_logic_vector(7 downto 0); |
signal addr : std_logic_vector(15 downto 0); |
signal inta : std_logic; |
signal inte : std_logic; |
signal intr : std_logic; |
signal halt : std_logic; |
|
-- signals for sram 'synchronization' |
signal sram_data_out : std_logic_vector(7 downto 0); -- sram output reg |
signal sram_write : std_logic; -- sram we register |
|
-- signals for debug |
signal address_reg : std_logic_vector(15 downto 0); -- registered addr bus |
|
signal rs_tx_data : std_logic_vector(7 downto 0); |
|
--############################################################################## |
-- General I/O control signals |
|
signal io_q : std_logic; |
signal rd_q : std_logic; |
signal io_read : std_logic; |
signal io_write : std_logic; |
signal low_ram_we : std_logic; |
|
--############################################################################## |
-- RS232 signals |
|
signal rx_rdy : std_logic; |
signal tx_rdy : std_logic; |
signal rs232_data_rx : std_logic_vector(7 downto 0); |
signal rs232_status : std_logic_vector(7 downto 0); |
signal data_io_out : std_logic_vector(7 downto 0); |
signal io_port : std_logic_vector(7 downto 0); |
signal read_rx : std_logic; |
signal write_tx : std_logic; |
|
|
--############################################################################## |
-- Application signals |
|
|
--############################################################################## |
|
-- Quad 7-segment display (non multiplexed) & LEDS |
signal display_data : std_logic_vector(15 downto 0); |
|
-- i/o signals |
signal p1in : std_logic_vector(7 downto 0); |
signal p2out : std_logic_vector(7 downto 0); |
|
-- Clock & reset signals |
signal clk_1hz : std_logic; |
signal clk_master : std_logic; |
signal counter_1hz : std_logic_vector(25 downto 0); |
signal reset : std_logic; |
signal clk : std_logic; |
|
-- SD control signals -- SD connector unused, unconnected |
|
|
begin |
|
mpu: entity work.l80soc |
generic map ( |
OBJ_CODE => obj_code |
) |
port map ( |
clk => clk, |
reset => reset, |
|
rxd => rxd, |
txd => txd, |
|
extint => "0000", |
|
p1in => p1in, |
p2out => p2out |
); |
|
|
p1in <= X"12"; -- DUMMY |
|
-- red leds (light with '1') -- some CPU control signals |
red_leds <= (others => '0'); |
|
|
--##### Input ports ########################################################### |
|
|
--############################################################################## |
-- terasIC Cyclone II STARTER KIT BOARD |
--############################################################################## |
|
--############################################################################## |
-- FLASH (flash is unused in this demo) |
--############################################################################## |
|
flash_addr <= (others => '0'); |
|
flash_we_n <= '1'; -- all enable signals inactive |
flash_oe_n <= '1'; |
flash_reset_n <= '1'; |
|
|
--############################################################################## |
-- SRAM (used as 64K x 8) |
-- |
-- NOTE: All writes go to SRAM independent of rom paging status |
--############################################################################## |
|
process(clk) |
begin |
if clk'event and clk='1' then |
if reset='1' then |
sram_addr <= "000000000000000000"; |
address_reg <= "0000000000000000"; |
sram_data_out <= X"00"; |
sram_write <= '0'; |
else |
end if; |
end if; |
end process; |
|
sram_data(15 downto 8) <= "ZZZZZZZZ"; -- high byte unused |
sram_data(7 downto 0) <= "ZZZZZZZZ" when sram_write='0' else sram_data_out; |
-- (the X"ZZ" will physically be the read input data) |
|
-- sram access controlled by WE_N |
sram_oe_n <= '0'; |
sram_ce_n <= '0'; |
sram_we_n <= not sram_write; |
sram_ub_n <= '1'; -- always disable |
sram_lb_n <= '0'; |
|
|
--############################################################################## |
-- RESET, CLOCK |
--############################################################################## |
|
-- Use button 3 as reset |
reset <= not buttons(3); |
|
|
-- Generate a 1-Hz 'clock' to flash a LED for visual reference. |
process(clk_50MHz) |
begin |
if clk_50MHz'event and clk_50MHz='1' then |
if reset = '1' then |
clk_1hz <= '0'; |
counter_1hz <= (others => '0'); |
else |
if conv_integer(counter_1hz) = 50000000 then |
counter_1hz <= (others => '0'); |
clk_1hz <= not clk_1hz; |
else |
counter_1hz <= counter_1hz + 1; |
end if; |
end if; |
end if; |
end process; |
|
-- Master clock is external 50MHz oscillator |
clk <= clk_50MHz; |
|
|
--############################################################################## |
-- LEDS, SWITCHES |
--############################################################################## |
|
-- Display the contents of a debug register at the green leds bar |
green_leds <= p2out; |
|
|
--############################################################################## |
-- QUAD 7-SEGMENT DISPLAYS |
--############################################################################## |
|
display_data <= X"12AB"; |
|
-- 7-segment encoders; the dev board displays are not multiplexed or encoded |
with display_data(15 downto 12) select hex3 <= |
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3", |
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7", |
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b", |
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others; |
|
with display_data(11 downto 8) select hex2 <= |
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3", |
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7", |
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b", |
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others; |
|
with display_data(7 downto 4) select hex1 <= |
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3", |
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7", |
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b", |
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others; |
|
with display_data(3 downto 0) select hex0 <= |
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3", |
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7", |
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b", |
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others; |
|
--############################################################################## |
-- SD card interface |
--############################################################################## |
|
-- SD card unused in this demo |
sd_cs <= '0'; |
sd_cmd <= '0'; |
sd_clk <= '0'; |
sd_in <= '0'; |
|
|
--############################################################################## |
-- SERIAL |
--############################################################################## |
|
-- UART is embedded in SoC entity, txd & rxd are connected straight to the SoC |
|
end minimal; |
/trunk/sw/demos/c2sb/c2sb_soc.vhdl
0,0 → 1,301
--############################################################################## |
-- Light8080 SoC demo on DE-1 board |
--############################################################################## |
-- |
-- This is a minimal demo of the light8080 SoC targetting Terasic's DE-1 |
-- development board for Cyclone-2 FPGAs. |
-- Since the demo uses little board resources other than the serial port it |
-- should be easy to port it to other platforms. |
-- This file is strictly for demonstration purposes and has not been tested |
-- |
-- The SoC contains a block of RAM that is used for both program and data. The |
-- BRAM is initialized at synthesis time with a constant taken from package |
-- 'obj_code_pkg'. This package can be built from an object code file in Intel |
-- HEX format with utility '/tools/obj2hdl' included with the project. |
-- |
-- This demo has been built from a generic template for designs targetting the |
-- DE-1 development board. The entity defines all the inputs and outputs present |
-- in the actual board, whether or not they are used in the design at hand. |
--############################################################################## |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
-- Package with utility functions for handling SoC object code. |
use work.l80pkg.all; |
-- Package that contains the program object code in VHDL constant format. |
use work.obj_code_pkg.all; |
|
|
-- Define the entity outputs as they are connected in the DE-1 development |
-- board. Many of the outputs will be left unused in this demo. |
entity c2sb_soc is |
port ( |
-- ***** Clocks |
clk_50MHz : in std_logic; |
|
-- ***** Flash 4MB |
flash_addr : out std_logic_vector(21 downto 0); |
flash_data : in std_logic_vector(7 downto 0); |
flash_oe_n : out std_logic; |
flash_we_n : out std_logic; |
flash_reset_n : out std_logic; |
|
-- ***** SRAM 256K x 16 |
sram_addr : out std_logic_vector(17 downto 0); |
sram_data : inout std_logic_vector(15 downto 0); |
sram_oe_n : out std_logic; |
sram_ub_n : out std_logic; |
sram_lb_n : out std_logic; |
sram_ce_n : out std_logic; |
sram_we_n : out std_logic; |
|
-- ***** RS-232 |
rxd : in std_logic; |
txd : out std_logic; |
|
-- ***** Switches and buttons |
switches : in std_logic_vector(9 downto 0); |
buttons : in std_logic_vector(3 downto 0); |
|
-- ***** Quad 7-seg displays |
hex0 : out std_logic_vector(0 to 6); |
hex1 : out std_logic_vector(0 to 6); |
hex2 : out std_logic_vector(0 to 6); |
hex3 : out std_logic_vector(0 to 6); |
|
-- ***** Leds |
red_leds : out std_logic_vector(9 downto 0); |
green_leds : out std_logic_vector(7 downto 0); |
|
-- ***** SD Card |
sd_data : in std_logic; |
sd_cs : out std_logic; |
sd_cmd : out std_logic; |
sd_clk : out std_logic |
); |
end c2sb_soc; |
|
architecture minimal of c2sb_soc is |
|
--############################################################################## |
-- Some of these signals are |
|
-- light8080 SoC signals ------------------------------------------------------- |
signal p1in : std_logic_vector(7 downto 0); |
signal p2out : std_logic_vector(7 downto 0); |
signal uart_txd : std_logic; |
signal uart_rxd : std_logic; |
|
-- Signals for external SRAM synchronization ----------------------------------- |
signal sram_data_out : std_logic_vector(7 downto 0); -- sram output reg |
signal sram_write : std_logic; -- sram we register |
signal address_reg : std_logic_vector(15 downto 0); -- registered addr bus |
|
|
--############################################################################## |
-- On-board device interface signals |
|
-- Quad 7-segment display (non multiplexed) & LEDS ----------------------------- |
signal display_data : std_logic_vector(15 downto 0); |
|
|
-- Clock & reset signals ------------------------------------------------------- |
signal clk_1hz : std_logic; |
signal clk_master : std_logic; |
signal reset : std_logic; |
signal clk : std_logic; |
signal counter_1hz : std_logic_vector(25 downto 0); |
|
-- SD control signals ---------------------------------------------------------- |
-- SD connector unused, unconnected |
|
|
--## Functions ################################################################# |
|
-- Converts hex nibble to 7-segment (sinthesizable). |
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF |
function nibble_to_7seg(nibble : std_logic_vector(3 downto 0)) |
return std_logic_vector is |
begin |
case nibble is |
when X"0" => return "0000001"; |
when X"1" => return "1001111"; |
when X"2" => return "0010010"; |
when X"3" => return "0000110"; |
when X"4" => return "1001100"; |
when X"5" => return "0100100"; |
when X"6" => return "0100000"; |
when X"7" => return "0001111"; |
when X"8" => return "0000000"; |
when X"9" => return "0000100"; |
when X"a" => return "0001000"; |
when X"b" => return "1100000"; |
when X"c" => return "0110001"; |
when X"d" => return "1000010"; |
when X"e" => return "0110000"; |
when X"f" => return "0111000"; |
when others => return "0111111"; -- can't happen |
end case; |
end function nibble_to_7seg; |
|
begin |
|
-- SOC instantiation |
mpu: entity work.l80soc |
generic map ( |
OBJ_CODE => work.obj_code_pkg.obj_code, |
UART_HARDWIRED => false, -- UART baud rate is programmable in run time |
UART_IRQ_LINE => 3 -- UART uses IRQ3 line of irq controller |
) |
port map ( |
clk => clk, |
reset => reset, |
|
rxd => uart_rxd, |
txd => uart_txd, |
|
extint => "0000", -- No external interrupts |
|
p1in => p1in, |
p2out => p2out |
); |
|
-- Input port connected to switches for lack of better use |
p1in <= switches(7 downto 0); |
|
|
--##### Input ports ########################################################### |
|
|
--############################################################################## |
-- terasIC Cyclone II STARTER KIT BOARD |
--############################################################################## |
|
--############################################################################## |
-- FLASH (flash is unused in this demo) |
--############################################################################## |
|
flash_addr <= (others => '0'); |
|
flash_we_n <= '1'; -- all enable signals inactive |
flash_oe_n <= '1'; |
flash_reset_n <= '1'; |
|
|
--############################################################################## |
-- SRAM (wired as 64K x 8) |
-- The SRAM is unused in this demo. |
--############################################################################## |
|
-- These registera make the external, asynchronous SRAM behave like an |
-- internal syncronous BRAM, except for the timing. |
-- Since the SoC has no wait state capability, the SoC clock rate must |
-- accomodate the SRAM timing -- including FPGA clock-to-output, RAM delays |
-- and FPGA input setup and hold times. Setting up the synthesis constraints |
-- is left to the user too. |
sram_registers: |
process(clk) |
begin |
if clk'event and clk='1' then |
if reset='1' then |
sram_addr <= "000000000000000000"; |
address_reg <= "0000000000000000"; |
sram_data_out <= X"00"; |
sram_write <= '0'; |
else |
end if; |
end if; |
end process sram_registers; |
|
sram_data(15 downto 8) <= "ZZZZZZZZ"; -- high byte unused |
sram_data(7 downto 0) <= "ZZZZZZZZ" when sram_write='0' else sram_data_out; |
-- (the X"ZZ" will physically be the read input data) |
|
-- sram access controlled by WE_N |
sram_oe_n <= '0'; |
sram_ce_n <= '0'; |
sram_we_n <= not sram_write; |
sram_ub_n <= '1'; -- always disable |
sram_lb_n <= '0'; |
|
|
--############################################################################## |
-- RESET, CLOCK |
--############################################################################## |
|
-- Use button 0 as reset |
reset <= not buttons(0); |
|
|
-- Generate a 1-Hz 'clock' to flash a LED for visual reference. |
process(clk_50MHz) |
begin |
if clk_50MHz'event and clk_50MHz='1' then |
if reset = '1' then |
clk_1hz <= '0'; |
counter_1hz <= (others => '0'); |
else |
if conv_integer(counter_1hz) = 50000000 then |
counter_1hz <= (others => '0'); |
clk_1hz <= not clk_1hz; |
else |
counter_1hz <= counter_1hz + 1; |
end if; |
end if; |
end if; |
end process; |
|
-- Master clock is external 50MHz oscillator |
clk <= clk_50MHz; |
|
|
--############################################################################## |
-- LEDS, SWITCHES |
--############################################################################## |
|
-- Display the contents of an output port at the green leds bar |
green_leds <= p2out; |
|
-- Red leds unused except for 1-Hz clock |
red_leds(9 downto 1) <= (others => '0'); |
red_leds(0) <= clk_1hz; |
|
|
--############################################################################## |
-- QUAD 7-SEGMENT DISPLAYS |
--############################################################################## |
|
-- Display the contents of the output port at the hex displays. |
display_data <= p2out & p1in; |
|
-- 7-segment encoders; the dev board displays are not multiplexed or encoded |
hex3 <= nibble_to_7seg(display_data(15 downto 12)); |
hex2 <= nibble_to_7seg(display_data(11 downto 8)); |
hex1 <= nibble_to_7seg(display_data( 7 downto 4)); |
hex0 <= nibble_to_7seg(display_data( 3 downto 0)); |
|
|
--############################################################################## |
-- SD card interface |
--############################################################################## |
|
-- SD card unused in this demo |
sd_cs <= '0'; |
sd_cmd <= '0'; |
sd_clk <= '0'; |
--sd_in <= '0'; |
|
|
--############################################################################## |
-- SERIAL |
--############################################################################## |
|
-- Txd & rxd connected straight to the SoC |
txd <= uart_txd; |
uart_rxd <= rxd; |
|
|
end minimal; |
/trunk/sw/demos/c2sb/c2sb_pins.csv
0,0 → 1,160
# Copyright (C) 1991-2009 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
|
# Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition |
# File: C:\altera\Kits\CycloneII_Starter_Kit-v1.0.0\proyectos\demo_tutorial\pin_assignment\c2sb_demo.csv |
# Generated on: Sun Jul 19 05:05:49 2009 |
|
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software. |
|
To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Group,Current Strength,PCB layer |
buttons[3],Input,PIN_T21,6,B6_N0,,,buttons[3..0],, |
buttons[2],Input,PIN_T22,6,B6_N0,,,buttons[3..0],, |
buttons[1],Input,PIN_R21,6,B6_N0,,,buttons[3..0],, |
buttons[0],Input,PIN_R22,6,B6_N0,,,buttons[3..0],, |
flash_addr[21],Output,PIN_R13,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[20],Output,PIN_U13,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[19],Output,PIN_V14,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[18],Output,PIN_U14,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[17],Output,PIN_AA20,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[16],Output,PIN_AB12,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[15],Output,PIN_AA12,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[14],Output,PIN_AB13,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[13],Output,PIN_AA13,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[12],Output,PIN_AB14,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[11],Output,PIN_T12,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[10],Output,PIN_R12,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[9],Output,PIN_Y13,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[8],Output,PIN_R14,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[7],Output,PIN_W15,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[6],Output,PIN_V15,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[5],Output,PIN_U15,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[4],Output,PIN_T15,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[3],Output,PIN_R15,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[2],Output,PIN_Y16,7,B7_N0,,,flash_addr[21..0],, |
flash_addr[1],Output,PIN_AA14,7,B7_N1,,,flash_addr[21..0],, |
flash_addr[0],Output,PIN_AB20,7,B7_N0,,,flash_addr[21..0],, |
flash_data[7],Input,PIN_AA19,7,B7_N0,,,flash_data[7..0],, |
flash_data[6],Input,PIN_AB19,7,B7_N0,,,flash_data[7..0],, |
flash_data[5],Input,PIN_AA18,7,B7_N0,,,flash_data[7..0],, |
flash_data[4],Input,PIN_AB18,7,B7_N0,,,flash_data[7..0],, |
flash_data[3],Input,PIN_AA17,7,B7_N1,,,flash_data[7..0],, |
flash_data[2],Input,PIN_AB17,7,B7_N1,,,flash_data[7..0],, |
flash_data[1],Input,PIN_AA16,7,B7_N1,,,flash_data[7..0],, |
flash_data[0],Input,PIN_AB16,7,B7_N1,,,flash_data[7..0],, |
flash_oe_n,Output,PIN_AA15,7,B7_N1,,,,, |
flash_reset_n,Output,PIN_W14,7,B7_N1,,,,, |
flash_we_n,Output,PIN_Y14,7,B7_N0,,,,, |
green_leds[7],Output,PIN_Y21,6,B6_N1,,,green_leds[7..0],, |
green_leds[6],Output,PIN_Y22,6,B6_N1,,,green_leds[7..0],, |
green_leds[5],Output,PIN_W21,6,B6_N1,,,green_leds[7..0],, |
green_leds[4],Output,PIN_W22,6,B6_N1,,,green_leds[7..0],, |
green_leds[3],Output,PIN_V21,6,B6_N1,,,green_leds[7..0],, |
green_leds[2],Output,PIN_V22,6,B6_N1,,,green_leds[7..0],, |
green_leds[1],Output,PIN_U21,6,B6_N1,,,green_leds[7..0],, |
green_leds[0],Output,PIN_U22,6,B6_N1,,,green_leds[7..0],, |
hex0[0],Output,PIN_J2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],, |
hex0[1],Output,PIN_J1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],, |
hex0[2],Output,PIN_H2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],, |
hex0[3],Output,PIN_H1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],, |
hex0[4],Output,PIN_F2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],, |
hex0[5],Output,PIN_F1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],, |
hex0[6],Output,PIN_E2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],, |
hex1[0],Output,PIN_E1,2,B2_N1,3.3-V LVTTL,,hex1[0..6],, |
hex1[1],Output,PIN_H6,2,B2_N0,3.3-V LVTTL,,hex1[0..6],, |
hex1[2],Output,PIN_H5,2,B2_N0,3.3-V LVTTL,,hex1[0..6],, |
hex1[3],Output,PIN_H4,2,B2_N0,3.3-V LVTTL,,hex1[0..6],, |
hex1[4],Output,PIN_G3,2,B2_N0,3.3-V LVTTL,,hex1[0..6],, |
hex1[5],Output,PIN_D2,2,B2_N0,3.3-V LVTTL,,hex1[0..6],, |
hex1[6],Output,PIN_D1,2,B2_N0,3.3-V LVTTL,,hex1[0..6],, |
hex2[0],Output,PIN_G5,2,B2_N0,3.3-V LVTTL,,hex2[0..6],, |
hex2[1],Output,PIN_G6,2,B2_N0,3.3-V LVTTL,,hex2[0..6],, |
hex2[2],Output,PIN_C2,2,B2_N0,3.3-V LVTTL,,hex2[0..6],, |
hex2[3],Output,PIN_C1,2,B2_N0,3.3-V LVTTL,,hex2[0..6],, |
hex2[4],Output,PIN_E3,2,B2_N0,3.3-V LVTTL,,hex2[0..6],, |
hex2[5],Output,PIN_E4,2,B2_N0,3.3-V LVTTL,,hex2[0..6],, |
hex2[6],Output,PIN_D3,2,B2_N0,3.3-V LVTTL,,hex2[0..6],, |
hex3[0],Output,PIN_F4,2,B2_N0,3.3-V LVTTL,,hex3[0..6],, |
hex3[1],Output,PIN_D5,2,B2_N0,3.3-V LVTTL,,hex3[0..6],, |
hex3[2],Output,PIN_D6,2,B2_N0,3.3-V LVTTL,,hex3[0..6],, |
hex3[3],Output,PIN_J4,2,B2_N1,3.3-V LVTTL,,hex3[0..6],, |
hex3[4],Output,PIN_L8,2,B2_N1,3.3-V LVTTL,,hex3[0..6],, |
hex3[5],Output,PIN_F3,2,B2_N0,3.3-V LVTTL,,hex3[0..6],, |
hex3[6],Output,PIN_D4,2,B2_N0,3.3-V LVTTL,,hex3[0..6],, |
red_leds[9],Output,PIN_R17,6,B6_N1,,,red_leds[9..0],, |
red_leds[8],Output,PIN_R18,6,B6_N0,,,red_leds[9..0],, |
red_leds[7],Output,PIN_U18,6,B6_N1,,,red_leds[9..0],, |
red_leds[6],Output,PIN_Y18,6,B6_N1,,,red_leds[9..0],, |
red_leds[5],Output,PIN_V19,6,B6_N1,,,red_leds[9..0],, |
red_leds[4],Output,PIN_T18,6,B6_N1,,,red_leds[9..0],, |
red_leds[3],Output,PIN_Y19,6,B6_N1,,,red_leds[9..0],, |
red_leds[2],Output,PIN_U19,6,B6_N1,,,red_leds[9..0],, |
red_leds[1],Output,PIN_R19,6,B6_N0,,,red_leds[9..0],, |
red_leds[0],Output,PIN_R20,6,B6_N0,,,red_leds[9..0],, |
rxd,Input,PIN_F14,4,B4_N1,,,,, |
sd_clk,Output,PIN_V20,6,B6_N1,,,,, |
sd_cmd,Output,PIN_Y20,6,B6_N1,,,,, |
sd_cs,Output,PIN_U20,6,B6_N1,,,,, |
sd_data,Input,PIN_W20,6,B6_N1,,,,, |
sram_addr[17],Output,PIN_Y5,8,B8_N1,,,sram_addr[17..0],, |
sram_addr[16],Output,PIN_Y6,8,B8_N1,,,sram_addr[17..0],, |
sram_addr[15],Output,PIN_T7,8,B8_N1,,,sram_addr[17..0],, |
sram_addr[14],Output,PIN_R10,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[13],Output,PIN_U10,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[12],Output,PIN_Y10,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[11],Output,PIN_T11,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[10],Output,PIN_R11,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[9],Output,PIN_W11,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[8],Output,PIN_V11,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[7],Output,PIN_AB11,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[6],Output,PIN_AA11,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[5],Output,PIN_AB10,8,B8_N0,,,sram_addr[17..0],, |
sram_addr[4],Output,PIN_AA5,8,B8_N1,,,sram_addr[17..0],, |
sram_addr[3],Output,PIN_AB4,8,B8_N1,,,sram_addr[17..0],, |
sram_addr[2],Output,PIN_AA4,8,B8_N1,,,sram_addr[17..0],, |
sram_addr[1],Output,PIN_AB3,8,B8_N1,,,sram_addr[17..0],, |
sram_addr[0],Output,PIN_AA3,8,B8_N1,,,sram_addr[17..0],, |
sram_ce_n,Output,PIN_AB5,8,B8_N1,,,,, |
sram_data[15],Bidir,PIN_U8,8,B8_N1,,,sram_data[15..0],, |
sram_data[14],Bidir,PIN_V8,8,B8_N1,,,sram_data[15..0],, |
sram_data[13],Bidir,PIN_W8,8,B8_N1,,,sram_data[15..0],, |
sram_data[12],Bidir,PIN_R9,8,B8_N0,,,sram_data[15..0],, |
sram_data[11],Bidir,PIN_U9,8,B8_N0,,,sram_data[15..0],, |
sram_data[10],Bidir,PIN_V9,8,B8_N1,,,sram_data[15..0],, |
sram_data[9],Bidir,PIN_W9,8,B8_N0,,,sram_data[15..0],, |
sram_data[8],Bidir,PIN_Y9,8,B8_N0,,,sram_data[15..0],, |
sram_data[7],Bidir,PIN_AB9,8,B8_N0,,,sram_data[15..0],, |
sram_data[6],Bidir,PIN_AA9,8,B8_N0,,,sram_data[15..0],, |
sram_data[5],Bidir,PIN_AB8,8,B8_N0,,,sram_data[15..0],, |
sram_data[4],Bidir,PIN_AA8,8,B8_N0,,,sram_data[15..0],, |
sram_data[3],Bidir,PIN_AB7,8,B8_N1,,,sram_data[15..0],, |
sram_data[2],Bidir,PIN_AA7,8,B8_N1,,,sram_data[15..0],, |
sram_data[1],Bidir,PIN_AB6,8,B8_N1,,,sram_data[15..0],, |
sram_data[0],Bidir,PIN_AA6,8,B8_N1,,,sram_data[15..0],, |
sram_lb_n,Output,PIN_Y7,8,B8_N1,,,,, |
sram_oe_n,Output,PIN_T8,8,B8_N1,,,,, |
sram_ub_n,Output,PIN_W7,8,B8_N1,,,,, |
sram_we_n,Output,PIN_AA10,8,B8_N0,,,,, |
switches[9],Input,PIN_L2,2,B2_N1,,,switches[9..0],, |
switches[8],Input,PIN_M1,1,B1_N0,,,switches[9..0],, |
switches[7],Input,PIN_M2,1,B1_N0,,,switches[9..0],, |
switches[6],Input,PIN_U11,8,B8_N0,,,switches[9..0],, |
switches[5],Input,PIN_U12,8,B8_N0,,,switches[9..0],, |
switches[4],Input,PIN_W12,7,B7_N1,,,switches[9..0],, |
switches[3],Input,PIN_V12,7,B7_N1,,,switches[9..0],, |
switches[2],Input,PIN_M22,6,B6_N0,,,switches[9..0],, |
switches[1],Input,PIN_L21,5,B5_N1,,,switches[9..0],, |
switches[0],Input,PIN_L22,5,B5_N1,,,switches[9..0],, |
txd,Output,PIN_G12,4,B4_N1,,,,, |
clk_50MHz,Unknown,PIN_L1,2,B2_N1,,,,, |
/trunk/sw/demos/c2sb/c2sb_soc_tb.vhdl
0,0 → 1,91
-------------------------------------------------------------------------------- |
-- c2sb_soc_tb.vhdl -- Minimal test bench for c2sb_soc. |
-- |
-- c2sb_soc is a light8080 SoC demo on a Cyclone 2 starter Board (C2SB). This |
-- is a minimalistic simulation test bench. The test bench only drives the clock |
-- and reset inputs. |
-- |
-- This simulation test bench can be marginally useful for basic troubleshooting |
-- of a C2SB board demo or as a starting point for a true test bench. |
-------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.ALL; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.ALL; |
|
entity c2sb_soc_tb is |
end entity c2sb_soc_tb; |
|
architecture behavior of c2sb_soc_tb is |
|
-------------------------------------------------------------------------------- |
-- Simulation parameters |
|
-- T: simulated clock period |
constant T : time := 100 ns; |
|
-- MAX_SIM_LENGTH: maximum simulation time |
constant MAX_SIM_LENGTH : time := T*7000; -- enough for most purposes |
|
|
-------------------------------------------------------------------------------- |
|
signal clk : std_logic := '0'; |
signal done : std_logic := '0'; |
signal buttons : std_logic_vector(3 downto 0); |
signal green_leds : std_logic_vector(7 downto 0); |
|
begin |
|
-- Instantiate the Unit Under Test (UUT) |
-- The only mandatory signals are clk and buttons(3) |
uut: entity work.c2sb_soc |
port map ( |
clk_50MHz => clk, |
buttons => buttons, |
|
rxd => '0', |
flash_data => (others => '0'), |
switches => (others => '0'), |
sd_data => '0', |
green_leds => green_leds |
); |
|
|
-- clock: run clock until test is done |
clock: |
process(done, clk) |
begin |
if done = '0' then |
clk <= not clk after T/2; |
end if; |
end process clock; |
|
|
-- Drive reset and done |
main_test: |
process |
begin |
-- Assert reset for at least one full clk period |
buttons(3) <= '0'; |
wait until clk = '1'; |
wait for T/2; |
buttons(3) <= '1'; |
|
-- Remember to 'cut away' the preceding 3 clk semiperiods from |
-- the wait statement... |
wait for (MAX_SIM_LENGTH - T*1.5); |
|
-- Maximum sim time elapsed, stop the clk process asserting 'done' (which |
-- will stop the simulation) |
done <= '1'; |
|
assert (done = '1') |
report "Test timed out." |
severity failure; |
|
wait; |
end process main_test; |
|
end; |