URL
https://opencores.org/ocsvn/logicprobe/logicprobe/trunk
Subversion Repositories logicprobe
Compare Revisions
- This comparison shows the changes necessary to convert path
/logicprobe/tags/LogicProbe-1.0/tst/boards/XESS-XST-3S1000
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/README
0,0 → 1,10
This board is equipped with a single RS-232 connector. The lines |
TXD, RXD, RTS, and CTS are connected (via level shifters) to the |
FPGA. Because in another project, two serial lines were required |
(and no hardware flow control was necessary), the signals RTS and |
CTS were used as TXD and RXD, respectively, in a separate (third) |
connector. In this way the single serial line with flow control |
has been split into two serial lines without flow control. The |
constraints file given here uses the second TXD line as output |
for the logic analyzer. This can be changed to the original TXD |
line by specifying "j2" instead of "f4" in the constraints file. |
/lfsr128/lfsr128.xise
0,0 → 1,347
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="../lfsr128.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="../../../../src/fpga/LogicProbe.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
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<file xil_pn:name="../lfsr128.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
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<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="lfsr128" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings/> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
</autoManagedFiles> |
|
</project> |
/lfsr128.v
0,0 → 1,76
// |
// lfsr128.v -- a linear feedback shift register with 128 bits |
// (actually constructed from 4 instances of a 32-bit lfsr) |
// |
|
|
module lfsr128(clk, reset_in_n, s, rs232_txd); |
input clk; |
input reset_in_n; |
output [3:0] s; |
output rs232_txd; |
|
wire reset; |
reg [23:0] reset_counter; |
|
reg [31:0] lfsr0; |
reg [31:0] lfsr1; |
reg [31:0] lfsr2; |
reg [31:0] lfsr3; |
|
wire trigger; |
wire sample; |
wire [127:0] log_data; |
|
assign reset = (reset_counter == 24'hFFFFFF) ? 0 : 1; |
always @(posedge clk) begin |
if (reset_in_n == 0) begin |
reset_counter <= 24'h000000; |
end else begin |
if (reset_counter != 24'hFFFFFF) begin |
reset_counter <= reset_counter + 1; |
end |
end |
end |
|
always @(posedge clk) begin |
if (reset == 1) begin |
lfsr0 <= 32'hC70337DB; |
lfsr1 <= 32'h7F4D514F; |
lfsr2 <= 32'h75377599; |
lfsr3 <= 32'h7D5937A3; |
end else begin |
if (lfsr0[0] == 0) begin |
lfsr0 <= lfsr0 >> 1; |
end else begin |
lfsr0 <= (lfsr0 >> 1) ^ 32'hD0000001; |
end |
if (lfsr1[0] == 0) begin |
lfsr1 <= lfsr1 >> 1; |
end else begin |
lfsr1 <= (lfsr1 >> 1) ^ 32'hD0000001; |
end |
if (lfsr2[0] == 0) begin |
lfsr2 <= lfsr2 >> 1; |
end else begin |
lfsr2 <= (lfsr2 >> 1) ^ 32'hD0000001; |
end |
if (lfsr3[0] == 0) begin |
lfsr3 <= lfsr3 >> 1; |
end else begin |
lfsr3 <= (lfsr3 >> 1) ^ 32'hD0000001; |
end |
end |
end |
|
assign s[3] = lfsr0[27]; |
assign s[2] = lfsr1[13]; |
assign s[1] = lfsr2[23]; |
assign s[0] = lfsr3[11]; |
|
assign trigger = (lfsr0 == 32'h7119C0CD) ? 1 : 0; |
assign sample = 1; |
assign log_data = { lfsr0, lfsr1, lfsr2, lfsr3 }; |
LogicProbe lp(clk, reset, trigger, sample, log_data, rs232_txd); |
|
endmodule |
/Makefile
0,0 → 1,12
# |
# Makefile to synthesize the project (this is only a dummy) |
# |
|
all: |
@echo "Please use Xilinx ISE 14.5 to synthesize the project!" |
|
clean: |
mv lfsr128/lfsr128.xise . |
rm -rf lfsr128/* |
mv lfsr128.xise lfsr128 |
rm -f *~ |
/lfsr128.ucf
0,0 → 1,7
NET "clk" LOC = "p8" ; |
NET "reset_in_n" LOC = "e11" ; |
NET "rs232_txd" LOC = "f4" ; |
NET "s<0>" LOC = "m6" ; |
NET "s<1>" LOC = "m11" ; |
NET "s<2>" LOC = "n6" ; |
NET "s<3>" LOC = "r7" ; |