URL
https://opencores.org/ocsvn/logicprobe/logicprobe/trunk
Subversion Repositories logicprobe
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/logicprobe
- from Rev 11 to Rev 12
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Rev 11 → Rev 12
/trunk/tst/boards/XESS-XST-3S1000/README
0,0 → 1,10
This board is equipped with a single RS-232 connector. The lines |
TXD, RXD, RTS, and CTS are connected (via level shifters) to the |
FPGA. Because in another project, two serial lines were required |
(and no hardware flow control was necessary), the signals RTS and |
CTS were used as TXD and RXD, respectively, in a separate (third) |
connector. In this way the single serial line with flow control |
has been split into two serial lines without flow control. The |
constraints file given here uses the second TXD line as output |
for the logic analyzer. This can be changed to the original TXD |
line by specifying "j2" instead of "f4" in the constraints file. |