OpenCores
URL https://opencores.org/ocsvn/logicprobe/logicprobe/trunk

Subversion Repositories logicprobe

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  • This comparison shows the changes necessary to convert path 
    /logicprobe
    from Rev 18 to Rev 19
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Rev 18 → Rev 19

/tags/LogicProbe-1.1/Makefile
0,0 → 1,25
#
# Makefile for LogicProbe project
#
 
VERSION = 1.1
 
DIRS = src tst
 
all:
for i in $(DIRS) ; do \
$(MAKE) -C $$i all ; \
done
 
clean:
for i in $(DIRS) ; do \
$(MAKE) -C $$i clean ; \
done
rm -f *~
 
dist: clean
(cd .. ; \
tar --exclude-vcs -cvf \
LogicProbe-$(VERSION).tar \
LogicProbe-$(VERSION)/* ; \
gzip -f LogicProbe-$(VERSION).tar)
/tags/LogicProbe-1.1/tst/boards/XESS-XST-3S1000/README
0,0 → 1,10
This board is equipped with a single RS-232 connector. The lines
TXD, RXD, RTS, and CTS are connected (via level shifters) to the
FPGA. Because in another project, two serial lines were required
(and no hardware flow control was necessary), the signals RTS and
CTS were used as TXD and RXD, respectively, in a separate (third)
connector. In this way the single serial line with flow control
has been split into two serial lines without flow control. The
constraints file given here uses the second TXD line as output
for the logic analyzer. This can be changed to the original TXD
line by specifying "j2" instead of "f4" in the constraints file.
/tags/LogicProbe-1.1/tst/boards/XESS-XST-3S1000/lfsr128/lfsr128.xise
0,0 → 1,347
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="../lfsr128.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../../src/fpga/LogicProbe.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../lfsr128.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
 
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="JTAG Clock" xil_pn:valueState="non-default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|lfsr128" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../lfsr128.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/lfsr128" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="lfsr128" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="lfsr128_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="lfsr128_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="lfsr128_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="lfsr128_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.5/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="lfsr128" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-12-18T10:31:41" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="794E4E60670A8681D759C981849C2AA9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
 
<libraries/>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
 
</project>
/tags/LogicProbe-1.1/tst/boards/XESS-XST-3S1000/lfsr128.v
0,0 → 1,76
//
// lfsr128.v -- a linear feedback shift register with 128 bits
// (actually constructed from 4 instances of a 32-bit lfsr)
//
 
 
module lfsr128(clk, reset_in_n, s, rs232_txd);
input clk;
input reset_in_n;
output [3:0] s;
output rs232_txd;
 
wire reset;
reg [23:0] reset_counter;
 
reg [31:0] lfsr0;
reg [31:0] lfsr1;
reg [31:0] lfsr2;
reg [31:0] lfsr3;
 
wire trigger;
wire sample;
wire [127:0] log_data;
 
assign reset = (reset_counter == 24'hFFFFFF) ? 0 : 1;
always @(posedge clk) begin
if (reset_in_n == 0) begin
reset_counter <= 24'h000000;
end else begin
if (reset_counter != 24'hFFFFFF) begin
reset_counter <= reset_counter + 1;
end
end
end
 
always @(posedge clk) begin
if (reset == 1) begin
lfsr0 <= 32'hC70337DB;
lfsr1 <= 32'h7F4D514F;
lfsr2 <= 32'h75377599;
lfsr3 <= 32'h7D5937A3;
end else begin
if (lfsr0[0] == 0) begin
lfsr0 <= lfsr0 >> 1;
end else begin
lfsr0 <= (lfsr0 >> 1) ^ 32'hD0000001;
end
if (lfsr1[0] == 0) begin
lfsr1 <= lfsr1 >> 1;
end else begin
lfsr1 <= (lfsr1 >> 1) ^ 32'hD0000001;
end
if (lfsr2[0] == 0) begin
lfsr2 <= lfsr2 >> 1;
end else begin
lfsr2 <= (lfsr2 >> 1) ^ 32'hD0000001;
end
if (lfsr3[0] == 0) begin
lfsr3 <= lfsr3 >> 1;
end else begin
lfsr3 <= (lfsr3 >> 1) ^ 32'hD0000001;
end
end
end
 
assign s[3] = lfsr0[27];
assign s[2] = lfsr1[13];
assign s[1] = lfsr2[23];
assign s[0] = lfsr3[11];
 
assign trigger = (lfsr0 == 32'h7119C0CD) ? 1 : 0;
assign sample = 1;
assign log_data = { lfsr0, lfsr1, lfsr2, lfsr3 };
LogicProbe lp(clk, reset, trigger, sample, log_data, rs232_txd);
 
endmodule
/tags/LogicProbe-1.1/tst/boards/XESS-XST-3S1000/Makefile
0,0 → 1,12
#
# Makefile to synthesize the project (this is only a dummy)
#
 
all:
@echo "Please use Xilinx ISE 14.5 to synthesize the project!"
 
clean:
mv lfsr128/lfsr128.xise .
rm -rf lfsr128/*
mv lfsr128.xise lfsr128
rm -f *~
/tags/LogicProbe-1.1/tst/boards/XESS-XST-3S1000/lfsr128.ucf
0,0 → 1,7
NET "clk" LOC = "p8" ;
NET "reset_in_n" LOC = "e11" ;
NET "rs232_txd" LOC = "f4" ;
NET "s<0>" LOC = "m6" ;
NET "s<1>" LOC = "m11" ;
NET "s<2>" LOC = "n6" ;
NET "s<3>" LOC = "r7" ;
/tags/LogicProbe-1.1/tst/boards/Digilent-S3E-500/Makefile
0,0 → 1,12
#
# Makefile to synthesize the project (this is only a dummy)
#
 
all:
@echo "Please use Xilinx ISE 14.5 to synthesize the project!"
 
clean:
#mv lfsr128/lfsr128.xise .
#rm -rf lfsr128/*
#mv lfsr128.xise lfsr128
rm -f *~
/tags/LogicProbe-1.1/tst/boards/Makefile
0,0 → 1,16
#
# Makefile to synthesize the project for different boards
#
 
DIRS = XESS-XST-3S1000 Digilent-S3E-500
 
all:
for i in $(DIRS) ; do \
$(MAKE) -C $$i all ; \
done
 
clean:
for i in $(DIRS) ; do \
$(MAKE) -C $$i clean ; \
done
rm -f *~
/tags/LogicProbe-1.1/tst/Makefile
0,0 → 1,17
#
# Makefile to build the simulation test programs and
# synthesize the project for different boards
#
 
DIRS = sim-c sim-v boards
 
all:
for i in $(DIRS) ; do \
$(MAKE) -C $$i all ; \
done
 
clean:
for i in $(DIRS) ; do \
$(MAKE) -C $$i clean ; \
done
rm -f *~
/tags/LogicProbe-1.1/tst/sim-c/lfsr128.c
0,0 → 1,50
/*
* lfsr128.c -- a linear feedback shift register with 128 bits
* (actually constructed from 4 instances of a 32-bit lfsr)
*/
 
 
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
 
 
int main(void) {
unsigned int startState[4] = {
0xC70337DB,
0x7F4D514F,
0x75377599,
0x7D5937A3
};
/* taps at 32 31 29 1 */
unsigned int taps = 0xD0000001;
unsigned int lfsr[4];
int i, n;
 
for (i = 0; i < 4; i++) {
lfsr[i] = startState[i];
}
for (n = 0; n < 530; n++) {
/*
* The trigger condition in the actual hardware test will be set
* to lfsr[0]==0x7119C0CD, which is reached at n==10. Therefore
* we print out n-10 instead of n to get identical index numbers.
*/
printf("%03d: ", n - 10);
for (i = 0; i < 4; i++) {
printf("%02X ", (lfsr[i] >> 24) & 0xFF);
printf("%02X ", (lfsr[i] >> 16) & 0xFF);
printf("%02X ", (lfsr[i] >> 8) & 0xFF);
printf("%02X ", (lfsr[i] >> 0) & 0xFF);
}
printf("\n");
for (i = 0; i < 4; i++) {
if ((lfsr[i] & 1) == 0) {
lfsr[i] = lfsr[i] >> 1;
} else {
lfsr[i] = (lfsr[i] >> 1) ^ taps;
}
}
}
return 0;
}
/tags/LogicProbe-1.1/tst/sim-c/Makefile
0,0 → 1,14
#
# Makefile to build a simulation of the test circuit
#
 
all: ref
 
ref: lfsr128
./lfsr128 >ref
 
lfsr128: lfsr128.c
gcc -Wall -o lfsr128 lfsr128.c
 
clean:
rm -f *~ lfsr128 ref
/tags/LogicProbe-1.1/tst/sim-v/top.cfg
0,0 → 1,20
*-5.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@28
top.clk
top.reset_in_n
top.lfsr.reset
@22
top.lfsr.lfsr0[31:0]
top.lfsr.lfsr1[31:0]
top.lfsr.lfsr2[31:0]
top.lfsr.lfsr3[31:0]
@28
top.lfsr.trigger
top.lfsr.sample
top.lfsr.lp.sampler.full
@22
top.lfsr.lp.rdaddr[12:0]
top.lfsr.lp.data[7:0]
@28
top.lfsr.lp.ready
top.lfsr.lp.write
/tags/LogicProbe-1.1/tst/sim-v/lfsr128.v
0,0 → 1,78
//
// lfsr128.v -- a linear feedback shift register with 128 bits
// (actually constructed from 4 instances of a 32-bit lfsr)
//
 
`include "../../src/fpga/LogicProbe.v"
`timescale 1ns/1ns
 
module lfsr128(clk, reset_in_n, s, rs232_txd);
input clk;
input reset_in_n;
output [3:0] s;
output rs232_txd;
 
wire reset;
reg [3:0] reset_counter;
 
reg [31:0] lfsr0;
reg [31:0] lfsr1;
reg [31:0] lfsr2;
reg [31:0] lfsr3;
 
wire trigger;
wire sample;
wire [127:0] log_data;
 
assign reset = (reset_counter == 4'hF) ? 0 : 1;
always @(posedge clk) begin
if (reset_in_n == 0) begin
reset_counter <= 4'h0;
end else begin
if (reset_counter != 4'hF) begin
reset_counter <= reset_counter + 1;
end
end
end
 
always @(posedge clk) begin
if (reset == 1) begin
lfsr0 <= 32'hC70337DB;
lfsr1 <= 32'h7F4D514F;
lfsr2 <= 32'h75377599;
lfsr3 <= 32'h7D5937A3;
end else begin
if (lfsr0[0] == 0) begin
lfsr0 <= lfsr0 >> 1;
end else begin
lfsr0 <= (lfsr0 >> 1) ^ 32'hD0000001;
end
if (lfsr1[0] == 0) begin
lfsr1 <= lfsr1 >> 1;
end else begin
lfsr1 <= (lfsr1 >> 1) ^ 32'hD0000001;
end
if (lfsr2[0] == 0) begin
lfsr2 <= lfsr2 >> 1;
end else begin
lfsr2 <= (lfsr2 >> 1) ^ 32'hD0000001;
end
if (lfsr3[0] == 0) begin
lfsr3 <= lfsr3 >> 1;
end else begin
lfsr3 <= (lfsr3 >> 1) ^ 32'hD0000001;
end
end
end
 
assign s[3] = lfsr0[27];
assign s[2] = lfsr1[13];
assign s[1] = lfsr2[23];
assign s[0] = lfsr3[11];
 
assign trigger = (lfsr0 == 32'h7119C0CD) ? 1 : 0;
assign sample = 1;
assign log_data = { lfsr0, lfsr1, lfsr2, lfsr3 };
LogicProbe lp(clk, reset, trigger, sample, log_data, rs232_txd);
 
endmodule
/tags/LogicProbe-1.1/tst/sim-v/top.v
0,0 → 1,30
//
// top.v -- top-level module to test lfsr128 with LogicProbe
//
 
`include "lfsr128.v"
`timescale 1ns/1ns
 
module top;
 
reg clk;
reg reset_in_n;
wire [3:0] s;
wire rs232_txd;
 
lfsr128 lfsr(clk, reset_in_n, s, rs232_txd);
 
initial begin
#0 $dumpfile("dump.vcd");
$dumpvars(0, top);
clk = 1;
reset_in_n = 0;
#145 reset_in_n = 1;
#20000 $finish;
end
 
always begin
#10 clk = ~clk;
end
 
endmodule
/tags/LogicProbe-1.1/tst/sim-v/Makefile
0,0 → 1,17
#
# Makefile to build a simulation of the test circuit
#
 
all: dump.vcd
 
show: dump.vcd
gtkwave dump.vcd top.cfg
 
dump.vcd: top
./top
 
top: top.v
iverilog -Wall -o top top.v
 
clean:
rm -f *~ top dump.vcd
/tags/LogicProbe-1.1/src/pc/receive.c
0,0 → 1,132
/*
* receive.c -- LogicProbe serial line receiver
*/
 
 
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#include <fcntl.h>
#include <unistd.h>
#include <termios.h>
 
 
static int debug = 0;
 
static FILE *diskFile = NULL;
static int sfd = 0;
static struct termios origOptions;
static struct termios currOptions;
 
 
void serialClose(void);
 
 
void error(char *fmt, ...) {
va_list ap;
 
va_start(ap, fmt);
printf("Error: ");
vprintf(fmt, ap);
printf("\n");
va_end(ap);
if (diskFile != NULL) {
fclose(diskFile);
diskFile = NULL;
}
if (sfd != 0) {
serialClose();
sfd = 0;
}
exit(1);
}
 
 
void serialOpen(char *serialPort) {
sfd = open(serialPort, O_RDWR | O_NOCTTY | O_NDELAY);
if (sfd == -1) {
error("cannot open serial port '%s'", serialPort);
}
tcgetattr(sfd, &origOptions);
currOptions = origOptions;
cfsetispeed(&currOptions, B38400);
cfsetospeed(&currOptions, B38400);
currOptions.c_cflag |= (CLOCAL | CREAD);
currOptions.c_cflag &= ~PARENB;
currOptions.c_cflag &= ~CSTOPB;
currOptions.c_cflag &= ~CSIZE;
currOptions.c_cflag |= CS8;
currOptions.c_cflag &= ~CRTSCTS;
currOptions.c_lflag &= ~(ICANON | ECHO | ECHONL | ISIG | IEXTEN);
currOptions.c_iflag &= ~(IGNBRK | BRKINT | IGNPAR | PARMRK);
currOptions.c_iflag &= ~(INPCK | ISTRIP | INLCR | IGNCR | ICRNL);
currOptions.c_iflag &= ~(IXON | IXOFF | IXANY);
currOptions.c_oflag &= ~(OPOST | ONLCR | OCRNL | ONOCR | ONLRET);
tcsetattr(sfd, TCSANOW, &currOptions);
}
 
 
void serialClose(void) {
tcsetattr(sfd, TCSANOW, &origOptions);
close(sfd);
}
 
 
int serialSnd(unsigned char b) {
int n;
 
n = write(sfd, &b, 1);
return n == 1;
}
 
 
int serialRcv(unsigned char *bp) {
int n;
 
n = read(sfd, bp, 1);
return n == 1;
}
 
 
int main(int argc, char *argv[]) {
unsigned char b;
int i, j;
 
if (argc != 3) {
printf("Usage: %s <serial_port> <data_file>\n", argv[0]);
exit(1);
}
serialOpen(argv[1]);
serialRcv(&b);
diskFile = fopen(argv[2], "wb");
if (diskFile == NULL) {
error("cannot open data file %s for write", argv[2]);
}
for (i = 0; i < 512; i++) {
if (debug) {
printf("%03d: ", i);
}
for (j = 0; j < 16; j++) {
while (!serialRcv(&b)) ;
if (fwrite(&b, 1, 1, diskFile) != 1) {
error("cannot write to data file %s", argv[2]);
}
if (debug) {
printf("%02X ", b);
}
}
if (debug) {
printf("\n");
}
}
if (diskFile != NULL) {
fclose(diskFile);
diskFile = NULL;
}
if (sfd != 0) {
serialClose();
sfd = 0;
}
return 0;
}
/tags/LogicProbe-1.1/src/pc/display.c
0,0 → 1,58
/*
* display.c -- LogicProbe data viewer
*/
 
 
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
 
 
static FILE *diskFile = NULL;
 
 
void error(char *fmt, ...) {
va_list ap;
 
va_start(ap, fmt);
printf("Error: ");
vprintf(fmt, ap);
printf("\n");
va_end(ap);
if (diskFile != NULL) {
fclose(diskFile);
diskFile = NULL;
}
exit(1);
}
 
 
int main(int argc, char *argv[]) {
unsigned char b;
int i, j;
 
if (argc != 2) {
printf("Usage: %s <data_file>\n", argv[0]);
exit(1);
}
diskFile = fopen(argv[1], "rb");
if (diskFile == NULL) {
error("cannot open data file %s for read", argv[1]);
}
for (i = 0; i < 512; i++) {
printf("%03d: ", i);
for (j = 0; j < 16; j++) {
if (fread(&b, 1, 1, diskFile) != 1) {
error("cannot read from data file %s", argv[1]);
}
printf("%02X ", b);
}
printf("\n");
}
if (diskFile != NULL) {
fclose(diskFile);
diskFile = NULL;
}
return 0;
}
/tags/LogicProbe-1.1/src/pc/Makefile
0,0 → 1,14
#
# Makefile to build the analyzer programs running on the PC side
#
 
all: receive display
 
receive: receive.c
gcc -Wall -o receive receive.c
 
display: display.c
gcc -Wall -o display display.c
 
clean:
rm -f *~ receive display
/tags/LogicProbe-1.1/src/fpga/LogicProbe.v
0,0 → 1,278
//
// LogicProbe.v -- on-chip logic probe with trace memory and read-out facility
//
 
`timescale 1ns/1ns
 
module LogicProbe(clock, reset, trigger, sample, channels, serial_out);
input clock;
input reset;
input trigger;
input sample;
input [127:0] channels;
output serial_out;
 
wire full;
reg [12:0] rdaddr;
wire [7:0] data;
reg write;
wire ready;
reg done;
reg state;
 
LogicProbe_sampler
sampler(clock, reset, trigger, sample, channels, full, rdaddr, data);
 
LogicProbe_xmtbuf
xmtbuf(clock, reset, write, ready, data, serial_out);
 
always @(posedge clock) begin
if (reset == 1) begin
rdaddr <= 13'd0;
write <= 0;
done <= 0;
state <= 0;
end else begin
if (full == 1 && done == 0) begin
if (state == 0) begin
if (ready == 1) begin
state <= 1;
write <= 1;
end
end else begin
if (rdaddr == 13'd8191) begin
done <= 1;
end
state <= 0;
write <= 0;
rdaddr <= rdaddr + 1;
end
end
end
end
 
endmodule
 
 
module LogicProbe_sampler(clock, reset, trigger, sample,
data_in, full, rdaddr, data_out);
input clock;
input reset;
input trigger;
input sample;
input [127:0] data_in;
output reg full;
input [12:0] rdaddr;
output reg [7:0] data_out;
 
reg [31:0] mem3[0:511];
reg [31:0] mem2[0:511];
reg [31:0] mem1[0:511];
reg [31:0] mem0[0:511];
 
reg [8:0] wraddr;
wire [8:0] addr;
reg [31:0] data3;
reg [31:0] data2;
reg [31:0] data1;
reg [31:0] data0;
 
reg [3:0] muxctrl;
reg triggered;
 
// addr for trace memory
// full == 0 means data capture
// full == 1 means data readout
assign addr = (full == 0) ? wraddr: rdaddr[12:4];
 
// pipeline register for output mux control: necessary
// because the trace memory has one clock delay too
always @(posedge clock) begin
muxctrl <= rdaddr[3:0];
end
 
// output multiplexer
always @(*) begin
case (muxctrl)
4'h0: data_out = data3[31:24];
4'h1: data_out = data3[23:16];
4'h2: data_out = data3[15: 8];
4'h3: data_out = data3[ 7: 0];
4'h4: data_out = data2[31:24];
4'h5: data_out = data2[23:16];
4'h6: data_out = data2[15: 8];
4'h7: data_out = data2[ 7: 0];
4'h8: data_out = data1[31:24];
4'h9: data_out = data1[23:16];
4'hA: data_out = data1[15: 8];
4'hB: data_out = data1[ 7: 0];
4'hC: data_out = data0[31:24];
4'hD: data_out = data0[23:16];
4'hE: data_out = data0[15: 8];
4'hF: data_out = data0[ 7: 0];
endcase
end
 
// trace memory
always @(posedge clock) begin
if (full == 0) begin
mem3[addr] <= data_in[127:96];
mem2[addr] <= data_in[ 95:64];
mem1[addr] <= data_in[ 63:32];
mem0[addr] <= data_in[ 31: 0];
end
data3 <= mem3[addr];
data2 <= mem2[addr];
data1 <= mem1[addr];
data0 <= mem0[addr];
end
 
// state machine which fills trace memory after trigger occurred
// it takes one sample per clock tick, but only when sample == 1
always @(posedge clock) begin
if (reset == 1) begin
wraddr <= 9'd0;
triggered <= 0;
full <= 0;
end else begin
if (triggered == 1) begin
// capture data, but only when sample == 1
if (sample == 1) begin
if (wraddr == 9'd511) begin
// last sample, memory is full
full <= 1;
end else begin
wraddr <= wraddr + 1;
end
end
end else begin
// wait for trigger, possibly capture first sample
if (trigger == 1) begin
triggered <= 1;
if (sample == 1) begin
wraddr <= wraddr + 1;
end
end
end
end
end
 
endmodule
 
 
module LogicProbe_xmtbuf(clock, reset, write, ready, data_in, serial_out);
input clock;
input reset;
input write;
output reg ready;
input [7:0] data_in;
output serial_out;
 
reg [1:0] state;
reg [7:0] data_hold;
reg load;
wire empty;
 
LogicProbe_xmt xmt(clock, reset, load, empty, data_hold, serial_out);
 
always @(posedge clock) begin
if (reset == 1) begin
state <= 2'b00;
ready <= 1;
load <= 0;
end else begin
case (state)
2'b00:
begin
if (write == 1) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 0;
load <= 1;
end
end
2'b01:
begin
state <= 2'b10;
ready <= 1;
load <= 0;
end
2'b10:
begin
if (empty == 1 && write == 0) begin
state <= 2'b00;
ready <= 1;
load <= 0;
end else
if (empty == 1 && write == 1) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 0;
load <= 1;
end else
if (empty == 0 && write == 1) begin
state <= 2'b11;
data_hold <= data_in;
ready <= 0;
load <= 0;
end
end
2'b11:
begin
if (empty == 1) begin
state <= 2'b01;
ready <= 0;
load <= 1;
end
end
endcase
end
end
 
endmodule
 
 
module LogicProbe_xmt(clock, reset, load, empty, parallel_in, serial_out);
input clock;
input reset;
input load;
output reg empty;
input [7:0] parallel_in;
output serial_out;
 
reg [3:0] state;
reg [8:0] shift;
reg [10:0] count;
 
assign serial_out = shift[0];
 
always @(posedge clock) begin
if (reset == 1) begin
state <= 4'h0;
shift <= 9'b111111111;
empty <= 1;
end else begin
if (state == 4'h0) begin
if (load == 1) begin
state <= 4'h1;
shift <= { parallel_in, 1'b0 };
count <= 1302;
empty <= 0;
end
end else
if (state == 4'hb) begin
state <= 4'h0;
empty <= 1;
end else begin
if (count == 0) begin
state <= state + 1;
shift[8:0] <= { 1'b1, shift[8:1] };
count <= 1302;
end else begin
count <= count - 1;
end
end
end
end
 
endmodule
/tags/LogicProbe-1.1/src/Makefile
0,0 → 1,10
#
# Makefile to build the analyzer programs running on the PC side
#
 
all:
$(MAKE) -C pc all
 
clean:
$(MAKE) -C pc clean
rm -f *~
/tags/LogicProbe-1.1/README
0,0 → 1,94
 
Welcome to LogicProbe!
 
 
1) What is it?
 
LogicProbe is a very simple logic analyzer which can be run on
an FPGA in parallel with the "device under test". The analyzer
has a width of 128 data channels, and is 512 samples deep. It
has a trigger (i.e., it starts catching the channels when this
signal got active once), and a sample enable (i.e., it does only
sample the channels when this line is 1). It uses the block RAM
on the FPGA to store the samples in real-time. When the sample
buffer is full, it begins to transmit the samples through a UART
(also included in the code) over the serial line to a PC where
the sample values are stored in a file. A simple listing program
allows to view the samples as hexadecimal values.
 
 
2) How do I use it?
 
You simply have to instanciate the module described below and setup
the constraints file so that "serial_out" is connected to the transmit
data line of an RS232 connector (via appropriate level shifters, of
course). The line speed is fixed at 38400 bps; this should certainly
be made a parameter of the design in the next version. Connect a PC
to the other end of the serial line and run the "receive" program,
which stores the transmitted samples into a file. You can then use
the "display" program to examine the samples as hexadecimal numbers.
 
Here is the interface to the analyzer module:
 
module LogicProbe(clock, reset, trigger, sample, channels, serial_out);
 
input clock; // master clock, also used for sampling
input reset; // master reset
input trigger; // start sampling when this line is 1
input sample; // enable sampling when this line is 1
input [127:0] channels; // the data to be sampled
output serial_out; // serial line to the PC
 
 
3) What do the directories and files in this package contain?
 
README this file
COPYING BSD license
Makefile Makefile for building the project
src source files
Makefile controls the build process on this level
fpga synthesizable Verilog (for running on the FPGA)
LogicProbe.v the logic analyzer proper
pc C source files (for running on the PC)
Makefile for building the analyzer programs
receive.c RS232 receiver program
display.c sample value viewer
tst test case, simulated as well as running on FPGAs
Makefile controls the build process on this level
sim-c simulation program in C
Makefile runs the simulation, generates reference data
lfsr128.c 128 bit LFSR
sim-v Verilog source to be simulated with Icarus Verilog
Makefile controls the simulation
top.v top-level simulation environment
top.cfg config file for GTK wave viewer
lfsr128.v same LFSR as in C, but now in Verilog
boards same LFSR as in sim-v, with LogicProbe attached,
configured for different FPGA evaluation boards
 
 
4) What else do I need?
 
If you want to run the tests, you need a Verilog simulator (I used
Icarus Verilog) and a VCD wave viewer (I used GTK-Wave). If you want
to use the analyzer in an FPGA, you must synthesize it (I used Xilinx
ISE 14.5). And you need a C compiler, preferably on a Linux system,
to receive and display the sample values.
 
 
5) Has the analyzer been used outside the test case?
 
Yes, it was instrumental in finding an error in my 32-bit CPU
which prohibited even the first instruction fetch from memory.
Simulation was of no help; the error didn't show up there. As
it turned out, I used initialization statements, which of course
couldn't be synthesized - so the start conditions inside the FPGA
differed from those of the simulation.
 
 
If you have any questions, write to
Hellwig.Geisse@mni.thm.de
 
Enjoy!
Hellwig
 
/tags/LogicProbe-1.1/COPYING
0,0 → 1,25
/*
* Copyright (c) 2007 - 2013 Hellwig Geisse
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/

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