OpenCores
URL https://opencores.org/ocsvn/lpffir/lpffir/trunk

Subversion Repositories lpffir

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /lpffir
    from Rev 10 to Rev 11
    ↔ Reverse comparison
  •

Rev 10 → Rev 11

/trunk/uvm/lpffir_uvm/dut/design.sv
0,0 → 1,38
module lpffir_axis (
input aclk_i,
input aresetn_i,
// AXI-Stream RX interface
input rx_tlast_i,
input rx_tvalid_i,
output logic rx_tready_o,
input [15:0] rx_tdata_i,
// AXI-Stream TX interface
output logic tx_tlast_o,
output reg tx_tvalid_o,
input tx_tready_i,
output logic [15:0] tx_tdata_o
);
 
wire lpffir_en;
assign lpffir_en = rx_tvalid_i && tx_tready_i;
 
// AXI-Stream interface
assign rx_tready_o = lpffir_en;
assign tx_tvalid_o = lpffir_en;
assign tx_tlast_o = rx_tlast_i;
// DEBUG
always @(posedge aclk_i or negedge aresetn_i)
if (aresetn_i)
$display("DUT: rx_tdata_i %0d, tx_tdata_o %0d", rx_tdata_i, tx_tdata_o);
 
// LPFFIR
lpffir_core lpffir_core(
.clk_i(aclk_i),
.rstn_i(aresetn_i),
.en_i(lpffir_en),
.x_i(rx_tdata_i),
.y_o(tx_tdata_o)
);
 
endmodule
/trunk/uvm/lpffir_uvm/dut/fa.sv
0,0 → 1,18
// Full Adder: adds three 1-bit numbers
module fa(
input a,
input b,
input ci, // Carry Input
 
output logic co, // Carry Output
output logic s // Sum
);
 
logic d,e,f;
 
xor(s,a,b,ci);
and(d,a,b);
and(e,b,ci);
and(f,a,ci);
or(co,d,e,f);
endmodule
/trunk/uvm/lpffir_uvm/dut/files.f
0,0 → 1,4
fa.sv
rca.sv
lpffir_core.sv
design.sv
/trunk/uvm/lpffir_uvm/dut/lpffir_core.sv
0,0 → 1,51
module lpffir_core (
input clk_i,
input rstn_i,
input en_i,
input [15:0] x_i,
output logic [15:0] y_o
);
 
reg [15:0] x1;
reg [15:0] x2;
reg [15:0] x3;
reg [15:0] x4;
reg [15:0] x5;
 
logic [15:0] h0;
logic [15:0] h1;
logic [15:0] h2;
logic [15:0] h01;
 
logic co0;
logic co1;
logic co2;
logic co3;
logic co4;
 
// Linear-phase FIR structure
rca rca_inst0 (.a(x_i),.b(x5),.ci(1'b0),.co(co0),.s(h0));
rca rca_inst1 (.a(x1),.b(x4),.ci(1'b0),.co(co1),.s(h1));
rca rca_inst2 (.a(x2),.b(x3),.ci(1'b0),.co(co2),.s(h2));
rca rca_inst3 (.a(h0),.b(h1),.ci(1'b0),.co(co3),.s(h01));
rca rca_inst4 (.a(h01),.b(h2),.ci(1'b0),.co(co4),.s(y_o));
 
always_ff @(posedge clk_i or posedge rstn_i)
if(!rstn_i)
begin
x1 <= 0;
x2 <= 0;
x3 <= 0;
x4 <= 0;
x5 <= 0;
end
else if (en_i)
begin
x1 <= x_i;
x2 <= x1;
x3 <= x2;
x4 <= x3;
x5 <= x4;
end
 
endmodule
/trunk/uvm/lpffir_uvm/dut/rca.sv
0,0 → 1,51
// Ripple Carry Adder: adds two 16-bit numbers
module rca(
input [15:0] a,
input [15:0] b,
input ci, // Carry Input
 
output logic co, // Carry Output
output logic [15:0] s // Sum
);
 
logic a0,a1,a2,a3,a4,a5,a6,a7;
logic a8,a9,a10,a11,a12,a13,a14,a15;
logic b0,b1,b2,b3,b4,b5,b6,b7;
logic b8,b9,b10,b11,b12,b13,b14,b15;
logic c0,c1,c2,c3,c4,c5,c6,c7;
logic c8,c9,c10,c11,c12,c13,c14;
logic s0,s1,s2,s3,s4,s5,s6,s7;
logic s8,s9,s10,s11,s12,s13,s14,s15;
 
assign a0 = a[0], a1 = a[1], a2 = a[2], a3 = a[3];
assign a4 = a[4], a5 = a[5], a6 = a[6], a7 = a[7];
assign a8 = a[8], a9 = a[9], a10 = a[10];
assign a11 = a[11], a12 = a[12], a13 = a[13];
assign a14 = a[14], a15 = a[15];
assign b0 = b[0], b1 = b[1], b2 = b[2], b3 = b[3];
assign b4 = b[4], b5 = b[5], b6 = b[6], b7 = b[7];
assign b8 = b[8], b9 = b[9], b10 = b[10], b11 = b[11];
assign b12 = b[12], b13 = b[13], b14 = b[14], b15 = b[15];
assign s[0] = s0, s[1] = s1, s[2] = s2, s[3] = s3;
assign s[4] = s4, s[5] = s5,s[6] = s6, s[7] = s7;
assign s[8] = s8, s[9] = s9, s[10] = s10, s[11] = s11;
assign s[12] = s12, s[13] = s13, s[14] = s14, s[15] = s15;
 
fa fa_inst0(.a(a0),.b(b0),.ci(ci),.co(c0),.s(s0));
fa fa_inst1(.a(a1),.b(b1),.ci(c0),.co(c1),.s(s1));
fa fa_inst2(.a(a2),.b(b2),.ci(c1),.co(c2),.s(s2));
fa fa_inst3(.a(a3),.b(b3),.ci(c2),.co(c3),.s(s3));
fa fa_inst4(.a(a4),.b(b4),.ci(c3),.co(c4),.s(s4));
fa fa_inst5(.a(a5),.b(b5),.ci(c4),.co(c5),.s(s5));
fa fa_inst6(.a(a6),.b(b6),.ci(c5),.co(c6),.s(s6));
fa fa_inst7(.a(a7),.b(b7),.ci(c6),.co(c7),.s(s7));
fa fa_inst8(.a(a8),.b(b8),.ci(c7),.co(c8),.s(s8));
fa fa_inst9(.a(a9),.b(b9),.ci(c8),.co(c9),.s(s9));
fa fa_inst10(.a(a10),.b(b10),.ci(c9),.co(c10),.s(s10));
fa fa_inst11(.a(a11),.b(b11),.ci(c10),.co(c11),.s(s11));
fa fa_inst12(.a(a12),.b(b12),.ci(c11),.co(c12),.s(s12));
fa fa_inst13(.a(a13),.b(b13),.ci(c12),.co(c13),.s(s13));
fa fa_inst14(.a(a14),.b(b14),.ci(c13),.co(c14),.s(s14));
fa fa_inst15(.a(a15),.b(b15),.ci(c14),.co(co),.s(s15));
 
endmodule
/trunk/uvm/lpffir_uvm/generated_tb/dut/design.sv
0,0 → 1,38
module lpffir_axis (
input aclk_i,
input aresetn_i,
// AXI-Stream RX interface
input rx_tlast_i,
input rx_tvalid_i,
output logic rx_tready_o,
input [15:0] rx_tdata_i,
// AXI-Stream TX interface
output logic tx_tlast_o,
output reg tx_tvalid_o,
input tx_tready_i,
output logic [15:0] tx_tdata_o
);
 
wire lpffir_en;
assign lpffir_en = rx_tvalid_i && tx_tready_i;
 
// AXI-Stream interface
assign rx_tready_o = lpffir_en;
assign tx_tvalid_o = lpffir_en;
assign tx_tlast_o = rx_tlast_i;
// DEBUG
always @(posedge aclk_i or negedge aresetn_i)
if (aresetn_i)
$display("DUT: rx_tdata_i %0d, tx_tdata_o %0d", rx_tdata_i, tx_tdata_o);
 
// LPFFIR
lpffir_core lpffir_core(
.clk_i(aclk_i),
.rstn_i(aresetn_i),
.en_i(lpffir_en),
.x_i(rx_tdata_i),
.y_o(tx_tdata_o)
);
 
endmodule
/trunk/uvm/lpffir_uvm/generated_tb/dut/fa.sv
0,0 → 1,18
// Full Adder: adds three 1-bit numbers
module fa(
input a,
input b,
input ci, // Carry Input
 
output logic co, // Carry Output
output logic s // Sum
);
 
logic d,e,f;
 
xor(s,a,b,ci);
and(d,a,b);
and(e,b,ci);
and(f,a,ci);
or(co,d,e,f);
endmodule
/trunk/uvm/lpffir_uvm/generated_tb/dut/files.f
0,0 → 1,4
fa.sv
rca.sv
lpffir_core.sv
design.sv
/trunk/uvm/lpffir_uvm/generated_tb/dut/lpffir_core.sv
0,0 → 1,51
module lpffir_core (
input clk_i,
input rstn_i,
input en_i,
input [15:0] x_i,
output logic [15:0] y_o
);
 
reg [15:0] x1;
reg [15:0] x2;
reg [15:0] x3;
reg [15:0] x4;
reg [15:0] x5;
 
logic [15:0] h0;
logic [15:0] h1;
logic [15:0] h2;
logic [15:0] h01;
 
logic co0;
logic co1;
logic co2;
logic co3;
logic co4;
 
// Linear-phase FIR structure
rca rca_inst0 (.a(x_i),.b(x5),.ci(1'b0),.co(co0),.s(h0));
rca rca_inst1 (.a(x1),.b(x4),.ci(1'b0),.co(co1),.s(h1));
rca rca_inst2 (.a(x2),.b(x3),.ci(1'b0),.co(co2),.s(h2));
rca rca_inst3 (.a(h0),.b(h1),.ci(1'b0),.co(co3),.s(h01));
rca rca_inst4 (.a(h01),.b(h2),.ci(1'b0),.co(co4),.s(y_o));
 
always_ff @(posedge clk_i or posedge rstn_i)
if(!rstn_i)
begin
x1 <= 0;
x2 <= 0;
x3 <= 0;
x4 <= 0;
x5 <= 0;
end
else if (en_i)
begin
x1 <= x_i;
x2 <= x1;
x3 <= x2;
x4 <= x3;
x5 <= x4;
end
 
endmodule
/trunk/uvm/lpffir_uvm/generated_tb/dut/rca.sv
0,0 → 1,51
// Ripple Carry Adder: adds two 16-bit numbers
module rca(
input [15:0] a,
input [15:0] b,
input ci, // Carry Input
 
output logic co, // Carry Output
output logic [15:0] s // Sum
);
 
logic a0,a1,a2,a3,a4,a5,a6,a7;
logic a8,a9,a10,a11,a12,a13,a14,a15;
logic b0,b1,b2,b3,b4,b5,b6,b7;
logic b8,b9,b10,b11,b12,b13,b14,b15;
logic c0,c1,c2,c3,c4,c5,c6,c7;
logic c8,c9,c10,c11,c12,c13,c14;
logic s0,s1,s2,s3,s4,s5,s6,s7;
logic s8,s9,s10,s11,s12,s13,s14,s15;
 
assign a0 = a[0], a1 = a[1], a2 = a[2], a3 = a[3];
assign a4 = a[4], a5 = a[5], a6 = a[6], a7 = a[7];
assign a8 = a[8], a9 = a[9], a10 = a[10];
assign a11 = a[11], a12 = a[12], a13 = a[13];
assign a14 = a[14], a15 = a[15];
assign b0 = b[0], b1 = b[1], b2 = b[2], b3 = b[3];
assign b4 = b[4], b5 = b[5], b6 = b[6], b7 = b[7];
assign b8 = b[8], b9 = b[9], b10 = b[10], b11 = b[11];
assign b12 = b[12], b13 = b[13], b14 = b[14], b15 = b[15];
assign s[0] = s0, s[1] = s1, s[2] = s2, s[3] = s3;
assign s[4] = s4, s[5] = s5,s[6] = s6, s[7] = s7;
assign s[8] = s8, s[9] = s9, s[10] = s10, s[11] = s11;
assign s[12] = s12, s[13] = s13, s[14] = s14, s[15] = s15;
 
fa fa_inst0(.a(a0),.b(b0),.ci(ci),.co(c0),.s(s0));
fa fa_inst1(.a(a1),.b(b1),.ci(c0),.co(c1),.s(s1));
fa fa_inst2(.a(a2),.b(b2),.ci(c1),.co(c2),.s(s2));
fa fa_inst3(.a(a3),.b(b3),.ci(c2),.co(c3),.s(s3));
fa fa_inst4(.a(a4),.b(b4),.ci(c3),.co(c4),.s(s4));
fa fa_inst5(.a(a5),.b(b5),.ci(c4),.co(c5),.s(s5));
fa fa_inst6(.a(a6),.b(b6),.ci(c5),.co(c6),.s(s6));
fa fa_inst7(.a(a7),.b(b7),.ci(c6),.co(c7),.s(s7));
fa fa_inst8(.a(a8),.b(b8),.ci(c7),.co(c8),.s(s8));
fa fa_inst9(.a(a9),.b(b9),.ci(c8),.co(c9),.s(s9));
fa fa_inst10(.a(a10),.b(b10),.ci(c9),.co(c10),.s(s10));
fa fa_inst11(.a(a11),.b(b11),.ci(c10),.co(c11),.s(s11));
fa fa_inst12(.a(a12),.b(b12),.ci(c11),.co(c12),.s(s12));
fa fa_inst13(.a(a13),.b(b13),.ci(c12),.co(c13),.s(s13));
fa fa_inst14(.a(a14),.b(b14),.ci(c13),.co(c14),.s(s14));
fa fa_inst15(.a(a15),.b(b15),.ci(c14),.co(co),.s(s15));
 
endmodule
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_agent.sv
0,0 → 1,111
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_agent.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Agent for data_input
//=============================================================================
 
`ifndef DATA_INPUT_AGENT_SV
`define DATA_INPUT_AGENT_SV
 
// You can insert code here by setting agent_inc_before_class in file data_input.tpl
 
class data_input_agent extends uvm_agent;
 
`uvm_component_utils(data_input_agent)
 
uvm_analysis_port #(input_tx) analysis_port;
 
data_input_config m_config;
data_input_sequencer_t m_sequencer;
data_input_driver m_driver;
data_input_monitor m_monitor;
 
local int m_is_active = -1;
 
extern function new(string name, uvm_component parent);
 
// You can remove build/connect_phase and get_is_active by setting agent_generate_methods_inside_class = no in file data_input.tpl
 
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
extern function uvm_active_passive_enum get_is_active();
 
// You can insert code here by setting agent_inc_inside_class in file data_input.tpl
 
endclass : data_input_agent
 
 
function data_input_agent::new(string name, uvm_component parent);
super.new(name, parent);
analysis_port = new("analysis_port", this);
endfunction : new
 
 
// You can remove build/connect_phase and get_is_active by setting agent_generate_methods_after_class = no in file data_input.tpl
 
function void data_input_agent::build_phase(uvm_phase phase);
 
// You can insert code here by setting agent_prepend_to_build_phase in file data_input.tpl
 
if (!uvm_config_db #(data_input_config)::get(this, "", "config", m_config))
`uvm_error(get_type_name(), "data_input config not found")
 
m_monitor = data_input_monitor ::type_id::create("m_monitor", this);
 
if (get_is_active() == UVM_ACTIVE)
begin
m_driver = data_input_driver ::type_id::create("m_driver", this);
m_sequencer = data_input_sequencer_t::type_id::create("m_sequencer", this);
end
 
// You can insert code here by setting agent_append_to_build_phase in file data_input.tpl
 
endfunction : build_phase
 
 
function void data_input_agent::connect_phase(uvm_phase phase);
if (m_config.vif == null)
`uvm_warning(get_type_name(), "data_input virtual interface is not set!")
 
m_monitor.vif = m_config.vif;
m_monitor.analysis_port.connect(analysis_port);
 
if (get_is_active() == UVM_ACTIVE)
begin
m_driver.seq_item_port.connect(m_sequencer.seq_item_export);
m_driver.vif = m_config.vif;
end
 
// You can insert code here by setting agent_append_to_connect_phase in file data_input.tpl
 
endfunction : connect_phase
 
 
function uvm_active_passive_enum data_input_agent::get_is_active();
if (m_is_active == -1)
begin
if (uvm_config_db#(uvm_bitstream_t)::get(this, "", "is_active", m_is_active))
begin
if (m_is_active != m_config.is_active)
`uvm_warning(get_type_name(), "is_active field in config_db conflicts with config object")
end
else
m_is_active = m_config.is_active;
end
return uvm_active_passive_enum'(m_is_active);
endfunction : get_is_active
 
 
// You can insert code here by setting agent_inc_after_class in file data_input.tpl
 
`endif // DATA_INPUT_AGENT_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_config.sv
0,0 → 1,52
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_config.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Configuration for agent data_input
//=============================================================================
 
`ifndef DATA_INPUT_CONFIG_SV
`define DATA_INPUT_CONFIG_SV
 
// You can insert code here by setting agent_config_inc_before_class in file data_input.tpl
 
class data_input_config extends uvm_object;
 
// Do not register config class with the factory
 
virtual data_input_if vif;
uvm_active_passive_enum is_active = UVM_ACTIVE;
bit coverage_enable;
bit checks_enable;
 
// You can insert variables here by setting config_var in file data_input.tpl
 
// You can remove new by setting agent_config_generate_methods_inside_class = no in file data_input.tpl
 
extern function new(string name = "");
 
// You can insert code here by setting agent_config_inc_inside_class in file data_input.tpl
 
endclass : data_input_config
 
 
// You can remove new by setting agent_config_generate_methods_after_class = no in file data_input.tpl
 
function data_input_config::new(string name = "");
super.new(name);
endfunction : new
 
 
// You can insert code here by setting agent_config_inc_after_class in file data_input.tpl
 
`endif // DATA_INPUT_CONFIG_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_coverage.sv
0,0 → 1,88
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_coverage.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Coverage for agent data_input
//=============================================================================
 
`ifndef DATA_INPUT_COVERAGE_SV
`define DATA_INPUT_COVERAGE_SV
 
// You can insert code here by setting agent_cover_inc_before_class in file data_input.tpl
 
class data_input_coverage extends uvm_subscriber #(input_tx);
 
`uvm_component_utils(data_input_coverage)
 
data_input_config m_config;
bit m_is_covered;
input_tx m_item;
// Start of inlined include file generated_tb/tb/include/data_input_cover_inc.sv
covergroup m_cov;
option.per_instance = 1;
cp_data: coverpoint m_item.data {
bins data_values[] = {[0:127]};
}
endgroup
// End of inlined include file
 
// You can remove new, write, and report_phase by setting agent_cover_generate_methods_inside_class = no in file data_input.tpl
 
extern function new(string name, uvm_component parent);
extern function void write(input input_tx t);
extern function void build_phase(uvm_phase phase);
extern function void report_phase(uvm_phase phase);
 
// You can insert code here by setting agent_cover_inc_inside_class in file data_input.tpl
 
endclass : data_input_coverage
 
 
// You can remove new, write, and report_phase by setting agent_cover_generate_methods_after_class = no in file data_input.tpl
 
function data_input_coverage::new(string name, uvm_component parent);
super.new(name, parent);
m_is_covered = 0;
m_cov = new();
endfunction : new
 
 
function void data_input_coverage::write(input input_tx t);
m_item = t;
if (m_config.coverage_enable)
begin
m_cov.sample();
// Check coverage - could use m_cov.option.goal instead of 100 if your simulator supports it
if (m_cov.get_inst_coverage() >= 100) m_is_covered = 1;
end
endfunction : write
 
 
function void data_input_coverage::build_phase(uvm_phase phase);
if (!uvm_config_db #(data_input_config)::get(this, "", "config", m_config))
`uvm_error(get_type_name(), "data_input config not found")
endfunction : build_phase
 
 
function void data_input_coverage::report_phase(uvm_phase phase);
if (m_config.coverage_enable)
`uvm_info(get_type_name(), $sformatf("Coverage score = %3.1f%%", m_cov.get_inst_coverage()), UVM_MEDIUM)
else
`uvm_info(get_type_name(), "Coverage disabled for this agent", UVM_MEDIUM)
endfunction : report_phase
 
 
// You can insert code here by setting agent_cover_inc_after_class in file data_input.tpl
 
`endif // DATA_INPUT_COVERAGE_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_driver.sv
0,0 → 1,67
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_driver.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Driver for data_input
//=============================================================================
 
`ifndef DATA_INPUT_DRIVER_SV
`define DATA_INPUT_DRIVER_SV
 
// You can insert code here by setting driver_inc_before_class in file data_input.tpl
 
class data_input_driver extends uvm_driver #(input_tx);
 
`uvm_component_utils(data_input_driver)
 
virtual data_input_if vif;
 
extern function new(string name, uvm_component parent);
 
// Start of inlined include file generated_tb/tb/include/data_input_driver_inc_inside_class.sv
extern task run_phase(uvm_phase phase);
// End of inlined include file
 
endclass : data_input_driver
 
 
function data_input_driver::new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
 
 
// Start of inlined include file generated_tb/tb/include/data_input_driver_inc_after_class.sv
task data_input_driver::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "run_phase", UVM_HIGH)
 
forever @(posedge vif.clk)
begin
seq_item_port.get_next_item(req);
phase.raise_objection(this);
wait (vif.reset == 1);
vif.data <= req.data;
vif.valid <= 1;
vif.last <= 0;
wait (vif.ready == 1);
fork
begin
repeat (10) @(posedge vif.clk);
phase.drop_objection(this);
end
join_none
seq_item_port.item_done();
end
endtask : run_phase
// End of inlined include file
 
`endif // DATA_INPUT_DRIVER_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_if.sv
0,0 → 1,40
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_if.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Signal interface for agent data_input
//=============================================================================
 
`ifndef DATA_INPUT_IF_SV
`define DATA_INPUT_IF_SV
 
interface data_input_if();
 
timeunit 1ns;
timeprecision 1ps;
 
import data_input_pkg::*;
 
logic last;
logic valid;
logic ready;
logic [15:0] data;
logic clk;
logic reset;
 
// You can insert properties and assertions here
 
// You can insert code here by setting if_inc_inside_interface in file data_input.tpl
 
endinterface : data_input_if
 
`endif // DATA_INPUT_IF_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_input_tx.sv
0,0 → 1,116
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_seq_item.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Sequence item for data_input_sequencer
//=============================================================================
 
`ifndef DATA_INPUT_SEQ_ITEM_SV
`define DATA_INPUT_SEQ_ITEM_SV
 
// You can insert code here by setting trans_inc_before_class in file data_input.tpl
 
class input_tx extends uvm_sequence_item;
 
`uvm_object_utils(input_tx)
 
// To include variables in copy, compare, print, record, pack, unpack, and compare2string, define them using trans_var in file data_input.tpl
// To exclude variables from compare, pack, and unpack methods, define them using trans_meta in file data_input.tpl
 
// Transaction variables
rand logic [15:0] data;
constraint c_data { 0 <= data; data < 128; }
 
 
extern function new(string name = "");
 
// You can remove do_copy/compare/print/record and convert2string method by setting trans_generate_methods_inside_class = no in file data_input.tpl
extern function void do_copy(uvm_object rhs);
extern function bit do_compare(uvm_object rhs, uvm_comparer comparer);
extern function void do_print(uvm_printer printer);
extern function void do_record(uvm_recorder recorder);
extern function void do_pack(uvm_packer packer);
extern function void do_unpack(uvm_packer packer);
extern function string convert2string();
 
// You can insert code here by setting trans_inc_inside_class in file data_input.tpl
 
endclass : input_tx
 
 
function input_tx::new(string name = "");
super.new(name);
endfunction : new
 
 
// You can remove do_copy/compare/print/record and convert2string method by setting trans_generate_methods_after_class = no in file data_input.tpl
 
function void input_tx::do_copy(uvm_object rhs);
input_tx rhs_;
if (!$cast(rhs_, rhs))
`uvm_fatal(get_type_name(), "Cast of rhs object failed")
super.do_copy(rhs);
data = rhs_.data;
endfunction : do_copy
 
 
function bit input_tx::do_compare(uvm_object rhs, uvm_comparer comparer);
bit result;
input_tx rhs_;
if (!$cast(rhs_, rhs))
`uvm_fatal(get_type_name(), "Cast of rhs object failed")
result = super.do_compare(rhs, comparer);
result &= comparer.compare_field("data", data, rhs_.data, $bits(data));
return result;
endfunction : do_compare
 
 
function void input_tx::do_print(uvm_printer printer);
if (printer.knobs.sprint == 0)
`uvm_info(get_type_name(), convert2string(), UVM_MEDIUM)
else
printer.m_string = convert2string();
endfunction : do_print
 
 
function void input_tx::do_record(uvm_recorder recorder);
super.do_record(recorder);
// Use the record macros to record the item fields:
`uvm_record_field("data", data)
endfunction : do_record
 
 
function void input_tx::do_pack(uvm_packer packer);
super.do_pack(packer);
`uvm_pack_int(data)
endfunction : do_pack
 
 
function void input_tx::do_unpack(uvm_packer packer);
super.do_unpack(packer);
`uvm_unpack_int(data)
endfunction : do_unpack
 
 
function string input_tx::convert2string();
string s;
$sformat(s, "%s\n", super.convert2string());
$sformat(s, {"%s\n",
"data = 'h%0h 'd%0d\n"},
get_full_name(), data, data);
return s;
endfunction : convert2string
 
 
// You can insert code here by setting trans_inc_after_class in file data_input.tpl
 
`endif // DATA_INPUT_SEQ_ITEM_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_monitor.sv
0,0 → 1,79
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_monitor.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Monitor for data_input
//=============================================================================
 
`ifndef DATA_INPUT_MONITOR_SV
`define DATA_INPUT_MONITOR_SV
 
// You can insert code here by setting monitor_inc_before_class in file data_input.tpl
 
class data_input_monitor extends uvm_monitor;
 
`uvm_component_utils(data_input_monitor)
 
virtual data_input_if vif;
 
uvm_analysis_port #(input_tx) analysis_port;
 
input_tx m_trans;
 
extern function new(string name, uvm_component parent);
 
// Methods build_phase, run_phase, and do_mon generated by setting monitor_inc in file data_input.tpl
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
extern task do_mon();
 
// You can insert code here by setting monitor_inc_inside_class in file data_input.tpl
 
endclass : data_input_monitor
 
 
function data_input_monitor::new(string name, uvm_component parent);
super.new(name, parent);
analysis_port = new("analysis_port", this);
endfunction : new
 
 
function void data_input_monitor::build_phase(uvm_phase phase);
endfunction : build_phase
 
 
task data_input_monitor::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "run_phase", UVM_HIGH)
 
m_trans = input_tx::type_id::create("m_trans");
do_mon();
endtask : run_phase
 
 
// Start of inlined include file generated_tb/tb/include/data_input_do_mon.sv
task data_input_monitor::do_mon;
forever @(posedge vif.clk)
begin
wait (vif.reset == 1);
if (vif.valid && vif.ready)
begin
m_trans.data = vif.data;
analysis_port.write(m_trans);
`uvm_info(get_type_name(), $sformatf("Input data = %0d", m_trans.data), UVM_HIGH)
end
end
endtask
// End of inlined include file
 
// You can insert code here by setting monitor_inc_after_class in file data_input.tpl
 
`endif // DATA_INPUT_MONITOR_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_pkg.sv
0,0 → 1,32
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_pkg.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Package for agent data_input
//=============================================================================
 
package data_input_pkg;
 
`include "uvm_macros.svh"
 
import uvm_pkg::*;
 
 
`include "data_input_input_tx.sv"
`include "data_input_config.sv"
`include "data_input_driver.sv"
`include "data_input_monitor.sv"
`include "data_input_sequencer.sv"
`include "data_input_coverage.sv"
`include "data_input_agent.sv"
`include "data_input_seq_lib.sv"
 
endpackage : data_input_pkg
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_seq_lib.sv
0,0 → 1,68
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_seq_lib.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Sequence for agent data_input
//=============================================================================
 
`ifndef DATA_INPUT_SEQ_LIB_SV
`define DATA_INPUT_SEQ_LIB_SV
 
class data_input_default_seq extends uvm_sequence #(input_tx);
 
`uvm_object_utils(data_input_default_seq)
 
extern function new(string name = "");
extern task body();
 
`ifndef UVM_POST_VERSION_1_1
// Functions to support UVM 1.2 objection API in UVM 1.1
extern function uvm_phase get_starting_phase();
extern function void set_starting_phase(uvm_phase phase);
`endif
 
endclass : data_input_default_seq
 
 
function data_input_default_seq::new(string name = "");
super.new(name);
endfunction : new
 
 
task data_input_default_seq::body();
`uvm_info(get_type_name(), "Default sequence starting", UVM_HIGH)
 
req = input_tx::type_id::create("req");
start_item(req);
if ( !req.randomize() )
`uvm_error(get_type_name(), "Failed to randomize transaction")
finish_item(req);
 
`uvm_info(get_type_name(), "Default sequence completed", UVM_HIGH)
endtask : body
 
 
`ifndef UVM_POST_VERSION_1_1
function uvm_phase data_input_default_seq::get_starting_phase();
return starting_phase;
endfunction: get_starting_phase
 
 
function void data_input_default_seq::set_starting_phase(uvm_phase phase);
starting_phase = phase;
endfunction: set_starting_phase
`endif
 
 
// You can insert code here by setting agent_seq_inc in file data_input.tpl
 
`endif // DATA_INPUT_SEQ_LIB_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_input/sv/data_input_sequencer.sv
0,0 → 1,24
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_input_sequencer.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Sequencer for data_input
//=============================================================================
 
`ifndef DATA_INPUT_SEQUENCER_SV
`define DATA_INPUT_SEQUENCER_SV
 
// Sequencer class is specialization of uvm_sequencer
typedef uvm_sequencer #(input_tx) data_input_sequencer_t;
 
 
`endif // DATA_INPUT_SEQUENCER_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_agent.sv
0,0 → 1,111
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_agent.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Agent for data_output
//=============================================================================
 
`ifndef DATA_OUTPUT_AGENT_SV
`define DATA_OUTPUT_AGENT_SV
 
// You can insert code here by setting agent_inc_before_class in file data_output.tpl
 
class data_output_agent extends uvm_agent;
 
`uvm_component_utils(data_output_agent)
 
uvm_analysis_port #(output_tx) analysis_port;
 
data_output_config m_config;
data_output_sequencer_t m_sequencer;
data_output_driver m_driver;
data_output_monitor m_monitor;
 
local int m_is_active = -1;
 
extern function new(string name, uvm_component parent);
 
// You can remove build/connect_phase and get_is_active by setting agent_generate_methods_inside_class = no in file data_output.tpl
 
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
extern function uvm_active_passive_enum get_is_active();
 
// You can insert code here by setting agent_inc_inside_class in file data_output.tpl
 
endclass : data_output_agent
 
 
function data_output_agent::new(string name, uvm_component parent);
super.new(name, parent);
analysis_port = new("analysis_port", this);
endfunction : new
 
 
// You can remove build/connect_phase and get_is_active by setting agent_generate_methods_after_class = no in file data_output.tpl
 
function void data_output_agent::build_phase(uvm_phase phase);
 
// You can insert code here by setting agent_prepend_to_build_phase in file data_output.tpl
 
if (!uvm_config_db #(data_output_config)::get(this, "", "config", m_config))
`uvm_error(get_type_name(), "data_output config not found")
 
m_monitor = data_output_monitor ::type_id::create("m_monitor", this);
 
if (get_is_active() == UVM_ACTIVE)
begin
m_driver = data_output_driver ::type_id::create("m_driver", this);
m_sequencer = data_output_sequencer_t::type_id::create("m_sequencer", this);
end
 
// You can insert code here by setting agent_append_to_build_phase in file data_output.tpl
 
endfunction : build_phase
 
 
function void data_output_agent::connect_phase(uvm_phase phase);
if (m_config.vif == null)
`uvm_warning(get_type_name(), "data_output virtual interface is not set!")
 
m_monitor.vif = m_config.vif;
m_monitor.analysis_port.connect(analysis_port);
 
if (get_is_active() == UVM_ACTIVE)
begin
m_driver.seq_item_port.connect(m_sequencer.seq_item_export);
m_driver.vif = m_config.vif;
end
 
// You can insert code here by setting agent_append_to_connect_phase in file data_output.tpl
 
endfunction : connect_phase
 
 
function uvm_active_passive_enum data_output_agent::get_is_active();
if (m_is_active == -1)
begin
if (uvm_config_db#(uvm_bitstream_t)::get(this, "", "is_active", m_is_active))
begin
if (m_is_active != m_config.is_active)
`uvm_warning(get_type_name(), "is_active field in config_db conflicts with config object")
end
else
m_is_active = m_config.is_active;
end
return uvm_active_passive_enum'(m_is_active);
endfunction : get_is_active
 
 
// You can insert code here by setting agent_inc_after_class in file data_output.tpl
 
`endif // DATA_OUTPUT_AGENT_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_config.sv
0,0 → 1,52
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_config.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Configuration for agent data_output
//=============================================================================
 
`ifndef DATA_OUTPUT_CONFIG_SV
`define DATA_OUTPUT_CONFIG_SV
 
// You can insert code here by setting agent_config_inc_before_class in file data_output.tpl
 
class data_output_config extends uvm_object;
 
// Do not register config class with the factory
 
virtual data_output_if vif;
uvm_active_passive_enum is_active = UVM_ACTIVE;
bit coverage_enable;
bit checks_enable;
 
// You can insert variables here by setting config_var in file data_output.tpl
 
// You can remove new by setting agent_config_generate_methods_inside_class = no in file data_output.tpl
 
extern function new(string name = "");
 
// You can insert code here by setting agent_config_inc_inside_class in file data_output.tpl
 
endclass : data_output_config
 
 
// You can remove new by setting agent_config_generate_methods_after_class = no in file data_output.tpl
 
function data_output_config::new(string name = "");
super.new(name);
endfunction : new
 
 
// You can insert code here by setting agent_config_inc_after_class in file data_output.tpl
 
`endif // DATA_OUTPUT_CONFIG_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_coverage.sv
0,0 → 1,90
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_coverage.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Coverage for agent data_output
//=============================================================================
 
`ifndef DATA_OUTPUT_COVERAGE_SV
`define DATA_OUTPUT_COVERAGE_SV
 
// You can insert code here by setting agent_cover_inc_before_class in file data_output.tpl
 
class data_output_coverage extends uvm_subscriber #(output_tx);
 
`uvm_component_utils(data_output_coverage)
 
data_output_config m_config;
bit m_is_covered;
output_tx m_item;
// You can replace covergroup m_cov by setting agent_cover_inc in file data_output.tpl
// or remove covergroup m_cov by setting agent_cover_generate_methods_inside_class = no in file data_output.tpl
 
covergroup m_cov;
option.per_instance = 1;
// You may insert additional coverpoints here ...
 
cp_data: coverpoint m_item.data;
// Add bins here if required
 
endgroup
 
// You can remove new, write, and report_phase by setting agent_cover_generate_methods_inside_class = no in file data_output.tpl
 
extern function new(string name, uvm_component parent);
extern function void write(input output_tx t);
extern function void build_phase(uvm_phase phase);
extern function void report_phase(uvm_phase phase);
 
// You can insert code here by setting agent_cover_inc_inside_class in file data_output.tpl
 
endclass : data_output_coverage
 
 
// You can remove new, write, and report_phase by setting agent_cover_generate_methods_after_class = no in file data_output.tpl
 
function data_output_coverage::new(string name, uvm_component parent);
super.new(name, parent);
m_is_covered = 0;
m_cov = new();
endfunction : new
 
 
function void data_output_coverage::write(input output_tx t);
m_item = t;
if (m_config.coverage_enable)
begin
m_cov.sample();
// Check coverage - could use m_cov.option.goal instead of 100 if your simulator supports it
if (m_cov.get_inst_coverage() >= 100) m_is_covered = 1;
end
endfunction : write
 
 
function void data_output_coverage::build_phase(uvm_phase phase);
if (!uvm_config_db #(data_output_config)::get(this, "", "config", m_config))
`uvm_error(get_type_name(), "data_output config not found")
endfunction : build_phase
 
 
function void data_output_coverage::report_phase(uvm_phase phase);
if (m_config.coverage_enable)
`uvm_info(get_type_name(), $sformatf("Coverage score = %3.1f%%", m_cov.get_inst_coverage()), UVM_MEDIUM)
else
`uvm_info(get_type_name(), "Coverage disabled for this agent", UVM_MEDIUM)
endfunction : report_phase
 
 
// You can insert code here by setting agent_cover_inc_after_class in file data_output.tpl
 
`endif // DATA_OUTPUT_COVERAGE_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_driver.sv
0,0 → 1,65
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_driver.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Driver for data_output
//=============================================================================
 
`ifndef DATA_OUTPUT_DRIVER_SV
`define DATA_OUTPUT_DRIVER_SV
 
// You can insert code here by setting driver_inc_before_class in file data_output.tpl
 
class data_output_driver extends uvm_driver #(output_tx);
 
`uvm_component_utils(data_output_driver)
 
virtual data_output_if vif;
 
extern function new(string name, uvm_component parent);
 
// Start of inlined include file generated_tb/tb/include/data_output_driver_inc_inside_class.sv
extern task run_phase(uvm_phase phase);
// End of inlined include file
 
endclass : data_output_driver
 
 
function data_output_driver::new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
 
 
// Start of inlined include file generated_tb/tb/include/data_output_driver_inc_after_class.sv
task data_output_driver::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "run_phase", UVM_HIGH)
 
forever @(posedge vif.clk)
begin
seq_item_port.get_next_item(req);
phase.raise_objection(this);
vif.ready <= 1;
wait (vif.reset == 1);
fork
begin
repeat (10) @(posedge vif.clk);
phase.drop_objection(this);
end
join_none
seq_item_port.item_done();
end
endtask : run_phase
// End of inlined include file
 
`endif // DATA_OUTPUT_DRIVER_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_if.sv
0,0 → 1,40
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_if.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Signal interface for agent data_output
//=============================================================================
 
`ifndef DATA_OUTPUT_IF_SV
`define DATA_OUTPUT_IF_SV
 
interface data_output_if();
 
timeunit 1ns;
timeprecision 1ps;
 
import data_output_pkg::*;
 
logic last;
logic valid;
logic ready;
logic [15:0] data;
logic clk;
logic reset;
 
// You can insert properties and assertions here
 
// You can insert code here by setting if_inc_inside_interface in file data_output.tpl
 
endinterface : data_output_if
 
`endif // DATA_OUTPUT_IF_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_monitor.sv
0,0 → 1,79
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_monitor.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Monitor for data_output
//=============================================================================
 
`ifndef DATA_OUTPUT_MONITOR_SV
`define DATA_OUTPUT_MONITOR_SV
 
// You can insert code here by setting monitor_inc_before_class in file data_output.tpl
 
class data_output_monitor extends uvm_monitor;
 
`uvm_component_utils(data_output_monitor)
 
virtual data_output_if vif;
 
uvm_analysis_port #(output_tx) analysis_port;
 
output_tx m_trans;
 
extern function new(string name, uvm_component parent);
 
// Methods build_phase, run_phase, and do_mon generated by setting monitor_inc in file data_output.tpl
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
extern task do_mon();
 
// You can insert code here by setting monitor_inc_inside_class in file data_output.tpl
 
endclass : data_output_monitor
 
 
function data_output_monitor::new(string name, uvm_component parent);
super.new(name, parent);
analysis_port = new("analysis_port", this);
endfunction : new
 
 
function void data_output_monitor::build_phase(uvm_phase phase);
endfunction : build_phase
 
 
task data_output_monitor::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "run_phase", UVM_HIGH)
 
m_trans = output_tx::type_id::create("m_trans");
do_mon();
endtask : run_phase
 
 
// Start of inlined include file generated_tb/tb/include/data_output_do_mon.sv
task data_output_monitor::do_mon;
forever @(posedge vif.clk)
begin
wait (vif.reset == 1);
if (vif.valid && vif.ready)
begin
m_trans.data = vif.data;
analysis_port.write(m_trans);
`uvm_info(get_type_name(), $sformatf("Output data = %0d",m_trans.data), UVM_HIGH)
end
end
endtask
// End of inlined include file
 
// You can insert code here by setting monitor_inc_after_class in file data_output.tpl
 
`endif // DATA_OUTPUT_MONITOR_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_output_tx.sv
0,0 → 1,115
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_seq_item.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Sequence item for data_output_sequencer
//=============================================================================
 
`ifndef DATA_OUTPUT_SEQ_ITEM_SV
`define DATA_OUTPUT_SEQ_ITEM_SV
 
// You can insert code here by setting trans_inc_before_class in file data_output.tpl
 
class output_tx extends uvm_sequence_item;
 
`uvm_object_utils(output_tx)
 
// To include variables in copy, compare, print, record, pack, unpack, and compare2string, define them using trans_var in file data_output.tpl
// To exclude variables from compare, pack, and unpack methods, define them using trans_meta in file data_output.tpl
 
// Transaction variables
rand logic [15:0] data;
 
 
extern function new(string name = "");
 
// You can remove do_copy/compare/print/record and convert2string method by setting trans_generate_methods_inside_class = no in file data_output.tpl
extern function void do_copy(uvm_object rhs);
extern function bit do_compare(uvm_object rhs, uvm_comparer comparer);
extern function void do_print(uvm_printer printer);
extern function void do_record(uvm_recorder recorder);
extern function void do_pack(uvm_packer packer);
extern function void do_unpack(uvm_packer packer);
extern function string convert2string();
 
// You can insert code here by setting trans_inc_inside_class in file data_output.tpl
 
endclass : output_tx
 
 
function output_tx::new(string name = "");
super.new(name);
endfunction : new
 
 
// You can remove do_copy/compare/print/record and convert2string method by setting trans_generate_methods_after_class = no in file data_output.tpl
 
function void output_tx::do_copy(uvm_object rhs);
output_tx rhs_;
if (!$cast(rhs_, rhs))
`uvm_fatal(get_type_name(), "Cast of rhs object failed")
super.do_copy(rhs);
data = rhs_.data;
endfunction : do_copy
 
 
function bit output_tx::do_compare(uvm_object rhs, uvm_comparer comparer);
bit result;
output_tx rhs_;
if (!$cast(rhs_, rhs))
`uvm_fatal(get_type_name(), "Cast of rhs object failed")
result = super.do_compare(rhs, comparer);
result &= comparer.compare_field("data", data, rhs_.data, $bits(data));
return result;
endfunction : do_compare
 
 
function void output_tx::do_print(uvm_printer printer);
if (printer.knobs.sprint == 0)
`uvm_info(get_type_name(), convert2string(), UVM_MEDIUM)
else
printer.m_string = convert2string();
endfunction : do_print
 
 
function void output_tx::do_record(uvm_recorder recorder);
super.do_record(recorder);
// Use the record macros to record the item fields:
`uvm_record_field("data", data)
endfunction : do_record
 
 
function void output_tx::do_pack(uvm_packer packer);
super.do_pack(packer);
`uvm_pack_int(data)
endfunction : do_pack
 
 
function void output_tx::do_unpack(uvm_packer packer);
super.do_unpack(packer);
`uvm_unpack_int(data)
endfunction : do_unpack
 
 
function string output_tx::convert2string();
string s;
$sformat(s, "%s\n", super.convert2string());
$sformat(s, {"%s\n",
"data = 'h%0h 'd%0d\n"},
get_full_name(), data, data);
return s;
endfunction : convert2string
 
 
// You can insert code here by setting trans_inc_after_class in file data_output.tpl
 
`endif // DATA_OUTPUT_SEQ_ITEM_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_pkg.sv
0,0 → 1,32
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_pkg.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Package for agent data_output
//=============================================================================
 
package data_output_pkg;
 
`include "uvm_macros.svh"
 
import uvm_pkg::*;
 
 
`include "data_output_output_tx.sv"
`include "data_output_config.sv"
`include "data_output_driver.sv"
`include "data_output_monitor.sv"
`include "data_output_sequencer.sv"
`include "data_output_coverage.sv"
`include "data_output_agent.sv"
`include "data_output_seq_lib.sv"
 
endpackage : data_output_pkg
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_seq_lib.sv
0,0 → 1,68
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_seq_lib.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Sequence for agent data_output
//=============================================================================
 
`ifndef DATA_OUTPUT_SEQ_LIB_SV
`define DATA_OUTPUT_SEQ_LIB_SV
 
class data_output_default_seq extends uvm_sequence #(output_tx);
 
`uvm_object_utils(data_output_default_seq)
 
extern function new(string name = "");
extern task body();
 
`ifndef UVM_POST_VERSION_1_1
// Functions to support UVM 1.2 objection API in UVM 1.1
extern function uvm_phase get_starting_phase();
extern function void set_starting_phase(uvm_phase phase);
`endif
 
endclass : data_output_default_seq
 
 
function data_output_default_seq::new(string name = "");
super.new(name);
endfunction : new
 
 
task data_output_default_seq::body();
`uvm_info(get_type_name(), "Default sequence starting", UVM_HIGH)
 
req = output_tx::type_id::create("req");
start_item(req);
if ( !req.randomize() )
`uvm_error(get_type_name(), "Failed to randomize transaction")
finish_item(req);
 
`uvm_info(get_type_name(), "Default sequence completed", UVM_HIGH)
endtask : body
 
 
`ifndef UVM_POST_VERSION_1_1
function uvm_phase data_output_default_seq::get_starting_phase();
return starting_phase;
endfunction: get_starting_phase
 
 
function void data_output_default_seq::set_starting_phase(uvm_phase phase);
starting_phase = phase;
endfunction: set_starting_phase
`endif
 
 
// You can insert code here by setting agent_seq_inc in file data_output.tpl
 
`endif // DATA_OUTPUT_SEQ_LIB_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/data_output/sv/data_output_sequencer.sv
0,0 → 1,24
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: data_output_sequencer.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Sequencer for data_output
//=============================================================================
 
`ifndef DATA_OUTPUT_SEQUENCER_SV
`define DATA_OUTPUT_SEQUENCER_SV
 
// Sequencer class is specialization of uvm_sequencer
typedef uvm_sequencer #(output_tx) data_output_sequencer_t;
 
 
`endif // DATA_OUTPUT_SEQUENCER_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/data_input_cover_inc.sv
0,0 → 1,7
covergroup m_cov;
option.per_instance = 1;
 
cp_data: coverpoint m_item.data {
bins data_values[] = {[0:127]};
}
endgroup
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/data_input_do_mon.sv
0,0 → 1,12
task data_input_monitor::do_mon;
forever @(posedge vif.clk)
begin
wait (vif.reset == 1);
if (vif.valid && vif.ready)
begin
m_trans.data = vif.data;
analysis_port.write(m_trans);
`uvm_info(get_type_name(), $sformatf("Input data = %0d", m_trans.data), UVM_HIGH)
end
end
endtask
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/data_input_driver_inc_after_class.sv
0,0 → 1,22
task data_input_driver::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "run_phase", UVM_HIGH)
 
forever @(posedge vif.clk)
begin
seq_item_port.get_next_item(req);
phase.raise_objection(this);
wait (vif.reset == 1);
vif.data <= req.data;
vif.valid <= 1;
vif.last <= 0;
wait (vif.ready == 1);
fork
begin
repeat (10) @(posedge vif.clk);
phase.drop_objection(this);
end
join_none
seq_item_port.item_done();
end
endtask : run_phase
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/data_input_driver_inc_inside_class.sv
0,0 → 1,22
extern task run_phase(uvm_phase phase);
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/data_output_do_mon.sv
0,0 → 1,12
task data_output_monitor::do_mon;
forever @(posedge vif.clk)
begin
wait (vif.reset == 1);
if (vif.valid && vif.ready)
begin
m_trans.data = vif.data;
analysis_port.write(m_trans);
`uvm_info(get_type_name(), $sformatf("Output data = %0d",m_trans.data), UVM_HIGH)
end
end
endtask
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/data_output_driver_inc_after_class.sv
0,0 → 1,20
task data_output_driver::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "run_phase", UVM_HIGH)
 
forever @(posedge vif.clk)
begin
seq_item_port.get_next_item(req);
phase.raise_objection(this);
vif.ready <= 1;
wait (vif.reset == 1);
fork
begin
repeat (10) @(posedge vif.clk);
phase.drop_objection(this);
end
join_none
seq_item_port.item_done();
end
endtask : run_phase
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/data_output_driver_inc_inside_class.sv
0,0 → 1,2
extern task run_phase(uvm_phase phase);
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/reference_inc_after_class.sv
0,0 → 1,22
function void reference::write_reference_0(input_tx t);
send(t);
endfunction
function void reference::send(input_tx t);
output_tx tx;
tx = output_tx::type_id::create("tx");
if (init_flag == 1)
begin
init_flag = 0;
foreach(tx_save[j])
tx_save[j] = 0;
end
if (save_pnt == 5)
save_pnt = 0;
else
save_pnt++;
tx_save[save_pnt] = t.data;
tx.data = tx_save[0] + tx_save[1] + tx_save[2] + tx_save[3] + tx_save[4] + tx_save[5];
analysis_port_0.write(tx);
`uvm_info(get_type_name(), $sformatf("Reference Model save_pnt = %0d, data = %0d",save_pnt, tx.data), UVM_HIGH)
endfunction
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/reference_inc_inside_class.sv
0,0 → 1,5
extern function void send(input_tx t);
 
int save_pnt = 5;
logic [15:0] tx_save [0:5];
int init_flag = 1;
/trunk/uvm/lpffir_uvm/generated_tb/tb/include/vcd_dump.sv
0,0 → 1,2
$dumpfile("dump.vcd");
$dumpvars;
/trunk/uvm/lpffir_uvm/generated_tb/tb/top/sv/port_converter.sv
0,0 → 1,40
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: port_converter.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Analysis port type converter class for use with Syosil scoreboard
//=============================================================================
 
`ifndef PORT_CONVERTER_SV
`define PORT_CONVERTER_SV
 
 
class port_converter #(type T = uvm_sequence_item) extends uvm_subscriber #(T);
`uvm_component_param_utils(port_converter#(T))
 
// For connecting analysis port of monitor to analysis export of Syosil scoreboard
 
uvm_analysis_port #(uvm_sequence_item) analysis_port;
 
function new(string name, uvm_component parent);
super.new(name, parent);
analysis_port = new("a_port", this);
endfunction
 
function void write(T t);
analysis_port.write(t);
endfunction
 
endclass
 
 
`endif // PORT_CONVERTER_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top/sv/reference.sv
0,0 → 1,77
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: reference.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Reference model for use with Syosil scoreboard
//=============================================================================
 
`ifndef REFERENCE_SV
`define REFERENCE_SV
 
// You can insert code here by setting ref_model_inc_before_class in file common.tpl
 
 
`uvm_analysis_imp_decl(_reference_0)
 
class reference extends uvm_component;
`uvm_component_utils(reference)
 
uvm_analysis_imp_reference_0 #(input_tx, reference) analysis_export_0; // m_data_input_agent
 
uvm_analysis_port #(uvm_sequence_item) analysis_port_0; // m_data_output_agent
 
extern function new(string name, uvm_component parent);
extern function void write_reference_0(input input_tx t);
 
// Start of inlined include file generated_tb/tb/include/reference_inc_inside_class.sv
extern function void send(input_tx t);
int save_pnt = 5;
logic [15:0] tx_save [0:5];
int init_flag = 1; // End of inlined include file
 
endclass
 
 
function reference::new(string name, uvm_component parent);
super.new(name, parent);
analysis_export_0 = new("analysis_export_0", this);
analysis_port_0 = new("analysis_port_0", this);
endfunction : new
 
 
// Start of inlined include file generated_tb/tb/include/reference_inc_after_class.sv
function void reference::write_reference_0(input_tx t);
send(t);
endfunction
function void reference::send(input_tx t);
output_tx tx;
tx = output_tx::type_id::create("tx");
if (init_flag == 1)
begin
init_flag = 0;
foreach(tx_save[j])
tx_save[j] = 0;
end
if (save_pnt == 5)
save_pnt = 0;
else
save_pnt++;
tx_save[save_pnt] = t.data;
tx.data = tx_save[0] + tx_save[1] + tx_save[2] + tx_save[3] + tx_save[4] + tx_save[5];
analysis_port_0.write(tx);
`uvm_info(get_type_name(), $sformatf("Reference Model save_pnt = %0d, data = %0d",save_pnt, tx.data), UVM_HIGH)
endfunction
// End of inlined include file
 
`endif // REFERENCE_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top/sv/top_config.sv
0,0 → 1,62
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: top_config.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Configuration for top
//=============================================================================
 
`ifndef TOP_CONFIG_SV
`define TOP_CONFIG_SV
 
// You can insert code here by setting top_env_config_inc_before_class in file common.tpl
 
class top_config extends uvm_object;
 
// Do not register config class with the factory
 
rand data_input_config m_data_input_config;
rand data_output_config m_data_output_config;
 
// You can insert variables here by setting config_var in file common.tpl
 
// You can remove new by setting top_env_config_generate_methods_inside_class = no in file common.tpl
 
extern function new(string name = "");
 
// You can insert code here by setting top_env_config_inc_inside_class in file common.tpl
 
endclass : top_config
 
 
// You can remove new by setting top_env_config_generate_methods_after_class = no in file common.tpl
 
function top_config::new(string name = "");
super.new(name);
 
m_data_input_config = new("m_data_input_config");
m_data_input_config.is_active = UVM_ACTIVE;
m_data_input_config.checks_enable = 1;
m_data_input_config.coverage_enable = 1;
 
m_data_output_config = new("m_data_output_config");
m_data_output_config.is_active = UVM_ACTIVE;
m_data_output_config.checks_enable = 1;
m_data_output_config.coverage_enable = 0;
 
// You can insert code here by setting top_env_config_append_to_new in file common.tpl
 
endfunction : new
 
 
// You can insert code here by setting top_env_config_inc_after_class in file common.tpl
 
`endif // TOP_CONFIG_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top/sv/top_env.sv
0,0 → 1,190
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: top_env.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Environment for top
//=============================================================================
 
`ifndef TOP_ENV_SV
`define TOP_ENV_SV
 
// You can insert code here by setting top_env_inc_before_class in file common.tpl
 
import pk_syoscb::*;
 
class top_env extends uvm_env;
 
`uvm_component_utils(top_env)
 
extern function new(string name, uvm_component parent);
 
// Reference model and Syosil scoreboard
typedef port_converter #(output_tx) converter_m_data_output_agent_t;
 
converter_m_data_output_agent_t m_converter_m_data_output_agent;
 
reference m_reference;
cl_syoscb m_reference_scoreboard;
cl_syoscb_cfg m_reference_config;
 
// Child agents
data_input_config m_data_input_config;
data_input_agent m_data_input_agent;
data_input_coverage m_data_input_coverage;
 
data_output_config m_data_output_config;
data_output_agent m_data_output_agent;
data_output_coverage m_data_output_coverage;
 
top_config m_config;
// You can remove build/connect/run_phase by setting top_env_generate_methods_inside_class = no in file common.tpl
 
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
extern function void end_of_elaboration_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
 
// You can insert code here by setting top_env_inc_inside_class in file common.tpl
 
endclass : top_env
 
 
function top_env::new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
 
 
// You can remove build/connect/run_phase by setting top_env_generate_methods_after_class = no in file common.tpl
 
function void top_env::build_phase(uvm_phase phase);
`uvm_info(get_type_name(), "In build_phase", UVM_HIGH)
 
// You can insert code here by setting top_env_prepend_to_build_phase in file common.tpl
 
if (!uvm_config_db #(top_config)::get(this, "", "config", m_config))
`uvm_error(get_type_name(), "Unable to get top_config")
 
m_data_input_config = m_config.m_data_input_config;
 
// You can insert code here by setting agent_copy_config_vars in file data_input.tpl
 
uvm_config_db #(data_input_config)::set(this, "m_data_input_agent", "config", m_data_input_config);
if (m_data_input_config.is_active == UVM_ACTIVE )
uvm_config_db #(data_input_config)::set(this, "m_data_input_agent.m_sequencer", "config", m_data_input_config);
uvm_config_db #(data_input_config)::set(this, "m_data_input_coverage", "config", m_data_input_config);
 
m_data_output_config = m_config.m_data_output_config;
 
// You can insert code here by setting agent_copy_config_vars in file data_output.tpl
 
uvm_config_db #(data_output_config)::set(this, "m_data_output_agent", "config", m_data_output_config);
if (m_data_output_config.is_active == UVM_ACTIVE )
uvm_config_db #(data_output_config)::set(this, "m_data_output_agent.m_sequencer", "config", m_data_output_config);
uvm_config_db #(data_output_config)::set(this, "m_data_output_coverage", "config", m_data_output_config);
 
// Default factory overrides for Syosil scoreboard
cl_syoscb_queue::type_id::set_type_override(cl_syoscb_queue_std::type_id::get());
 
begin
bit ok;
uvm_factory factory = uvm_factory::get();
 
if (factory.find_override_by_type(cl_syoscb_compare_base::type_id::get(), "*") == cl_syoscb_compare_base::type_id::get())
cl_syoscb_compare_base::type_id::set_inst_override(cl_syoscb_compare_iop::type_id::get(), "m_reference_scoreboard.*", this);
 
// Configuration object for Syosil scoreboard
m_reference_config = cl_syoscb_cfg::type_id::create("m_reference_config");
m_reference_config.set_queues( {"DUT", "REF"} );
ok = m_reference_config.set_primary_queue("DUT");
assert(ok);
ok = m_reference_config.set_producer("m_data_output_agent", {"DUT", "REF"} );
assert(ok);
 
uvm_config_db#(cl_syoscb_cfg)::set(this, "m_reference_scoreboard", "cfg", m_reference_config);
 
// Instantiate reference model and Syosil scoreboard
m_reference = reference ::type_id::create("m_reference", this);
m_converter_m_data_output_agent = converter_m_data_output_agent_t::type_id::create("m_converter_m_data_output_agent", this);
m_reference_scoreboard = cl_syoscb ::type_id::create("m_reference_scoreboard", this);
end
 
 
m_data_input_agent = data_input_agent ::type_id::create("m_data_input_agent", this);
m_data_input_coverage = data_input_coverage ::type_id::create("m_data_input_coverage", this);
 
m_data_output_agent = data_output_agent ::type_id::create("m_data_output_agent", this);
m_data_output_coverage = data_output_coverage::type_id::create("m_data_output_coverage", this);
 
// You can insert code here by setting top_env_append_to_build_phase in file common.tpl
 
endfunction : build_phase
 
 
function void top_env::connect_phase(uvm_phase phase);
`uvm_info(get_type_name(), "In connect_phase", UVM_HIGH)
 
m_data_input_agent.analysis_port.connect(m_data_input_coverage.analysis_export);
 
m_data_output_agent.analysis_port.connect(m_data_output_coverage.analysis_export);
 
begin
// Connect reference model and Syosil scoreboard
cl_syoscb_subscriber subscriber;
 
m_data_input_agent.analysis_port.connect(m_reference.analysis_export_0);
 
subscriber = m_reference_scoreboard.get_subscriber("REF", "m_data_output_agent");
m_reference.analysis_port_0.connect(subscriber.analysis_export);
 
subscriber = m_reference_scoreboard.get_subscriber("DUT", "m_data_output_agent");
m_data_output_agent.analysis_port.connect(m_converter_m_data_output_agent.analysis_export);
m_converter_m_data_output_agent.analysis_port.connect(subscriber.analysis_export);
end
 
// You can insert code here by setting top_env_append_to_connect_phase in file common.tpl
 
endfunction : connect_phase
 
 
// You can remove end_of_elaboration_phase by setting top_env_generate_end_of_elaboration = no in file common.tpl
 
function void top_env::end_of_elaboration_phase(uvm_phase phase);
uvm_factory factory = uvm_factory::get();
`uvm_info(get_type_name(), "Information printed from top_env::end_of_elaboration_phase method", UVM_MEDIUM)
`uvm_info(get_type_name(), $sformatf("Verbosity threshold is %d", get_report_verbosity_level()), UVM_MEDIUM)
uvm_top.print_topology();
factory.print();
endfunction : end_of_elaboration_phase
 
 
// You can remove run_phase by setting top_env_generate_run_phase = no in file common.tpl
 
task top_env::run_phase(uvm_phase phase);
top_default_seq vseq;
vseq = top_default_seq::type_id::create("vseq");
vseq.set_item_context(null, null);
if ( !vseq.randomize() )
`uvm_fatal(get_type_name(), "Failed to randomize virtual sequence")
vseq.m_data_input_agent = m_data_input_agent;
vseq.m_data_output_agent = m_data_output_agent;
vseq.set_starting_phase(phase);
vseq.start(null);
 
// You can insert code here by setting top_env_append_to_run_phase in file common.tpl
 
endtask : run_phase
 
 
// You can insert code here by setting top_env_inc_after_class in file common.tpl
 
`endif // TOP_ENV_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top/sv/top_pkg.sv
0,0 → 1,32
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: top_pkg.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Package for top
//=============================================================================
 
package top_pkg;
 
`include "uvm_macros.svh"
 
import uvm_pkg::*;
 
import data_input_pkg::*;
import data_output_pkg::*;
 
`include "top_config.sv"
`include "top_seq_lib.sv"
`include "port_converter.sv"
`include "reference.sv"
`include "top_env.sv"
 
endpackage : top_pkg
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top/sv/top_seq_lib.sv
0,0 → 1,111
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: top_seq_lib.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Sequence for top
//=============================================================================
 
`ifndef TOP_SEQ_LIB_SV
`define TOP_SEQ_LIB_SV
 
class top_default_seq extends uvm_sequence #(uvm_sequence_item);
 
`uvm_object_utils(top_default_seq)
 
data_input_agent m_data_input_agent;
data_output_agent m_data_output_agent;
 
// Number of times to repeat child sequences
int m_seq_count = 10;
 
extern function new(string name = "");
extern task body();
extern task pre_start();
extern task post_start();
 
`ifndef UVM_POST_VERSION_1_1
// Functions to support UVM 1.2 objection API in UVM 1.1
extern function uvm_phase get_starting_phase();
extern function void set_starting_phase(uvm_phase phase);
`endif
 
endclass : top_default_seq
 
 
function top_default_seq::new(string name = "");
super.new(name);
endfunction : new
 
 
task top_default_seq::body();
`uvm_info(get_type_name(), "Default sequence starting", UVM_HIGH)
 
 
repeat (m_seq_count)
begin
fork
if (m_data_input_agent.m_config.is_active == UVM_ACTIVE)
begin
data_input_default_seq seq;
seq = data_input_default_seq::type_id::create("seq");
seq.set_item_context(this, m_data_input_agent.m_sequencer);
if ( !seq.randomize() )
`uvm_error(get_type_name(), "Failed to randomize sequence")
seq.set_starting_phase( get_starting_phase() );
seq.start(m_data_input_agent.m_sequencer, this);
end
if (m_data_output_agent.m_config.is_active == UVM_ACTIVE)
begin
data_output_default_seq seq;
seq = data_output_default_seq::type_id::create("seq");
seq.set_item_context(this, m_data_output_agent.m_sequencer);
if ( !seq.randomize() )
`uvm_error(get_type_name(), "Failed to randomize sequence")
seq.set_starting_phase( get_starting_phase() );
seq.start(m_data_output_agent.m_sequencer, this);
end
join
end
 
`uvm_info(get_type_name(), "Default sequence completed", UVM_HIGH)
endtask : body
 
 
task top_default_seq::pre_start();
uvm_phase phase = get_starting_phase();
if (phase != null)
phase.raise_objection(this);
endtask: pre_start
 
 
task top_default_seq::post_start();
uvm_phase phase = get_starting_phase();
if (phase != null)
phase.drop_objection(this);
endtask: post_start
 
 
`ifndef UVM_POST_VERSION_1_1
function uvm_phase top_default_seq::get_starting_phase();
return starting_phase;
endfunction: get_starting_phase
 
 
function void top_default_seq::set_starting_phase(uvm_phase phase);
starting_phase = phase;
endfunction: set_starting_phase
`endif
 
 
// You can insert code here by setting top_seq_inc in file common.tpl
 
`endif // TOP_SEQ_LIB_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top_tb/sv/top_tb.sv
0,0 → 1,62
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: top_tb.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Testbench
//=============================================================================
 
module top_tb;
 
timeunit 1ns;
timeprecision 1ps;
 
`include "uvm_macros.svh"
 
import uvm_pkg::*;
 
import top_test_pkg::*;
import top_pkg::top_config;
 
// Configuration object for top-level environment
top_config top_env_config;
 
// Test harness
top_th th();
 
// You can insert code here by setting tb_inc_inside_module in file common.tpl
 
// You can remove the initial block below by setting tb_generate_run_test = no in file common.tpl
 
initial
begin
// Start of inlined include file generated_tb/tb/include/vcd_dump.sv
$dumpfile("dump.vcd");
$dumpvars;
// End of inlined include file
 
// Create and populate top-level configuration object
top_env_config = new("top_env_config");
if ( !top_env_config.randomize() )
`uvm_error("top_tb", "Failed to randomize top-level configuration object" )
 
top_env_config.m_data_input_config.vif = th.data_input_if_0;
top_env_config.m_data_output_config.vif = th.data_output_if_0;
 
uvm_config_db #(top_config)::set(null, "uvm_test_top", "config", top_env_config);
uvm_config_db #(top_config)::set(null, "uvm_test_top.m_env", "config", top_env_config);
 
// You can insert code here by setting tb_inc_before_run_test in file common.tpl
 
run_test();
end
 
endmodule
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top_tb/sv/top_th.sv
0,0 → 1,66
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: top_th.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Test Harness
//=============================================================================
 
module top_th;
 
timeunit 1ns;
timeprecision 1ps;
 
 
// You can remove clock and reset below by setting th_generate_clock_and_reset = no in file common.tpl
 
// Example clock and reset declarations
logic clock = 0;
logic reset;
 
// Example clock generator process
always #10 clock = ~clock;
 
// Example reset generator process
initial
begin
reset = 0; // Active low reset in this example
#75 reset = 1;
end
 
assign data_input_if_0.reset = reset;
assign data_output_if_0.reset = reset;
 
assign data_input_if_0.clk = clock;
assign data_output_if_0.clk = clock;
 
// You can insert code here by setting th_inc_inside_module in file common.tpl
 
// Pin-level interfaces connected to DUT
// You can remove interface instances by setting generate_interface_instance = no in the interface template file
 
data_input_if data_input_if_0 ();
data_output_if data_output_if_0 ();
 
lpffir_axis uut (
.rx_tlast_i (data_input_if_0.last),
.rx_tvalid_i(data_input_if_0.valid),
.rx_tready_o(data_input_if_0.ready),
.rx_tdata_i (data_input_if_0.data),
.tx_tlast_o (data_output_if_0.last),
.tx_tvalid_o(data_output_if_0.valid),
.tx_tready_i(data_output_if_0.ready),
.tx_tdata_o (data_output_if_0.data),
.aclk_i (clock),
.aresetn_i (reset)
);
 
endmodule
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top_test/sv/top_test.sv
0,0 → 1,63
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: top_test.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Test class for top (included in package top_test_pkg)
//=============================================================================
 
`ifndef TOP_TEST_SV
`define TOP_TEST_SV
 
// You can insert code here by setting test_inc_before_class in file common.tpl
 
class top_test extends uvm_test;
 
`uvm_component_utils(top_test)
 
top_env m_env;
 
extern function new(string name, uvm_component parent);
 
// You can remove build_phase method by setting test_generate_methods_inside_class = no in file common.tpl
 
extern function void build_phase(uvm_phase phase);
 
// You can insert code here by setting test_inc_inside_class in file common.tpl
 
endclass : top_test
 
 
function top_test::new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
 
 
// You can remove build_phase method by setting test_generate_methods_after_class = no in file common.tpl
 
function void top_test::build_phase(uvm_phase phase);
 
// You can insert code here by setting test_prepend_to_build_phase in file common.tpl
 
// You could modify any test-specific configuration object variables here
 
 
 
m_env = top_env::type_id::create("m_env", this);
 
// You can insert code here by setting test_append_to_build_phase in file common.tpl
 
endfunction : build_phase
 
 
// You can insert code here by setting test_inc_after_class in file common.tpl
 
`endif // TOP_TEST_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/tb/top_test/sv/top_test_pkg.sv
0,0 → 1,34
// You can insert code here by setting file_header_inc in file common.tpl
 
//=============================================================================
// Project : generated_tb
//
// File Name: top_test_pkg.sv
//
//
// Version: 1.0
//
// Code created by Easier UVM Code Generator version 2016-04-18-EP on Sat Apr 27 13:59:59 2019
//=============================================================================
// Description: Test package for top
//=============================================================================
 
`ifndef TOP_TEST_PKG_SV
`define TOP_TEST_PKG_SV
 
package top_test_pkg;
 
`include "uvm_macros.svh"
 
import uvm_pkg::*;
 
import data_input_pkg::*;
import data_output_pkg::*;
import top_pkg::*;
 
`include "top_test.sv"
 
endpackage : top_test_pkg
 
`endif // TOP_TEST_PKG_SV
 
/trunk/uvm/lpffir_uvm/generated_tb/sim.log
0,0 → 1,1027
[2019-04-27 10:02:44 EDT] EU_INC_PATH=`perl /playground_lib/easier_uvm_gen/easier_uvm_gen.pl -x inc_path` ; EU_DUT_SOURCE_PATH=`perl /playground_lib/easier_uvm_gen/easier_uvm_gen.pl -x dut_source_path` ; EU_PROJECT=`perl /playground_lib/easier_uvm_gen/easier_uvm_gen.pl -x project` ; EU_REGMODEL_FILE=`perl /playground_lib/easier_uvm_gen/easier_uvm_gen.pl -x regmodel_file` ; mkdir $EU_INC_PATH ; mv data_input_cover_inc.sv data_input_do_mon.sv data_input_driver_inc_after_class.sv data_input_driver_inc_inside_class.sv data_output_do_mon.sv reference_inc_after_class.sv reference_inc_inside_class.sv vcd_dump.sv data_output_driver_inc_inside_class.sv data_output_driver_inc_after_class.sv $EU_INC_PATH ; mkdir $EU_DUT_SOURCE_PATH ; mv design.sv lpffir_core.sv rca.sv fa.sv files.f $EU_DUT_SOURCE_PATH ; if [ -f $EU_INC_PATH/$EU_REGMODEL_FILE ]; then cp $EU_INC_PATH/$EU_REGMODEL_FILE . ; fi; perl /playground_lib/easier_uvm_gen/easier_uvm_gen.pl -s ../../playground_lib/uvm_syoscb/src -c data_input.tpl data_output.tpl ; cd $EU_PROJECT && cd sim ; chmod 755 compile_vcs.sh ; source ./compile_vcs.sh ; cd /home/runner
Easier UVM Code Generator version 2016-04-18-EP
Copying dut files to generated_tb/dut
Copying include files to generated_tb/tb/include
Generating testbench in generated_tb/tb
Generating simulator scripts in generated_tb/sim
Generated hierarchy of envs and agents:
m_data_input_agent
m_data_output_agent
 
Warning-[LNX_OS_VERUN] Unsupported Linux version
Linux version 'CentOS Linux release 7.1.1503 (Core) ' is not supported on
'x86_64' officially, assuming linux compatibility by default. Set
VCS_ARCH_OVERRIDE to linux or suse32 to override.
Please refer to release notes for information on supported platforms.
 
 
Warning-[LINX_KRNL] Unsupported Linux kernel
Linux kernel '3.13.0-71-generic' is not supported.
Supported versions are 2.4* or 2.6*.
 
Chronologic VCS (TM)
Version J-2014.12-SP1-1 -- Sat Apr 27 14:02:46 2019
Copyright (c) 1991-2014 by Synopsys Inc.
ALL RIGHTS RESERVED
 
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
 
Warning : License for product VCSCompiler_Net(723) will expire within 4 days, on: 30-apr-2019.
 
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
Parsing design file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'
Parsing included file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_version_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_global_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_message_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_phase_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_object_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_printer_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_tlm_defines.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm_imps.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_tlm_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_sequence_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_callback_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_reg_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/macros/uvm_deprecated_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dpi/uvm_dpi.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dpi/uvm_hdl.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/dpi/uvm_dpi.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dpi/uvm_svcmd_dpi.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/dpi/uvm_dpi.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dpi/uvm_regex.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/dpi/uvm_dpi.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_coreservice.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_version.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_object_globals.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_misc.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_object.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_pool.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_queue.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_factory.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_registry.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_spell_chkr.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_resource.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_resource_specializations.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_resource_db.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_config_db.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_printer.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_comparer.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_packer.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_links.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_tr_database.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_tr_stream.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_recorder.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_event_callback.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_event.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_barrier.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_callback.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_callback.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_report_message.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_report_catcher.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_report_server.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_report_handler.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_report_object.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_transaction.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_phase.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_domain.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_bottomup_phase.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_topdown_phase.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_task_phase.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_common_phases.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_runtime_phases.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_component.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_root.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_component.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_objection.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_heartbeat.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_globals.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_cmdline_processor.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_traversal.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/base/uvm_base.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_dap.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_set_get_dap_base.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_dap.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_simple_lock_dap.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_dap.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_get_to_lock_dap.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_dap.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_set_before_get_dap.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/dap/uvm_dap.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm_ifs.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_sqr_ifs.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/base/uvm_port_base.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm_imps.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_imps.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_ports.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_exports.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_analysis_port.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm_fifo_base.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm_fifos.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm_req_rsp.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_sqr_connections.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm1/uvm_tlm.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_pair.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_policies.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_in_order_comparator.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_algorithmic_comparator.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_random_stimulus.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_subscriber.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_monitor.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_driver.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_push_driver.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_scoreboard.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_agent.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_env.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_test.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/comps/uvm_comps.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequence_item.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequencer_base.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequencer_analysis_fifo.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequencer_param_base.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequencer.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_push_sequencer.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequence_base.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequence.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequence_library.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_sequence_builtin.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/seq/uvm_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_defines.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_time.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_generic_payload.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_ifs.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_imps.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_ports.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_exports.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_sockets_base.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2_sockets.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/tlm2/uvm_tlm2.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_item.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_adapter.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_predictor.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_sequence.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_cbs.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_backdoor.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_field.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_vreg_field.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_indirect.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_fifo.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_file.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_mem_mam.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_vreg.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_mem.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_map.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_block.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/sequences/uvm_reg_hw_reset_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/sequences/uvm_reg_bit_bash_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/sequences/uvm_mem_walk_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/sequences/uvm_mem_access_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/sequences/uvm_reg_access_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/sequences/uvm_reg_mem_shared_access_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/sequences/uvm_reg_mem_built_in_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Parsing included file '/apps/vcsmx/etc/uvm-1.2/reg/snps_uvm_reg_bank.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/reg/uvm_reg_model.svh'.
Back to file '/apps/vcsmx/etc/uvm-1.2/uvm_pkg.sv'.
Parsing design file '../dut/fa.sv'
Parsing design file '../dut/rca.sv'
Parsing design file '../dut/lpffir_core.sv'
Parsing design file '../dut/design.sv'
Parsing design file '../tb/data_input/sv/data_input_pkg.sv'
Parsing included file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing included file '../tb/data_input/sv/data_input_input_tx.sv'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing included file '../tb/data_input/sv/data_input_config.sv'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing included file '../tb/data_input/sv/data_input_driver.sv'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing included file '../tb/data_input/sv/data_input_monitor.sv'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing included file '../tb/data_input/sv/data_input_sequencer.sv'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing included file '../tb/data_input/sv/data_input_coverage.sv'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing included file '../tb/data_input/sv/data_input_agent.sv'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing included file '../tb/data_input/sv/data_input_seq_lib.sv'.
Back to file '../tb/data_input/sv/data_input_pkg.sv'.
Parsing design file '../tb/data_input/sv/data_input_if.sv'
Parsing design file '../tb/data_output/sv/data_output_pkg.sv'
Parsing included file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing included file '../tb/data_output/sv/data_output_output_tx.sv'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing included file '../tb/data_output/sv/data_output_config.sv'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing included file '../tb/data_output/sv/data_output_driver.sv'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing included file '../tb/data_output/sv/data_output_monitor.sv'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing included file '../tb/data_output/sv/data_output_sequencer.sv'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing included file '../tb/data_output/sv/data_output_coverage.sv'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing included file '../tb/data_output/sv/data_output_agent.sv'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing included file '../tb/data_output/sv/data_output_seq_lib.sv'.
Back to file '../tb/data_output/sv/data_output_pkg.sv'.
Parsing design file '../tb/data_output/sv/data_output_if.sv'
Parsing design file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'
Parsing included file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_cfg_pl.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_cfg.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_item.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_queue_iterator_base.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_queue_iterator_std.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_queue.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_queue_std.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_compare_base.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_compare.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_compare_ooo.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_compare_io.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_compare_iop.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_report_catcher.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb_subscriber.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing included file '../../../../playground_lib/uvm_syoscb/src/cl_syoscb.svh'.
Back to file '../../../../playground_lib/uvm_syoscb/src/pk_syoscb.sv'.
Parsing design file '../tb/top/sv/top_pkg.sv'
Parsing included file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Back to file '../tb/top/sv/top_pkg.sv'.
Parsing included file '../tb/top/sv/top_config.sv'.
Back to file '../tb/top/sv/top_pkg.sv'.
Parsing included file '../tb/top/sv/top_seq_lib.sv'.
Back to file '../tb/top/sv/top_pkg.sv'.
Parsing included file '../tb/top/sv/port_converter.sv'.
Back to file '../tb/top/sv/top_pkg.sv'.
Parsing included file '../tb/top/sv/reference.sv'.
Back to file '../tb/top/sv/top_pkg.sv'.
Parsing included file '../tb/top/sv/top_env.sv'.
Back to file '../tb/top/sv/top_pkg.sv'.
Parsing design file '../tb/top_test/sv/top_test_pkg.sv'
Parsing included file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Back to file '../tb/top_test/sv/top_test_pkg.sv'.
Parsing included file '../tb/top_test/sv/top_test.sv'.
Back to file '../tb/top_test/sv/top_test_pkg.sv'.
Parsing design file '../tb/top_tb/sv/top_th.sv'
Parsing design file '../tb/top_tb/sv/top_tb.sv'
Parsing included file '/apps/vcsmx/etc/uvm-1.2/uvm_macros.svh'.
Back to file '../tb/top_tb/sv/top_tb.sv'.
Top Level Modules:
top_tb
TimeScale is 1 ns / 1 ps
Warning : License for product VT_Testbench(772) will expire within 4 days, on: 30-apr-2019.
 
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
Starting vcs inline pass...
15 modules and 0 UDP read.
recompiling package vcs_paramclassrepository
recompiling package _vcs_DPI_package
recompiling package uvm_pkg
recompiling module fa
recompiling module rca
recompiling module lpffir_axis
recompiling package data_input_pkg
recompiling module data_input_if
recompiling package data_output_pkg
recompiling module data_output_if
recompiling package pk_syoscb
recompiling package top_pkg
recompiling package top_test_pkg
recompiling module top_tb
All of 15 modules done
Warning : License for product VCSCompiler_Net(723) will expire within 4 days, on: 30-apr-2019.
 
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
rm -f _csrc*.so linux_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
g++ -w -pipe -m32 -DVCSMX -O -I/apps/vcsmx/include -c /apps/vcsmx/etc/uvm-1.2/dpi/uvm_dpi.cc
ld -m elf_i386 -shared -o .//../simv.daidir//_csrc0.so amcQwB.o
rm -f _csrc0.so
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv -m32 -m32 -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir /apps/vcsmx/linux/lib/vpdlogstub.o uvm_dpi.o _729_archive_1.so _csrc0.so SIM_l.o _csrc0.so rmapats_mop.o rmapats.o rmar.o rmar_llvm_0_1.o rmar_llvm_0_0.o /apps/vcsmx/linux/lib/libzerosoft_rt_stubs.so /apps/vcsmx/linux/lib/libvirsim.so /apps/vcsmx/linux/lib/liberrorinf.so /apps/vcsmx/linux/lib/libsnpsmalloc.so /apps/vcsmx/linux/lib/libvcsnew.so /apps/vcsmx/linux/lib/libuclinative.so -Wl,-whole-archive /apps/vcsmx/linux/lib/libvcsucli.so -Wl,-no-whole-archive ./../simv.daidir/vc_hdrs.o /apps/vcsmx/linux/lib/vcs_save_restore_new.o /apps/vcsmx/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -ldl
../simv up to date
Warning : License for product VCSRuntime_Net(725) will expire within 4 days, on: 30-apr-2019.
 
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version J-2014.12-SP1-1; Runtime version J-2014.12-SP1-1; Apr 27 14:03 2019
Warning : License for product VT_TestbenchRuntime(802) will expire within 4 days, on: 30-apr-2019.
 
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 0).
UVM_INFO /apps/vcsmx/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------
 
*********** IMPORTANT RELEASE NOTES ************
 
You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See http://www.eda.org/svdb/view.php?id=3313 for more details.
 
You are using a version of the UVM library that has been compiled
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
See http://www.eda.org/svdb/view.php?id=3770 for more details.
 
(Specify +UVM_NO_RELNOTES to turn off this notice)
 
UVM_INFO @ 0: reporter [RNTST] Running test top_test...
UVM_INFO ../tb/top/sv/top_env.sv(69) @ 0: uvm_test_top.m_env [top_env] In build_phase
 
Note-[FCICIO] Instance coverage is ON
/home/runner/generated_tb/sim/../tb/data_input/sv/data_input_coverage.sv, 30
data_input_pkg, "data_input_pkg::data_input_coverage::m_cov"
Instance coverage is set (option.per_instance = 1) for covergroup
'data_input_pkg::data_input_coverage::m_cov'
 
Covergroup Instance: top_tb.me.obj.m_cov
Design hierarchy: data_input_pkg
 
 
Note-[FCICIO] Instance coverage is ON
/home/runner/generated_tb/sim/../tb/data_output/sv/data_output_coverage.sv, 32
data_output_pkg, "data_output_pkg::data_output_coverage::m_cov"
Instance coverage is set (option.per_instance = 1) for covergroup
'data_output_pkg::data_output_coverage::m_cov'
 
Covergroup Instance: top_tb.me.obj.m_cov
Design hierarchy: data_output_pkg
 
UVM_INFO ../tb/top/sv/top_env.sv(133) @ 0: uvm_test_top.m_env [top_env] In connect_phase
UVM_INFO ../tb/top/sv/top_env.sv(162) @ 0: uvm_test_top.m_env [top_env] Information printed from top_env::end_of_elaboration_phase method
UVM_INFO ../tb/top/sv/top_env.sv(163) @ 0: uvm_test_top.m_env [top_env] Verbosity threshold is 300
UVM_INFO /apps/vcsmx/etc/uvm-1.2/base/uvm_root.svh(589) @ 0: reporter [UVMTOP] UVM testbench topology:
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
uvm_test_top top_test - @347
m_env top_env - @360
m_converter_m_data_output_agent uvm_component - @417
a_port uvm_analysis_port - @436
analysis_imp uvm_analysis_imp - @426
m_data_input_agent data_input_agent - @455
analysis_port uvm_analysis_port - @464
m_driver data_input_driver - @552
rsp_port uvm_analysis_port - @571
seq_item_port uvm_seq_item_pull_port - @561
m_monitor data_input_monitor - @532
analysis_port uvm_analysis_port - @541
m_sequencer uvm_sequencer - @581
rsp_export uvm_analysis_export - @590
seq_item_export uvm_seq_item_pull_imp - @708
arbitration_queue array 0 -
lock_queue array 0 -
num_last_reqs integral 32 'd1
num_last_rsps integral 32 'd1
m_data_input_coverage data_input_coverage - @474
analysis_imp uvm_analysis_imp - @483
m_data_output_agent data_output_agent - @493
analysis_port uvm_analysis_port - @502
m_driver data_output_driver - @745
rsp_port uvm_analysis_port - @764
seq_item_port uvm_seq_item_pull_port - @754
m_monitor data_output_monitor - @725
analysis_port uvm_analysis_port - @734
m_sequencer uvm_sequencer - @774
rsp_export uvm_analysis_export - @783
seq_item_export uvm_seq_item_pull_imp - @901
arbitration_queue array 0 -
lock_queue array 0 -
num_last_reqs integral 32 'd1
num_last_rsps integral 32 'd1
m_data_output_coverage data_output_coverage - @512
analysis_imp uvm_analysis_imp - @521
m_reference reference - @388
analysis_export_0 uvm_analysis_imp_reference_0 - @397
analysis_port_0 uvm_analysis_port - @407
m_reference_scoreboard cl_syoscb - @446
DUT cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
[REF] cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
REF cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
[REF] cl_syoscb_queue_std - @929
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
compare_strategy cl_syoscb_compare - @940
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
[REF] cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
compare_algo cl_syoscb_compare_iop - @991
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
[REF] cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
m_data_output_agent_DUT_subscr cl_syoscb_subscriber - @950
analysis_imp uvm_analysis_imp - @959
queue_name string 3 DUT
producer string 19 m_data_output_agent
m_data_output_agent_REF_subscr cl_syoscb_subscriber - @969
analysis_imp uvm_analysis_imp - @978
queue_name string 3 REF
producer string 19 m_data_output_agent
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
[REF] cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
queues da(object) 2 -
[0] cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
[REF] cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
[1] cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
[REF] cl_syoscb_queue_std - @929
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
compare_strategy cl_syoscb_compare - @940
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
[REF] cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
compare_algo cl_syoscb_compare_iop - @991
cfg cl_syoscb_cfg - @382
queues aa(object,string) 2 -
[DUT] cl_syoscb_queue_std - @918
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
[REF] cl_syoscb_queue_std - @929
cfg cl_syoscb_cfg - @382
iter_idx integral 32 'h0
cnt_add_item integral 32 'h0
items da(object) 0 -
producers aa(object,string) 1 -
[m_data_output_agent] cl_syoscb_cfg_pl - @383
list da(string) 2 -
[0] string 3 DUT
[1] string 3 REF
primary_queue string 3 DUT
disable_clone integral 1 'h0
max_queue_size aa(int,string) 2 -
[DUT] integral 32 'h0
[REF] integral 32 'h0
scb_name string 22 m_reference_scoreboard
subscribers aa(object,string) 2 -
[DUTm_data_output_agent] cl_syoscb_subscriber - @950
analysis_imp uvm_analysis_imp - @959
queue_name string 3 DUT
producer string 19 m_data_output_agent
[REFm_data_output_agent] cl_syoscb_subscriber - @969
analysis_imp uvm_analysis_imp - @978
queue_name string 3 REF
producer string 19 m_data_output_agent
------------------------------------------------------------------------------------------------
 
UVM_INFO /apps/vcsmx/etc/uvm-1.2/base/uvm_factory.svh(1645) @ 0: reporter [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
 
Instance Overrides:
 
Requested Type Override Path Override Type
---------------------- ------------------------------------------- ---------------------
cl_syoscb_compare_base uvm_test_top.m_env.m_reference_scoreboard.* cl_syoscb_compare_iop
 
Type Overrides:
 
Requested Type Override Type
---------------------- -------------------------------------------
cl_syoscb_queue cl_syoscb_queue_std
 
All types registered with the factory: 85 total
Type Name
---------
cl_syoscb
cl_syoscb_cfg
cl_syoscb_cfg_pl
cl_syoscb_compare
cl_syoscb_compare_base
cl_syoscb_compare_io
cl_syoscb_compare_iop
cl_syoscb_compare_ooo
cl_syoscb_item
cl_syoscb_queue
cl_syoscb_queue_iterator_base
cl_syoscb_queue_iterator_std
cl_syoscb_queue_std
cl_syoscb_subscriber
data_input_agent
data_input_coverage
data_input_default_seq
data_input_driver
data_input_monitor
data_output_agent
data_output_coverage
data_output_default_seq
data_output_driver
data_output_monitor
input_tx
output_tx
reference
snps_uvm_reg_bank_group
snps_uvm_reg_map
top_default_seq
top_env
top_test
(*) Types with no associated type name will be printed as <unknown>
 
####
 
 
UVM_INFO ../tb/data_input/sv/data_input_driver.sv(43) @ 0: uvm_test_top.m_env.m_data_input_agent.m_driver [data_input_driver] run_phase
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(54) @ 0: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] run_phase
UVM_INFO ../tb/data_output/sv/data_output_driver.sv(43) @ 0: uvm_test_top.m_env.m_data_output_agent.m_driver [data_output_driver] run_phase
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(54) @ 0: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] run_phase
UVM_INFO ../tb/top/sv/top_seq_lib.sv(49) @ 0: reporter@@vseq [top_default_seq] Default sequence starting
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 0: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 0: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 75000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 75000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 75000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 75000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 46, tx_tdata_o 46
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 90000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 46
UVM_INFO ../tb/top/sv/reference.sv(72) @ 90000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 0, data = 46
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 90000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 46
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 90000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 90000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 90000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 90000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 2, tx_tdata_o 48
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 110000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 48
UVM_INFO ../tb/top/sv/reference.sv(72) @ 110000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 1, data = 48
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 110000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 2
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 110000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 110000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 110000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 110000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 82, tx_tdata_o 130
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 130000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 130
UVM_INFO ../tb/top/sv/reference.sv(72) @ 130000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 2, data = 130
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 130000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 82
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 130000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 130000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 130000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 130000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 21, tx_tdata_o 151
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 150000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 151
UVM_INFO ../tb/top/sv/reference.sv(72) @ 150000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 3, data = 151
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 150000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 21
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 150000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 150000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 150000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 150000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 8, tx_tdata_o 159
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 170000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 159
UVM_INFO ../tb/top/sv/reference.sv(72) @ 170000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 4, data = 159
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 170000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 8
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 170000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 170000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 170000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 170000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 21, tx_tdata_o 180
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 190000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 180
UVM_INFO ../tb/top/sv/reference.sv(72) @ 190000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 5, data = 180
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 190000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 21
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 190000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 190000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 190000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 190000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 11, tx_tdata_o 145
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 210000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 145
UVM_INFO ../tb/top/sv/reference.sv(72) @ 210000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 0, data = 145
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 210000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 11
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 210000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 210000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 210000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 210000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 125, tx_tdata_o 268
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 230000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 268
UVM_INFO ../tb/top/sv/reference.sv(72) @ 230000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 1, data = 268
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 230000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 125
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 230000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 230000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(41) @ 230000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence starting
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(41) @ 230000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence starting
DUT: rx_tdata_i 79, tx_tdata_o 265
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 250000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 265
UVM_INFO ../tb/top/sv/reference.sv(72) @ 250000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 2, data = 265
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 250000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 79
UVM_INFO ../tb/data_input/sv/data_input_seq_lib.sv(49) @ 250000: uvm_test_top.m_env.m_data_input_agent.m_sequencer@@vseq.seq [data_input_default_seq] Default sequence completed
UVM_INFO ../tb/data_output/sv/data_output_seq_lib.sv(49) @ 250000: uvm_test_top.m_env.m_data_output_agent.m_sequencer@@vseq.seq [data_output_default_seq] Default sequence completed
UVM_INFO ../tb/top/sv/top_seq_lib.sv(78) @ 250000: reporter@@vseq [top_default_seq] Default sequence completed
DUT: rx_tdata_i 38, tx_tdata_o 282
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 270000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 282
UVM_INFO ../tb/top/sv/reference.sv(72) @ 270000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 3, data = 282
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 270000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 312
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 290000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 312
UVM_INFO ../tb/top/sv/reference.sv(72) @ 290000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 4, data = 312
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 290000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 329
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 310000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 329
UVM_INFO ../tb/top/sv/reference.sv(72) @ 310000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 5, data = 329
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 310000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 356
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 330000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 356
UVM_INFO ../tb/top/sv/reference.sv(72) @ 330000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 0, data = 356
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 330000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 269
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 350000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 269
UVM_INFO ../tb/top/sv/reference.sv(72) @ 350000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 1, data = 269
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 350000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 228
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 370000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 228
UVM_INFO ../tb/top/sv/reference.sv(72) @ 370000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 2, data = 228
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 370000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 228
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 390000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 228
UVM_INFO ../tb/top/sv/reference.sv(72) @ 390000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 3, data = 228
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 390000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 228
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 410000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 228
UVM_INFO ../tb/top/sv/reference.sv(72) @ 410000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 4, data = 228
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 410000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 228
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 430000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 228
UVM_INFO ../tb/top/sv/reference.sv(72) @ 430000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 5, data = 228
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 430000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
DUT: rx_tdata_i 38, tx_tdata_o 228
UVM_INFO ../tb/data_output/sv/data_output_monitor.sv(70) @ 450000: uvm_test_top.m_env.m_data_output_agent.m_monitor [data_output_monitor] Output data = 228
UVM_INFO ../tb/top/sv/reference.sv(72) @ 450000: uvm_test_top.m_env.m_reference [reference] Reference Model save_pnt = 0, data = 228
UVM_INFO ../tb/data_input/sv/data_input_monitor.sv(70) @ 450000: uvm_test_top.m_env.m_data_input_agent.m_monitor [data_input_monitor] Input data = 38
UVM_INFO /apps/vcsmx/etc/uvm-1.2/base/uvm_objection.svh(1270) @ 450000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO ../tb/data_input/sv/data_input_coverage.sv(79) @ 450000: uvm_test_top.m_env.m_data_input_coverage [data_input_coverage] Coverage score = 7.0%
UVM_INFO ../tb/data_output/sv/data_output_coverage.sv(83) @ 450000: uvm_test_top.m_env.m_data_output_coverage [data_output_coverage] Coverage disabled for this agent
UVM_INFO ../../../../playground_lib/uvm_syoscb/src/cl_syoscb_queue.svh(118) @ 450000: uvm_test_top.m_env.m_reference_scoreboard.DUT [QUEUE] [m_reference_scoreboard]: Statistics for queue: DUT:
Inserts: 19, Macthed: 19, Orphans: 0
UVM_INFO ../../../../playground_lib/uvm_syoscb/src/cl_syoscb_queue.svh(118) @ 450000: uvm_test_top.m_env.m_reference_scoreboard.REF [QUEUE] [m_reference_scoreboard]: Statistics for queue: REF:
Inserts: 19, Macthed: 19, Orphans: 0
UVM_INFO /apps/vcsmx/etc/uvm-1.2/base/uvm_report_catcher.svh(705) @ 450000: reporter [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
 
 
Number of demoted UVM_FATAL reports : 0
Number of demoted UVM_ERROR reports : 0
Number of demoted UVM_WARNING reports: 0
Number of caught UVM_FATAL reports : 0
Number of caught UVM_ERROR reports : 0
Number of caught UVM_WARNING reports : 0
 
UVM_INFO /apps/vcsmx/etc/uvm-1.2/base/uvm_report_server.svh(847) @ 450000: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---
 
** Report counts by severity
UVM_INFO : 117
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[QUEUE] 2
[RNTST] 1
[TEST_DONE] 1
[UVM/FACTORY/PRINT] 1
[UVM/RELNOTES] 1
[UVM/REPORT/CATCHER] 1
[UVMTOP] 1
[data_input_coverage] 1
[data_input_default_seq] 20
[data_input_driver] 1
[data_input_monitor] 20
[data_output_coverage] 1
[data_output_default_seq] 20
[data_output_driver] 1
[data_output_monitor] 20
[reference] 19
[top_default_seq] 2
[top_env] 4
 
$finish called from file "/apps/vcsmx/etc/uvm-1.2/base/uvm_root.svh", line 527.
$finish at simulation time 450000
V C S S i m u l a t i o n R e p o r t
Time: 450000 ps
CPU Time: 0.560 seconds; Data structure size: 0.3Mb
Sat Apr 27 14:03:02 2019
CPU time: 13.223 seconds to compile + .377 seconds to elab + .860 seconds to link + .697 seconds in simulation
Done
/trunk/uvm/lpffir_uvm/generated_tb/tb_tree.txt
0,0 → 1,54
tb
├── data_input
│ └── sv
│ ├── data_input_agent.sv
│ ├── data_input_config.sv
│ ├── data_input_coverage.sv
│ ├── data_input_driver.sv
│ ├── data_input_if.sv
│ ├── data_input_input_tx.sv
│ ├── data_input_monitor.sv
│ ├── data_input_pkg.sv
│ ├── data_input_seq_lib.sv
│ └── data_input_sequencer.sv
├── data_output
│ └── sv
│ ├── data_output_agent.sv
│ ├── data_output_config.sv
│ ├── data_output_coverage.sv
│ ├── data_output_driver.sv
│ ├── data_output_if.sv
│ ├── data_output_monitor.sv
│ ├── data_output_output_tx.sv
│ ├── data_output_pkg.sv
│ ├── data_output_seq_lib.sv
│ └── data_output_sequencer.sv
├── include
│ ├── data_input_cover_inc.sv
│ ├── data_input_do_mon.sv
│ ├── data_input_driver_inc_after_class.sv
│ ├── data_input_driver_inc_inside_class.sv
│ ├── data_output_do_mon.sv
│ ├── data_output_driver_inc_after_class.sv
│ ├── data_output_driver_inc_inside_class.sv
│ ├── reference_inc_after_class.sv
│ ├── reference_inc_inside_class.sv
│ └── vcd_dump.sv
├── top
│ └── sv
│ ├── port_converter.sv
│ ├── reference.sv
│ ├── top_config.sv
│ ├── top_env.sv
│ ├── top_pkg.sv
│ └── top_seq_lib.sv
├── top_tb
│ └── sv
│ ├── top_tb.sv
│ └── top_th.sv
└── top_test
└── sv
├── top_test_pkg.sv
└── top_test.sv
 
11 directories, 40 files
/trunk/uvm/lpffir_uvm/include/data_input_cover_inc.sv
0,0 → 1,7
covergroup m_cov;
option.per_instance = 1;
 
cp_data: coverpoint m_item.data {
bins data_values[] = {[0:127]};
}
endgroup
/trunk/uvm/lpffir_uvm/include/data_input_do_mon.sv
0,0 → 1,12
task data_input_monitor::do_mon;
forever @(posedge vif.clk)
begin
wait (vif.reset == 1);
if (vif.valid && vif.ready)
begin
m_trans.data = vif.data;
analysis_port.write(m_trans);
`uvm_info(get_type_name(), $sformatf("Input data = %0d", m_trans.data), UVM_HIGH)
end
end
endtask
/trunk/uvm/lpffir_uvm/include/data_input_driver_inc_after_class.sv
0,0 → 1,22
task data_input_driver::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "run_phase", UVM_HIGH)
 
forever @(posedge vif.clk)
begin
seq_item_port.get_next_item(req);
phase.raise_objection(this);
wait (vif.reset == 1);
vif.data <= req.data;
vif.valid <= 1;
vif.last <= 0;
wait (vif.ready == 1);
fork
begin
repeat (10) @(posedge vif.clk);
phase.drop_objection(this);
end
join_none
seq_item_port.item_done();
end
endtask : run_phase
/trunk/uvm/lpffir_uvm/include/data_input_driver_inc_inside_class.sv
0,0 → 1,22
extern task run_phase(uvm_phase phase);
/trunk/uvm/lpffir_uvm/include/data_output_do_mon.sv
0,0 → 1,12
task data_output_monitor::do_mon;
forever @(posedge vif.clk)
begin
wait (vif.reset == 1);
if (vif.valid && vif.ready)
begin
m_trans.data = vif.data;
analysis_port.write(m_trans);
`uvm_info(get_type_name(), $sformatf("Output data = %0d",m_trans.data), UVM_HIGH)
end
end
endtask
/trunk/uvm/lpffir_uvm/include/data_output_driver_inc_after_class.sv
0,0 → 1,20
task data_output_driver::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "run_phase", UVM_HIGH)
 
forever @(posedge vif.clk)
begin
seq_item_port.get_next_item(req);
phase.raise_objection(this);
vif.ready <= 1;
wait (vif.reset == 1);
fork
begin
repeat (10) @(posedge vif.clk);
phase.drop_objection(this);
end
join_none
seq_item_port.item_done();
end
endtask : run_phase
/trunk/uvm/lpffir_uvm/include/data_output_driver_inc_inside_class.sv
0,0 → 1,2
extern task run_phase(uvm_phase phase);
/trunk/uvm/lpffir_uvm/include/reference_inc_after_class.sv
0,0 → 1,22
function void reference::write_reference_0(input_tx t);
send(t);
endfunction
function void reference::send(input_tx t);
output_tx tx;
tx = output_tx::type_id::create("tx");
if (init_flag == 1)
begin
init_flag = 0;
foreach(tx_save[j])
tx_save[j] = 0;
end
if (save_pnt == 5)
save_pnt = 0;
else
save_pnt++;
tx_save[save_pnt] = t.data;
tx.data = tx_save[0] + tx_save[1] + tx_save[2] + tx_save[3] + tx_save[4] + tx_save[5];
analysis_port_0.write(tx);
`uvm_info(get_type_name(), $sformatf("Reference Model save_pnt = %0d, data = %0d",save_pnt, tx.data), UVM_HIGH)
endfunction
/trunk/uvm/lpffir_uvm/include/reference_inc_inside_class.sv
0,0 → 1,5
extern function void send(input_tx t);
 
int save_pnt = 5;
logic [15:0] tx_save [0:5];
int init_flag = 1;
/trunk/uvm/lpffir_uvm/include/vcd_dump.sv
0,0 → 1,2
$dumpfile("dump.vcd");
$dumpvars;
/trunk/uvm/lpffir_uvm/common.tpl
0,0 → 1,20
dut_top = lpffir_axis
nested_config_objects = yes
 
tb_prepend_to_initial = vcd_dump.sv inline
 
#Path ignored on EDA Playground
#syosil_scoreboard_src_path = ../../syosil/src
 
ref_model_input = reference m_data_input_agent
 
ref_model_output = reference m_data_output_agent
 
ref_model_compare_method = reference iop
 
ref_model_inc_inside_class = reference reference_inc_inside_class.sv inline
ref_model_inc_after_class = reference reference_inc_after_class.sv inline
 
top_default_seq_count = 10
 
uvm_cmdline = +UVM_VERBOSITY=UVM_HIGH
/trunk/uvm/lpffir_uvm/data_input.tpl
0,0 → 1,22
agent_name = data_input
 
number_of_instances = 1
 
trans_item = input_tx
trans_var = rand logic [15:0] data;
 
trans_var = constraint c_data { 0 <= data; data < 128; }
 
driver_inc_inside_class = data_input_driver_inc_inside_class.sv inline
driver_inc_after_class = data_input_driver_inc_after_class.sv inline
monitor_inc = data_input_do_mon.sv inline
agent_cover_inc = data_input_cover_inc.sv inline
 
if_port = logic last;
if_port = logic valid;
if_port = logic ready;
if_port = logic [15:0] data;
if_port = logic clk;
if_port = logic reset;
if_clock = clk
if_reset = reset
/trunk/uvm/lpffir_uvm/data_output.tpl
0,0 → 1,21
agent_name = data_output
 
number_of_instances = 1
 
trans_item = output_tx
trans_var = rand logic [15:0] data;
 
agent_coverage_enable = no
 
driver_inc_inside_class = data_output_driver_inc_inside_class.sv inline
driver_inc_after_class = data_output_driver_inc_after_class.sv inline
monitor_inc = data_output_do_mon.sv inline
 
if_port = logic last;
if_port = logic valid;
if_port = logic ready;
if_port = logic [15:0] data;
if_port = logic clk;
if_port = logic reset;
if_clock = clk
if_reset = reset
/trunk/uvm/lpffir_uvm/pinlist
0,0 → 1,15
!data_input_if_0
rx_tlast_i last
rx_tvalid_i valid
rx_tready_o ready
rx_tdata_i data
 
!data_output_if_0
tx_tlast_o last
tx_tvalid_o valid
tx_tready_i ready
tx_tdata_o data
 
!
aclk_i clock
aresetn_i reset
/trunk/uvm/rca_uvm/generated_tb/tb_tree.txt
0,0 → 1,32
tb
├── include
│ ├── rca_driver_inc.sv
│ └── rca_monitor_inc.sv
├── rca
│ └── sv
│ ├── rca_agent.sv
│ ├── rca_config.sv
│ ├── rca_coverage.sv
│ ├── rca_driver.sv
│ ├── rca_if.sv
│ ├── rca_monitor.sv
│ ├── rca_pkg.sv
│ ├── rca_seq_lib.sv
│ ├── rca_sequencer.sv
│ └── rca_trans.sv
├── top
│ └── sv
│ ├── top_config.sv
│ ├── top_env.sv
│ ├── top_pkg.sv
│ └── top_seq_lib.sv
├── top_tb
│ └── sv
│ ├── top_tb.sv
│ └── top_th.sv
└── top_test
└── sv
├── top_test_pkg.sv
└── top_test.sv
 
9 directories, 20 files

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.