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Subversion Repositories lwrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /lwrisc/trunk/SYN/rev_1/syntmp
    from Rev 9 to Rev 19
    ↔ Reverse comparison
  •

Rev 9 → Rev 19

/rom256x12_flink.htm
0,0 → 1,9
<table border="0" cellpadding="0" cellspacing="2">
<tr>
<td nowrap width="500" class="content" valign="top">
<body bgcolor="rgb(245,245,255)">
<font size=2 face="arial">
<a><b>Log File Links:</a></b><br>
<a href="C:\Program Files\Synplicity\fpga_81\examples\stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br>
<br><b>rev_1</a></b><br>
<br><b>rev_1\par_1</a></b><br>
/ClaiRISC_core_cons_ui.tcl
0,0 → 1,5
source "C:/Program Files/Synplicity/fpga_81/lib/altera/quartus_cons.tcl"
syn_create_and_open_prj ClaiRISC_core
source $::quartus(binpath)/prj_asd_import.tcl
syn_create_and_open_csf ClaiRISC_core
syn_handle_cons ClaiRISC_core
/ClaiRISC_core.plg
0,0 → 1,11
@P: Part : EP1C6QC240-6
@P: Worst Slack : -1.463
@P: ClaiRISC_core|clk - Estimated Frequency : 102.6 MHz
@P: ClaiRISC_core|clk - Requested Frequency : 120.7 MHz
@P: ClaiRISC_core|clk - Estimated Period : 9.750
@P: ClaiRISC_core|clk - Requested Period : 8.288
@P: ClaiRISC_core|clk - Slack : -1.463
@P: ClaiRISC_core Part : ep1c6qc240-6
@P: ClaiRISC_core I/O ATOMs : 34
@P: ClaiRISC_core Total LUTs: : 247 of 5980 ( 4%)
@P: ClaiRISC_core Logic resources : 247 ATOMs of 5980 ( 4%)
/ClaiRISC_core.msg --- ClaiRISC_core_toc.htm (nonexistent) +++ ClaiRISC_core_toc.htm (revision 19) @@ -0,0 +1,8 @@ + + +
+ + +
+rev_1 (ClaiRISC_core)

 +
Compiler Report

/ClaiRISC_core_srr.htm
0,0 → 1,67
<html>
<body><samp><pre>
<!@TC:1205142074>
#Program: Synplify Pro 8.1
#OS: Windows_NT
 
<a name=compilerReport13>$ Start of Compile
#Mon Mar 10 17:41:12 2008
 
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
 
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"
@I::"D:\LWRISC\RTL\sim_rom.v"
@I::"D:\LWRISC\RTL\test.v"
@I::"D:\LWRISC\RTL\mem_man.v"
@I:"D:\LWRISC\RTL\mem_man.v":"D:\LWRISC\RTL\clairisc_def.h"
@I::"D:\LWRISC\RTL\memory.v"
@I:"D:\LWRISC\RTL\memory.v":"D:\LWRISC\RTL\clairisc_def.h"
@I:"D:\LWRISC\RTL\memory.v":"D:\LWRISC\RTL\rom_set.h"
@I::"D:\LWRISC\RTL\risc_core.v"
@I:"D:\LWRISC\RTL\risc_core.v":"D:\LWRISC\RTL\clairisc_def.h"
@I::"D:\LWRISC\RTL\altera\rom512x12.v"
@N: : <a href="d:\lwrisc\rtl\altera\rom512x12.v:39:12:39:25:@N::@XP_MSG">rom512x12.v(39)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom512x12.v:41:12:41:24:@N::@XP_MSG">rom512x12.v(41)</a><!@TM:1205142084> | Read directive translate_on
@N: : <a href="d:\lwrisc\rtl\altera\rom512x12.v:58:16:58:29:@N::@XP_MSG">rom512x12.v(58)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom512x12.v:76:16:76:28:@N::@XP_MSG">rom512x12.v(76)</a><!@TM:1205142084> | Read directive translate_on
@I::"D:\LWRISC\RTL\altera\rom1024x12.v"
@N: : <a href="d:\lwrisc\rtl\altera\rom1024x12.v:39:12:39:25:@N::@XP_MSG">rom1024x12.v(39)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom1024x12.v:41:12:41:24:@N::@XP_MSG">rom1024x12.v(41)</a><!@TM:1205142084> | Read directive translate_on
@N: : <a href="d:\lwrisc\rtl\altera\rom1024x12.v:58:16:58:29:@N::@XP_MSG">rom1024x12.v(58)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom1024x12.v:76:16:76:28:@N::@XP_MSG">rom1024x12.v(76)</a><!@TM:1205142084> | Read directive translate_on
@I::"D:\LWRISC\RTL\altera\rom2048x12.v"
@N: : <a href="d:\lwrisc\rtl\altera\rom2048x12.v:39:12:39:25:@N::@XP_MSG">rom2048x12.v(39)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom2048x12.v:41:12:41:24:@N::@XP_MSG">rom2048x12.v(41)</a><!@TM:1205142084> | Read directive translate_on
@N: : <a href="d:\lwrisc\rtl\altera\rom2048x12.v:58:16:58:29:@N::@XP_MSG">rom2048x12.v(58)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom2048x12.v:76:16:76:28:@N::@XP_MSG">rom2048x12.v(76)</a><!@TM:1205142084> | Read directive translate_on
@I::"D:\LWRISC\RTL\altera\ram128x8.v"
@N: : <a href="d:\lwrisc\rtl\altera\ram128x8.v:141:12:141:25:@N::@XP_MSG">ram128x8.v(141)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\ram128x8.v:143:12:143:24:@N::@XP_MSG">ram128x8.v(143)</a><!@TM:1205142084> | Read directive translate_on
@N: : <a href="d:\lwrisc\rtl\altera\ram128x8.v:169:31:169:44:@N::@XP_MSG">ram128x8.v(169)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\ram128x8.v:184:31:184:43:@N::@XP_MSG">ram128x8.v(184)</a><!@TM:1205142084> | Read directive translate_on
@I::"D:\LWRISC\RTL\altera\rom32x12.v"
@N: : <a href="d:\lwrisc\rtl\altera\rom32x12.v:39:12:39:25:@N::@XP_MSG">rom32x12.v(39)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom32x12.v:41:12:41:24:@N::@XP_MSG">rom32x12.v(41)</a><!@TM:1205142084> | Read directive translate_on
@N: : <a href="d:\lwrisc\rtl\altera\rom32x12.v:58:16:58:29:@N::@XP_MSG">rom32x12.v(58)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom32x12.v:76:16:76:28:@N::@XP_MSG">rom32x12.v(76)</a><!@TM:1205142084> | Read directive translate_on
@I::"D:\LWRISC\RTL\altera\rom64x12.v"
@N: : <a href="d:\lwrisc\rtl\altera\rom64x12.v:39:12:39:25:@N::@XP_MSG">rom64x12.v(39)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom64x12.v:41:12:41:24:@N::@XP_MSG">rom64x12.v(41)</a><!@TM:1205142084> | Read directive translate_on
@N: : <a href="d:\lwrisc\rtl\altera\rom64x12.v:58:16:58:29:@N::@XP_MSG">rom64x12.v(58)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom64x12.v:76:16:76:28:@N::@XP_MSG">rom64x12.v(76)</a><!@TM:1205142084> | Read directive translate_on
@I::"D:\LWRISC\RTL\altera\rom128x12.v"
@N: : <a href="d:\lwrisc\rtl\altera\rom128x12.v:39:12:39:25:@N::@XP_MSG">rom128x12.v(39)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom128x12.v:41:12:41:24:@N::@XP_MSG">rom128x12.v(41)</a><!@TM:1205142084> | Read directive translate_on
@N: : <a href="d:\lwrisc\rtl\altera\rom128x12.v:58:16:58:29:@N::@XP_MSG">rom128x12.v(58)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom128x12.v:76:16:76:28:@N::@XP_MSG">rom128x12.v(76)</a><!@TM:1205142084> | Read directive translate_on
@I::"D:\LWRISC\RTL\altera\rom256x12.v"
@N: : <a href="d:\lwrisc\rtl\altera\rom256x12.v:39:12:39:25:@N::@XP_MSG">rom256x12.v(39)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom256x12.v:41:12:41:24:@N::@XP_MSG">rom256x12.v(41)</a><!@TM:1205142084> | Read directive translate_on
@N: : <a href="d:\lwrisc\rtl\altera\rom256x12.v:58:16:58:29:@N::@XP_MSG">rom256x12.v(58)</a><!@TM:1205142084> | Read directive translate_off
@N: : <a href="d:\lwrisc\rtl\altera\rom256x12.v:76:16:76:28:@N::@XP_MSG">rom256x12.v(76)</a><!@TM:1205142084> | Read directive translate_on
Verilog syntax check successful!
File D:\LWRISC\RTL\sim_rom.v changed - recompiling

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