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URL https://opencores.org/ocsvn/m32632/m32632/trunk

Subversion Repositories m32632

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  • This comparison shows the changes necessary to convert path
    /m32632/trunk/rtl
    from Rev 15 to Rev 16
    Reverse comparison

Rev 15 → Rev 16

/ADDR_UNIT.v
4,9 → 4,10
// http://opencores.org/project,m32632
//
// Filename: ADDR_UNIT.v
// Version: 1.1 bug fix
// History: 1.0 first release of 30 Mai 2015
// Date: 7 October 2015
// Version: 1.2 bug fix
// History: 1.1 bug fix release of 7 October 2015
// 1.0 first release of 30 Mai 2015
// Date: 8 March 2016
//
// Copyright (C) 2015 Udo Moeller
//
158,7 → 159,7
always @(index_sel or sign_ext_src1 or SRC1)
casex (index_sel)
 
4'b1_0xx : index_val = sign_ext_src1; // f�r CASE
4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
4'b0_100 : index_val = SRC1;
4'b0_101 : index_val = {SRC1[30:0],1'b0};
319,13 → 320,13
//
7'b01_xxxx_1 : acc_step = acc_ok; // Word : aligned access , only 1 packet
7'b01_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
7'b01_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
7'b01_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
7'b01_0x1x_0 : acc_step = acc_ok; // WRITE Adr. is not perfect and waits for last packet
7'b01_0100_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
//
7'b10_xxxx_1 : acc_step = acc_ok; // DWord : aligned access , only 1 packet
7'b10_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
7'b10_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
7'b10_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
7'b10_0x1x_0 : acc_step = acc_ok; // WRITE Adr. is not perfect and waits for last packet
7'b10_0100_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
// fast QWord READ : there would be a 2. acc_step if not ~PACK...
7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
7'b11_0x1x_x : acc_step = acc_ok;

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