URL
https://opencores.org/ocsvn/m32632/m32632/trunk
Subversion Repositories m32632
Compare Revisions
- This comparison shows the changes necessary to convert path
/m32632
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/trunk/rtl/DATENPFAD.v
4,8 → 4,9
// http://opencores.org/project,m32632 |
// |
// Filename: DATENPFAD.v |
// Version: 1.0 |
// Date: 30 May 2015 |
// Version: 1.1 bug fix |
// History: 1.0 first release of 30 Mai 2015 |
// Date: 7 October 2015 |
// |
// Copyright (C) 2015 Udo Moeller |
// |
39,7 → 40,7
|
module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX, |
IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE, |
WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, ACC_DONE, REG_OUT, PTB_SEL, PTB_WR, ACB_ZERO, |
WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, REG_OUT, PTB_SEL, PTB_WR, ACB_ZERO, |
ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG, |
DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT); |
|
81,6 → 82,7
output READ_OUT; |
output ZTEST; |
output RMW; |
output QWATWO; |
output ACC_DONE; |
output REG_OUT; |
output PTB_SEL; |
301,6 → 303,7
.VADR(VADR), |
.ZTEST(ZTEST), |
.RMW(RMW), |
.QWATWO(QWATWO), |
.OP_RMW(INFO_AU[4]), |
.PHASE_17(INFO_AU[5]), |
.NO_TRAP(INFO_AU[6]) ); |
/trunk/rtl/CACHE_LOGIK.v
4,8 → 4,9
// http://opencores.org/project,m32632 |
// |
// Filename: CACHE_LOGIK.v |
// Version: 1.0 |
// Date: 30 May 2015 |
// Version: 1.1 bug fix |
// History: 1.0 first release of 30 Mai 2015 |
// Date: 7 October 2015 |
// |
// Copyright (C) 2015 Udo Moeller |
// |
409,7 → 410,7
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA, |
USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, FILLRAM, ICTODC, |
RWVAL, VIRTUELL, |
RWVAL, VIRTUELL, QWATWO, |
DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK, |
ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX, |
KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT ); |
437,6 → 438,7
input [3:0] ICTODC; // multiple signals from ICACHE, especially DMA |
input [1:0] RWVAL; // RDVAL+WRVAL Operation |
input VIRTUELL; // for RDVAL/WRVAL |
input QWATWO; |
|
output reg DRAM_ACC,DRAM_WR; |
output IO_ACC,IO_RD,IO_WR; |
666,9 → 668,10
|
assign kostart = pte_go | rd_level2; |
|
assign run_dc = ~ko_state[2] & ~dma_run; |
assign KOMUX = ko_state[1] | DMA_MUX; |
assign KDET = ko_state[0] | dma_kdet; |
// ko_state[2] suppresses ACC_OK at READ |
assign run_dc = (~ko_state[2] | QWATWO) & ~dma_run; // Bugfix of 7.10.2015 |
assign KOMUX = ko_state[1] | DMA_MUX; |
assign KDET = ko_state[0] | dma_kdet; |
|
assign HIT_ALL = MMU_HIT & CA_HIT & run_dc & ~pte_acc; // for Update "Last-Set" , MMU_HIT contains ZUGRIFF |
|
/trunk/rtl/M32632.v
4,8 → 4,9
// http://opencores.org/project,m32632 |
// |
// Filename: M32632.v |
// Version: 1.0 |
// Date: 30 May 2015 |
// Version: 1.1 bug fix |
// History: 1.0 first release of 30 Mai 2015 |
// Date: 7 October 2015 |
// |
// Copyright (C) 2015 Udo Moeller |
// |
123,6 → 124,7
wire WRITE; |
wire ZTEST; |
wire RMW; |
wire QWATWO; |
wire [2:0] RWVAL; |
wire RWVFLAG; |
wire [3:0] D_IOBE; |
190,6 → 192,7
.READ(READ), |
.ZTEST(ZTEST), |
.RMW(RMW), |
.QWATWO(QWATWO), |
.WAMUX(WAMUX), |
.ENWR(ENWR), |
.IC_PREQ(IC_PREQ), |
268,6 → 271,7
.WRITE_OUT(WRITE), |
.ZTEST(ZTEST), |
.RMW(RMW), |
.QWATWO(QWATWO), |
.ACC_DONE(ACC_DONE), |
.REG_OUT(REG_OUT), |
.Y_INIT(Y_INIT), |
/trunk/rtl/DCACHE.v
4,8 → 4,9
// http://opencores.org/project,m32632 |
// |
// Filename: DCACHE.v |
// Version: 1.0 |
// Date: 30 May 2015 |
// Version: 1.1 bug fix |
// History: 1.0 first release of 30 Mai 2015 |
// Date: 7 October 2015 |
// |
// Copyright (C) 2015 Udo Moeller |
// |
37,7 → 38,7
// |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|
module DCACHE( BCLK, MCLK, WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, |
module DCACHE( BCLK, MCLK, WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, QWATWO, |
WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS, |
PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA, |
ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST, |
57,6 → 58,7
input READ; |
input ZTEST; |
input RMW; |
input QWATWO; |
input WAMUX; |
input ENWR; |
input IC_PREQ; |
216,7 → 218,7
|
assign BE_SET = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE}; |
|
assign ADDR = KOMUX ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ; |
assign ADDR = KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ; |
|
assign A_SET = WAMUX ? WADDR : VADR_R[11:2] ; |
|
324,6 → 326,7
.WRITE(WRITE), |
.ZTEST(ZTEST), |
.RMW(RMW), |
.QWATWO(QWATWO), |
.USE_CA(USE_CA), |
.PTB_WR(PTB_WR), |
.PTB_SEL(PTB_SEL), |
/trunk/rtl/ADDR_UNIT.v
4,8 → 4,9
// http://opencores.org/project,m32632 |
// |
// Filename: ADDR_UNIT.v |
// Version: 1.0 |
// Date: 30 May 2015 |
// Version: 1.1 bug fix |
// History: 1.0 first release of 30 Mai 2015 |
// Date: 7 October 2015 |
// |
// Copyright (C) 2015 Udo Moeller |
// |
39,7 → 40,8
|
module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD, |
DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17, |
NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL ); |
NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL, |
QWATWO ); |
|
input BCLK,BRESET; |
input READ,WRITE,LDEA; |
74,6 → 76,7
output ABORT; |
output REG_OUT; |
output [2:0] BITSEL; |
output reg QWATWO; |
|
reg [31:0] VADR; |
reg READ_OUT,write_reg,ZTEST,RMW; |
338,6 → 341,9
// The final DONE Multiplexer |
assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok; |
|
// Bugfix of 7.October 2015 |
always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done; |
|
always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i); |
|
always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT); |