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URL https://opencores.org/ocsvn/m32632/m32632/trunk

Subversion Repositories m32632

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Rev 17 → Rev 18

/trunk/DE0-Nano/MAINPLL.v
0,0 → 1,404
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: MAINPLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 153 11/29/2010 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MAINPLL (
areset,
inclk0,
c0,
c1,
c2,
c3,
locked);
 
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
 
wire [4:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire8 = 1'h0;
wire [2:2] sub_wire5 = sub_wire0[2:2];
wire [0:0] sub_wire4 = sub_wire0[0:0];
wire [3:3] sub_wire2 = sub_wire0[3:3];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c3 = sub_wire2;
wire locked = sub_wire3;
wire c0 = sub_wire4;
wire c2 = sub_wire5;
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
 
altpll altpll_component (
.areset (areset),
.inclk (sub_wire7),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "3333",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 2,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 2,
altpll_component.clk3_phase_shift = "1250",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=MAINPLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "60.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "45.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "MAINPLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "3333"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "1250"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MAINPLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MAINPLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MAINPLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MAINPLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MAINPLL.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MAINPLL_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MAINPLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
/trunk/DE0-Nano/PERIMOD.v
0,0 → 1,64
module PERIMOD (BCLK, NRST, WRITE, READ, ADDR, IO_DI, SENSE,
DE0_LED, IO_Q, READY, RST_N, ENDRAM ) ;
input BCLK;
input NRST;
input WRITE;
input READ;
input [27:2] ADDR;
input [7:0] IO_DI;
 
input SENSE;
output reg [7:0] DE0_LED;
 
output [31:0] IO_Q;
output READY;
output reg RST_N;
output reg ENDRAM;
reg rd_rdy;
reg [3:0] init_cou;
wire [31:0] rom_q;
wire en_dram,wr_led;
always @(posedge BCLK) rd_rdy <= READ & ~rd_rdy; // all read accesses 2 clock cycles
 
assign READY = WRITE | rd_rdy;
 
assign IO_Q = ADDR[20] ? {31'd0,SENSE} : rom_q;
 
BOOT_ROM irom( // ROM
.clock(BCLK),
.address(ADDR[9:2]),
.q(rom_q));
// Enable DRAM : a WRITE access to address x'8002000 will switch on the DRAM. Then the ROM is no longer accessible at address 0.
assign en_dram = ADDR[27] & ADDR[13] & WRITE;
always @(posedge BCLK) ENDRAM <= (en_dram | ENDRAM ) & RST_N;
 
// LED Latch : address x'8001000;
 
assign wr_led = ADDR[27] & ADDR[12] & WRITE;
always @(posedge BCLK or negedge RST_N)
if (!RST_N) DE0_LED <= 8'd0;
else
if (wr_led) DE0_LED <= IO_DI[7:0];
// ++++++++++++++++++++++++++ RESET Signal ++++++++++++++++++++++++++
always @(posedge BCLK or negedge NRST)
if (!NRST) init_cou <= 4'h0;
else init_cou <= init_cou + 4'h1;
always @(posedge BCLK or negedge NRST)
if (!NRST) RST_N <= 1'b0;
else
if (init_cou == 4'hF) RST_N <= 1'b1;
 
endmodule
/trunk/DE0-Nano/BOOT_ROM.v
0,0 → 1,159
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: BOOT_ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 153 11/29/2010 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module BOOT_ROM (
address,
clock,
q);
 
input [7:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
 
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
 
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "bootcode.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "bootcode.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "bootcode.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL BOOT_ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BOOT_ROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL BOOT_ROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL BOOT_ROM.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BOOT_ROM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL BOOT_ROM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
/trunk/DE0-Nano/DRAMIF.v
0,0 → 1,690
 
module WB_CONTROL ( BCLK, MCLK, BRESET, MRESET, CLR_REQ, DRAM_WR, FREEZE, ENBYTE, WR_ADDR,
WR_REQ, WRA_WB, RDA_WB, WB_BE, WRA, WB_USED, ENWR );
 
input BCLK;
input MCLK;
input BRESET;
input MRESET;
input CLR_REQ;
input DRAM_WR;
input FREEZE;
input [3:0] ENBYTE;
input [24:2] WR_ADDR;
 
output reg WR_REQ;
output [5:2] WRA_WB;
output [5:1] RDA_WB;
output [1:0] WB_BE;
output [24:4] WRA;
output reg WB_USED;
output ENWR;
reg [24:4] WRA;
reg select;
reg used_0,used_1;
reg [24:4] addresse_0,addresse_1;
reg [15:0] init_be,be_feld0,be_feld1;
reg rd_msb;
reg [2:0] rd_lsb;
reg [1:0] sh_used_0,sh_used_1;
reg sel_adr;
reg [15:0] shifter;
wire clr_0,clr_1;
wire do_flip;
wire update_0,update_1;
wire edge_0,edge_1;
wire run_lsb;
 
always @(posedge BCLK or negedge BRESET)
if (!BRESET) select <= 1'b0;
else
if (DRAM_WR && do_flip) select <= ~select;
assign do_flip = ((select ? addresse_1 : addresse_0) != WR_ADDR[24:4]) & (used_0 | used_1); // 32 MB
assign ENWR = ~(used_0 & used_1) & ~(DRAM_WR & do_flip); // ENABLE WRITE for CPU
assign WRA_WB = {1'b0,(do_flip ? ~select : select),WR_ADDR[3:2]};
assign update_0 = DRAM_WR & (do_flip ? select : ~select);
assign update_1 = DRAM_WR & (do_flip ? ~select : select);
always @(posedge BCLK or negedge BRESET)
if (!BRESET) used_0 <= 1'b0;
else
begin
if (clr_0) used_0 <= 1'b0;
else
if (update_0) used_0 <= 1'b1;
end
always @(posedge BCLK or negedge BRESET)
if (!BRESET) used_1 <= 1'b0;
else
begin
if (clr_1) used_1 <= 1'b0;
else
if (update_1) used_1 <= 1'b1;
end
always @(posedge BCLK) if (update_0) addresse_0 <= WR_ADDR[24:4];
always @(posedge BCLK) if (update_1) addresse_1 <= WR_ADDR[24:4];
always @(WR_ADDR or ENBYTE)
case(WR_ADDR[3:2])
2'b00 : init_be = {12'd0,ENBYTE};
2'b01 : init_be = { 8'd0,ENBYTE, 4'd0};
2'b10 : init_be = { 4'd0,ENBYTE, 8'd0};
2'b11 : init_be = { ENBYTE,12'd0};
endcase
always @(posedge BCLK) if (update_0) be_feld0 <= used_0 ? (be_feld0 | init_be) : init_be;
always @(posedge BCLK) if (update_1) be_feld1 <= used_1 ? (be_feld1 | init_be) : init_be;
// ++++++++++++++++++++++++++++++ BCLK-MCLK Interface ++++++++++++++++++++++++++++++
 
always @(negedge MCLK) WR_REQ <= used_0 & used_1;
always @(negedge MCLK) sh_used_0 <= {used_0,sh_used_0[1]};
always @(negedge MCLK) sh_used_1 <= {used_1,sh_used_1[1]};
assign edge_0 = ~sh_used_0[1] & sh_used_0[0];
assign edge_1 = ~sh_used_1[1] & sh_used_1[0];
always @(negedge MCLK or negedge MRESET)
if (!MRESET) sel_adr <= 1'b0;
else
if (edge_0 || edge_1) sel_adr <= (edge_0 & sh_used_1[1]) | (edge_1 & ~sh_used_0[1]);
 
assign clr_0 = CLR_REQ & ~sel_adr;
assign clr_1 = CLR_REQ & sel_adr;
// ++++++++++++++++++++++++++++++ WB read address ++++++++++++++++++++++++++++++++++
always @(negedge MCLK) if (rd_lsb == 3'd0) rd_msb <= sel_adr;
assign run_lsb = FREEZE | (rd_lsb != 3'd0);
always @(negedge MCLK or negedge MRESET)
if (!MRESET) rd_lsb <= 3'b000;
else rd_lsb <= rd_lsb + {2'b00,run_lsb};
assign RDA_WB = {1'b0,rd_msb,rd_lsb};
 
// ++++++++++++++++++++++++++++++ Signals to DRAM Controller ++++++++++++++++++++
always @(negedge MCLK) WRA <= sel_adr ? addresse_1 : addresse_0;
always @(negedge MCLK) WB_USED <= sel_adr ? used_1 : used_0;
always @(negedge MCLK)
if (FREEZE) shifter <= sel_adr ? be_feld1 : be_feld0;
else shifter <= {shifter[1:0],shifter[15:2]};
assign WB_BE = shifter[1:0];
endmodule
 
module DRAM_SM
( MCLK, BCLK, MRESET, DC_ACC, DRAM_ADR, IC_ACC, IDRAM_ADR, DMA_ACC, DMA_WR, DMA_ADR, WB_USED, WRA, WB_BE, WR_REQ,
CKE_FF, CMD_FF, ADDR_FF, CLR_REQ, DATMUX, DQM_FF, WR_DONE, RD_DONE, IC_MDONE, IWCTRL, DC_MDONE, DWCTRL, WAMUX, WADDR,
FREEZE, LDEN, OE );
input MCLK;
input BCLK;
input MRESET;
input DC_ACC;
input [27:0] DRAM_ADR;
input IC_ACC;
input [27:0] IDRAM_ADR;
input DMA_ACC;
input DMA_WR;
input [27:9] DMA_ADR;
 
input WB_USED;
input [24:4] WRA;
input [1:0] WB_BE;
input WR_REQ;
output reg CKE_FF;
output [3:0] CMD_FF; // CS RAS CAS WE
output reg [14:0] ADDR_FF; // BA[1:0],ADDR[12:0]
output reg CLR_REQ;
output reg DATMUX;
output [1:0] DQM_FF;
output WR_DONE;
output reg RD_DONE;
output reg IC_MDONE;
output reg [2:0] IWCTRL;
output reg DC_MDONE;
output reg [2:0] DWCTRL;
output reg WAMUX;
output [11:2] WADDR;
output FREEZE;
output LDEN;
output reg OE;
reg synclk;
reg [1:0] lsbcou;
reg [2:0] state;
reg [1:0] test_bck;
reg [3:0] request;
reg [24:9] dma_a;
reg [1:0] dma_c;
reg [24:0] dc_a,ic_a;
reg dc_c,ic_c;
reg [24:0] addr;
reg check_op;
reg top_match,bot_match;
reg [2:0] cmd_i,cmd_out;
reg [11:2] cadr,col_adr;
reg wr_flag,wr_dma;
reg [5:0] col_cou,col_count;
reg [2:0] new_sta;
reg [2:0] dest_i,dest;
reg [2:0] frez_ctrl,do_frez;
reg [14:0] adr_reg;
reg rd_op;
reg wr_up,do_wr;
reg [9:0] reftimer;
reg refreq;
reg rw_acc;
reg oe_flag,oe_t2;
reg [14:0] icounter;
reg [2:0] cmd_reg;
reg [14:0] addr_i;
reg enadram;
reg dqm_lang,dqm_kurz;
reg [2:0] col_code;
reg inc_op;
reg ende;
reg [1:0] lsb_reg;
reg new_lsba;
reg [1:0] lsba_c,pipe_lsb;
reg cap_puls;
reg [2:0] burst_c;
reg dc_ende,ic_ende;
reg pipeicmd;
reg do_count;
reg [8:4] upd_adr;
wire do_col_op;
wire dma_op;
wire ena;
wire autopre;
wire [5:0] inc_cadr;
wire [8:4] mid_adr;
wire [3:2] low_adr;
wire init_c;
wire burst_add;
// ++++++++++++++ Synchronisation BCLK - MCLK ++++++++++++++++++++++++++++++
always @(negedge MCLK) test_bck <= {test_bck[0],BCLK};
 
always @(negedge MCLK)
if (test_bck == 2'b01) synclk <= 1'b0;
else synclk <= ~synclk;
 
always @(negedge MCLK) check_op <= (state == 3'd0) & synclk & enadram;
// ++++++++++++++ all synchronise on MCLK +++++++++++++++++
always @(negedge MCLK)
begin
dma_c <= {DMA_ACC,DMA_WR};
dma_a <= DMA_ADR[24:9];
dc_c <= DC_ACC;
dc_a <= DRAM_ADR[24:0];
ic_c <= IC_ACC;
ic_a <= IDRAM_ADR[24:0];
end
always @(negedge MCLK) addr[24:9] <= dma_c[1] ? dma_a[24:9] : (dc_c ? dc_a[24:9] : ic_a[24:9]);
always @(negedge MCLK) addr[8:0] <= dc_c ? dc_a[8:0] : ic_a[8:0];
 
always @(negedge MCLK) top_match = (addr[24:9] == WRA[24:9]);
always @(negedge MCLK) bot_match = (addr[8:4] == WRA[8:4]);
// +++++++++++++++++++++++++++++++
always @(negedge MCLK) request <= {WR_REQ,dma_c[1],dc_c,ic_c};
always @(*)
casex ({check_op,refreq,request})
6'b11_xxxx : begin
cmd_out <= 3'b001; // Refresh : RAS/CAS/WE , active low
ADDR_FF <= 15'hxxxx;
col_adr <= 10'hxxx;
wr_flag <= 1'b0;
col_cou <= 6'h00;
new_sta <= 3'd5;
dest_i <= 3'b000;
do_frez <= 3'b000;
end
6'b10_1xxx : begin
cmd_out <= 3'b011; // Activate WRITE Zugriff
ADDR_FF <= {WRA[11:10],WRA[24:12]}; // 1 kB Page , BA = MSB
col_adr <= {WRA[11:4],2'b00};
wr_flag <= 1'b0;
col_cou <= 6'h00;
new_sta <= 3'd5;
dest_i <= 3'b100;
do_frez <= 3'b100;
end
6'b10_01xx : begin
cmd_out <= 3'b011; // Activate DMA Zugriff
ADDR_FF <= {addr[11:10],addr[24:12]};
col_adr <= {addr[11:9],7'b0};
wr_flag <= DMA_WR;
col_cou <= 6'h3F;
new_sta <= 3'd5;
dest_i <= 3'b100;
do_frez <= 3'b010;
end
6'b10_001x : begin
cmd_out <= 3'b011; // Activate DCACHE
ADDR_FF <= {addr[11:10],addr[24:12]};
col_adr <= addr[11:2];
wr_flag <= 1'b0;
col_cou <= 6'h01;
new_sta <= 3'd5;
dest_i <= 3'b010;
do_frez <= 3'b011;
end
6'b10_0001 : begin
cmd_out <= 3'b011; // Activate ICACHE
ADDR_FF <= {addr[11:10],addr[24:12]};
col_adr <= addr[11:2];
wr_flag <= 1'b0;
col_cou <= 6'h01;
new_sta <= 3'd5;
dest_i <= 3'b001;
do_frez <= 3'b011;
end
default : begin
cmd_out <= cmd_reg;
ADDR_FF <= adr_reg;
col_adr <= 10'hxxx;
wr_flag <= 1'b0;
col_cou <= 6'h00;
new_sta <= 3'd0;
dest_i <= 3'b000;
do_frez <= 3'b000;
end
endcase
assign CMD_FF = {(cmd_out[2:1] == 2'b11),cmd_out}; // generate CS , BST is suppressed
 
// Control signals:
always @(negedge MCLK) frez_ctrl <= do_frez;
assign FREEZE = frez_ctrl[2]
| (frez_ctrl[1] & top_match & WB_USED & (~frez_ctrl[0] | bot_match));
always @(negedge MCLK) if ((state == 3'd5) && (lsbcou == 2'd0)) wr_up <= FREEZE;
always @(negedge MCLK) if (check_op) wr_dma <= wr_flag;
always @(negedge MCLK) if (check_op) dest <= dest_i;
always @(negedge MCLK) if (check_op) rd_op <= addr[1];
always @(negedge MCLK) if (check_op) rw_acc <= cmd_out[1];
always @(negedge MCLK) if (check_op) do_wr <= do_frez[2];
assign dma_op = dest[2];
// +++++++++++++++ Master State-Machine +++++++++++++++++++++++++++++++++
always @(negedge MCLK or negedge MRESET)
if (!MRESET) lsbcou <= 2'd0;
else lsbcou <= lsbcou + {1'b0,(state != 3'd0)};
 
always @(negedge MCLK or negedge MRESET)
if (!MRESET) state <= 3'd0;
else
begin
if (check_op || (lsbcou == 2'd3))
casex ({wr_up,do_wr,rw_acc,ende,state}) // Die Sequenz 5-2-0 wird fuer Refresh genutzt !
// 0 : nothing to do
7'bxx_xx_000 : state <= new_sta;
// 5 : Master-State : from here go to ...
7'b1x_xx_101 : state <= 3'd4; // Write necessary
7'b0x_xx_101 : state <= 3'd2; // general read access : Caches/DMA
// 4 : 1. Clock Write to DRAM
7'bxx_xx_100 : state <= 3'd3; //
// 3 : at the end of Write split to ...
7'bx1_xx_011 : state <= 3'd0; // only Write , back to start
7'bx0_xx_011 : state <= 3'd2; // general read access : Caches/DMA
// 2 : Data read or write : DMA can also write
7'bxx_0x_010 : state <= 3'd0; // Refresh is only 2 states long
7'bxx_10_010 : state <= 3'd2; // not last Burst
7'bxx_11_010 : state <= 3'd1; // access finished
// 1 : last State
7'bxx_xx_001 : state <= 3'd0; // back to start
default : state <= 3'bxxx; // should not happen
endcase
end
// +++++++++++++++++++++++++++++++++++++++++++++++++
// Page-Length is only 512 Word : A8-A0 at DRAM
always @(negedge MCLK) CLR_REQ <= (state == 3'd4) & ~lsbcou[1];
assign do_col_op = (state != 3'd0) & (lsbcou == 2'd0) & rw_acc;
always @(*)
casex ({do_col_op,state})
4'b1_101 : col_code = {2'b10,~(FREEZE | wr_dma)};
4'b1_100 : col_code = 3'b100;
4'b1_011 : col_code = do_wr ? 3'b111 : {2'b10,~wr_dma};
4'b1_010 : col_code = {2'b10,~wr_dma};
4'b1_001 : col_code = 3'b111;
default : col_code = 3'b111;
endcase
always @(negedge MCLK) cmd_reg <= enadram ? col_code : cmd_i;
 
always @(negedge MCLK) do_count <= (state == 3'd2) & (lsbcou == 2'd0);
always @(negedge MCLK)
if (check_op) col_count <= col_cou;
else
if (do_count) col_count <= col_count - {5'h0,~ende};
always @(negedge MCLK) ende <= (col_count == 6'h00);
always @(negedge MCLK) inc_op <= ~cmd_out[1];
assign inc_cadr = {5'h0,(dma_op & ~(wr_up & ((state == 3'd5) | (state == 3'd4))))};
always @(negedge MCLK)
if (check_op) cadr <= col_adr;
else
if (inc_op) cadr <= {cadr[11:9],(cadr[8:3] + inc_cadr),cadr[2]};
assign autopre = ((state == 3'd2) & (col_count == 6'h01))
| ((state == 3'd4) & do_wr);
always @(*)
casex (state)
3'd5 : lsb_reg <= cadr[3:2];
3'd4 : lsb_reg <= 2'b10;
3'd3 : lsb_reg <= cadr[3:2];
3'd2 : lsb_reg <= dma_op ? cadr[3:2] : {~cadr[3],1'b0};
default : lsb_reg <= cadr[3:2];
endcase
 
always @(negedge MCLK) if (check_op) upd_adr <= WRA[8:4];
assign low_adr = FREEZE ? 2'b00 : lsb_reg;
assign mid_adr = (FREEZE | (state == 3'd4)) ? upd_adr : cadr[8:4];
always @(negedge MCLK) adr_reg <= enadram ? {cadr[11:10],addr_i[12:11],autopre,1'b0,cadr[9],mid_adr,low_adr,1'b0} : addr_i;
always @(negedge MCLK) if (check_op) pipe_lsb <= col_adr[3:2];
// +++++++++++++++++++++ generate external signals ++++++++++++++++++++++++++++++++
assign init_c = (state == 3'd2) & (lsbcou == 2'd0);
always @(negedge MCLK) cap_puls <= init_c;
assign burst_add = (burst_c != 3'b000);
always @(posedge MCLK or negedge MRESET)
if (!MRESET) burst_c <= 3'd0;
else
begin
if (init_c) burst_c <= 3'b111;
else
burst_c <= burst_c + {{3{burst_add}}};
end
 
always @(posedge MCLK) DWCTRL[2] <= cap_puls & dest[1];
always @(posedge MCLK) DWCTRL[1] <= burst_c[0] & dest[1] & rd_op;
always @(posedge MCLK) DWCTRL[0] <= 1'b0;
always @(posedge MCLK) IWCTRL[2] <= cap_puls & dest[0];
always @(posedge MCLK) IWCTRL[1] <= burst_c[0] & dest[0] & rd_op;
always @(posedge MCLK) IWCTRL[0] <= 1'b0;
always @(posedge MCLK) WAMUX <= (init_c & dest[1] & rd_op) | (WAMUX & burst_add);
assign LDEN = burst_c[0];
 
always @(posedge MCLK) new_lsba <= burst_c[0];
always @(posedge MCLK)
if (init_c) lsba_c <= pipe_lsb;
else
if (new_lsba) lsba_c <= burst_c[1] ? {lsba_c[1],~lsba_c[0]} : {~lsba_c[1],1'b0};
assign WADDR = {cadr[11:4],lsba_c};
always @(negedge MCLK) dc_ende <= dest[1] & (state == 3'd2) & (lsbcou == 2'd2);
always @(posedge BCLK) DC_MDONE <= dc_ende;
always @(negedge MCLK) ic_ende <= dest[0] & (state == 3'd2) & (lsbcou == 2'd2);
always @(posedge BCLK) pipeicmd <= ic_ende;
always @(posedge BCLK) IC_MDONE <= pipeicmd;
always @(negedge MCLK) if (do_col_op) DATMUX <= ((state == 3'd5) & FREEZE) | (state == 3'd4);
 
always @(posedge MCLK) RD_DONE <= (init_c & dma_op & ~wr_dma) | (RD_DONE & burst_add);
assign WR_DONE = (state != 3'd0) & (state != 3'd4) & wr_dma;
always @(negedge MCLK) dqm_kurz <= ((state == 3'd5) | (state == 3'd3)) & (lsbcou == 2'b00) & rw_acc;
always @(negedge MCLK) if (lsbcou == 2'd1) dqm_lang <= ((state == 3'd5) | (state == 3'd3) | (state == 3'd2)) & rw_acc;
assign DQM_FF = DATMUX ? ~WB_BE : ( (dqm_lang | dqm_kurz) ? 2'b00 : 2'b11 );
 
always @(negedge MCLK) if (do_col_op) oe_flag <= (((state == 3'd5) & FREEZE) | (state == 3'd4))
| (((state == 3'd5) | (state == 3'd3) | (state == 3'd2)) & wr_dma);
always @(negedge MCLK) oe_t2 <= oe_flag;
always @(posedge MCLK) OE <= oe_flag | oe_t2;
// +++++++++++++++ Refresh Controller +++++++++++++++++++++++
 
if (!enadram) reftimer <= 10'h0;
else
begin
if (reftimer == 10'd780) reftimer <= 10'h0;
else
reftimer <= reftimer + 10'h1;
end
always @(negedge MCLK)
if (!enadram) refreq <= 1'b0;
else
begin
if (reftimer == 10'd780) refreq <= 1'b1;
else
if (check_op && (CMD_FF[2:1] == 2'b00)) refreq <= 1'b0;
end
// ++++++++++++++ DRAM Initialisierungs Controller +++++++++++++++++++++++++++
// CKE is active high : Clock-Enable , at 0 = Powerdown/SRF
always @(negedge MCLK) CKE_FF <= MRESET;
always @(negedge MCLK) icounter <= MRESET ? (icounter + 15'd1) : 15'h0;
assign ena = (icounter[14:8] == 7'h70) & (icounter[3:0] == 4'hF) & ~enadram;
always @(negedge MCLK)
casex ({ena,icounter[7:4]})
5'b1_0001 : cmd_i <= 3'b010; // PRE Precharge , active low !
5'b1_01xx : cmd_i <= 3'b001; // 4 * ARF
5'b1_10xx : cmd_i <= 3'b001; // 4 * ARF
5'b1_1101 : cmd_i <= 3'b000; // MRS
default : cmd_i <= 3'b111; // NOP bzw. DESELECT
endcase
// MRS : CL=2 , Sequentiell , Burstlaenge = 4
always @(negedge MCLK) addr_i <= ((icounter[7:4] == 4'hD) & ena) ? 15'h0022 : 15'h7FFF;
always @(negedge MCLK) enadram <= MRESET & (enadram | (icounter[14:8] == 7'h71));
endmodule
 
module DRAMIF (DRAM_DI, DC_WR, BRESET, MCLK, BCLK, DC_ACC, DRAM_ADR, IC_ACC, IDRAM_ADR, DMA_ACC, DMA_WR, DMA_ADR, MCLK_DIN, DMA_DI,
ENWR, MCLK_EXT, CKE, CMD, ADDR, WR_DONE, RD_DONE, IC_MDONE, IWCTRL, WAMUX, WADDR, DC_MDONE, DWCTRL, DQM, DRAM_Q, DQ );
input [35:0] DRAM_DI;
input DC_WR;
input BRESET;
input MCLK;
input BCLK;
input DC_ACC;
input [27:0] DRAM_ADR;
input IC_ACC;
input [27:0] IDRAM_ADR;
input DMA_ACC;
input DMA_WR;
input [27:9] DMA_ADR;
input MCLK_DIN;
input [15:0] DMA_DI;
output ENWR;
output WR_DONE;
output RD_DONE;
output IC_MDONE;
output [2:0] IWCTRL;
output WAMUX;
output [11:2] WADDR;
output DC_MDONE;
output [2:0] DWCTRL;
output [31:0] DRAM_Q;
output MCLK_EXT;
output CKE;
output [3:0] CMD;
output [14:0] ADDR;
output [1:0] DQM;
inout [15:0] DQ;
reg MRESET;
reg RCKE;
reg [3:0] RCMD;
reg [14:0] RADR;
reg [1:0] RDQM;
reg [15:0] RDIN,RDQL,RDQ;
wire CKE_FF;
wire [3:0] CMD_FF;
wire [14:0] ADDR_FF;
wire [1:0] DQM_FF;
wire WB_USED;
wire [24:4] WRA;
wire WR_REQ;
wire [1:0] WB_BE;
wire LDEN,OE,DATMUX;
wire FREEZE,CLR_REQ;
wire [15:0] WBDAT,BUSM;
wire [5:2] WRA_WB;
wire [5:1] RDA_WB;
reg [7:0] mem_3 [0:15];
reg [7:0] mem_2 [0:15];
reg [7:0] mem_1 [0:15];
reg [7:0] mem_0 [0:15];
reg [7:0] data_3,data_2,data_1,data_0;
reg outmux;
always @(negedge MCLK) MRESET <= BRESET;
always @(negedge MCLK) // Memory Signals
begin
RCKE <= CKE_FF;
RCMD <= CMD_FF;
RADR <= ADDR_FF;
RDQM <= DQM_FF;
RDQ <= BUSM;
end
assign CKE = RCKE;
assign CMD = RCMD;
assign ADDR = RADR;
assign DQM = RDQM;
always @(posedge MCLK_DIN) RDIN <= DQ;
always @(posedge MCLK) if (LDEN) RDQL <= RDIN;
assign DRAM_Q = {RDIN,RDQL};
assign DQ = OE ? RDQ : 16'hzzzz;
assign BUSM = DATMUX ? WBDAT : DMA_DI;
assign MCLK_EXT = MCLK;
DRAM_SM SM_DRAM(
.MCLK(MCLK),
.DMA_ACC(DMA_ACC),
.DMA_WR(DMA_WR),
.BCLK(BCLK),
.MRESET(MRESET),
.WR_REQ(WR_REQ),
.WB_USED(WB_USED),
.IC_ACC(IC_ACC),
.DC_ACC(DC_ACC),
.DMA_ADR(DMA_ADR),
.DRAM_ADR(DRAM_ADR),
.IDRAM_ADR(IDRAM_ADR),
.WB_BE(WB_BE),
.WRA(WRA),
.OE(OE),
.CKE_FF(CKE_FF),
.LDEN(LDEN),
.RD_DONE(RD_DONE),
.WR_DONE(WR_DONE),
.IC_MDONE(IC_MDONE),
.DC_MDONE(DC_MDONE),
.WAMUX(WAMUX),
.FREEZE(FREEZE),
.ADDR_FF(ADDR_FF),
.CMD_FF(CMD_FF),
.DATMUX(DATMUX),
.DQM_FF(DQM_FF),
.DWCTRL(DWCTRL),
.IWCTRL(IWCTRL),
.CLR_REQ(CLR_REQ),
.WADDR(WADDR));
 
WB_CONTROL WBC(
.MCLK(MCLK),
.MRESET(MRESET),
.BCLK(BCLK),
.BRESET(BRESET),
.CLR_REQ(CLR_REQ),
.FREEZE(FREEZE),
.DRAM_WR(DC_WR),
.ENBYTE(DRAM_DI[35:32]),
.WR_ADDR(DRAM_ADR[24:2]),
.ENWR(ENWR),
.WB_USED(WB_USED),
.WR_REQ(WR_REQ),
.RDA_WB(RDA_WB),
.WB_BE(WB_BE),
.WRA(WRA),
.WRA_WB(WRA_WB));
 
// Memory of Write Buffer
always @(posedge BCLK) if (DC_WR && DRAM_DI[35]) mem_3[WRA_WB] <= DRAM_DI[31:24];
always @(posedge BCLK) if (DC_WR && DRAM_DI[34]) mem_2[WRA_WB] <= DRAM_DI[23:16];
always @(posedge BCLK) if (DC_WR && DRAM_DI[33]) mem_1[WRA_WB] <= DRAM_DI[15:8];
always @(posedge BCLK) if (DC_WR && DRAM_DI[32]) mem_0[WRA_WB] <= DRAM_DI[7:0];
 
always @(negedge MCLK) data_3 <= mem_3[RDA_WB[5:2]];
always @(negedge MCLK) data_2 <= mem_2[RDA_WB[5:2]];
always @(negedge MCLK) data_1 <= mem_1[RDA_WB[5:2]];
always @(negedge MCLK) data_0 <= mem_0[RDA_WB[5:2]];
always @(negedge MCLK) outmux <= RDA_WB[1];
assign WBDAT = outmux ? {data_3,data_2} : {data_1,data_0};
endmodule
/trunk/DE0-Nano/DE0-Nano.sof Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/DE0-Nano/DE0-Nano.sof
trunk/DE0-Nano/DE0-Nano.sof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/DE0-Nano/bootcode.mif =================================================================== --- trunk/DE0-Nano/bootcode.mif (nonexistent) +++ trunk/DE0-Nano/bootcode.mif (revision 18) @@ -0,0 +1,67 @@ +-- Program Source : test.32K + +WIDTH=32; +DEPTH=256; + +ADDRESS_RADIX=UNS; +DATA_RADIX=HEX; + +CONTENT BEGIN + 0 : A85C385F ; + 1 : 001000C8 ; + 2 : 0000A66F ; + 3 : AA7FFE0B ; + 4 : 200000C8 ; + 5 : 00000000 ; + 6 : 00000000 ; + 7 : 00000000 ; + 8 : 0000A4EF ; + 9 : A56F0002 ; + 10 : 00030000 ; + 11 : 00C83D54 ; + 12 : D8670020 ; + 13 : 80D8271E ; + 14 : 970823A8 ; + 15 : 040000A0 ; + 16 : D7089400 ; + 17 : 00000E10 ; + 18 : 00001A7F ; + 19 : 00000000 ; + 20 : 5780D827 ; + 21 : 5C12A054 ; + 22 : 00A0D720 ; + 23 : 04204E00 ; + 24 : 41543FA1 ; + 25 : 54071A00 ; + 26 : 0EEA2441 ; + 27 : A1A82194 ; + 28 : 1A339C07 ; + 29 : 12415405 ; + 30 : C800A574 ; + 31 : BF000010 ; + 32 : A0A0CE14 ; + 33 : 541178FF ; + 34 : 1000C82D ; + 35 : 64A19400 ; + 36 : 301C378C ; + 37 : 208F7C1A ; + 38 : CF3FA128 ; + 39 : 008F441F ; + 40 : B7BF0FCC ; + 41 : 00ACBFEA ; + 42 : 08040201 ; + 43 : 80402010 ; + 44 : 20408000 ; + 45 : 02040810 ; + 46 : 03010001 ; + 47 : 30180C06 ; + 48 : 8000C060 ; + 49 : 183060C0 ; + 50 : 0003060C ; + 51 : 0E070301 ; + 52 : E070381C ; + 53 : E0C08000 ; + 54 : 0E1C3870 ; + 55 : 00000007 ; + [56..255] : 00000000 ; +END; Index: trunk/DE0-Nano/DE0-Nano.qsf =================================================================== --- trunk/DE0-Nano/DE0-Nano.qsf (nonexistent) +++ trunk/DE0-Nano/DE0-Nano.qsf (revision 18) @@ -0,0 +1,272 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 10.1 Build 153 11/29/2010 SJ Web Edition +# Date created = 23:02:04 November 01, 2015 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# SECP_TS20_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name TOP_LEVEL_ENTITY "DE0-Nano" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:02:04 NOVEMBER 01, 2015" +set_global_assignment -name LAST_QUARTUS_VERSION 10.1 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_location_assignment PIN_A10 -to ADC_CSN +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_CSN +set_location_assignment PIN_B10 -to ADC_SADDR +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_SADDR +set_location_assignment PIN_A9 -to ADC_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_SDAT +set_location_assignment PIN_B14 -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_SCLK +set_location_assignment PIN_L4 -to ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[12] +set_location_assignment PIN_N1 -to ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[11] +set_location_assignment PIN_N2 -to ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[10] +set_location_assignment PIN_P1 -to ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[9] +set_location_assignment PIN_R1 -to ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[8] +set_location_assignment PIN_T6 -to ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[7] +set_location_assignment PIN_N8 -to ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[6] +set_location_assignment PIN_T7 -to ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[5] +set_location_assignment PIN_P8 -to ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[4] +set_location_assignment PIN_M8 -to ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[3] +set_location_assignment PIN_N6 -to ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[2] +set_location_assignment PIN_N5 -to ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[1] +set_location_assignment PIN_P2 -to ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADDR[0] +set_location_assignment PIN_M6 -to BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BA[1] +set_location_assignment PIN_M7 -to BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BA[0] +set_location_assignment PIN_L1 -to CAS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAS +set_location_assignment PIN_L7 -to CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CKE +set_location_assignment PIN_P6 -to CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CS +set_location_assignment PIN_F2 -to DE0_I2C[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_I2C[1] +set_location_assignment PIN_F1 -to DE0_I2C[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_I2C[0] +set_location_assignment PIN_K1 -to DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[15] +set_location_assignment PIN_N3 -to DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[14] +set_location_assignment PIN_P3 -to DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[13] +set_location_assignment PIN_R5 -to DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[12] +set_location_assignment PIN_R3 -to DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[11] +set_location_assignment PIN_T3 -to DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[10] +set_location_assignment PIN_T2 -to DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[9] +set_location_assignment PIN_T4 -to DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[8] +set_location_assignment PIN_R7 -to DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[7] +set_location_assignment PIN_J1 -to DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[6] +set_location_assignment PIN_J2 -to DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[5] +set_location_assignment PIN_K2 -to DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[4] +set_location_assignment PIN_K5 -to DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[3] +set_location_assignment PIN_L8 -to DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[2] +set_location_assignment PIN_G1 -to DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[1] +set_location_assignment PIN_G2 -to DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQ[0] +set_location_assignment PIN_L3 -to DE0_LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_LED[7] +set_location_assignment PIN_B1 -to DE0_LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_LED[6] +set_location_assignment PIN_F3 -to DE0_LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_LED[5] +set_location_assignment PIN_D1 -to DE0_LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_LED[4] +set_location_assignment PIN_A11 -to DE0_LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_LED[3] +set_location_assignment PIN_B13 -to DE0_LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_LED[2] +set_location_assignment PIN_A13 -to DE0_LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_LED[1] +set_location_assignment PIN_A15 -to DE0_LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DE0_LED[0] +set_location_assignment PIN_E1 -to KEY_SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to KEY_SW[5] +set_location_assignment PIN_J15 -to KEY_SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to KEY_SW[4] +set_location_assignment PIN_M15 -to KEY_SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to KEY_SW[3] +set_location_assignment PIN_B9 -to KEY_SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to KEY_SW[2] +set_location_assignment PIN_T8 -to KEY_SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to KEY_SW[1] +set_location_assignment PIN_M1 -to KEY_SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to KEY_SW[0] +set_location_assignment PIN_R8 -to RCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK +set_location_assignment PIN_R4 -to MCLK_EXT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MCLK_EXT +set_location_assignment PIN_L2 -to RAS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAS +set_location_assignment PIN_C2 -to WE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WE +set_location_assignment PIN_T5 -to DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQM[1] +set_location_assignment PIN_R6 -to DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQM[0] +set_location_assignment PIN_G5 -to G_SENSOR_CSN +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to G_SENSOR_CSN +set_location_assignment PIN_M2 -to G_SENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to G_SENSOR_INT +set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3 +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name DISABLE_OCP_HW_EVAL ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF +set_global_assignment -name AUTO_ROM_RECOGNITION OFF +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation + +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SENSE +set_location_assignment PIN_J14 -to DRV0 +set_location_assignment PIN_J13 -to SENSE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DRV0 +set_global_assignment -name SEARCH_PATH "c:/qdesigns/example_v2" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAMIF:DRAM_IF|RCKE" +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAMIF:DRAM_IF|RCMD" +set_instance_assignment -name FAST_INPUT_REGISTER ON -to "DRAMIF:DRAM_IF|RDIN" +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAMIF:DRAM_IF|RADR" +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAMIF:DRAM_IF|RDQ" +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAMIF:DRAM_IF|RDQM" +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to MCLK_EXT +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to RAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to WE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to ADDR[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQM[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to DQM[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SENSE +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to DRV0 +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to DE0_LED +set_global_assignment -name VERILOG_FILE ../../qdesigns/example_V2/I_PFAD.v +set_global_assignment -name VERILOG_FILE ../../qdesigns/example_V2/ALIGNER.v +set_global_assignment -name VERILOG_FILE ../../qdesigns/example_V2/TOP_MISC.v +set_global_assignment -name VERILOG_FILE ../../qdesigns/example_V2/STEUER_MISC.v +set_global_assignment -name VERILOG_FILE ../../qdesigns/example_V2/REGISTERS.v +set_global_assignment -name VERILOG_FILE ../../qdesigns/example_V2/CACHE_LOGIK.v +set_global_assignment -name BDF_FILE "DE0-Nano.bdf" +set_global_assignment -name VERILOG_FILE DRAMIF.v +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name MISC_FILE "C:/qdesigns101/DE0-Nano/DE0-Nano.dpf" +set_location_assignment PIN_J16 -to NRST +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to NRST +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to NRST +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name SEED 1 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: trunk/DE0-Nano/DE0-Nano.sdc =================================================================== --- trunk/DE0-Nano/DE0-Nano.sdc (nonexistent) +++ trunk/DE0-Nano/DE0-Nano.sdc (revision 18) @@ -0,0 +1,109 @@ +## Copyright (C) 1991-2008 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition" + +## DATE "Mon Mar 08 15:49:34 2010" + +## +## DEVICE "EP4CE22F17C6" +## + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clock_ref} -period 20.000 -waveform { 0.000 10.000 } [get_ports {RCLK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + +#derive_pll_clocks +#create_generated_clock -name {clock_4} -source [get_ports {CLK12}] -divide_by 3 -master_clock {clock_12} [get_registers {TEST_CONTROL:INSTAGE|takt[2]}] +# Info: Node: PCM_CLOCK|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 67.819 +#create_generated_clock -name {clock_} -source [get_ports {MCLK_IN}] -divide_by 50 -multiply_by 4 [get_registers {DRAM_IF|MPLL|altpll_component|pll|clk[0]}] +create_generated_clock -name {clock_bclk} -source [get_ports {RCLK}] -divide_by 1 -multiply_by 1 [get_pins {MPLL|altpll_component|auto_generated|pll1|clk[0]}] +create_generated_clock -name {clock_mclk} -source [get_ports {RCLK}] -divide_by 1 -multiply_by 2 [get_pins {MPLL|altpll_component|auto_generated|pll1|clk[2]}] +create_generated_clock -name {clock_mclkm} -source [get_ports {RCLK}] -phase 45 -divide_by 1 -multiply_by 2 [get_pins {MPLL|altpll_component|auto_generated|pll1|clk[3]}] +# Warning: Node: DRAM_IF|MPLL|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 40.000 + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +set_clock_uncertainty 0.1 -to clock_ref +set_clock_uncertainty 0.1 -to clock_bclk +set_clock_uncertainty 0.1 -to clock_mclk +set_clock_uncertainty 0.1 -to clock_mclkm + +#set_clock_uncertainty 0.0ns -to PCM_CLOCK|altpll_component|auto_generated|pll1|clk[0] + +#************************************************************** +# Set Input Delay +#************************************************************** + + +#************************************************************** +# Set Output Delay +#************************************************************** + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + Index: trunk/DE0-Nano/read_me.txt =================================================================== --- trunk/DE0-Nano/read_me.txt (nonexistent) +++ trunk/DE0-Nano/read_me.txt (revision 18) @@ -0,0 +1,24 @@ +++++++++++++++++++++++++++ Demonstration System ++++++++++++++++++++++++++++++ + +This is a small demo of M32632 running on a DE0-Nano board. The CPU is running +at 50 MHz and uses the on-board SDRAM. The SDRAM is running at 100 MHz. The demo +uses the 8 LEDs on board. 3 pins have functions which can be used by the user. +GPIO_133 is driving GND = 0 Volt +GPIO_130 is RST_N, connecting it to GPIO_133 will reset the CPU +GPIO_132 is SENSE, when connected to GPIO_133 will be inverting the LED output + +The only file needed for the demo is DE0-Nano.sof . Simply download it to your +DE0-Nano board and watch the LEDs. If you want to change something you have +to create a project called DE0-Nano in Quartus. Load all of the files in this +directory and the M32632 files in the directory "rtl" to your project directory. + +The top-level of this design is a scheamtic: DE0-Nano.bdf . This is unusual for +opencores but this time the demo is only for a specific device! A schematic +gives a good overview of the connections between the modules. The BOOT_ROM.v +is included in PERIMOD.v + +Then you compile the design. A small change would be to add a pin which stops +LED flashing. You can create a new program with the help of "software/ans32k.exe". +The example program is given in test.32K. + +Hopefully everything is running ok. If not put your questions to fpga@cpu-ns32k.net . \ No newline at end of file Index: trunk/DE0-Nano/DE0-Nano.bdf =================================================================== --- trunk/DE0-Nano/DE0-Nano.bdf (nonexistent) +++ trunk/DE0-Nano/DE0-Nano.bdf (revision 18) @@ -0,0 +1,2191 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 848 160 1016 176) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "KEY_SW[5..0]" (rect 5 0 85 14)(font " Arial" (font_size 8))) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 848 128 1016 144) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "DE0_I2C[1..0]" (rect 5 0 80 14)(font " Arial" (font_size 8))) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 848 192 1016 208) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "ADC_SDAT" (rect 5 0 71 14)(font " Arial" (font_size 8))) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 840 216 1016 232) + (text "INPUT" (rect 141 0 169 10)(font "Arial" (font_size 6))) + (text "G_SENSOR_INT" (rect 5 0 95 14)(font " Arial" (font_size 8))) + (pt 176 8) + (drawing + (line (pt 100 12)(pt 125 12)) + (line (pt 100 4)(pt 125 4)) + (line (pt 129 8)(pt 176 8)) + (line (pt 100 12)(pt 100 4)) + (line (pt 125 4)(pt 129 8)) + (line (pt 125 12)(pt 129 8)) + ) + (text "VCC" (rect 144 7 164 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 96 48 264 64) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "RCLK" (rect 5 0 36 14)(font "Arial" (font_size 8))) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 96 -128 264 -112) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "SENSE" (rect 5 0 43 14)(font " Arial" (font_size 8))) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 96 -224 264 -208) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "NRST" (rect 5 0 36 14)(font "Arial" (font_size 8))) + (pt 168 8) + (drawing + (line (pt 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(line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1360 -784 1488 -768)) +) +(pin + (output) + (rect 1152 -128 1328 -112) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "DE0_LED[7..0]" (rect 90 0 170 14)(font " Arial" (font_size 8))) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 1152 96 1328 112) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "ADC_SCLK" (rect 90 0 154 14)(font " Arial" (font_size 8))) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 1152 136 1328 152) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" 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(font_size 10)))(border)) + (section (rect 240 96 310 120)(text "SHEET" (rect 2 0 37 12)(font "Arial" ))(text "1" (rect 55 5 63 21)(font "Arial" (font_size 10)))) + (section (rect 0 0 368 24)(text "TITLE" (rect 2 0 30 12)(font "Arial" ))(text "DE0-Nano" (rect 56 2 143 20)(font "Arial" (font_size 12)))(border)) + (drawing + ) +) Index: trunk/DE0-Nano/test.32K =================================================================== --- trunk/DE0-Nano/test.32K (nonexistent) +++ trunk/DE0-Nano/test.32K (revision 18) @@ -0,0 +1,59 @@ +; Testprogram , 14.8.2016 + movqd 0,r7 + movqb 0,@x'8001000 + lprd cfg,x'BFE ; Direct Exception, Interrupts not vektor + jump @x'8000020 + + .align 32 + lprd sp,x'200 + lprd sb,x'300 + movb r7,@x'8002000 ; Enable DRAM +; Load program to DRAM + addr prog,r1 + addr ende,r0 + subd r1,r0 + movd x'400,r2 + movb r1,r2 + movd r2,r3 + movsb + jump r3 + +; Testprogramm + .align 16 +prog: addr data,r0 + movb 18,r1 +; Main loop +loop: movqb 0,r4 + movd 20000,r3 +lti: cmpb 63,r4 + movb 0(r0),r5 + bne L01 + movb 36(r0),r5 + br L02 +L01: movb r4,r6 + andb 7,r6 + cmpqb 7,r6 + bne L02 + movb 18(r0),r5 +L02: tbitb 0,@x'8100000 ; read SENSE pin + sfcd r2 + mulb x'FF,r2 + xorb r2,r5 + movb r5,@x'8001000 ; to LEDs + movb 100,r6 +time: addqb -1,r6 + cmpqb 0,r6 + bne time + addqd 1,r4 + andb 63,r4 + acbd -1,r3,lti +; + addqd 1,r0 + acbb -1,r1,loop + br prog ; to start again + +data: .byte 0,1,2,4, 8,16,32, 64,x'80,0,x'80,x'40,x'20, 16, 8, 4, 2,1 + .byte 0,1,3,6,12,24,48, 96,x'C0,0,x'80,x'C0,x'60, 48,24,12, 6,3 + .byte 0,1,3,7,14,28,56,112,x'E0,0,x'80,x'C0,x'E0,112,56,28,14,7 +ende: +

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