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URL https://opencores.org/ocsvn/m65c02/m65c02/trunk

Subversion Repositories m65c02

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  • This comparison shows the changes necessary to convert path 
    /m65c02/trunk/Sim
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/tb_M65C02.v
100,11 → 100,6
tri1 [15:0] A;
tri1 [ 7:0] DB;
 
//tri1 nSel;
//tri1 SCk;
//tri1 MOSI;
//reg MISO;
 
wire [4:0] LED;
 
// Define simulation variables
113,8 → 108,6
reg [ 7:0] TestNum;
reg [17:0] chkdad, chkadd;
 
//integer i = 0;
 
integer cycle_cnt = 0;
integer instr_cnt = 0;
 
121,20 → 114,15
integer Loop_Start = 0;
 
integer Hist_File = 0; // File handle for instruction histogram
//integer SV_Output = 0; // File handle for State Vector Outputs
 
reg [31:0] Hist [255:0]; // Instruction Histogram array
reg [31:0] val; // Instruction Histogram variable
reg [31:0] i, j; // loop counters
 
//reg [((5*8) - 1):0] Op; // Processor Mode Mnemonics String
//reg [((6*8) - 1):0] Opcode; // Opcode Mnemonics String
//reg [((9*8) - 1):0] AddrMd; // Addressing Mode Mnemonics String
 
// Instantiate the Unit Under Test (UUT)
 
M65C02 #(
.pBootROM_File("M65C02_Tst5.txt")
.pBootROM_File("Src/M65C02_Tst5.txt")
) uut (
.nRst(nRst),
.nRstO(nRstO),
144,7 → 132,6
.Phi1O(Phi1O),
.Phi2O(Phi2O),
 
.nSO(nSO),
.nNMI(nNMI),
.nIRQ(nIRQ),
.nVP(nVP),
155,8 → 142,8
 
.nCE(nCE),
.RnW(RnW),
.nWr(nWr),
.nOE(nOE),
.nWE(nWr),
.Rdy(Rdy),
.XA(XA),
.A(A),
164,39 → 151,18
 
.nWP_In(1'b0),
.nWait(nWait),
.nWait(nWait),
 
.LED(LED)
.LED(LED),
.nSel(nSel),
.SCk(SCk),
.MOSI(MOSI),
.MISO(MISO)
// .LED(LED),
//
// .nSel(nSel),
// .SCk(SCk),
// .MOSI(MOSI),
// .MISO(MISO)
);
 
//// Instantiate Boot/Monitor ROM Module
//
//wire [7:0] ROM_DO;
//reg ROM_WE;
//
//M65C02_RAM #(
// .pAddrSize(pRAM_AddrWidth),
// .pDataSize(8),
// .pFileName("M65C02_Tst3.txt")
// ) ROM (
// .Clk(~Phi2O),
//// .Ext(1'b1), // 4 cycle memory
//// .ZP(1'b0),
//// .Ext(1'b0), // 2 cycle memory
//// .ZP(1'b0),
// .Ext(1'b0), // 1 cycle memory
// .ZP(1'b1),
// .WE(ROM_WE),
// .AI(A[(pRAM_AddrWidth - 1):0]),
// .DI(DB),
// .DO(ROM_DO)
// );
 
// Instantiate RAM Module
 
wire [7:0] RAM_DO;
205,7 → 171,7
M65C02_RAM #(
.pAddrSize(pRAM_AddrWidth),
.pDataSize(8),
.pFileName("65C02_FT.txt")
.pFileName("Src/65C02_FT.txt")
) RAM (
.Clk(~Phi2O),
// .Ext(1'b1), // 4 cycle memory
228,8 → 194,6
Sim_nNMI = 0;
Sim_nIRQ = 0;
BE_In = 1;
//Rdy = 1;
//MISO = 1;
TestNum = 0;
chkdad = 0;
chkadd = 0;
245,14 → 209,11
cycle_cnt = 0;
Hist_File = $fopen("M65C02_Hist_File.txt", "w");
// SV_Output = $fopen("M65C02_SV_Output.txt", "w");
 
// Wait 100 ns for global reset to finish
 
#101 nRst = 1;
// Add stimulus here
// Start the Simulation Loop
wait(A == pSim_Loop);
276,8 → 237,13
@(posedge Phi1O);
@(posedge Phi1O);
@(posedge Phi1O);
$display("End of Simulation - Looping to Start detected/n");
$display("\tSuccess - All enabled tests passed.\n");
 
$display("\n\tTest Loop Complete\n");
$display("\tEnd of Simulation-Looping to Start detected\n");
$display("\t\tSuccess - All enabled tests passed.\n");
 
$fclose(Hist_File);
 
$stop;
end
end
317,10 → 283,8
 
// Connect ROM/RAM to M65C02 memory bus
 
//always @(*) ROM_WE <= Phi2O & A[15] & ~nWr;
always @(*) RAM_WE <= Phi2O & ~A[15] & ~nWr;
 
//assign DB = ((~nOE) ? ((A[15]) ? ROM_DO : RAM_DO) : {8{1'bZ}});
assign DB = ((~nOE) ? RAM_DO : {8{1'bZ}});
 
// Generate Simulate nIRQ signal based on writes by test program to address
347,7 → 311,7
begin
if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
cycle_cnt = 0;
else if(Phi1O & uut.C4)
else if(Phi1O & uut.Rdy)
cycle_cnt = ((A == 16'h0400) ? 1 : (cycle_cnt + 1));
end
 
355,7 → 319,7
begin
if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
instr_cnt = 0;
else if(Sync & Phi1O & uut.C4)
else if(Sync & Phi1O & uut.Rdy)
instr_cnt = ((A == 16'h0400) ? 1 : (instr_cnt + 1));
end
 
363,45 → 327,29
 
always @(posedge uut.ClkGen.Clk)
begin
// $fstrobe(SV_Output, "%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
// IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);
 
if(~(uut.ClkGen.Rst | ~uut.ClkGen.nRst)) begin
if(Sync & Phi2O & uut.C3) begin
if((A == 16'h0400)) begin
if(uut.Rdy & uut.uP.CE_IR) begin
if((A == pSim_Loop)) begin
if((Loop_Start == 1)) begin
for(i = 0; i < 16; i = i + 1)
for(j = 0; j < 16; j = j + 1) begin
for(i = 0; i < 16; i = i + 1) begin // lower nibble
for(j = 0; j < 16; j = j + 1) begin // upper nibble
val = Hist[(j * 16) + i];
Hist[(j * 16) + i] = 0;
if((j == 0))
$fwrite(Hist_File, "\n%h : %h", ((j * 16) + i), val);
if((j == 0) || (j == 8))
$fwrite(Hist_File, "\n%h : %d", (j*16)+i, val);
else
$fwrite(Hist_File, " %h", val);
$fwrite(Hist_File, " %d", val);
end
$fclose(Hist_File);
// $fclose(SV_Output);
 
$display("\nTest Loop Complete\n");
 
// $stop;
end
end else begin
Loop_Start = 1;
end
end
val = Hist[DB];
Hist[DB] = val + 1;
end
val = Hist[uut.uP.DI];
Hist[uut.uP.DI] = val + 1;
end
end
end
 
//// Test Monitor System Function
//
//always @(posedge Phi1O)
//begin
// $monitor("%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
// IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);
//end
 
endmodule
 

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