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    /mac_layer_switch/trunk
    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/rtl/verilog/switch.v
137,7 → 137,7
input [3:0] pi1,pi2,pi3,pi4,pi5,pi6;
output [3:0] po1, po2,po3, po4,po5, po6;
output [31:0] Dw1o,Dw2o,Dw3o,Dw4o,Dw5o,Dw6o;// to IBA
input [31:0] Dw1i,Dw2i,Dw3i,Dw4i,Dw5i,Dw6i;// from IBA
input [31:0] Dw1i,Dw2i,Dw3i,Dw4i,Dw5i,Dw6i;// from Xbar
output plu2iba_start_pack_1 , plu2iba_start_pack_2,plu2iba_start_pack_3,plu2iba_start_pack_4,plu2iba_start_pack_5,plu2iba_start_pack_6;
input iba2plu_start_pack_1 , iba2plu_start_pack_2,iba2plu_start_pack_3,iba2plu_start_pack_4,iba2plu_start_pack_5,iba2plu_start_pack_6;
output plu2iba_end_pack_1 , plu2iba_end_pack_2,plu2iba_end_pack_3,plu2iba_end_pack_4,plu2iba_end_pack_5,plu2iba_end_pack_6;
234,22 → 234,22
transmit_done5,
transmit_done6;
assign Dw1_iba_o=Dw1_iba_i; //initial LB configuration
assign Dw2_iba_o=Dw2_iba_i; //initial LB configuration
assign Dw3_iba_o=Dw3_iba_i; //initial LB configuration
assign Dw4_iba_o=Dw4_iba_i; //initial LB configuration
assign Dw5_iba_o=Dw5_iba_i; //initial LB configuration
assign Dw6_iba_o=Dw6_iba_i; //initial LB configuration
assign Dw1_iba_o=mem_u_o1;
assign Dw2_iba_o=mem_u_o2; //Dw2_iba_i for LB
assign Dw3_iba_o=mem_u_o3;
assign Dw4_iba_o=mem_u_o4;
assign Dw5_iba_o=mem_u_o5;
assign Dw6_iba_o=mem_u_o6;
 
assign iba2plu_start_pack_1 = plu2iba_start_pack_1;
assign iba2plu_start_pack_2 = plu2iba_start_pack_2;
assign iba2plu_start_pack_1 = 0;
assign iba2plu_start_pack_2 = 0;
assign iba2plu_start_pack_3 = plu2iba_start_pack_3;
assign iba2plu_start_pack_4 = plu2iba_start_pack_4;
assign iba2plu_start_pack_5 = plu2iba_start_pack_5;
assign iba2plu_start_pack_6 = plu2iba_start_pack_6;
 
assign iba2plu_end_pack_1 = plu2iba_end_pack_1;
assign iba2plu_end_pack_2 = plu2iba_end_pack_2;
assign iba2plu_end_pack_1 = 0;
assign iba2plu_end_pack_2 = 0;
assign iba2plu_end_pack_3 = plu2iba_end_pack_3;
assign iba2plu_end_pack_4 = plu2iba_end_pack_4;
assign iba2plu_end_pack_5 = plu2iba_end_pack_5;
330,6 → 330,11
//fifo Qps need to validate addr_valid in the end
Qp qp1(.reset(reset),.clk(clk),.transmit_done(transmit_done1),.Din(start_addr1),.start_adr(start_length1),.T_q(T_q1),.adr_valid(adr_valid1));
Qp qp2(.reset(reset),.clk(clk),.transmit_done(transmit_done2),.Din(start_addr2),.start_adr(start_length2),.T_q(T_q2),.adr_valid(adr_valid2));
Qp qp3(.reset(reset),.clk(clk),.transmit_done(transmit_done3),.Din(start_addr3),.start_adr(start_length3),.T_q(T_q3),.adr_valid(adr_valid3));
Qp qp4(.reset(reset),.clk(clk),.transmit_done(transmit_done4),.Din(start_addr4),.start_adr(start_length4),.T_q(T_q4),.adr_valid(adr_valid4));
Qp qp5(.reset(reset),.clk(clk),.transmit_done(transmit_done5),.Din(start_addr5),.start_adr(start_length5),.T_q(T_q5),.adr_valid(adr_valid5));
Qp qp6(.reset(reset),.clk(clk),.transmit_done(transmit_done6),.Din(start_addr6),.start_adr(start_length6),.T_q(T_q6),.adr_valid(adr_valid6));
endmodule
 
/rtl/verilog/plu_moduls.v
376,13 → 376,15
output TxStartFrm_0 , TxEndFrm_1;
// output TxStartFrm_ , TxEndFrm_;
reg clk_div2 ,clk_div4 ;
reg [2:0] mod4;
reg [1:0] mod4;
reg [1:0] mod4_;
reg [7:0] byte;
reg TxStartFrm_ , TxEndFrm_ ,TxStartFrm_1,TxStartFrm_2, start_en , start_en_ ,end_en , start_signal_detect;
reg [9:0] counter;
reg [1:0] FSMState;
wire TxStartFrm_0 , TxEndFrm_1;
initial begin
FSMState = 0;
mod4=0;
mod4_=0;
counter =0;
402,12 → 404,12
always @(posedge TxEndFrm )
begin
end_en<=1;
mod4 <=0 ;
// mod4 <=0 ;
end
always @(posedge TxStartFrm )
begin
mod4_ <= 0;
mod4 <= 0;
// mod4 <= 0;
counter=0;
// start_en<=1; //push simultaneously
//clk_div2=1;
427,7 → 429,7
begin
TxEndFrm_<=(mod4==4)?(~clk_div2)&end_en:TxEndFrm;
end_en<= (mod4==5)?0:end_en;
mod4<=mod4+1;
mod4_<=mod4_+1;
start_signal_detect = |Dword;
TxStartFrm_=start_signal_detect & clk_div2;
439,7 → 441,13
begin
TxStartFrm_ =0;
end
case(mod4_)
end
always @(negedge clk_div2)
begin
case(mod4)
 
2'h0: byte<= Dword[31:24] ;
2'h1: byte<= Dword[23:16] ;
446,9 → 454,42
2'h2: byte<= Dword[15:8] ;
2'h3: byte<= Dword[7:0] ;
endcase
end
end
always @ (posedge clk_div2)
begin
case (FSMState)
2'b00: begin // this is non recieving frame state
if (start_signal_detect == 0)
begin
//FSMState <= 2'b00;
mod4 <= 0;
end
else if (start_signal_detect == 1)
begin
FSMState <= 2'b11;
mod4 <= mod4+1;
end
end
// 2'b01: begin
// if (start_signal_detect == 1)
// begin
// FSMState <= 2'b11;
// mod4 <= 0;
// end
// end
2'b11: begin
if (start_signal_detect == 1)
begin
//FSMState <= 2'b11;
mod4 <= mod4 +1;
end
else if (start_signal_detect==0)
begin
FSMState<= 2'b00;
end
end
endcase
end
endmodule
 
/rtl/verilog/iba_modules.v
188,7 → 188,7
prev_input <= Dw_iba_i;
 
ram_we <= |(prev_input^Dw_iba_i); //ram_we pulse every word change
ram_oe <= (~|(prev_input^Dw_iba_i)) & read_argumets_valid_delay_unit2;
ram_oe <= (~|(prev_input^Dw_iba_i)) & read_argumets_valid_delay_unit1;
read_argumets_valid_delay_unit1 <= read_arguments_valid;
read_argumets_valid_delay_unit2 <=read_argumets_valid_delay_unit1;
end

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