URL
https://opencores.org/ocsvn/manchesterwireless/manchesterwireless/trunk
Subversion Repositories manchesterwireless
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- This comparison shows the changes necessary to convert path
/manchesterwireless
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/branches/singledouble/singleDouble/synthTest.ucf
0,0 → 1,18
#PACE: Start of Constraints generated by PACE |
|
#PACE: Start of PACE I/O Pin Assignments |
NET "ce_i" LOC = "k13" ; |
NET "clk" LOC = "t9" ; |
NET "data_i" LOC = "c10" ; |
NET "nd_new" LOC = "a13" ; |
NET "out_new<0>" LOC = "a12" ; |
NET "out_new<1>" LOC = "b11" ; |
NET "out_new<2>" LOC = "b10" ; |
NET "out_new<3>" LOC = "a8" ; |
NET "reset" LOC = "m13" ; |
|
#PACE: Start of PACE Area Constraints |
|
#PACE: Start of PACE Prohibit Constraints |
|
#PACE: End of Constraints generated by PACE |
/branches/singledouble/singleDouble/synthTest.vhd
0,0 → 1,68
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 16:03:52 06/22/2009 |
-- Design Name: |
-- Module Name: synthTest - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity synthTest is |
port ( |
clk : in std_logic; |
ce_i : in std_logic; |
reset : in std_logic; |
data_i : in std_logic; |
out_new : out std_logic_vector(3 downto 0); |
nd_new : out std_logic |
); |
end synthTest; |
|
architecture Behavioral of synthTest is |
|
|
COMPONENT singleDouble |
PORT( |
clk_i : in std_logic; |
ce_i : in std_logic; |
rst_i : in std_logic; |
data_i : in std_logic; |
q_o : out std_logic_vector(3 downto 0); |
ready_o : out std_logic |
); |
END COMPONENT; |
|
begin |
|
|
Inst_modified: singleDouble PORT MAP( |
clk_i => clk, |
ce_i => ce_i, |
rst_i => reset, |
data_i => data_i, |
q_o => out_new, |
ready_o => nd_new |
); |
|
end Behavioral; |
|
/branches/singledouble/singleDouble/simTest.vhd
9,16 → 9,6
|
architecture Behavioral of test_sim is |
|
COMPONENT singleDouble_original |
PORT( |
clk_i : in std_logic; |
ce_i : in std_logic; |
rst_i : in std_logic; |
data_i : in std_logic; |
q_o : out std_logic_vector(3 downto 0); |
ready_o : out std_logic |
); |
END COMPONENT; |
|
COMPONENT singleDouble |
PORT( |
34,8 → 24,6
signal clk : std_logic := '0'; |
signal ce_i : std_logic := '0'; |
signal mdi : std_logic := '0'; |
signal q_orig : std_logic_vector(3 downto 0); |
signal nd_orig : std_logic; |
signal q_modified : std_logic_vector(3 downto 0); |
signal nd_modified : std_logic; |
|
44,15 → 32,6
signal reset : std_logic := '1'; |
begin |
|
Inst_orig: singleDouble_original PORT MAP( |
clk_i => clk, |
ce_i => ce_i, |
rst_i => reset, |
data_i => mdi, |
q_o => q_orig, |
ready_o => nd_orig |
); |
|
Inst_modified: singleDouble PORT MAP( |
clk_i => clk, |
ce_i => ce_i, |
branches/singledouble/singleDouble
Property changes :
Added: svn:ignore
## -0,0 +1 ##
+synthTest.ucf