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    /mb-jpeg/tags/STEP1_1/microblaze_0/libsrc
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Rev 14 → Rev 66

/uartlite_v1_00_b/src/xuartlite_i.h
0,0 → 1,129
/* $Id: xuartlite_i.h,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite_i.h
*
* Contains data which is shared between the files of the XUartLite component.
* It is intended for internal use only.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 08/31/01 First release
* 1.00b jhl 02/21/02 Reparitioned the driver for smaller files
* 1.00b rpm 04/24/02 Moved register definitions to xuartlite_l.h and
* updated macro naming convention
* </pre>
*
*****************************************************************************/
 
#ifndef XUARTLITE_I_H /* prevent circular inclusions */
#define XUARTLITE_I_H /* by using protection macros */
 
/***************************** Include Files ********************************/
 
#include "xuartlite.h"
#include "xuartlite_l.h"
 
/************************** Constant Definitions ****************************/
 
/**************************** Type Definitions ******************************/
 
/***************** Macros (Inline Functions) Definitions ********************/
 
/****************************************************************************
*
* Update the statistics of the instance.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
* @param StatusRegister contains the contents of the UART status register
* to update the statistics with.
*
* @return
*
* None.
*
* @note
*
* Signature: void XUartLite_mUpdateStats(XUartLite *InstancePtr,
* Xuint32 StatusRegister)
*
*****************************************************************************/
#define XUartLite_mUpdateStats(InstancePtr, StatusRegister) \
{ \
if ((StatusRegister) & XUL_SR_OVERRUN_ERROR) \
{ \
(InstancePtr)->Stats.ReceiveOverrunErrors++; \
} \
if ((StatusRegister) & XUL_SR_PARITY_ERROR) \
{ \
(InstancePtr)->Stats.ReceiveParityErrors++; \
} \
if ((StatusRegister) & XUL_SR_FRAMING_ERROR) \
{ \
(InstancePtr)->Stats.ReceiveFramingErrors++; \
} \
}
 
/****************************************************************************
*
* Clear the statistics for the instance.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* Signature: void XUartLite_mClearStats(XUartLite *InstancePtr)
*
*****************************************************************************/
#define XUartLite_mClearStats(InstancePtr) \
{ \
(InstancePtr)->Stats.TransmitInterrupts = 0UL; \
(InstancePtr)->Stats.ReceiveInterrupts = 0UL; \
(InstancePtr)->Stats.CharactersTransmitted = 0UL; \
(InstancePtr)->Stats.CharactersReceived = 0UL; \
(InstancePtr)->Stats.ReceiveOverrunErrors = 0UL; \
(InstancePtr)->Stats.ReceiveFramingErrors = 0UL; \
(InstancePtr)->Stats.ReceiveParityErrors = 0UL; \
}
 
/************************** Variable Definitions ****************************/
 
/* the configuration table */
extern XUartLite_Config XUartLite_ConfigTable[];
 
/************************** Function Prototypes *****************************/
 
unsigned int XUartLite_SendBuffer(XUartLite *InstancePtr);
unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr);
 
 
#endif /* end of protection macro */
 
/uartlite_v1_00_b/src/xuartlite_stats.c
0,0 → 1,128
/* $Id: xuartlite_stats.c,v 1.1 2006-06-23 19:03:46 quickwayne Exp $ */
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite_stats.c
*
* This file contains the statistics functions for the UART Lite component
* (XUartLite).
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 08/31/01 First release
* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
 
#include "xbasic_types.h"
#include "xuartlite.h"
#include "xuartlite_i.h"
 
/************************** Constant Definitions ****************************/
 
 
/**************************** Type Definitions ******************************/
 
 
/***************** Macros (Inline Functions) Definitions ********************/
 
 
/************************** Variable Definitions ****************************/
 
 
/************************** Function Prototypes *****************************/
 
 
/****************************************************************************/
/**
*
* Returns a snapshot of the current statistics in the structure specified.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
* @param StatsPtr is a pointer to a XUartLiteStats structure to where the
* statistics are to be copied.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XUartLite_GetStats(XUartLite *InstancePtr, XUartLite_Stats *StatsPtr)
{
/*
* Assert validates the input arguments
*/
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(StatsPtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Copy the stats from the instance to the specified stats */
 
StatsPtr->TransmitInterrupts = InstancePtr->Stats.TransmitInterrupts;
StatsPtr->ReceiveInterrupts = InstancePtr->Stats.ReceiveInterrupts;
StatsPtr->CharactersTransmitted = InstancePtr->Stats.CharactersTransmitted;
StatsPtr->CharactersReceived = InstancePtr->Stats.CharactersReceived;
StatsPtr->ReceiveOverrunErrors = InstancePtr->Stats.ReceiveOverrunErrors;
StatsPtr->ReceiveFramingErrors = InstancePtr->Stats.ReceiveFramingErrors;
StatsPtr->ReceiveParityErrors = InstancePtr->Stats.ReceiveParityErrors;
}
 
/****************************************************************************/
/**
*
* This function zeros the statistics for the given instance.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XUartLite_ClearStats(XUartLite *InstancePtr)
{
/*
* Assert validates the input arguments
*/
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* clear the stats using the provided macro */
 
XUartLite_mClearStats(InstancePtr);
}
 
/uartlite_v1_00_b/src/xuartlite.c
0,0 → 1,627
/* $Id: xuartlite.c,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite.c
*
* Contains required functions for the XUartLite driver. See the xuartlite.h
* header file for more details on this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 08/31/01 First release
* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
* 1.00b rmm 05/13/03 Fixed diab compiler warnings relating to asserts
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
 
#include "xbasic_types.h"
#include "xstatus.h"
#include "xparameters.h"
#include "xuartlite.h"
#include "xuartlite_i.h"
#include "xio.h"
 
/************************** Constant Definitions ****************************/
 
 
/**************************** Type Definitions ******************************/
 
 
/***************** Macros (Inline Functions) Definitions ********************/
 
 
/************************** Variable Definitions ****************************/
 
 
/************************** Function Prototypes *****************************/
 
static void StubHandler(void *CallBackRef, unsigned int ByteCount);
 
/****************************************************************************/
/**
*
* Initialize a XUartLite instance. The receive and transmit FIFOs of the
* UART are not flushed, so the user may want to flush them. The hardware
* device does not have any way to disable the receiver such that any valid
* data may be present in the receive FIFO. This function disables the UART
* interrupt. The baudrate and format of the data are fixed in the hardware
* at hardware build time.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
* @param DeviceId is the unique id of the device controlled by this
* XUartLite instance. Passing in a device id associates the
* generic XUartLite instance to a specific device, as chosen by
* the caller or application developer.
*
* @return
*
* - XST_SUCCESS if everything starts up as expected.
* - XST_DEVICE_NOT_FOUND if the device is not found in the configuration table.
*
* @note
*
* None.
*
*****************************************************************************/
XStatus XUartLite_Initialize(XUartLite *InstancePtr, Xuint16 DeviceId)
{
XUartLite_Config *UartLiteConfigPtr;
 
/*
* Assert validates the input arguments
*/
XASSERT_NONVOID(InstancePtr != XNULL);
 
/*
* Lookup the device configuration in the configuration table. Use this
* configuration info when initializing this component.
*/
UartLiteConfigPtr = XUartLite_LookupConfig(DeviceId);
 
if (UartLiteConfigPtr == (XUartLite_Config *)XNULL)
{
return XST_DEVICE_NOT_FOUND;
}
 
/*
* Set some default values, including setting the callback
* handlers to stubs.
*/
 
InstancePtr->SendBuffer.NextBytePtr = XNULL;
InstancePtr->SendBuffer.RemainingBytes = 0;
InstancePtr->SendBuffer.RequestedBytes = 0;
 
InstancePtr->ReceiveBuffer.NextBytePtr = XNULL;
InstancePtr->ReceiveBuffer.RemainingBytes = 0;
InstancePtr->ReceiveBuffer.RequestedBytes = 0;
 
InstancePtr->IsReady = XCOMPONENT_IS_READY;
InstancePtr->RegBaseAddress = UartLiteConfigPtr->RegBaseAddr;
InstancePtr->RecvHandler = StubHandler;
InstancePtr->SendHandler = StubHandler;
 
/* Write to the control register to disable the interrupts, don't
* reset the FIFOs are the user may want the data that's present
*/
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET, 0);
 
/*
* Clear the statistics for this driver
*/
XUartLite_mClearStats(InstancePtr);
 
return XST_SUCCESS;
}
 
/****************************************************************************/
/**
*
* This functions sends the specified buffer of data using the UART in either
* polled or interrupt driven modes. This function is non-blocking such that it
* will return before the data has been sent by the UART. If the UART is busy
* sending data, it will return and indicate zero bytes were sent.
*
* In a polled mode, this function will only send as much data as the UART can
* buffer in the FIFO. The application may need to call it repeatedly to
* send a buffer.
*
* In interrupt mode, this function will start sending the specified buffer and
* then the interrupt handler of the driver will continue sending data until the
* buffer has been sent. A callback function, as specified by the application,
* will be called to indicate the completion of sending the buffer.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
* @param BufferPtr is pointer to a buffer of data to be sent.
* @param NumBytes contains the number of bytes to be sent. A value of zero
* will stop a previous send operation that is in progress in interrupt
* mode. Any data that was already put into the transmit FIFO will be
* sent.
*
* @return
*
* The number of bytes actually sent.
*
* @note
*
* The number of bytes is not asserted so that this function may be called with
* a value of zero to stop an operation that is already in progress.
*
******************************************************************************/
unsigned int XUartLite_Send(XUartLite *InstancePtr, Xuint8 *DataBufferPtr,
unsigned int NumBytes)
{
unsigned int BytesSent;
Xuint32 StatusRegister;
 
/*
* Assert validates the input arguments
*/
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(DataBufferPtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_NONVOID(((signed)NumBytes) >= 0);
 
/* Enter a critical region by disabling the UART interrupts to
* allow this call to stop a previous operation that may be interrupt
* driven
*/
StatusRegister = XUartLite_mGetStatusReg(InstancePtr->RegBaseAddress);
 
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET, 0);
 
/* Setup the specified buffer to be sent by setting the instance
* variables so it can be sent with polled or interrupt mode
*/
InstancePtr->SendBuffer.RequestedBytes = NumBytes;
InstancePtr->SendBuffer.RemainingBytes = NumBytes;
InstancePtr->SendBuffer.NextBytePtr = DataBufferPtr;
 
/* Restore the interrupt enable register to it's previous value such
* that the critical region is exited.
* This is done here to minimize the amount of time the interrupt is
* disabled since there is only one interrupt and the receive could
* be filling up while interrupts are blocked.
*/
 
StatusRegister &= XUL_CR_ENABLE_INTR;
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET, StatusRegister);
 
/* Send the buffer using the UART and return the number of bytes sent */
 
BytesSent = XUartLite_SendBuffer(InstancePtr);
 
return BytesSent;
}
 
 
/****************************************************************************/
/**
*
* This function will attempt to receive a specified number of bytes of data
* from the UART and store it into the specified buffer. This function is
* designed for either polled or interrupt driven modes. It is non-blocking
* such that it will return if no data has already received by the UART.
*
* In a polled mode, this function will only receive as much data as the UART
* can buffer in the FIFO. The application may need to call it repeatedly to
* receive a buffer. Polled mode is the default mode of operation for the driver.
*
* In interrupt mode, this function will start receiving and then the interrupt
* handler of the driver will continue receiving data until the buffer has been
* received. A callback function, as specified by the application, will be called
* to indicate the completion of receiving the buffer or when any receive errors
* or timeouts occur. Interrupt mode must be enabled using the SetOptions function.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
* @param BufferPtr is pointer to buffer for data to be received into
* @param NumBytes is the number of bytes to be received. A value of zero will
* stop a previous receive operation that is in progress in interrupt mode.
*
* @return
*
* The number of bytes received.
*
* @note
*
* The number of bytes is not asserted so that this function may be called with
* a value of zero to stop an operation that is already in progress.
*
*****************************************************************************/
unsigned int XUartLite_Recv(XUartLite *InstancePtr, Xuint8 *DataBufferPtr,
unsigned int NumBytes)
{
unsigned int ReceivedCount;
Xuint32 StatusRegister;
 
/*
* Assert validates the input arguments
*/
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(DataBufferPtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_NONVOID(((signed)NumBytes) >= 0);
 
/* Enter a critical region by disabling all the UART interrupts to allow
* this call to stop a previous operation that may be interrupt driven
*/
StatusRegister = XUartLite_mGetStatusReg(InstancePtr->RegBaseAddress);
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET, 0);
 
/* Setup the specified buffer to be received by setting the instance
* variables so it can be received with polled or interrupt mode
*/
InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
InstancePtr->ReceiveBuffer.NextBytePtr = DataBufferPtr;
 
/* Restore the interrupt enable register to it's previous value such
* that the critical region is exited
*/
StatusRegister &= XUL_CR_ENABLE_INTR;
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET, StatusRegister);
 
/* Receive the data from the UART and return the number of bytes
* received
* This is done here to minimize the amount of time the interrupt is
* disabled since there is only one interrupt and the transmit could
* be emptying out while interrupts are blocked.
*/
 
ReceivedCount = XUartLite_ReceiveBuffer(InstancePtr);
 
return ReceivedCount;
 
}
 
/****************************************************************************/
/**
*
* This function resets the FIFOs, both transmit and receive, of the UART such
* that they are emptied. Since the UART does not have any way to disable it
* from receiving data, it may be necessary for the application to reset the
* FIFOs to get rid of any unwanted data.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XUartLite_ResetFifos(XUartLite *InstancePtr)
{
Xuint32 Register;
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Read the status register 1st such that the next write to the control
* register won't destroy the state of the interrupt enable bit
*/
Register =
XIo_In32(InstancePtr->RegBaseAddress + XUL_STATUS_REG_OFFSET);
 
/*
* Mask off the interrupt enable bit to maintain it's state.
*/
 
Register &= XUL_SR_INTR_ENABLED;
 
/* Write to the control register to reset both FIFOs, these bits are
* self-clearing such that there's no need to clear them
*/
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET,
Register | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET);
}
 
/****************************************************************************/
/**
*
* This function determines if the specified UART is sending data. If the
* transmitter register is not empty, it is sending data.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* A value of XTRUE if the UART is sending data, otherwise XFALSE.
*
* @note
*
* None.
*
*****************************************************************************/
Xboolean XUartLite_IsSending(XUartLite *InstancePtr)
{
Xuint32 StatusRegister;
 
/*
* Assert validates the input arguments
*/
XASSERT_NONVOID(InstancePtr != XNULL);
 
/* Read the status register to determine if the transmitter is
* empty
*/
StatusRegister = XIo_In32(InstancePtr->RegBaseAddress + XUL_STATUS_REG_OFFSET);
 
/* If the transmitter is not empty then indicate that the UART is still
* sending some data
*/
return ((StatusRegister & XUL_SR_TX_FIFO_EMPTY) == 0);
}
 
 
/****************************************************************************
*
* This function provides a stub handler such that if the application does not
* define a handler but enables interrupts, this function will be called.
*
* @param CallBackRef has no purpose but is necessary to match the
* interface for a handler.
* @param ByteCount has no purpose but is necessary to match the
* interface for a handler.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
static void StubHandler(void *CallBackRef, unsigned int ByteCount)
{
/*
* Assert occurs always since this is a stub and should never be called
*/
XASSERT_VOID_ALWAYS();
}
 
/****************************************************************************
*
* Looks up the device configuration based on the unique device ID. The table
* UartliteConfigTable contains the configuration info for each device in the
* system.
*
* @param DeviceId is the unique device ID to match on.
*
* @return
*
* A pointer to the configuration data for the device, or XNULL if no match
* was found.
*
* @note
*
* None.
*
******************************************************************************/
XUartLite_Config *XUartLite_LookupConfig(Xuint16 DeviceId)
{
XUartLite_Config *CfgPtr = XNULL;
int i;
 
for (i=0; i < XPAR_XUARTLITE_NUM_INSTANCES; i++)
{
if (XUartLite_ConfigTable[i].DeviceId == DeviceId)
{
CfgPtr = &XUartLite_ConfigTable[i];
break;
}
}
 
return CfgPtr;
}
 
/****************************************************************************/
/**
*
* This function sends a buffer that has been previously specified by setting
* up the instance variables of the instance. This function is designed to be
* an internal function for the XUartLite component such that it may be called
* from a shell function that sets up the buffer or from an interrupt handler.
*
* This function sends the specified buffer of data to the UART in either
* polled or interrupt driven modes. This function is non-blocking such that
* it will return before the data has been sent by the UART.
*
* In a polled mode, this function will only send as much data as the UART can
* buffer, either in the transmitter or in the FIFO if present and enabled.
* The application may need to call it repeatedly to send a buffer.
*
* In interrupt mode, this function will start sending the specified buffer and
* then the interrupt handler of the driver will continue until the buffer
* has been sent. A callback function, as specified by the application, will
* be called to indicate the completion of sending the buffer.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* NumBytes is the number of bytes actually sent (put into the UART transmitter
* and/or FIFO).
*
* @note
*
* None.
*
*****************************************************************************/
unsigned int XUartLite_SendBuffer(XUartLite *InstancePtr)
{
unsigned int SentCount = 0;
Xuint32 StatusRegister;
 
/* Read the line status register to determine if the transmitter is
* full
*/
 
StatusRegister = XUartLite_mGetStatusReg(InstancePtr->RegBaseAddress);
 
/*
* Fill the FIFO from the the buffer that was specified
*/
 
SentCount = 0;
 
while (((StatusRegister & XUL_SR_TX_FIFO_FULL) == 0) &&
(SentCount < InstancePtr->SendBuffer.RemainingBytes))
{
XIo_Out32(InstancePtr->RegBaseAddress + XUL_TX_FIFO_OFFSET,
InstancePtr->SendBuffer.NextBytePtr[SentCount]);
 
SentCount++;
 
StatusRegister = XUartLite_mGetStatusReg(InstancePtr->RegBaseAddress);
 
}
 
/*
* Update the buffer to reflect the bytes that were sent from it
*/
InstancePtr->SendBuffer.NextBytePtr += SentCount;
InstancePtr->SendBuffer.RemainingBytes -= SentCount;
 
/*
* Increment associated counters
*/
InstancePtr->Stats.CharactersTransmitted += SentCount;
 
/*
* Return the number of bytes that were sent, althought they really were
* only put into the FIFO, not completely sent yet
*/
return SentCount;
}
 
/****************************************************************************/
/**
*
* This function receives a buffer that has been previously specified by setting
* up the instance variables of the instance. This function is designed to be
* an internal function for the XUartLite component such that it may be called
* from a shell function that sets up the buffer or from an interrupt handler.
*
* This function will attempt to receive a specified number of bytes of data
* from the UART and store it into the specified buffer. This function is
* designed for either polled or interrupt driven modes. It is non-blocking
* such that it will return if there is no data has already received by the
* UART.
*
* In a polled mode, this function will only receive as much data as the UART
* can buffer, either in the receiver or in the FIFO if present and enabled.
* The application may need to call it repeatedly to receive a buffer. Polled
* mode is the default mode of operation for the driver.
*
* In interrupt mode, this function will start receiving and then the interrupt
* handler of the driver will continue until the buffer has been received. A
* callback function, as specified by the application, will be called to indicate
* the completion of receiving the buffer or when any receive errors or timeouts
* occur. Interrupt mode must be enabled using the SetOptions function.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* The number of bytes received.
*
* @note
*
* None.
*
*****************************************************************************/
unsigned int XUartLite_ReceiveBuffer(XUartLite *InstancePtr)
{
Xuint8 StatusRegister;
unsigned int ReceivedCount = 0;
 
/* Loop until there is not more data buffered by the UART or the specified
* number of bytes is received
*/
 
while (ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)
{
/* Read the Status Register to determine if there is any data in
* the receiver/FIFO
*/
StatusRegister = XUartLite_mGetStatusReg(InstancePtr->RegBaseAddress);
 
/* If there is data ready to be removed, then put the next byte
* received into the specified buffer and update the stats to reflect
* any receive errors for the byte
*/
if (StatusRegister & XUL_SR_RX_FIFO_VALID_DATA)
{
InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount++] =
XIo_In32(InstancePtr->RegBaseAddress + XUL_RX_FIFO_OFFSET);
 
XUartLite_mUpdateStats(InstancePtr, StatusRegister);
}
 
/* There's no more data buffered, so exit such that this function does
* not block waiting for data
*/
else
{
break;
}
}
 
/* Enter a critical region by disabling all the UART interrupts to allow
* this call to stop a previous operation that may be interrupt driven
*/
StatusRegister = XUartLite_mGetStatusReg(InstancePtr->RegBaseAddress);
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET, 0);
 
/* Update the receive buffer to reflect the number of bytes that was
* received
*/
InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
 
/*
* Increment associated counters in the statistics
*/
InstancePtr->Stats.CharactersReceived += ReceivedCount;
 
/* Restore the interrupt enable register to it's previous value such
* that the critical region is exited
*/
StatusRegister &= XUL_CR_ENABLE_INTR;
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET, StatusRegister);
 
return ReceivedCount;
}
 
/uartlite_v1_00_b/src/xuartlite_l.h
0,0 → 1,247
/* $Id: xuartlite_l.h,v 1.1 2006-06-23 19:03:46 quickwayne Exp $ */
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. High-level driver functions
* are defined in xuartlite.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b rpm 04/25/02 First release
* 1.00b rpm 07/07/03 Removed references to XUartLite_mGetControlReg macro
* since the control register is write-only
* </pre>
*
*****************************************************************************/
 
#ifndef XUARTLITE_L_H /* prevent circular inclusions */
#define XUARTLITE_L_H /* by using protection macros */
 
/***************************** Include Files ********************************/
 
#include "xbasic_types.h"
#include "xio.h"
 
/************************** Constant Definitions ****************************/
 
/* UART Lite register offsets */
 
#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */
#define XUL_CONTROL_REG_OFFSET 12 /* control register, write only */
 
/* control register bit positions */
 
#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */
#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */
#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */
 
/* status register bit positions */
 
#define XUL_SR_PARITY_ERROR 0x80
#define XUL_SR_FRAMING_ERROR 0x40
#define XUL_SR_OVERRUN_ERROR 0x20
#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */
#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */
#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
 
/* the following constant specifies the size of the FIFOs, the size of the
* FIFOs includes the transmitter and receiver such that it is the total number
* of bytes that the UART can buffer
*/
#define XUL_FIFO_SIZE 16
 
/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
* per instance basis
*/
#define XUL_STOP_BITS 1
 
/* Parity definitions
*/
#define XUL_PARITY_NONE 0
#define XUL_PARITY_ODD 1
#define XUL_PARITY_EVEN 2
 
/**************************** Type Definitions ******************************/
 
/***************** Macros (Inline Functions) Definitions ********************/
 
/*****************************************************************************
*
* Low-level driver macros and functions. The list below provides signatures
* to help the user use the macros.
*
* void XUartLite_mSetControlReg(Xuint32 BaseAddress, Xuint32 Mask)
* Xuint32 XUartLite_mGetStatusReg(Xuint32 BaseAddress)
*
* Xboolean XUartLite_mIsReceiveEmpty(Xuint32 BaseAddress)
* Xboolean XUartLite_mIsTransmitFull(Xuint32 BaseAddress)
* Xboolean XUartLite_mIsIntrEnabled(Xuint32 BaseAddress)
*
* void XUartLite_mEnableIntr(Xuint32 BaseAddress)
* void XUartLite_mDisableIntr(Xuint32 BaseAddress)
*
* void XUartLite_SendByte(Xuint32 BaseAddress, Xuint8 Data);
* Xuint8 XUartLite_RecvByte(Xuint32 BaseAddress);
*
*****************************************************************************/
 
/****************************************************************************/
/**
*
* Set the contents of the control register. Use the XUL_CR_* constants defined
* above to create the bit-mask to be written to the register.
*
* @param BaseAddress is the base address of the device
* @param Mask is the 32-bit value to write to the control register
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mSetControlReg(BaseAddress, Mask) \
XIo_Out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask))
 
 
/****************************************************************************/
/**
*
* Get the contents of the status register. Use the XUL_SR_* constants defined
* above to interpret the bit-mask returned.
*
* @param BaseAddress is the base address of the device
*
* @return A 32-bit value representing the contents of the status register.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mGetStatusReg(BaseAddress) \
XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)
 
 
/****************************************************************************/
/**
*
* Check to see if the receiver has data.
*
* @param BaseAddress is the base address of the device
*
* @return XTRUE if the receiver is empty, XFALSE if there is data present.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mIsReceiveEmpty(BaseAddress) \
((XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
XUL_SR_RX_FIFO_VALID_DATA)
 
 
/****************************************************************************/
/**
*
* Check to see if the transmitter is full.
*
* @param BaseAddress is the base address of the device
*
* @return XTRUE if the transmitter is full, XFALSE otherwise.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mIsTransmitFull(BaseAddress) \
((XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
XUL_SR_TX_FIFO_FULL)
 
 
/****************************************************************************/
/**
*
* Check to see if the interrupt is enabled.
*
* @param BaseAddress is the base address of the device
*
* @return XTRUE if the interrupt is enabled, XFALSE otherwise.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mIsIntrEnabled(BaseAddress) \
((XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \
XUL_SR_INTR_ENABLED)
 
 
/****************************************************************************/
/**
*
* Enable the device interrupt. We cannot read the control register, so we
* just write the enable interrupt bit and clear all others. Since the only
* other ones are the FIFO reset bits, this works without side effects.
*
* @param BaseAddress is the base address of the device
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mEnableIntr(BaseAddress) \
XUartLite_mSetControlReg((BaseAddress), XUL_CR_ENABLE_INTR)
 
 
/****************************************************************************/
/**
*
* Disable the device interrupt. We cannot read the control register, so we
* just clear all bits. Since the only other ones are the FIFO reset bits,
* this works without side effects.
*
* @param BaseAddress is the base address of the device
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XUartLite_mDisableIntr(BaseAddress) \
XUartLite_mSetControlReg((BaseAddress), 0)
 
 
/************************** Function Prototypes *****************************/
 
void XUartLite_SendByte(Xuint32 BaseAddress, Xuint8 Data);
Xuint8 XUartLite_RecvByte(Xuint32 BaseAddress);
 
 
#endif /* end of protection macro */
 
/uartlite_v1_00_b/src/xuartlite.h
0,0 → 1,211
/* $Id: xuartlite.h,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite.h
*
* This component contains the implementation of the XUartLite component which is
* the driver for the Xilinx UART Lite device. This UART is a minimal hardware
* implementation with minimal features. Most of the features, including baud
* rate, parity, and number of data bits are only configurable when the hardware
* device is built, rather than at run time by software.
*
* The device has 16 byte transmit and receive FIFOs and supports interrupts.
* The device does not have any way to disable the receiver such that the
* receive FIFO may contain unwanted data. The FIFOs are not flushed when the
* driver is initialized, but a function is provided to allow the user to
* reset the FIFOs if desired.
*
* The driver defaults to no interrupts at initialization such that interrupts
* must be enabled if desired. An interrupt is generated when the transmit FIFO
* transitions from having data to being empty or when any data is contained in
* the receive FIFO.
*
* In order to use interrupts, it's necessary for the user to connect the driver
* interrupt handler, XUartLite_InterruptHandler, to the interrupt system of the
* application. This function does not save and restore the processor context
* such that the user must provide it. Send and receive handlers may be set for
* the driver such that the handlers are called when transmit and receive
* interrupts occur. The handlers are called from interrupt context and are
* designed to allow application specific processing to be performed.
*
* The functions, XUartLite_Send and XUartLite_Recv, are provided in the driver
* to allow data to be sent and received. They are designed to be used in
* polled or interrupt modes.
*
* The driver provides a status for each received byte indicating any parity
* frame or overrun error. The driver provides statistics which allow visibility
* into these errors.
*
* <b>RTOS Independence</b>
*
* This driver is intended to be RTOS and processor independent. It works
* with physical addresses only. Any needs for dynamic memory management,
* threads or thread mutual exclusion, virtual memory, or cache control must
* be satisfied by the layer above this driver.
*
* @note
*
* The driver is partitioned such that a minimal implementation may be used.
* More features require additional files to be linked in.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 08/31/01 First release
* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
* </pre>
*
*****************************************************************************/
 
#ifndef XUARTLITE_H /* prevent circular inclusions */
#define XUARTLITE_H /* by using protection macros */
 
/***************************** Include Files ********************************/
 
#include "xbasic_types.h"
#include "xstatus.h"
 
/************************** Constant Definitions ****************************/
 
/**************************** Type Definitions ******************************/
 
/**
* Callback function. The first argument is a callback reference passed in by
* the upper layer when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
* The second argument is the ByteCount which is the number of bytes that
* actually moved from/to the buffer provided in the _Send/_Receive call.
*/
typedef void (*XUartLite_Handler)(void *CallBackRef, unsigned int ByteCount);
 
/**
* Statistics for the XUartLite driver
*/
typedef struct
{
Xuint32 TransmitInterrupts; /**< Number of transmit interrupts */
Xuint32 ReceiveInterrupts; /**< Number of receive interrupts */
Xuint32 CharactersTransmitted; /**< Number of characters transmitted */
Xuint32 CharactersReceived; /**< Number of characters received */
Xuint32 ReceiveOverrunErrors; /**< Number of receive overruns */
Xuint32 ReceiveParityErrors; /**< Number of receive parity errors */
Xuint32 ReceiveFramingErrors; /**< Number of receive framing errors */
} XUartLite_Stats;
 
/**
* The following data type is used to manage the buffers that are handled
* when sending and receiving data in the interrupt mode. It is intended
* for internal use only.
*/
typedef struct
{
Xuint8 *NextBytePtr;
unsigned int RequestedBytes;
unsigned int RemainingBytes;
} XUartLite_Buffer;
 
/**
* This typedef contains configuration information for the device.
*/
typedef struct
{
Xuint16 DeviceId; /**< Unique ID of device */
Xuint32 RegBaseAddr; /**< Register base address */
Xuint32 BaudRate; /**< Fixed baud rate */
Xuint8 UseParity; /**< Parity generator enabled when XTRUE */
Xuint8 ParityOdd; /**< Parity generated is odd when XTRUE, even when
XFALSE */
Xuint8 DataBits; /**< Fixed data bits */
} XUartLite_Config;
 
/**
* The XUartLite driver instance data. The user is required to allocate a
* variable of this type for every UART Lite device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct
{
XUartLite_Stats Stats; /* Component Statistics */
Xuint32 RegBaseAddress; /* Base address of registers */
Xuint32 IsReady; /* Device is initialized and ready */
 
 
XUartLite_Buffer SendBuffer;
XUartLite_Buffer ReceiveBuffer;
 
XUartLite_Handler RecvHandler;
void *RecvCallBackRef; /* Callback reference for recv handler */
XUartLite_Handler SendHandler;
void *SendCallBackRef; /* Callback reference for send handler */
} XUartLite;
 
 
/***************** Macros (Inline Functions) Definitions ********************/
 
 
/************************** Function Prototypes *****************************/
 
/*
* Required functions, in file xuart.c
*/
XStatus XUartLite_Initialize(XUartLite *InstancePtr, Xuint16 DeviceId);
 
void XUartLite_ResetFifos(XUartLite *InstancePtr);
 
unsigned int XUartLite_Send(XUartLite *InstancePtr, Xuint8 *DataBufferPtr,
unsigned int NumBytes);
unsigned int XUartLite_Recv(XUartLite *InstancePtr, Xuint8 *DataBufferPtr,
unsigned int NumBytes);
 
Xboolean XUartLite_IsSending(XUartLite *InstancePtr);
XUartLite_Config *XUartLite_LookupConfig(Xuint16 DeviceId);
 
/*
* Functions for statistics, in file xuartlite_stats.c
*/
void XUartLite_GetStats(XUartLite *InstancePtr, XUartLite_Stats *StatsPtr);
void XUartLite_ClearStats(XUartLite *InstancePtr);
 
/*
* Functions for self-test, in file xuartlite_selftest.c
*/
XStatus XUartLite_SelfTest(XUartLite *InstancePtr);
 
/*
* Functions for interrupts, in file xuartlite_intr.c
*/
void XUartLite_EnableInterrupt(XUartLite *InstancePtr);
void XUartLite_DisableInterrupt(XUartLite *InstancePtr);
 
void XUartLite_SetRecvHandler(XUartLite *InstancePtr, XUartLite_Handler FuncPtr,
void *CallBackRef);
void XUartLite_SetSendHandler(XUartLite *InstancePtr, XUartLite_Handler FuncPtr,
void *CallBackRef);
 
void XUartLite_InterruptHandler(XUartLite *InstancePtr);
 
#endif /* end of protection macro */
 
/uartlite_v1_00_b/src/xuartlite_g.c
0,0 → 1,41
 
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Driver configuration
*
*******************************************************************/
 
#include "xparameters.h"
#include "xuartlite.h"
 
/*
* The configuration table for devices
*/
 
XUartLite_Config XUartLite_ConfigTable[] =
{
{
XPAR_DEBUG_MODULE_DEVICE_ID,
XPAR_DEBUG_MODULE_BASEADDR,
XPAR_DEBUG_MODULE_BAUDRATE,
XPAR_DEBUG_MODULE_USE_PARITY,
XPAR_DEBUG_MODULE_ODD_PARITY,
XPAR_DEBUG_MODULE_DATA_BITS
},
{
XPAR_RS232_UART_1_DEVICE_ID,
XPAR_RS232_UART_1_BASEADDR,
XPAR_RS232_UART_1_BAUDRATE,
XPAR_RS232_UART_1_USE_PARITY,
XPAR_RS232_UART_1_ODD_PARITY,
XPAR_RS232_UART_1_DATA_BITS
}
};
 
 
/uartlite_v1_00_b/src/xuartlite_selftest.c
0,0 → 1,112
/* $Id: xuartlite_selftest.c,v 1.1 2006-06-23 19:03:46 quickwayne Exp $ */
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite_selftest.c
*
* This file contains the self-test functions for the UART Lite component
* (XUartLite).
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 08/31/01 First release
* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
 
#include "xbasic_types.h"
#include "xstatus.h"
#include "xuartlite.h"
#include "xuartlite_i.h"
#include "xio.h"
 
/************************** Constant Definitions ****************************/
 
 
/**************************** Type Definitions ******************************/
 
 
/***************** Macros (Inline Functions) Definitions ********************/
 
 
/************************** Variable Definitions ****************************/
 
 
/************************** Function Prototypes *****************************/
 
 
/****************************************************************************/
/**
*
* Runs a self-test on the device hardware. Since there is no way to perform a
* loopback in the hardware, this test can only check the state of the status
* register to verify it is correct. This test assumes that the hardware
* device is still in its reset state, but has been initialized with the
* Initialize function.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* - XST_SUCCESS if the self-test was successful.
* - XST_FAILURE if the self-test failed, the status register value was not
* correct
*
* @note
*
* None.
*
******************************************************************************/
XStatus XUartLite_SelfTest(XUartLite *InstancePtr)
{
Xuint32 StatusRegister;
 
/*
* Assert validates the input arguments
*/
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* get the control register value to check if it's the correct value after
* a reset
*/
StatusRegister = XIo_In32(InstancePtr->RegBaseAddress +
XUL_STATUS_REG_OFFSET);
 
/* if the status register is any other value other than XUL_SR_TX_FIFO_EMPTY
* then the test is a failure since this is the not the value after reset
*/
if (StatusRegister != XUL_SR_TX_FIFO_EMPTY)
{
return XST_FAILURE;
}
 
return XST_SUCCESS;
}
 
/uartlite_v1_00_b/src/Makefile
0,0 → 1,28
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
 
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
 
INCLUDEFILES=xuartlite.h xuartlite_l.h
LIBSOURCES=*.c
OUTS = *.o
 
 
libs:
echo "Compiling uartlite"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
 
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
 
clean:
rm -rf ${OUTS}
 
/uartlite_v1_00_b/src/xuartlite_l.c
0,0 → 1,111
/* $Id: xuartlite_l.c,v 1.1 2006-06-23 19:03:46 quickwayne Exp $ */
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite_l.c
*
* This file contains low-level driver functions that can be used to access the
* device. The user should refer to the hardware device specification for more
* details of the device operation.
 
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b rpm 04/25/02 First release
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xuartlite_l.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
 
/************************** Variable Prototypes ******************************/
 
 
/****************************************************************************/
/**
*
* This functions sends a single byte using the UART. It is blocking in that it
* waits for the transmitter to become non-full before it writes the byte to
* the transmit register.
*
* @param BaseAddress is the base address of the device
* @param Data is the byte of data to send
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XUartLite_SendByte(Xuint32 BaseAddress, Xuint8 Data)
{
while (XUartLite_mIsTransmitFull(BaseAddress));
 
XIo_Out32(BaseAddress + XUL_TX_FIFO_OFFSET, Data);
}
 
 
/****************************************************************************/
/**
*
* This functions receives a single byte using the UART. It is blocking in that
* it waits for the receiver to become non-empty before it reads from the
* receive register.
*
* @param BaseAddress is the base address of the device
*
* @return
*
* The byte of data received.
*
* @note
*
* None.
*
******************************************************************************/
Xuint8 XUartLite_RecvByte(Xuint32 BaseAddress)
{
while (XUartLite_mIsReceiveEmpty(BaseAddress));
 
return (Xuint8)XIo_In32(BaseAddress + XUL_RX_FIFO_OFFSET);
}
 
/uartlite_v1_00_b/src/xuartlite_intr.c
0,0 → 1,333
/* $Id: xuartlite_intr.c,v 1.1 2006-06-23 19:03:46 quickwayne Exp $ */
/*****************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
*****************************************************************************/
/****************************************************************************/
/**
*
* @file xuartlite_intr.c
*
* This file contains interrupt-related functions for the UART Lite component
* (XUartLite).
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 08/31/01 First release
* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
 
#include "xbasic_types.h"
#include "xuartlite.h"
#include "xuartlite_i.h"
#include "xio.h"
 
/************************** Constant Definitions ****************************/
 
/**************************** Type Definitions ******************************/
 
/***************** Macros (Inline Functions) Definitions ********************/
 
/************************** Function Prototypes *****************************/
 
static void ReceiveDataHandler(XUartLite *InstancePtr);
static void SendDataHandler(XUartLite *InstancePtr);
 
/************************** Variable Definitions ****************************/
 
typedef void (*Handler)(XUartLite *InstancePtr);
 
/****************************************************************************/
/**
*
* This function sets the handler that will be called when an event (interrupt)
* occurs in the driver. The purpose of the handler is to allow application
* specific processing to be performed.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
* @param FuncPtr is the pointer to the callback function.
* @param CallBackRef is the upper layer callback reference passed back when
* the callback function is invoked.
*
* @return
*
* None.
*
* @notes
*
* There is no assert on the CallBackRef since the driver doesn't know what it
* is (nor should it)
*
*****************************************************************************/
void XUartLite_SetRecvHandler(XUartLite *InstancePtr,
XUartLite_Handler FuncPtr, void *CallBackRef)
{
/*
* Assert validates the input arguments
* CallBackRef not checked, no way to know what is valid
*/
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(FuncPtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
InstancePtr->RecvHandler = FuncPtr;
InstancePtr->RecvCallBackRef = CallBackRef;
}
 
/****************************************************************************/
/**
*
* This function sets the handler that will be called when an event (interrupt)
* occurs in the driver. The purpose of the handler is to allow application
* specific processing to be performed.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
* @param FuncPtr is the pointer to the callback function.
* @param CallBackRef is the upper layer callback reference passed back when
* the callback function is invoked.
*
* @return
*
* None.
*
* @notes
*
* There is no assert on the CallBackRef since the driver doesn't know what it
* is (nor should it)
*
*****************************************************************************/
void XUartLite_SetSendHandler(XUartLite *InstancePtr,
XUartLite_Handler FuncPtr, void *CallBackRef)
{
/*
* Assert validates the input arguments
* CallBackRef not checked, no way to know what is valid
*/
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(FuncPtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
InstancePtr->SendHandler = FuncPtr;
InstancePtr->SendCallBackRef = CallBackRef;
}
 
/****************************************************************************/
/**
*
* This function is the interrupt handler for the UART lite driver.
* It must be connected to an interrupt system by the user such that it is
* called when an interrupt for any UART lite occurs. This function
* does not save or restore the processor context such that the user must
* ensure this occurs.
*
* @param InstancePtr contains a pointer to the instance of the UART that
* the interrupt is for.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XUartLite_InterruptHandler(XUartLite *InstancePtr)
{
Xuint32 IsrStatus;
 
XASSERT_VOID(InstancePtr != XNULL);
 
/* Read the status register to determine which, coulb be both
* interrupt is active
*/
IsrStatus = XIo_In32(InstancePtr->RegBaseAddress + XUL_STATUS_REG_OFFSET);
 
if ((IsrStatus & (XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA)) != 0)
{
ReceiveDataHandler(InstancePtr);
}
 
if ((IsrStatus & XUL_SR_TX_FIFO_EMPTY) != 0)
{
SendDataHandler(InstancePtr);
}
}
 
/****************************************************************************/
/**
*
* This function handles the interrupt when data is received, either a single
* byte when FIFOs are not enabled, or multiple bytes with the FIFO.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
static void ReceiveDataHandler(XUartLite *InstancePtr)
{
/*
* If there are bytes still to be received in the specified buffer
* go ahead and receive them
*/
if (InstancePtr->ReceiveBuffer.RemainingBytes != 0)
{
XUartLite_ReceiveBuffer(InstancePtr);
}
 
/* If the last byte of a message was received then call the application
* handler, this code should not use an else from the previous check of
* the number of bytes to receive because the call to receive the buffer
* updates the bytes to receive
*/
if (InstancePtr->ReceiveBuffer.RemainingBytes == 0)
{
InstancePtr->RecvHandler(InstancePtr->RecvCallBackRef,
InstancePtr->ReceiveBuffer.RequestedBytes -
InstancePtr->ReceiveBuffer.RemainingBytes);
}
 
/* Update the receive stats to reflect the receive interrupt */
 
InstancePtr->Stats.ReceiveInterrupts++;
}
 
/****************************************************************************/
/**
*
* This function handles the interrupt when data has been sent, the transmit
* FIFO is empty (transmitter holding register).
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
static void SendDataHandler(XUartLite *InstancePtr)
{
/*
* If there are not bytes to be sent from the specified buffer ,
* call the callback function
*/
if (InstancePtr->SendBuffer.RemainingBytes == 0)
{
/* Call the application handler to indicate the data has been sent */
 
InstancePtr->SendHandler(InstancePtr->SendCallBackRef,
InstancePtr->SendBuffer.RequestedBytes -
InstancePtr->SendBuffer.RemainingBytes);
}
/*
* Otherwise there is still more data to send in the specified buffer
* so go ahead and send it
*/
else
{
XUartLite_SendBuffer(InstancePtr);
}
 
/* Update the transmit stats to reflect the transmit interrupt */
 
InstancePtr->Stats.TransmitInterrupts++;
}
 
 
/*****************************************************************************/
/**
*
* This function disables the UART interrupt. After calling this function,
* data may still be received by the UART but no interrupt will be generated
* since the hardware device has no way to disable the receiver.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XUartLite_DisableInterrupt(XUartLite *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Write to the control register to disable the interrupts, the only other
* bits in this register are the FIFO reset bits such that writing them
* to zero will not affect them.
*/
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET, 0);
}
 
/*****************************************************************************/
/**
*
* This function enables the UART interrupt such that an interrupt will occur
* when data is received or data has been transmitted. The device contains
* 16 byte receive and transmit FIFOs such that an interrupt is generated
* anytime there is data in the receive FIFO and when the transmit FIFO
* transitions from not empty to empty.
*
* @param InstancePtr is a pointer to the XUartLite instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XUartLite_EnableInterrupt(XUartLite *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Write to the control register to enable the interrupts, the only other
* bits in this register are the FIFO reset bits such that writing them
* to zero will not affect them.
*/
XIo_Out32(InstancePtr->RegBaseAddress + XUL_CONTROL_REG_OFFSET,
XUL_CR_ENABLE_INTR);
}
 
/ipif_v1_23_b/src/xipif_v1_23_b.h
0,0 → 1,648
/* $Id: xipif_v1_23_b.h,v 1.1 2006-06-23 19:03:42 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xipif_v1_23_b.h
*
* The XIpIf component encapsulates the IPIF, which is the standard interface
* that IP must adhere to when connecting to a bus. The purpose of this
* component is to encapsulate the IPIF processing such that maintainability
* is increased. This component does not provide a lot of abstraction from
* from the details of the IPIF as it is considered a building block for
* device drivers. A device driver designer must be familiar with the
* details of the IPIF hardware to use this component.
*
* The IPIF hardware provides a building block for all hardware devices such
* that each device does not need to reimplement these building blocks. The
* IPIF contains other building blocks, such as FIFOs and DMA channels, which
* are also common to many devices. These blocks are implemented as separate
* hardware blocks and instantiated within the IPIF. The primary hardware of
* the IPIF which is implemented by this software component is the interrupt
* architecture. Since there are many blocks of a device which may generate
* interrupts, all the interrupt processing is contained in the common part
* of the device, the IPIF. This interrupt processing is for the device level
* only and does not include any processing for the interrupt controller.
*
* A device is a mechanism such as an Ethernet MAC. The device is made
* up of several parts which include an IPIF and the IP. The IPIF contains most
* of the device infrastructure which is common to all devices, such as
* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
* be referred to as IPIF internal blocks since they are part of the IPIF and
* are separate blocks that can be selected based upon the needs of the device.
* The IP of the device is the logic that is unique to the device and interfaces
* to the IPIF of the device.
*
* In general, there are two levels of registers within the IPIF. The first
* level, referred to as the device level, contains registers which are for the
* entire device. The second level, referred to as the IP level, contains
* registers which are specific to the IP of the device. The two levels of
* registers are designed to be hierarchical such that the device level is
* is a more general register set above the more specific registers of the IP.
* The IP level of registers provides functionality which is typically common
* across all devices and allows IP designers to focus on the unique aspects
* of the IP.
*
* <b>Critical Sections</b>
*
* It is the responsibility of the device driver designer to use critical
* sections as necessary when calling functions of the IPIF. This component
* does not use critical sections and it does access registers using
* read-modify-write operations. Calls to IPIF functions from a main thread
* and from an interrupt context could produce unpredictable behavior such that
* the caller must provide the appropriate critical sections.
*
* <b>Mutual Exclusion</b>
*
* The functions of the IPIF are not thread safe such that the caller of all
* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
* exclusion across multiple IPIF components is not necessary.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.23b jhl 02/27/01 Repartioned to minimize size
* 1.23b rpm 07/16/04 Changed ifdef for circular inclusion to be more qualified
* 1.23b rpm 08/17/04 Doxygenated for inclusion of API documentation
* 1.23b xd 10/27/04 Improve Doxygen format
* </pre>
*
******************************************************************************/
 
#ifndef XIPIF_V123B_H /* prevent circular inclusions */
#define XIPIF_V123B_H /* by using protection macros */
 
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xstatus.h"
#include "xversion.h"
 
/************************** Constant Definitions *****************************/
 
/** @name Register Offsets
*
* The following constants define the register offsets for the registers of the
* IPIF, there are some holes in the memory map for reserved addresses to allow
* other registers to be added and still match the memory map of the interrupt
* controller registers
* @{
*/
#define XIIF_V123B_DISR_OFFSET 0UL /**< device interrupt status register */
#define XIIF_V123B_DIPR_OFFSET 4UL /**< device interrupt pending register */
#define XIIF_V123B_DIER_OFFSET 8UL /**< device interrupt enable register */
#define XIIF_V123B_DIIR_OFFSET 24UL /**< device interrupt ID register */
#define XIIF_V123B_DGIER_OFFSET 28UL /**< device global interrupt enable register */
#define XIIF_V123B_IISR_OFFSET 32UL /**< IP interrupt status register */
#define XIIF_V123B_IIER_OFFSET 40UL /**< IP interrupt enable register */
#define XIIF_V123B_RESETR_OFFSET 64UL /**< reset register */
/* @} */
 
/**
* The value used for the reset register to reset the IPIF
*/
#define XIIF_V123B_RESET_MASK 0xAUL
 
/**
* The following constant is used for the device global interrupt enable
* register, to enable all interrupts for the device, this is the only bit
* in the register
*/
#define XIIF_V123B_GINTR_ENABLE_MASK 0x80000000UL
 
/**
* The mask to identify each internal IPIF error condition in the device
* registers of the IPIF. Interrupts are assigned in the register from LSB
* to the MSB
*/
#define XIIF_V123B_ERROR_MASK 1UL /**< LSB of the register */
 
/** @name Interrupt IDs
*
* The interrupt IDs which identify each internal IPIF condition, this value
* must correlate with the mask constant for the error
* @{
*/
#define XIIF_V123B_ERROR_INTERRUPT_ID 0 /**< interrupt bit #, (LSB = 0) */
#define XIIF_V123B_NO_INTERRUPT_ID 128 /**< no interrupts are pending */
/* @} */
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/*****************************************************************************/
/**
*
* Reset the IPIF component and hardware. This is a destructive operation that
* could cause the loss of data since resetting the IPIF of a device also
* resets the device using the IPIF and any blocks, such as FIFOs or DMA
* channels, within the IPIF. All registers of the IPIF will contain their
* reset value when this function returns.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return None
*
* @note None
*
******************************************************************************/
#define XIIF_V123B_RESET(RegBaseAddress) \
XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK)
 
/*****************************************************************************/
/**
*
* This macro sets the device interrupt status register to the value.
* This register indicates the status of interrupt sources for a device
* which contains the IPIF. The status is independent of whether interrupts
* are enabled and could be used for polling a device at a higher level rather
* than a more detailed level.
*
* Each bit of the register correlates to a specific interrupt source within the
* device which contains the IPIF. With the exception of some internal IPIF
* conditions, the contents of this register are not latched but indicate
* the live status of the interrupt sources within the device. Writing any of
* the non-latched bits of the register will have no effect on the register.
*
* For the latched bits of this register only, setting a bit which is zero
* within this register causes an interrupt to generated. The device global
* interrupt enable register and the device interrupt enable register must be set
* appropriately to allow an interrupt to be passed out of the device. The
* interrupt is cleared by writing to this register with the bits to be
* cleared set to a one and all others to zero. This register implements a
* toggle on write functionality meaning any bits which are set in the value
* written cause the bits in the register to change to the opposite state.
*
* This function writes the specified value to the register such that
* some bits may be set and others cleared. It is the caller's responsibility
* to get the value of the register prior to setting the value to prevent a
* destructive behavior.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @param Status contains the value to be written to the interrupt status
* register of the device. The only bits which can be written are
* the latched bits which contain the internal IPIF conditions. The
* following values may be used to set the status register or clear an
* interrupt condition.
* - XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \
XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status))
 
/*****************************************************************************/
/**
*
* This macro gets the device interrupt status register contents.
* This register indicates the status of interrupt sources for a device
* which contains the IPIF. The status is independent of whether interrupts
* are enabled and could be used for polling a device at a higher level.
*
* Each bit of the register correlates to a specific interrupt source within the
* device which contains the IPIF. With the exception of some internal IPIF
* conditions, the contents of this register are not latched but indicate
* the live status of the interrupt sources within the device.
*
* For only the latched bits of this register, the interrupt may be cleared by
* writing to these bits in the status register.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* A status which contains the value read from the interrupt status register of
* the device. The bit definitions are specific to the device with
* the exception of the latched internal IPIF condition bits. The following
* values may be used to detect internal IPIF conditions in the status.
* <br><br>
* - XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_READ_DISR(RegBaseAddress) \
XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET)
 
/*****************************************************************************/
/**
*
* This function sets the device interrupt enable register contents.
* This register controls which interrupt sources of the device are allowed to
* generate an interrupt. The device global interrupt enable register must also
* be set appropriately for an interrupt to be passed out of the device.
*
* Each bit of the register correlates to a specific interrupt source within the
* device which contains the IPIF. Setting a bit in this register enables that
* interrupt source to generate an interrupt. Clearing a bit in this register
* disables interrupt generation for that interrupt source.
*
* This function writes only the specified value to the register such that
* some interrupts source may be enabled and others disabled. It is the
* caller's responsibility to get the value of the interrupt enable register
* prior to setting the value to prevent an destructive behavior.
*
* An interrupt source may not be enabled to generate an interrupt, but can
* still be polled in the interrupt status register.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @param
*
* Enable contains the value to be written to the interrupt enable register
* of the device. The bit definitions are specific to the device with
* the exception of the internal IPIF conditions. The following
* values may be used to enable the internal IPIF conditions interrupts.
* - XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
*
* @return
*
* None.
*
* @note
*
* Signature: Xuint32 XIIF_V123B_WRITE_DIER(Xuint32 RegBaseAddress,
* Xuint32 Enable)
*
******************************************************************************/
#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \
XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable))
 
/*****************************************************************************/
/**
*
* This function gets the device interrupt enable register contents.
* This register controls which interrupt sources of the device
* are allowed to generate an interrupt. The device global interrupt enable
* register and the device interrupt enable register must also be set
* appropriately for an interrupt to be passed out of the device.
*
* Each bit of the register correlates to a specific interrupt source within the
* device which contains the IPIF. Setting a bit in this register enables that
* interrupt source to generate an interrupt if the global enable is set
* appropriately. Clearing a bit in this register disables interrupt generation
* for that interrupt source regardless of the global interrupt enable.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* The value read from the interrupt enable register of the device. The bit
* definitions are specific to the device with the exception of the internal
* IPIF conditions. The following values may be used to determine from the
* value if the internal IPIF conditions interrupts are enabled.
* <br><br>
* - XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_READ_DIER(RegBaseAddress) \
XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET)
 
/*****************************************************************************/
/**
*
* This function gets the device interrupt pending register contents.
* This register indicates the pending interrupt sources, those that are waiting
* to be serviced by the software, for a device which contains the IPIF.
* An interrupt must be enabled in the interrupt enable register of the IPIF to
* be pending.
*
* Each bit of the register correlates to a specific interrupt source within the
* the device which contains the IPIF. With the exception of some internal IPIF
* conditions, the contents of this register are not latched since the condition
* is latched in the IP interrupt status register, by an internal block of the
* IPIF such as a FIFO or DMA channel, or by the IP of the device. This register
* is read only and is not latched, but it is necessary to acknowledge (clear)
* the interrupt condition by performing the appropriate processing for the IP
* or block within the IPIF.
*
* This register can be thought of as the contents of the interrupt status
* register ANDed with the contents of the interrupt enable register.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* The value read from the interrupt pending register of the device. The bit
* definitions are specific to the device with the exception of the latched
* internal IPIF condition bits. The following values may be used to detect
* internal IPIF conditions in the value.
* <br><br>
* - XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_READ_DIPR(RegBaseAddress) \
XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)
 
/*****************************************************************************/
/**
*
* This macro gets the device interrupt ID for the highest priority interrupt
* which is pending from the interrupt ID register. This function provides
* priority resolution such that faster interrupt processing is possible.
* Without priority resolution, it is necessary for the software to read the
* interrupt pending register and then check each interrupt source to determine
* if an interrupt is pending. Priority resolution becomes more important as the
* number of interrupt sources becomes larger.
*
* Interrupt priorities are based upon the bit position of the interrupt in the
* interrupt pending register with bit 0 being the highest priority. The
* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the
* highest priority. The interrupt ID register is live rather than latched such
* that multiple calls to this function may not yield the same results. A
* special value, outside of the interrupt priority range of 0 - 31, is
* contained in the register which indicates that no interrupt is pending. This
* may be useful for allowing software to continue processing interrupts in a
* loop until there are no longer any interrupts pending.
*
* The interrupt ID is designed to allow a function pointer table to be used
* in the software such that the interrupt ID is used as an index into that
* table. The function pointer table could contain an instance pointer, such
* as to DMA channel, and a function pointer to the function which handles
* that interrupt. This design requires the interrupt processing of the device
* driver to be partitioned into smaller more granular pieces based upon
* hardware used by the device, such as DMA channels and FIFOs.
*
* It is not mandatory that this function be used by the device driver software.
* It may choose to read the pending register and resolve the pending interrupt
* priorities on it's own.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* An interrupt ID, 0 - 31, which identifies the highest priority interrupt
* which is pending. A value of XIIF_NO_INTERRUPT_ID indicates that there is
* no interrupt pending. The following values may be used to identify the
* interrupt ID for the internal IPIF interrupts.
* <br><br>
* - XIIF_V123B_ERROR_INTERRUPT_ID Indicates a device error in the IPIF
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_READ_DIIR(RegBaseAddress) \
XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)
 
/*****************************************************************************/
/**
*
* This function disables all interrupts for the device by writing to the global
* interrupt enable register. This register provides the ability to disable
* interrupts without any modifications to the interrupt enable register such
* that it is minimal effort to restore the interrupts to the previous enabled
* state. The corresponding function, XIpIf_GlobalIntrEnable, is provided to
* restore the interrupts to the previous enabled state. This function is
* designed to be used in critical sections of device drivers such that it is
* not necessary to disable other device interrupts.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \
XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)
 
/*****************************************************************************/
/**
*
* This function writes to the global interrupt enable register to enable
* interrupts from the device. This register provides the ability to enable
* interrupts without any modifications to the interrupt enable register such
* that it is minimal effort to restore the interrupts to the previous enabled
* state. This function does not enable individual interrupts as the interrupt
* enable register must be set appropriately. This function is designed to be
* used in critical sections of device drivers such that it is not necessary to
* disable other device interrupts.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress) \
XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \
XIIF_V123B_GINTR_ENABLE_MASK)
 
/*****************************************************************************/
/**
*
* This function determines if interrupts are enabled at the global level by
* reading the global interrupt register. This register provides the ability to
* disable interrupts without any modifications to the interrupt enable register
* such that it is minimal effort to restore the interrupts to the previous
* enabled state.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress) \
(XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) == \
XIIF_V123B_GINTR_ENABLE_MASK)
 
/*****************************************************************************/
/**
*
* This function sets the IP interrupt status register to the specified value.
* This register indicates the status of interrupt sources for the IP of the
* device. The IP is defined as the part of the device that connects to the
* IPIF. The status is independent of whether interrupts are enabled such that
* the status register may also be polled when interrupts are not enabled.
*
* Each bit of the register correlates to a specific interrupt source within the
* IP. All bits of this register are latched. Setting a bit which is zero
* within this register causes an interrupt to be generated. The device global
* interrupt enable register and the device interrupt enable register must be set
* appropriately to allow an interrupt to be passed out of the device. The
* interrupt is cleared by writing to this register with the bits to be
* cleared set to a one and all others to zero. This register implements a
* toggle on write functionality meaning any bits which are set in the value
* written cause the bits in the register to change to the opposite state.
*
* This function writes only the specified value to the register such that
* some status bits may be set and others cleared. It is the caller's
* responsibility to get the value of the register prior to setting the value
* to prevent an destructive behavior.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @param Status contains the value to be written to the IP interrupt status
* register. The bit definitions are specific to the device IP.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \
XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))
 
/*****************************************************************************/
/**
*
* This macro gets the contents of the IP interrupt status register.
* This register indicates the status of interrupt sources for the IP of the
* device. The IP is defined as the part of the device that connects to the
* IPIF. The status is independent of whether interrupts are enabled such
* that the status register may also be polled when interrupts are not enabled.
*
* Each bit of the register correlates to a specific interrupt source within the
* device. All bits of this register are latched. Writing a 1 to a bit within
* this register causes an interrupt to be generated if enabled in the interrupt
* enable register and the global interrupt enable is set. Since the status is
* latched, each status bit must be acknowledged in order for the bit in the
* status register to be updated. Each bit can be acknowledged by writing a
* 0 to the bit in the status register.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* A status which contains the value read from the IP interrupt status register.
* The bit definitions are specific to the device IP.
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_READ_IISR(RegBaseAddress) \
XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)
 
/*****************************************************************************/
/**
*
* This macro sets the IP interrupt enable register contents. This register
* controls which interrupt sources of the IP are allowed to generate an
* interrupt. The global interrupt enable register and the device interrupt
* enable register must also be set appropriately for an interrupt to be
* passed out of the device containing the IPIF and the IP.
*
* Each bit of the register correlates to a specific interrupt source within the
* IP. Setting a bit in this register enables the interrupt source to generate
* an interrupt. Clearing a bit in this register disables interrupt generation
* for that interrupt source.
*
* This function writes only the specified value to the register such that
* some interrupt sources may be enabled and others disabled. It is the
* caller's responsibility to get the value of the interrupt enable register
* prior to setting the value to prevent an destructive behavior.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @param Enable contains the value to be written to the IP interrupt enable
* register. The bit definitions are specific to the device IP.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \
XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))
 
/*****************************************************************************/
/**
*
* This macro gets the IP interrupt enable register contents. This register
* controls which interrupt sources of the IP are allowed to generate an
* interrupt. The global interrupt enable register and the device interrupt
* enable register must also be set appropriately for an interrupt to be
* passed out of the device containing the IPIF and the IP.
*
* Each bit of the register correlates to a specific interrupt source within the
* IP. Setting a bit in this register enables the interrupt source to generate
* an interrupt. Clearing a bit in this register disables interrupt generation
* for that interrupt source.
*
* @param RegBaseAddress contains the base address of the IPIF registers.
*
* @return
*
* The contents read from the IP interrupt enable register. The bit definitions
* are specific to the device IP.
*
* @note
*
* Signature: Xuint32 XIIF_V123B_READ_IIER(Xuint32 RegBaseAddress)
*
******************************************************************************/
#define XIIF_V123B_READ_IIER(RegBaseAddress) \
XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)
 
/************************** Function Prototypes ******************************/
 
/**
* Initialization Functions
*/
XStatus XIpIfV123b_SelfTest(Xuint32 RegBaseAddress, Xuint8 IpRegistersWidth);
 
#endif /* end of protection macro */
/ipif_v1_23_b/src/xipif_v1_23_b.c
0,0 → 1,328
/* $Id: xipif_v1_23_b.c,v 1.1 2006-06-23 19:03:42 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xipif_v1_23_b.c
*
* This file contains the implementation of the XIpIf component. The
* XIpIf component encapsulates the IPIF, which is the standard interface
* that IP must adhere to when connecting to a bus. The purpose of this
* component is to encapsulate the IPIF processing such that maintainability
* is increased. This component does not provide a lot of abstraction from
* from the details of the IPIF as it is considered a building block for
* device drivers. A device driver designer must be familiar with the
* details of the IPIF hardware to use this component.
*
* The IPIF hardware provides a building block for all hardware devices such
* that each device does not need to reimplement these building blocks. The
* IPIF contains other building blocks, such as FIFOs and DMA channels, which
* are also common to many devices. These blocks are implemented as separate
* hardware blocks and instantiated within the IPIF. The primary hardware of
* the IPIF which is implemented by this software component is the interrupt
* architecture. Since there are many blocks of a device which may generate
* interrupts, all the interrupt processing is contained in the common part
* of the device, the IPIF. This interrupt processing is for the device level
* only and does not include any processing for the interrupt controller.
*
* A device is a mechanism such as an Ethernet MAC. The device is made
* up of several parts which include an IPIF and the IP. The IPIF contains most
* of the device infrastructure which is common to all devices, such as
* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
* be referred to as IPIF internal blocks since they are part of the IPIF and
* are separate blocks that can be selected based upon the needs of the device.
* The IP of the device is the logic that is unique to the device and interfaces
* to the IPIF of the device.
*
* In general, there are two levels of registers within the IPIF. The first
* level, referred to as the device level, contains registers which are for the
* entire device. The second level, referred to as the IP level, contains
* registers which are specific to the IP of the device. The two levels of
* registers are designed to be hierarchical such that the device level is
* is a more general register set above the more specific registers of the IP.
* The IP level of registers provides functionality which is typically common
* across all devices and allows IP designers to focus on the unique aspects
* of the IP.
*
* The interrupt registers of the IPIF are parameterizable such that the only
* the number of bits necessary for the device are implemented. The functions
* of this component do not attempt to validate that the passed in arguments are
* valid based upon the number of implemented bits. This is necessary to
* maintain the level of performance required for the common components. Bits
* of the registers are assigned starting at the least significant bit of the
* registers.
*
* <b>Critical Sections</b>
*
* It is the responsibility of the device driver designer to use critical
* sections as necessary when calling functions of the IPIF. This component
* does not use critical sections and it does access registers using
* read-modify-write operations. Calls to IPIF functions from a main thread
* and from an interrupt context could produce unpredictable behavior such that
* the caller must provide the appropriate critical sections.
*
* <b>Mutual Exclusion</b>
*
* The functions of the IPIF are not thread safe such that the caller of all
* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
* exclusion across multiple IPIF components is not necessary.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.23b jhl 02/27/01 Repartioned to reduce size
* 1.23b rpm 08/17/04 Doxygenated for inclusion in API documentation
* 1.23b xd 10/27/04 Improve Doxygen format
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xipif_v1_23_b.h"
#include "xio.h"
 
/************************** Constant Definitions *****************************/
 
/* the following constant is used to generate bit masks for register testing
* in the self test functions, it defines the starting bit mask that is to be
* shifted from the LSB to MSB in creating a register test mask
*/
#define XIIF_V123B_FIRST_BIT_MASK 1UL
 
 
/* the following constant defines the maximum number of bits which may be
* used in the registers at the device and IP levels, this is based upon the
* number of bits available in the registers
*/
#define XIIF_V123B_MAX_REG_BIT_COUNT 32
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Variable Definitions *****************************/
 
 
/************************** Function Prototypes ******************************/
 
static XStatus IpIntrSelfTest(Xuint32 RegBaseAddress,
Xuint32 IpRegistersWidth);
 
/*****************************************************************************/
/**
*
* This function performs a self test on the specified IPIF component. Many
* of the registers in the IPIF are tested to ensure proper operation. This
* function is destructive because the IPIF is reset at the start of the test
* and at the end of the test to ensure predictable results. The IPIF reset
* also resets the entire device that uses the IPIF. This function exits with
* all interrupts for the device disabled.
*
* @param RegBaseAddress is the base address of the device's IPIF registers
*
* @param IpRegistersWidth contains the number of bits in the IP interrupt
* registers of the device. The hardware is parameterizable such that
* only the number of bits necessary to support a device are implemented.
* This value must be between 0 and 32 with 0 indicating there are no IP
* interrupt registers used.
*
* @return
*
* A value of XST_SUCCESS indicates the test was successful with no errors.
* Any one of the following error values may also be returned.
* <br><br>
* - XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
* not valid
* <br><br>
* - XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
* register did not read back correctly
* <br><br>
* - XST_IPIF_IP_ACK_ERROR One or more bits in the IP interrupt
* status register did not reset when acked
* <br><br>
* - XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
* did not read back correctly based upon
* what was written to it
*
* @note
*
* None.
*
******************************************************************************/
XStatus XIpIfV123b_SelfTest(Xuint32 RegBaseAddress,
Xuint8 IpRegistersWidth)
{
XStatus Status;
 
/* assert to verify arguments are valid */
 
XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT);
 
/* reset the IPIF such that it's in a known state before the test
* and interrupts are globally disabled
*/
XIIF_V123B_RESET(RegBaseAddress);
 
/* perform the self test on the IP interrupt registers, if
* it is not successful exit with the status
*/
Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth);
if (Status != XST_SUCCESS)
{
return Status;
}
 
/* reset the IPIF such that it's in a known state before exiting test */
 
XIIF_V123B_RESET(RegBaseAddress);
 
/* reaching this point means there were no errors, return success */
 
return XST_SUCCESS;
}
 
/*****************************************************************************
*
* Perform a self test on the IP interrupt registers of the IPIF. This
* function modifies registers of the IPIF such that they are not guaranteed
* to be in the same state when it returns. Any bits in the IP interrupt
* status register which are set are assumed to be set by default after a reset
* and are not tested in the test.
*
* @param RegBaseAddress is the base address of the device's IPIF registers
*
* @param IpRegistersWidth contains the number of bits in the IP interrupt
* registers of the device. The hardware is parameterizable such that
* only the number of bits necessary to support a device are implemented.
* This value must be between 0 and 32 with 0 indicating there are no IP
* interrupt registers used.
*
* @return
*
* A status indicating XST_SUCCESS if the test was successful. Otherwise, one
* of the following values is returned.
* - XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
* not valid
* <br><br>
* - XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
* register did not read back correctly
* <br><br>
* - XST_IPIF_IP_ACK_ERROR One or more bits in the IP status
* register did not reset when acked
* <br><br>
* - XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
* did not read back correctly based upon
* what was written to it
* @note
*
* None.
*
******************************************************************************/
static XStatus IpIntrSelfTest(Xuint32 RegBaseAddress, Xuint32 IpRegistersWidth)
{
/* ensure that the IP interrupt enable register is zero
* as it should be at reset, the interrupt status is dependent upon the
* IP such that it's reset value is not known
*/
if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0)
{
return XST_IPIF_RESET_REGISTER_ERROR;
}
 
/* if there are any used IP interrupts, then test all of the interrupt
* bits in all testable registers
*/
if (IpRegistersWidth > 0)
{
Xuint32 BitCount;
Xuint32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
Xuint32 Mask = XIIF_V123B_FIRST_BIT_MASK; /* bits assigned MSB to LSB */
Xuint32 InterruptStatus;
 
/* generate the register masks to be used for IP register tests, the
* number of bits supported by the hardware is parameterizable such
* that only that number of bits are implemented in the registers, the
* bits are allocated starting at the MSB of the registers
*/
for (BitCount = 1;
BitCount < IpRegistersWidth;
BitCount++)
{
Mask = Mask << 1;
IpInterruptMask |= Mask;
}
 
/* get the current IP interrupt status register contents, any bits
* already set must default to 1 at reset in the device and these
* bits can't be tested in the following test, remove these bits from
* the mask that was generated for the test
*/
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
IpInterruptMask &= ~InterruptStatus;
 
/* set the bits in the device status register and verify them by reading
* the register again, all bits of the register are latched
*/
XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
 
{
return XST_IPIF_IP_STATUS_ERROR;
}
 
/* test to ensure that the bits set in the IP interrupt status register
* can be cleared by acknowledging them in the IP interrupt status
* register then read it again and verify it was cleared
*/
XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
if ((InterruptStatus & IpInterruptMask) != 0)
{
return XST_IPIF_IP_ACK_ERROR;
}
 
/* set the IP interrupt enable set register and then read the IP
* interrupt enable register and verify the interrupts were enabled
*/
XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask)
{
return XST_IPIF_IP_ENABLE_ERROR;
}
 
/* clear the IP interrupt enable register and then read the
* IP interrupt enable register and verify the interrupts were disabled
*/
XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0)
{
return XST_IPIF_IP_ENABLE_ERROR;
}
}
return XST_SUCCESS;
}
/ipif_v1_23_b/src/Makefile
0,0 → 1,28
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
 
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
 
OUTS = *.o
 
LIBSOURCES=*.c
INCLUDEFILES=*.h
 
libs:
echo "Compiling ipif"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
 
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
 
clean:
rm -rf $(OUTS)
 
/gpio_v2_00_a/src/xgpio_selftest.c
0,0 → 1,99
/* $Id: xgpio_selftest.c,v 1.1 2006-06-23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/**
* @file xgpio_selftest.c
*
* The implementation of the XGpio component's self test function.
* See xgpio.h for more information about the component.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
#include "xgpio.h"
 
/************************** Constant Definitions ****************************/
 
/**************************** Type Definitions ******************************/
 
/***************** Macros (Inline Functions) Definitions ********************/
 
/************************** Variable Definitions ****************************/
 
/************************** Function Prototypes *****************************/
 
 
/******************************************************************************/
/**
* Run a self-test on the driver/device. This function does a minimal test
* in which the data register is read. It only does a read without any kind
* of test because the hardware has been parameterized such that it may be only
* an input such that the state of the inputs won't be known.
*
* All other hardware features of the device are not guaranteed to be in the
* hardware since they are parameterizable.
*
* ARGUMENTS:
*
* @param InstancePtr is a pointer to the XGpio instance to be worked on.
* This parameter must have been previously initialized with
* XGpio_Initialize().
*
* @return
*
* XST_SUCCESS always. If the GPIO device was not present in the hardware a bus
* error could be generated. Other indicators of a bus error, such as registers
* in bridges or buses, may be necessary to determine if this function caused
* a bus error.
*
* @note
*
* None.
*
******************************************************************************/
XStatus XGpio_SelfTest(XGpio *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Read from the data register of channel 1 which is always guaranteed
* to be in the hardware device. Since the data may be configured as
* all inputs, there is not way to guarantee the value read so don't
* test it.
*/
(void)XGpio_DiscreteRead(InstancePtr, 1);
 
return(XST_SUCCESS);
}
 
/gpio_v2_00_a/src/xgpio_intr.c
0,0 → 1,300
/* $Id */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_intr.c
*
* Implements GPIO interrupt processing functions for the XGpio
* component. See xgpio.h for more information about the component.
*
* The functions in this file require the hardware device to be built with
* interrupt capabilities. The functions will assert if called using hardware
* that does not have interrupt capabilities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.00a jhl 11/26/03 Initial release
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
#include "xgpio.h"
#include "xipif_v1_23_b.h"
 
/************************** Constant Definitions ****************************/
 
/* The following constant describes the offset of the interrupt registers
* that are contained in the IPIF. This offset should be added to the base
* address of the device when using the IPIF access functions.
*/
#define XGPIO_IPIF_OFFSET 0x100
 
/**************************** Type Definitions ******************************/
 
/***************** Macros (Inline Functions) Definitions ********************/
 
/************************** Variable Definitions ****************************/
 
/************************** Function Prototypes *****************************/
 
 
/****************************************************************************/
/**
* Enable the interrupt output signal. Interrupts enabled through
* XGpio_InterruptEnable() will not be passed through until the global enable
* bit is set by this function. This function is designed to allow all
* interrupts (both channels) to be enabled easily for exiting a critical
* section. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
 
 
XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET);
}
 
 
/****************************************************************************/
/**
* Disable the interrupt output signal. Interrupts enabled through
* XGpio_InterruptEnable() will no longer be passed through until the global
* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
* designed to allow all interrupts (both channels) to be disabled easily for
* entering a critical section. This function will assert if the hardware
* device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
 
XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET);
}
 
 
/****************************************************************************/
/**
* Enable interrupts. The global interrupt must also be enabled by calling
* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
* assert if the hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
* @param Mask is the mask to enable. Bit positions of 1 are enabled. This mask
* is formed by OR'ing bits from XGPIO_IR* bits which are contained in
* xgpio_l.h.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptEnable(XGpio *InstancePtr, Xuint32 Mask)
{
Xuint32 Register;
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
 
/* Read the interrupt enable register and only enable the specified
* interrupts without disabling or enabling any others.
*/
Register = XIIF_V123B_READ_IIER(InstancePtr->BaseAddress +
XGPIO_IPIF_OFFSET);
XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET,
Mask | Register);
}
 
 
/****************************************************************************/
/**
* Disable interrupts. This function allows specific interrupts for each
* channel to be disabled. This function will assert if the hardware device
* has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
* @param Mask is the mask to disable. Bits set to 1 are disabled. This mask
* is formed by OR'ing bits from XGPIO_IR* bits which are contained in
* xgpio_l.h.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptDisable(XGpio *InstancePtr, Xuint32 Mask)
{
Xuint32 Register;
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
 
/* Read the interrupt enable register and only disable the specified
* interrupts without enabling or disabling any others.
*/
Register = XIIF_V123B_READ_IIER(InstancePtr->BaseAddress +
XGPIO_IPIF_OFFSET);
XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET,
Mask & ~Register);
}
 
/****************************************************************************/
/**
* Clear pending interrupts with the provided mask. This function should be
* called after the software has serviced the interrupts that are pending.
* This function will assert if the hardware device has not been built with
* interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
* @param Mask is the mask to clear pending interrupts for. Bit positions of 1
* are cleared. This mask is formed by OR'ing bits from
* XGPIO_IR* bits which are contained in xgpio_l.h.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptClear(XGpio *InstancePtr, Xuint32 Mask)
{
Xuint32 Register;
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
 
/* Read the interrupt status register and only clear the interrupts
* that are specified without affecting any others. Since the register
* is a toggle on write, make sure any bits to be written are already
* set.
*/
Register = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress +
XGPIO_IPIF_OFFSET);
XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET,
Register & Mask);
}
 
 
/****************************************************************************/
/**
* Returns the interrupt enable mask. This function will assert if the
* hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
*
* @return A mask of bits made from XGPIO_IR* bits which are contained in
* xgpio_l.h.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
Xuint32 XGpio_InterruptGetEnabled(XGpio *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_NONVOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
 
 
return XIIF_V123B_READ_IIER(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET);
}
 
 
/****************************************************************************/
/**
* Returns the status of interrupt signals. Any bit in the mask set to 1
* indicates that the channel associated with the bit has asserted an interrupt
* condition. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
*
* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
* contained in xgpio_l.h.
*
* @note
*
* The interrupt status indicates the status of the device irregardless if
* the interrupts from the devices have been enabled or not through
* XGpio_InterruptEnable().
*
*****************************************************************************/
Xuint32 XGpio_InterruptGetStatus(XGpio *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_NONVOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
 
 
return XIIF_V123B_READ_IISR(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET);
}
 
/gpio_v2_00_a/src/xgpio_i.h
0,0 → 1,66
/* $Id: xgpio_i.h,v 1.1 2006-06-23 19:03:41 quickwayne Exp $: */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/******************************************************************************/
/**
* @file xgpio_i.h
*
* This header file contains internal identifiers, which are those shared
* between the files of the driver. It is intended for internal use only.
*
* NOTES:
*
* None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* </pre>
******************************************************************************/
 
#ifndef XGPIO_I_H /* prevent circular inclusions */
#define XGPIO_I_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xgpio.h"
 
/************************** Constant Definitions ****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
 
/************************** Variable Definitions ****************************/
 
extern XGpio_Config XGpio_ConfigTable[];
 
#endif /* end of protection macro */
 
/gpio_v2_00_a/src/xgpio.c
0,0 → 1,255
/* $Id: xgpio.c,v 1.1 2006-06-23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/**
* @file xgpio.c
*
* The implementation of the XGpio component's basic functionality. See xgpio.h
* for more information about the component.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
 
#include "xparameters.h"
#include "xgpio.h"
#include "xgpio_i.h"
#include "xstatus.h"
 
/************************** Constant Definitions ****************************/
 
/**************************** Type Definitions ******************************/
 
/***************** Macros (Inline Functions) Definitions ********************/
 
/************************** Variable Definitions ****************************/
 
 
/************************** Function Prototypes *****************************/
 
 
/****************************************************************************/
/**
* Initialize the XGpio instance provided by the caller based on the
* given DeviceID.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XGpio instance. The memory the pointer
* references must be pre-allocated by the caller. Further calls to
* manipulate the component through the XGpio API must be made with this
* pointer.
*
* @param DeviceId is the unique id of the device controlled by this XGpio
* component. Passing in a device id associates the generic XGpio
* instance to a specific device, as chosen by the caller or application
* developer.
*
* @return
*
* - XST_SUCCESS Initialization was successfull.
* - XST_DEVICE_NOT_FOUND Device configuration data was not found for a device
* with the supplied device ID.
*
* @note
*
* None.
*
*****************************************************************************/
XStatus XGpio_Initialize(XGpio *InstancePtr, Xuint16 DeviceId)
{
XGpio_Config *ConfigPtr;
 
/*
* Assert arguments
*/
XASSERT_NONVOID(InstancePtr != XNULL);
 
/*
* Lookup configuration data in the device configuration table.
* Use this configuration info down below when initializing this component.
*/
ConfigPtr = XGpio_LookupConfig(DeviceId);
if (ConfigPtr == (XGpio_Config *)XNULL)
{
InstancePtr->IsReady = 0;
return(XST_DEVICE_NOT_FOUND);
}
 
/*
* Set some default values.
*/
InstancePtr->BaseAddress = ConfigPtr->BaseAddress;
InstancePtr->ConfigPtr = ConfigPtr;
 
/*
* Indicate the instance is now ready to use, initialized without error
*/
InstancePtr->IsReady = XCOMPONENT_IS_READY;
return(XST_SUCCESS);
}
 
 
/******************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* ConfigTable contains the configuration info for each device in the system.
*
* @param DeviceId is the device identifier to lookup.
*
* @return
*
* - A pointer of data type XGpio_Config which points to the device
* configuration if DeviceID is found.
* - XNULL if DeviceID is not found.
*
* @note
*
* None.
*
******************************************************************************/
XGpio_Config *XGpio_LookupConfig(Xuint16 DeviceId)
{
XGpio_Config *CfgPtr = XNULL;
 
int i;
 
for (i=0; i < XPAR_XGPIO_NUM_INSTANCES; i++)
{
if (XGpio_ConfigTable[i].DeviceId == DeviceId)
{
CfgPtr = &XGpio_ConfigTable[i];
break;
}
}
 
return CfgPtr;
}
 
 
/****************************************************************************/
/**
* Set the input/output direction of all discrete signals for the specified
* GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param DirectionMask is a bitmask specifying which discretes are input and
* which are output. Bits set to 0 are output and bits set to 1 are input.
*
* @return
*
* None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
Xuint32 DirectionMask)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
 
XGpio_mWriteReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
DirectionMask);
}
 
 
/****************************************************************************/
/**
* Read state of discretes for the specified GPIO channnel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
*
* @return Current copy of the discretes register.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
Xuint32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_NONVOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
return XGpio_mReadReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) +
XGPIO_DATA_OFFSET);
}
 
/****************************************************************************/
/**
* Write to discretes register for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Data is the value to be written to the discretes register.
*
* @return
*
* None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
* See also XGpio_DiscreteSet() and XGpio_DiscreteClear().
*
*****************************************************************************/
void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, Xuint32 Data)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
 
XGpio_mWriteReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
Data);
}
 
/gpio_v2_00_a/src/xgpio_l.h
0,0 → 1,221
/* $Id: xgpio_l.h,v 1.1 2006-06-23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpio_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xgpio.h.
*
* The macros that are available in this file use a multiply to calculate the
* addresses of registers. The user can control whether that multiply is done
* at run time or at compile time. A constant passed as the channel parameter
* will cause the multiply to be done at compile time. A variable passed as the
* channel parameter will cause it to occur at run time.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a jhl 04/24/02 First release of low level driver
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
* change required the functions to be changed such that
* the interface is not compatible with previous versions.
* See the examples in the example directory for macros
* to help compile an application that was designed for
* previous versions of the driver. The interrupt registers
* are accessible using the ReadReg and WriteReg macros and
* a channel parameter was added to the other macros.
* </pre>
*
******************************************************************************/
 
#ifndef XGPIO_L_H /* prevent circular inclusions */
#define XGPIO_L_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
#include "xio.h"
 
/************************** Constant Definitions *****************************/
 
/** @name Registers
*
* Register offsets for this device. This device utilizes IPIF interrupt
* registers.
* @{
*/
#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction register for 1st channel */
#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction register for 2nd channel */
 
#define XGPIO_GIER_OFFSET 0x11C /**< Glogal interrupt enable register */
#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
 
/* @} */
 
/* The following constant describes the offset of each channels data and
* tristate register from the base address.
*/
#define XGPIO_CHAN_OFFSET 8
 
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the interrupt status register and interrupt enable
* registers.
* @{
*/
#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
/*@}*/
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/****************************************************************************/
/**
*
* Write a value to a GPIO register. A 32 bit write is performed. If the
* GPIO component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the GPIO device.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note None.
*
* C-style signature:
* void XGpio_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset,
* Xuint32 Data)
*
****************************************************************************/
#define XGpio_mWriteReg(BaseAddress, RegOffset, Data) \
XIo_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
 
/****************************************************************************/
/**
*
* Read a value from a GPIO register. A 32 bit read is performed. If the
* GPIO component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the GPIO device.
* @param Register is the register offset from the base to read from.
* @param Data is the data from the register.
*
* @return None.
*
* @note None.
*
* C-style signature:
* Xuint32 XGpio_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
*
****************************************************************************/
#define XGpio_mReadReg(BaseAddress, RegOffset) \
XIo_In32((BaseAddress) + (RegOffset))
 
/*****************************************************************************
*
* Set the input/output direction of the signals of the specified GPIO channel.
*
* @param BaseAddress contains the base address of the GPIO device.
* @param Channel contains the channel (1 or 2) to operate on.
* @param DirectionMask is a bitmask specifying which discretes are input and
* which are output. Bits set to 0 are output and bits set to 1 are
* input.
*
* @return None.
*
* @note None.
*
* C-style signature:
* void XGpio_mSetDataDirection(Xuint32 BaseAddress, unsigned Channel,
* Xuint32 DirectionMask)
*
******************************************************************************/
#define XGpio_mSetDataDirection(BaseAddress, Channel, DirectionMask) \
XGpio_mWriteReg((BaseAddress), \
(((Channel) - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET, \
(DirectionMask))
 
/****************************************************************************/
/**
* Get the data register of the specified GPIO channel.
*
* @param BaseAddress contains the base address of the GPIO device.
* @param Channel contains the channel (1 or 2) to operate on.
*
* @return The contents of the data register.
*
* @note None.
*
* C-style signature:
* Xuint32 XGpio_mGetDataReg(Xuint32 BaseAddress, unsigned Channel)
*
*****************************************************************************/
#define XGpio_mGetDataReg(BaseAddress, Channel) \
XGpio_mReadReg((BaseAddress), \
(((Channel) - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET)
 
/****************************************************************************/
/**
* Set the data register of the specified GPIO channel.
*
* @param BaseAddress contains the base address of the GPIO device.
* @param Channel contains the channel (1 or 2) to operate on.
* @param Data is the value to be written to the data register.
*
* @return None.
*
* @note None.
*
* C-style signature:
* void XGpio_mSetDataReg(Xuint32 BaseAddress, unsigned Channel,
* Xuint32 Data)
*
*****************************************************************************/
#define XGpio_mSetDataReg(BaseAddress, Channel, Data) \
XGpio_mWriteReg((BaseAddress), \
(((Channel) - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,\
(Data))
 
/************************** Function Prototypes ******************************/
 
/************************** Variable Definitions *****************************/
 
#endif /* end of protection macro */
 
/gpio_v2_00_a/src/xgpio_extra.c
0,0 → 1,143
/* $Id: xgpio_extra.c,v 1.1 2006-06-23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 -2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/**
* @file xgpio_extra.c
*
* The implementation of the XGpio component's advanced discrete functions.
* See xgpio.h for more information about the component.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
 
#include "xgpio.h"
#include "xgpio_i.h"
 
/************************** Constant Definitions ****************************/
 
/**************************** Type Definitions ******************************/
 
/***************** Macros (Inline Functions) Definitions ********************/
 
/************************** Variable Definitions ****************************/
 
/************************** Function Prototypes *****************************/
 
 
/****************************************************************************/
/**
* Set output discrete(s) to logic 1 for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Mask is the set of bits that will be set to 1 in the discrete data
* register. All other bits in the data register are unaffected.
*
* @return
*
* None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask)
{
Xuint32 Current;
unsigned DataOffset;
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
 
/* Calculate the offset to the data register of the GPIO once */
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
* Read the contents of the data register, merge in Mask and write
* back results
*/
Current = XGpio_mReadReg(InstancePtr->BaseAddress, DataOffset);
Current |= Mask;
XGpio_mWriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}
 
 
/****************************************************************************/
/**
* Set output discrete(s) to logic 0 for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Mask is the set of bits that will be set to 0 in the discrete data
* register. All other bits in the data register are unaffected.
*
* @return
*
* None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask)
{
Xuint32 Current;
unsigned DataOffset;
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
 
/* Calculate the offset to the data register of the GPIO once */
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
* Read the contents of the data register, merge in Mask and write
* back results
*/
Current = XGpio_mReadReg(InstancePtr->BaseAddress, DataOffset);
Current &= ~Mask;
XGpio_mWriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}
 
/gpio_v2_00_a/src/xgpio.h
0,0 → 1,133
/* $Id: xgpio.h,v 1.1 2006-06-23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio.h
*
* This file contains the software API definition of the Xilinx General Purpose
* I/O (XGpio) device driver component.
*
* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs on
* the OPB or PLB bus and contains the following general features:
* - Support for up to 32 I/O discretes for each channel (64 bits total).
* - Each of the discretes can be configured for input or output.
* - Configurable support for dual channels and interrupt generation.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* @note
*
* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
* the unused bits from registers are read as zero and written as don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
* </pre>
*****************************************************************************/
 
#ifndef XGPIO_H /* prevent circular inclusions */
#define XGPIO_H /* by using protection macros */
 
/***************************** Include Files ********************************/
 
#include "xbasic_types.h"
#include "xstatus.h"
#include "xgpio_l.h"
 
/************************** Constant Definitions ****************************/
 
/**************************** Type Definitions ******************************/
 
/**
* This typedef contains configuration information for the device.
*/
typedef struct
{
Xuint16 DeviceId; /* Unique ID of device */
Xuint32 BaseAddress; /* Device base address */
Xboolean InterruptPresent; /* Are interrupts supported in h/w */
Xboolean IsDual; /* Are 2 channels supported in h/w */
} XGpio_Config;
 
/**
* The XGpio driver instance data. The user is required to allocate a
* variable of this type for every GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct
{
Xuint32 BaseAddress; /* Device base address */
Xuint32 IsReady; /* Device is initialized and ready */
XGpio_Config *ConfigPtr;/* Pointer to the configuration */
} XGpio;
 
/***************** Macros (Inline Functions) Definitions ********************/
 
 
/************************** Function Prototypes *****************************/
 
/*
* API Basic functions implemented in xgpio.c
*/
XStatus XGpio_Initialize(XGpio *InstancePtr, Xuint16 DeviceId);
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
Xuint32 DirectionMask);
Xuint32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask);
 
XGpio_Config *XGpio_LookupConfig(Xuint16 DeviceId);
 
/*
* API Functions implemented in xgpio_extra.c
*/
void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask);
void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask);
 
/*
* API Functions implemented in xgpio_selftest.c
*/
XStatus XGpio_SelfTest(XGpio *InstancePtr);
 
/*
* API Functions implemented in xgpio_intr.c
*/
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
void XGpio_InterruptEnable(XGpio *InstancePtr, Xuint32 Mask);
void XGpio_InterruptDisable(XGpio *InstancePtr, Xuint32 Mask);
void XGpio_InterruptClear(XGpio *InstancePtr, Xuint32 Mask);
Xuint32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
Xuint32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
 
#endif /* end of protection macro */
 
/gpio_v2_00_a/src/Makefile
0,0 → 1,28
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
 
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
 
INCLUDEFILES=xgpio_l.h xgpio.h
 
LIBSOURCES=*.c
OUTS = *.o
 
 
libs:
echo "Compiling gpio"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
make clean
 
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
 
clean:
rm -rf ${OUTS}
/gpio_v2_00_a/src/xgpio_g.c
0,0 → 1,43
 
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Driver configuration
*
*******************************************************************/
 
#include "xparameters.h"
#include "xgpio.h"
 
/*
* The configuration table for devices
*/
 
XGpio_Config XGpio_ConfigTable[] =
{
{
XPAR_LEDS_4BIT_DEVICE_ID,
XPAR_LEDS_4BIT_BASEADDR,
XPAR_LEDS_4BIT_INTERRUPT_PRESENT,
XPAR_LEDS_4BIT_IS_DUAL
},
{
XPAR_DIPSWS_4BIT_DEVICE_ID,
XPAR_DIPSWS_4BIT_BASEADDR,
XPAR_DIPSWS_4BIT_INTERRUPT_PRESENT,
XPAR_DIPSWS_4BIT_IS_DUAL
},
{
XPAR_PUSHBUTTONS_5BIT_DEVICE_ID,
XPAR_PUSHBUTTONS_5BIT_BASEADDR,
XPAR_PUSHBUTTONS_5BIT_INTERRUPT_PRESENT,
XPAR_PUSHBUTTONS_5BIT_IS_DUAL
}
};
 
 
/xilfatfs_v1_00_a/src/Makefile.config --- xilfatfs_v1_00_a/src/include/sysace_stdio.h (nonexistent) +++ xilfatfs_v1_00_a/src/include/sysace_stdio.h (revision 66) @@ -0,0 +1,51 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2002-2004 Xilinx, Inc. All rights reserved. +// +// Xilinx, Inc. +// +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +///////////////////////////////////////////////////////////////////////////// + + +#ifndef _SYSACE_STDIO_H_ +#define _SYSACE_STDIO_H_ + + +#define SYSACE_FILE void +#include + +// IF YOU WANT TO USE fopen instead of sysace_fopen, +// and fclose, fread and fwrite instead of the corresponding +// sysace_ prefixed function names uncomment the following few lines +// and comment out the preceding two lines of code +// WARNING: This will cause link time failures for functions +// such as printf and scanf that depend on standard definitions of fwrite/fread +// so use with caution +// #define SYSACE_FILE FILE +// typedef void FILE; +// +// #define fopen sysace_fopen +// #define fclose sysace_fclose +// #define fread sysace_fread +// #define fwrite sysace_fwrite + + +SYSACE_FILE *sysace_fopen(const char *file, const char *mode ); +int sysace_fclose(SYSACE_FILE *stream ); +int sysace_fread(void *buffer, int size, int count, SYSACE_FILE *stream ); +int sysace_fwrite(void *buffer, int size, int count, SYSACE_FILE *stream ); +int sysace_mkdir(const char *path); +int sysace_chdir(const char *path); + +#endif
/xilfatfs_v1_00_a/src/include/alloc.h
0,0 → 1,35
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#ifndef __ALLOC_H_
#define __ALLOC_H_
 
#include "filestatus.h"
#include "fat.h"
 
#define MAXWD MAXFILES * 10
 
FileStatus * malloc_fs(void);
void free_fs(FileStatus *fs);
 
WorkingDirectory *malloc_wd(const char *name);
void free_wd(WorkingDirectory *wd);
 
#endif
/xilfatfs_v1_00_a/src/include/fat.h
0,0 → 1,144
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
#ifndef __FAT_H_
#define __FAT_H_
 
#include "sysace.h"
#include "part.h"
#include "directory.h"
#include "fsinfo.h"
 
#define MAX_BYTES_PER_CLUSTER (32*1024)
 
#define MAX_FAT12_CLUSTERS 0x0FF5
#define MAX_FAT16_CLUSTERS 0xFFF5
#define MAX_FAT32_CLUSTERS 0x0FFFFFF5
 
#define FAT12_BAD_CLUSTER 0x0FF7
#define FAT16_BAD_CLUSTER 0xFFF7
#define FAT32_BAD_CLUSTER 0x0FFFFFF7
 
#define FAT12_EOC 0x0FF8
#define FAT16_EOC 0xFFF8
#define FAT32_EOC 0x0FFFFFF8
 
/* defined for convenience, not per spec */
#define BAD_CLUSTER 0xFFFFFFFF
 
/* FAT file system info present in a FAT partition */
typedef struct _BiosParameterBlock {
BYTE BytesPerSector[2];
BYTE SectorsPerCluster;
BYTE ReservedSector[2];
BYTE NumberOfFats;
BYTE RootDirCount[2];
BYTE TotalSectors16[2];
BYTE MediaType;
BYTE SectorsPerFat[2];
BYTE SectorsPerTrack[2];
BYTE NumberOfHeads[2];
BYTE NumberOfHiddenSect[4];
BYTE TotalSectors32[4];
 
/* following fields are present only in FAT32 */
BYTE SectorsPerFat_32[4];
BYTE ExtFlags[2];
BYTE FSVer[2];
BYTE RootCluster[4];
BYTE FSInfo[2];
BYTE BkBootSector[2];
BYTE Reserved[12];
 
} __attribute__((packed)) BiosParameterBlock;
 
/* organization of the first sector of a FAT partition */
typedef struct _PartitionBootRecord {
BYTE JMPCode[3];
BYTE OEMNameVersion[8];
BiosParameterBlock BPB;
BYTE DriverNumber;
BYTE Reserved;
BYTE ExtendBootSig;
BYTE VolID[4];
BYTE VolLable[11];
BYTE FileSysType[8];
BYTE BootCode[420];
BYTE BootCodeSignature[2];
} __attribute__((packed)) PartitionBootRecord;
 
/* Information about the current working directory */
#define MAXFILENAMESIZE 13 // 8.3 plus a trailing 0
 
typedef struct _WorkingDirectory {
char name[MAXFILENAMESIZE];
 
/* If this is null, this is a root directory */
struct _WorkingDirectory *parent;
 
/* This is a pointer to statically allocated information - never free */
PartitionInfo *pi;
 
union {
struct { /* These values are only defined for a root directory */
UINT32 StartSector;
UINT16 DirCount;
} root;
 
struct { /* These values are only defined for a child directory */
UINT32 FirstCluster;
UINT32 FileSize;
DirectoryEntryLocation DirLocation;
} child;
} v;
} WorkingDirectory;
 
UINT32 next_cluster(UINT32 cluster, PartitionInfo *pi);
UINT32 starting_sector(UINT32 cluster, PartitionInfo *pi);
 
PartitionInfo *get_partition_info(int partition);
int find_in_directory(WorkingDirectory *wd, const char *name,
const char *ext, UINT32 *firstcluster, UINT32 *filesize,
UINT32 *de_sector, UINT32 *de_offset);
void delete_working_directory_stack(WorkingDirectory *wd);
WorkingDirectory *build_working_directory_stack(const char *path, int is_dir, int is_write);
WorkingDirectory *make_root_directory(int partition);
WorkingDirectory *make_child_directory(const char *name, const char *ext, WorkingDirectory *parent);
WorkingDirectory *copy_directory_stack(WorkingDirectory *stack);
WorkingDirectory *create_file_entry(const char *name, const char *ext,
WorkingDirectory *parent, BYTE attributes);
 
/* FIXME */
UINT32 allocate_one_cluster(PartitionInfo *pi);
void initialize_de(DirectoryEntry *de, char *name, char *ext,
UINT32 firstcluster, UINT32 filesize, PartitionInfo *pi, BYTE attrib);
 
int link_cluster(UINT32 from_cluster, UINT32 to_cluster, PartitionInfo *pi);
int truncate_file(UINT32 cluster, PartitionInfo *pi);
 
UINT32 next_cluster_generic(UINT32 cluster, PartitionInfo * pi);
int free_cluster_chain_generic(UINT32 cluster, PartitionInfo *pi);
UINT32 allocate_one_cluster_generic(PartitionInfo *pi);
int link_cluster_generic(UINT32 from_cluster, UINT32 to_cluster, PartitionInfo *pi);
 
extern WorkingDirectory *cwd[MAXPARTITION];
extern int DefaultPartition;
extern DirectoryEntry dotdot_entry[2];
 
#endif
/xilfatfs_v1_00_a/src/include/filespec.h
0,0 → 1,28
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
////////////////////////////////////////////////////////////////////////////
 
// Directory separator
#define DIRSEPCHAR '\\'
#define DIRSEPSTRING "\\"
 
typedef enum _field_type { PATH_START, DEVICE_NAME, DIR_NAME,
FILE_NAME, FILE_EXT, PATH_ERROR, PATH_DONE } field_type;
 
 
int parse_path( const char *path, char *buf, int length, int is_dir, field_type *type );
/xilfatfs_v1_00_a/src/include/fatops.h
0,0 → 1,43
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
#ifndef __FAT_OPS_H_
#define __FAT_OPS_H_
 
#include <sysace.h>
 
/* forward reference */
struct _PartitionInfo;
 
typedef struct _fat_ops {
UINT32 (*get_fat_sector_for_cluster)(UINT32 cluster, struct _PartitionInfo *pi);
UINT32 (*get_fat_offset_for_cluster)(UINT32 cluster, struct _PartitionInfo *pi);
UINT32 (*get_next_cluster)(BYTE *fat_entry, struct _PartitionInfo *pi);
void (*set_next_cluster)(BYTE *fat_entry, UINT32 next_cluster, struct _PartitionInfo *pi);
int (*is_eoc)(UINT32 cluster, struct _PartitionInfo *pi);
int (*is_valid_cluster)(UINT32 cluster, struct _PartitionInfo *pi);
UINT32 (*next_cluster)(UINT32 cluster, struct _PartitionInfo * pi);
int (*free_cluster_chain)(UINT32 cluster, struct _PartitionInfo *pi);
UINT32 (*allocate_one_cluster)(struct _PartitionInfo *pi);
int (*link_cluster)(UINT32 from_cluster, UINT32 to_cluster, struct _PartitionInfo *pi);
} fat_ops;
 
extern fat_ops fat12_ops, fat16_ops, fat32_ops;
 
#endif
/xilfatfs_v1_00_a/src/include/util.h
0,0 → 1,42
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
#ifndef __STANDALONE_UTILS_H_
#define __STANDALONE_UTILS_H_
 
#ifdef TESTING_XILFATFS
 
int printf(char *, ...);
 
#define xil_printf printf
#define print printf
 
#define debug_xil_printf(format, ...) printf(format, __VA_ARGS__)
#define debug_print(format) printf(format)
#define debug_putnum(num) printf("%x\n", num)
 
#else
 
#define debug_xil_printf(...)
#define debug_print(...)
#define debug_putnum(...)
 
#endif
 
#endif
/xilfatfs_v1_00_a/src/include/stats.h
0,0 → 1,30
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#ifndef __STATS_H_
#define __STATS_H_
 
extern unsigned int xilfatfs_stats_read;
extern unsigned int xilfatfs_stats_write;
 
extern void init_xilfatfs_stats();
extern void dump_xilfatfs_stats();
 
#endif
/xilfatfs_v1_00_a/src/include/bufcache.h
0,0 → 1,45
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#ifndef __BUFCACHE_H_
#define __BUFCACHE_H_
 
#include "sysace.h"
 
/* return the index of sector in buffer cache if present,
* -1 if sector not in buffer cache
*/
int is_buffered(unsigned int sector);
 
/* initialize buffer cache.
* should be called before any other function to bufcache
*/
void init_bufcache(int (*ll_write)(UINT32 sector, BYTE *buf));
 
/* update buffer cache with data for @sector */
int update_bufcache(int sector, unsigned char *sector_buf, int dirty);
 
/* read data for @sector from buffer cache */
int read_bufcache(int sector, unsigned char *sector_buf);
 
/* sync dirty entries to the disk using the low level write function (*ll_write) */
int sync_bufcache();
 
#endif
/xilfatfs_v1_00_a/src/include/filestatus.h
0,0 → 1,43
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#ifndef __FILESTATUS_H_
#define __FILESTATUS_H_
 
#include "fat.h"
#include "sysace_stdio.h"
 
typedef struct _FileStatus {
WorkingDirectory *wd;
BYTE read;
BYTE write;
UINT32 CurrentCluster;
UINT32 PositionInCluster; // Bytes from start of cluster
UINT32 PositionInFile; // Bytes from start of file
struct _FileStatus *next;
int reserved; // Reserved for allocation code
} FileStatus;
 
FileStatus *find_file_status(SYSACE_FILE *stream);
FileStatus *create_file_status(WorkingDirectory * wd,
BYTE read, BYTE write);
int delete_file_status(FileStatus * status);
 
#endif
/xilfatfs_v1_00_a/src/include/directory.h
0,0 → 1,63
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
#ifndef __DIRECTORY_H_
#define __DIRECTORY_H_
 
#include "fsinfo.h"
 
#define DIRENT_SIZE 32 // Directory entry size in bytes
#define LOG2_DIRENT_SIZE 5
 
/* File attributes */
#define ATTR_ARCHIVE 0x20
#define ATTR_DIRECTORY 0x10
#define ATTR_VOLUME_ID 0x08
#define ATTR_SYSTEM 0x04
#define ATTR_HIDDEN 0x02
#define ATTR_READ_ONLY 0x01
 
#define ATTR_LONG_NAME (ATTR_READ_ONLY|ATTR_HIDDEN|ATTR_SYSTEM|ATTR_VOLUME_ID)
#define ATTR_LONG_NAME_MASK (ATTR_LONG_NAME|ATTR_DIRECTORY|ATTR_ARCHIVE)
 
typedef struct _DirectoryEntry {
BYTE Name[8];
BYTE Extension[3];
BYTE Attributes;
BYTE Reserved[8];
BYTE FirstClusterOfFile_hi[2];
BYTE TimeStamp[2];
BYTE Date[2];
BYTE FirstClusterOfFile[2];
BYTE FileSize[4];
} __attribute__((packed)) DirectoryEntry;
 
/* Pointer to the sector/offset of the directory entry
* corresponding to a file
*/
typedef struct _DirectoryEntryLocation {
UINT32 sector;
UINT32 offset;
} DirectoryEntryLocation;
 
void update_de_filesize(DirectoryEntry *de, UINT32 filesize);
void update_de_firstcluster(DirectoryEntry *de, UINT32 firstcluster,
PartitionInfo *pi);
 
#endif
/xilfatfs_v1_00_a/src/include/fsinfo.h
0,0 → 1,51
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
#ifndef __FSINFO_H_
#define __FSINFO_H_
 
#include <fatops.h>
 
/* Structures for internal use */
typedef enum _FSType { FAT12, FAT16, FAT32 } FSType;
 
/* This hold pertinent information about a partition.
* This can only be created if the partition is FAT
* and all parameters are valid.
*/
typedef struct _PartitionInfo {
int PartitionNum;
UINT32 StartSector;
UINT32 TotalSectors;
UINT16 BytesPerSector;
BYTE SectorsPerCluster;
UINT32 SectorsPerFat;
BYTE NumberOfFats;
UINT16 RootDirCount;
UINT32 FatSector;
UINT32 RootDirSector;
UINT32 DataSector;
 
FSType FatType;
UINT32 RootCluster; /* used only for FAT32 */
 
fat_ops *op;
} PartitionInfo;
 
#endif
/xilfatfs_v1_00_a/src/include/part.h
0,0 → 1,45
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
 
#ifndef __PART_H_
#define __PART_H_
 
#define MAXPARTITION 4 /* Maximum number of partitions */
 
typedef struct _PartitionEntry {
BYTE x86DefaultBP;
BYTE startHead;
BYTE StartSector;
BYTE StartCyclinder;
BYTE PartitionEntryType; /* Describes Partition Type FAT12, 16 */
BYTE EndHead;
BYTE EndSector;
BYTE EndCyclinder;
BYTE PartitionSector[4];
BYTE TotalSectors[4]; /* partition size */
} __attribute__((packed)) PartitionEntry;
 
typedef struct _MasterBootRecord {
BYTE BootCode[446];
PartitionEntry PartitionEntry[MAXPARTITION];
BYTE Signature[2];
} __attribute__((packed)) MasterBootRecord;
 
#endif
/xilfatfs_v1_00_a/src/include/sysace.h
0,0 → 1,50
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003, 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//////////////////////////////////////////////////////////////////////////
 
 
#ifndef __SYSACE_H__
#define __SYSACE_H__
 
typedef unsigned char BYTE;
typedef unsigned short UINT16;
typedef unsigned long UINT32;
 
#define SECTORSIZE 512 // sector size in bytes
 
/* interface functions to SystemAce */
int init_ace();
int read_sector(UINT32 sector, BYTE *pSectorBuffer );
int write_sector(UINT32 sector, BYTE *pSectorBuffer );
 
#define make_UINT16(b1, b0) ( ((b1)<<8) | (b0) )
#define make_UINT32(b3, b2, b1, b0) ( ((b3)<<24) | ((b2)<<16) | ((b1)<<8) | (b0) )
 
#define write_UINT32(addr, val) do { \
*((BYTE *)addr) = ((BYTE)val&0xff); \
*(((BYTE *)addr) + 1) = ((BYTE)(val>>8)&0xff); \
*(((BYTE *)addr) + 2) = ((BYTE)(val>>16)&0xff); \
*(((BYTE *)addr) + 3) = ((BYTE)(val>>24)&0xff); \
} while (0);
 
#define write_UINT16(addr, val) do { \
*((BYTE *)addr) = ((BYTE)val&0xff); \
*(((BYTE *)addr) + 1) = ((BYTE)(val>>8)&0xff); \
} while (0);
 
#endif /* __SYSACE_H__ */
/xilfatfs_v1_00_a/src/src/xilfatfs_stats.c
0,0 → 1,39
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include <stdio.h>
 
#include "stats.h"
#include "util.h"
 
unsigned int xilfatfs_stats_read;
unsigned int xilfatfs_stats_write;
 
void init_xilfatfs_stats()
{
xilfatfs_stats_read = 0;
xilfatfs_stats_write = 0;
}
 
void dump_xilfatfs_stats()
{
xil_printf("# of sysace reads: %d\n\r", xilfatfs_stats_read);
xil_printf("# of sysace writes: %d\n\r", xilfatfs_stats_write);
}
/xilfatfs_v1_00_a/src/src/xilfatfs_bufcache.c
0,0 → 1,148
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include <string.h>
 
#include "xparameters.h"
#include "sysace.h"
#include "bufcache.h"
#include "util.h"
 
struct bufcache_status_s {
unsigned char valid;
unsigned char dirty;
int sector;
};
 
#define N_BUFCACHE_ENTRIES ((XILFATFS_BUFCACHE_SIZE/SECTORSIZE))
 
struct bufcache_status_s bc_status[N_BUFCACHE_ENTRIES];
unsigned char bc[XILFATFS_BUFCACHE_SIZE];
int bc_replace_index;
 
int (*ll_write)(UINT32 sector, BYTE *buf);
 
/* return the index of sector in buffer cache if present,
* -1 if sector not in buffer cache
*/
int is_buffered(unsigned int sector)
{
int i;
 
for (i = 0; i < N_BUFCACHE_ENTRIES; i++)
if (bc_status[i].valid && bc_status[i].sector == sector)
return i;
return -1;
}
 
/* get a free entry in the buffer cache */
int bc_get_free_entry()
{
int i;
 
for (i = 0; i < N_BUFCACHE_ENTRIES; i++)
if (!bc_status[i].valid)
return i;
 
return -1;
}
 
/* find free space by replacing an entry */
int sequential_replace()
{
int cur_index = bc_replace_index;
bc_replace_index = (bc_replace_index + 1)%N_BUFCACHE_ENTRIES;
 
if (!bc_status[cur_index].valid) {
/* current entry to be replaced is not in use */
return cur_index;
}
 
if (bc_status[cur_index].dirty) {
/* sync the current entry to disk */
int n = (*ll_write)(bc_status[cur_index].sector,
(bc+cur_index*SECTORSIZE));
if (n != SECTORSIZE) {
/* fatal - cannot be synced */
return -1;
}
bc_status[cur_index].dirty = 0;
}
 
return cur_index;
}
 
/* initialize buffer cache.
* use the low level write function (*ll_write_fn) when required to sync to disk
* should be called before any other function to bufcache
*/
void init_bufcache(int (*ll_write_fn)(UINT32 sector, BYTE *buf))
{
memset(bc_status, 0, sizeof (bc_status));
bc_replace_index = 0;
ll_write = ll_write_fn;
}
 
/* update buffer cache with data for @sector */
int update_bufcache(int sector, unsigned char *sector_buf, int dirty)
{
int index = is_buffered(sector);
 
if (index < 0) /* if not buffered */
index = bc_get_free_entry();
 
if (index < 0) { /* not buffered, and no free entry in the cache */
index = sequential_replace(); /* replace something */
if (index < 0)
return -1;
}
bc_status[index].valid = 1;
bc_status[index].dirty = dirty;
bc_status[index].sector = sector;
 
memcpy(bc + index*SECTORSIZE, sector_buf, SECTORSIZE);
return SECTORSIZE;
}
 
/* read data for @sector from buffer cache */
int read_bufcache(int sector, unsigned char *sector_buf)
{
int n = is_buffered(sector);
if (n < 0)
return -1;
memcpy(sector_buf, bc + n*SECTORSIZE, SECTORSIZE);
return SECTORSIZE;
}
 
/* sync dirty entries to the disk */
int sync_bufcache()
{
int i, error = 0;
 
for (i = 0; i < N_BUFCACHE_ENTRIES; i++)
if (bc_status[i].valid && bc_status[i].dirty) {
if ((*ll_write)(bc_status[i].sector, bc + i*SECTORSIZE) != SECTORSIZE)
error = 1;
bc_status[i].dirty = 0;
}
 
return -error;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_open.c
0,0 → 1,51
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include <string.h>
#include "sysace_stdio.h"
#include "fat.h"
#include "filestatus.h"
 
SYSACE_FILE *sysace_fopen(const char *file, const char *mode)
{
BYTE read = 0;
BYTE write = 0;
WorkingDirectory *wd;
FileStatus *ps;
 
/* only "r" and "w" modes are supported */
if (!strcmp(mode, "r"))
read = 1;
else if (!strcmp(mode, "w"))
write = 1;
else
return 0;
 
/* create a working directory stack for the file */
if ((wd = build_working_directory_stack(file, 0, write)) == 0)
return 0;
 
if ((ps = create_file_status(wd, read, write)) == 0) {
delete_working_directory_stack(wd);
return 0;
}
 
return (SYSACE_FILE *) ps;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_directory.c
0,0 → 1,273
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include <ctype.h>
#include <string.h>
#include "fat.h"
#include "filespec.h"
#include "alloc.h"
#include "directory.h"
 
int dir_name_compare(const char *a, const char *b, int n)
{
char ac, bc;
int an = strlen(a);
 
while (an > 0 && *a) {
ac = tolower(*a);
bc = tolower(*b);
 
if (ac < bc)
return -1;
if (ac > bc)
return 1;
 
++a;
++b;
--n;
--an;
}
 
while (n > 0) { /* finished text chars now check for trailing spaces */
if (*b != ' ')
return -1;
 
++b;
--n;
}
 
if (n == 0)
return 0;
if (*b)
return 1;
 
return 0;
}
 
/* Locate the named file or directory in the specified working directory
* The name is not hierarchical. Set ext = NULL to find a directory.
* Set ext = name = NULL to find an free entry
*/
int find_in_directory(WorkingDirectory *wd, const char *name,
const char *ext, UINT32 * firstcluster,
UINT32 * filesize, UINT32 *de_sector, UINT32 *de_offset)
{
BYTE buf[SECTORSIZE];
int bufcount;
int is_sub_dir = 0;
UINT32 sector;
UINT32 filecount;
UINT32 nsectors;
UINT32 cluster;
DirectoryEntry *de;
 
if (wd->pi->FatType != FAT32 && wd->parent == 0) {
/* Root directory */
filecount = wd->v.root.DirCount * DIRENT_SIZE;
sector = wd->v.root.StartSector;
nsectors = filecount / SECTORSIZE;
cluster = 0;
} else {
/* Child directory || FAT32
* (In Fat32 root & child are treated similarly) */
cluster = wd->v.child.FirstCluster;
sector = starting_sector(cluster, wd->pi);
nsectors = wd->pi->SectorsPerCluster;
filecount = nsectors * SECTORSIZE;
is_sub_dir = 1;
 
if (sector == 0) {
/* FAT problem ? */
return 0;
}
}
 
/* Keep going until the whole directory has been read.
* Note: it is necessary to check filecount in the inner
* loops as well because we can hit end-of-file anywhere
* within a cluster. */
while (filecount) {
/* Keep going until the whole root or cluster has been read */
while (nsectors && filecount) {
/* Get the current sector */
if (read_sector(sector, buf) != SECTORSIZE)
return 0;
bufcount = 0;
++sector;
--nsectors;
 
while ((bufcount < SECTORSIZE) && filecount) {
/* Process a single directory entry */
filecount -= DIRENT_SIZE;
 
if (filecount < 0) {
/* This is some wierd error, both filesize and
* SECTORSIZE should be an integer multiple of DIRENT_SIZE.
*/
return 0;
}
 
de = (DirectoryEntry *) (buf + bufcount);
 
switch (de->Name[0]) {
case 0x00: /* This, and all subsequent entries are empty */
if (!name) { /* we are looking for a free entry */
*de_sector = sector - 1;
*de_offset = bufcount;
return 1;
}
return 0;
break;
 
case 0xe5: /* This entry is empty, but there may be more after it */
if (!name) { /* we are looking for a free entry */
*de_sector = sector - 1;
*de_offset = bufcount;
return 1;
}
break;
 
case 0x05: /* escaped Kanji character */
de->Name[0] = 0xe5;
/* fall through to default case ... */
 
default:
if (!name) /* we are looking for a free entry */
break; /* and this is not it.. */
 
if ((de->Attributes & ATTR_LONG_NAME_MASK) ==
ATTR_LONG_NAME) {
/* This is a long file name */
break;
}
 
/* Must be a file, directory or volume ID */
switch (de->Attributes & (ATTR_DIRECTORY | ATTR_VOLUME_ID)) {
case 0x00: /* This entry is a file */
if (ext) { /* Here if we are looking for a file */
if (!dir_name_compare(name, (char *) (de->Name), 8)
&& !dir_name_compare(ext, (char *) (de->Extension), 3)) {
if (wd->pi->FatType == FAT32) {
/* first cluster is a 32 bit entry for FAT32 */
*firstcluster = make_UINT32
(de->FirstClusterOfFile_hi[1],
de->FirstClusterOfFile_hi[0],
de->FirstClusterOfFile[1],
de->FirstClusterOfFile[0]);
} else {
*firstcluster = (UINT32)make_UINT16
(de->FirstClusterOfFile[1],
de->FirstClusterOfFile[0]);
}
*filesize = make_UINT32(de->FileSize[3],
de->FileSize[2],
de->FileSize[1],
de->FileSize[0]);
*de_sector = sector - 1;
*de_offset = bufcount;
return 1;
}
}
break;
 
case ATTR_DIRECTORY: /* This entry is a directory */
if (ext == 0) {
if (!dir_name_compare(name, (char *) (de->Name), 8)) {
if (wd->pi->FatType == FAT32) {
/* first cluster is a 32 bit entry for FAT32 */
*firstcluster = make_UINT32
(de->FirstClusterOfFile_hi[1],
de->FirstClusterOfFile_hi[0],
de->FirstClusterOfFile[1],
de->FirstClusterOfFile[0]);
} else {
*firstcluster = (UINT32)make_UINT16
(de->FirstClusterOfFile[1],
de->FirstClusterOfFile[0]);
}
*filesize = make_UINT32(de->FileSize[3],
de->FileSize[2],
de->FileSize[1],
de->FileSize[0]);
*de_sector = sector - 1;
*de_offset = bufcount;
return 1;
}
}
break;
 
case ATTR_VOLUME_ID: /* Volume ID */
break;
 
default: /* Bad directory */
return 0;
}
}
bufcount += DIRENT_SIZE;
}
}
 
/* Finished with root or current cluster. If this is not the
* root, then move to the next cluster. */
 
/* Root directory (in FAT12/16) has one continuous list of sectors */
if (wd->pi->FatType != FAT32 && wd->parent == 0)
return 0;
 
/* If this is a child directory go to next cluster */
cluster = next_cluster(cluster, wd->pi);
if (cluster == BAD_CLUSTER) {
/* FAT problem ? */
return 0;
}
 
if (is_sub_dir) {
/* reset filesize to read another clusters worth of directory entries */
filecount = (wd->pi->SectorsPerCluster * SECTORSIZE);
}
 
if ((sector = starting_sector(cluster, wd->pi)) == 0) {
/* FAT problem ? */
return 0;
}
nsectors = wd->pi->SectorsPerCluster;
 
 
} /* while(filesize) */
 
/* Never found it */
return 0;
}
 
void update_de_filesize(DirectoryEntry *de, UINT32 filesize)
{
write_UINT32(de->FileSize, filesize);
}
 
void update_de_firstcluster(DirectoryEntry *de, UINT32 firstcluster, PartitionInfo *pi)
{
UINT16 f_lo, f_hi;
f_lo = (UINT16)(firstcluster & 0xFFFF);
f_hi = (UINT16)(firstcluster >> 16);
write_UINT16(de->FirstClusterOfFile, f_lo);
if (pi->FatType == FAT32)
write_UINT16(de->FirstClusterOfFile_hi, f_hi);
}
/xilfatfs_v1_00_a/src/src/xilfatfs_close.c
0,0 → 1,34
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include "sysace_stdio.h"
#include "filestatus.h"
#include "bufcache.h"
 
int sysace_fclose(SYSACE_FILE *stream)
{
if (stream == 0)
return 0;
 
/* sync the buffer cache to the disk */
sync_bufcache();
 
return delete_file_status((FileStatus *) stream);
}
/xilfatfs_v1_00_a/src/src/xilfatfs_mkdir.c
0,0 → 1,38
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include "fat.h"
#include "filespec.h"
#include "directory.h"
#include "util.h"
 
DirectoryEntry dotdot_entry[2];
 
int sysace_mkdir(const char *path)
{
WorkingDirectory *wd = build_working_directory_stack(path, 1, 1);
 
if (wd) { /* create dir succeeded */
delete_working_directory_stack(wd);
sync_bufcache();
return 0;
} else
return -1;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_part.c
0,0 → 1,217
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include <ctype.h>
#include <string.h>
#include "fat.h"
#include "directory.h"
#include "util.h"
 
/* The partition info buffers can be statically allocated.
* Never free a pi !
*/
static PartitionInfo pibuf[MAXPARTITION];
 
/* Make a new PartitionInfo structure and populate it */
PartitionInfo *get_partition_info(int partition)
{
BYTE buf[SECTORSIZE];
MasterBootRecord *mbr;
PartitionEntry *pe;
PartitionBootRecord *pbr;
UINT16 total16;
UINT32 total32;
UINT16 reserved;
UINT32 partitionSize, rootSize, dataClusters, dataOffset, fatSize;
PartitionInfo *pi;
 
static int sysace_initialized = 0;
 
if (partition < 0 || partition >= MAXPARTITION)
return 0;
 
pi = pibuf + partition;
pi->PartitionNum = partition;
 
if (!sysace_initialized) { /* initialize sysace the first time around */
if (init_ace() < 0)
return 0;
sysace_initialized = 1;
}
/* Master Boot Record is always sector 0 */
if (read_sector(0, buf) != SECTORSIZE)
return 0;
mbr = (MasterBootRecord *) buf;
 
/* Check Signature */
if (mbr->Signature[0] != 0x55 || mbr->Signature[1] != 0xaa)
return 0;
 
/* Point to the Relevant Partition Entry */
pe = &(mbr->PartitionEntry[partition]);
 
pi->StartSector =
make_UINT32(pe->PartitionSector[3], pe->PartitionSector[2],
pe->PartitionSector[1], pe->PartitionSector[0]);
 
partitionSize =
make_UINT32(pe->TotalSectors[3], pe->TotalSectors[2],
pe->TotalSectors[1], pe->TotalSectors[0]);
/* Read the Partition Boot Record */
if (read_sector(pi->StartSector, buf) != SECTORSIZE)
return 0;
 
pbr = (PartitionBootRecord *) buf;
 
/* Determine the total number of sectors in this partition
* It may be specified in 16 or 32 bits */
total16 =
make_UINT16(pbr->BPB.TotalSectors16[1],
pbr->BPB.TotalSectors16[0]);
total32 =
make_UINT32(pbr->BPB.TotalSectors32[3],
pbr->BPB.TotalSectors32[2],
pbr->BPB.TotalSectors32[1],
pbr->BPB.TotalSectors32[0]);
if (total16) {
if (total32 != 0 && total32 != total16)
return 0;
pi->TotalSectors = (UINT32) total16;
} else {
if (total32 == 0)
return 0;
pi->TotalSectors = total32;
}
 
if (pi->TotalSectors > partitionSize)
return 0;
 
pi->BytesPerSector = make_UINT16(pbr->BPB.BytesPerSector[1],
pbr->BPB.BytesPerSector[0]);
 
/* Check against compile-time constants
* currently allow only 512 bytes per sec */
if (pi->BytesPerSector != SECTORSIZE)
return 0;
 
pi->SectorsPerCluster = pbr->BPB.SectorsPerCluster;
if (pi->SectorsPerCluster == 0) {
/* Protect division later on! */
return 0;
}
/* sanity check for SectorsPerCluster:
* should be a power of 2
* should be <= 128
* should be such that bytes per cluster <= 32k (MAX_BYTES_PER_CLUSTER)
*/
if (pi->SectorsPerCluster & (pi->SectorsPerCluster - 1))
return 0;
if (pi->SectorsPerCluster > 128)
return 0;
if (pi->SectorsPerCluster * pi->BytesPerSector > MAX_BYTES_PER_CLUSTER)
return 0;
 
reserved = make_UINT16(pbr->BPB.ReservedSector[1],
pbr->BPB.ReservedSector[0]);
 
pi->NumberOfFats = pbr->BPB.NumberOfFats;
 
pi->RootDirCount = make_UINT16(pbr->BPB.RootDirCount[1],
pbr->BPB.RootDirCount[0]);
 
pi->SectorsPerFat = (UINT32) make_UINT16(pbr->BPB.SectorsPerFat[1],
pbr->BPB.SectorsPerFat[0]);
 
if (pi->SectorsPerFat == 0) {
/* check if the fat32 entry is present
* if not then this is invalid FAT
*/
pi->SectorsPerFat = make_UINT32(pbr->BPB.SectorsPerFat_32[3],
pbr->BPB.SectorsPerFat_32[2],
pbr->BPB.SectorsPerFat_32[1],
pbr->BPB.SectorsPerFat_32[0]);
if (pi->SectorsPerFat == 0)
return 0;
}
 
/* Determine the FAT type based on the # of data clusters */
rootSize =
((pi->RootDirCount << LOG2_DIRENT_SIZE) + SECTORSIZE -
1) / SECTORSIZE;
fatSize = pi->SectorsPerFat * pi->NumberOfFats;
dataOffset = reserved + fatSize + rootSize;
dataClusters =
(pi->TotalSectors - dataOffset) / pi->SectorsPerCluster;
 
if (dataClusters < MAX_FAT12_CLUSTERS) {
debug_print("FAT12 PARTITION\n\r");
pi->FatType = FAT12;
#ifdef CONFIG_FAT12
pi->op = &fat12_ops;
#else
pi->op = NULL;
#endif
} else if (dataClusters < MAX_FAT16_CLUSTERS) {
debug_print("FAT16 PARTITION\n\r");
pi->FatType = FAT16;
pi->op = &fat16_ops;
} else {
pi->FatType = FAT32;
debug_print("FaT32 PARTITION\n\r");
pi->op = &fat32_ops;
}
 
/* more consistency checks */
switch (pi->FatType) {
case FAT12:
case FAT16:
if (reserved != 1)
return 0;
 
/* pi->RootDirCount * 32 should be an even multiple
* of BytesPerSector */
if ((pi->RootDirCount * 32) % pi->BytesPerSector)
return 0;
if (((pi->RootDirCount * 32) / pi->BytesPerSector) % 2)
return 0;
break;
case FAT32:
if (pi->RootDirCount != 0)
return 0;
break;
default:
return 0;
}
 
pi->FatSector = pi->StartSector + reserved;
pi->RootDirSector = pi->FatSector + fatSize;
pi->DataSector = pi->RootDirSector + rootSize;
 
if (pi->FatType == FAT32) {
pi->RootCluster = make_UINT32(pbr->BPB.RootCluster[3],
pbr->BPB.RootCluster[2],
pbr->BPB.RootCluster[1],
pbr->BPB.RootCluster[0]);
}
 
return pi;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_wd.c
0,0 → 1,377
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
 
#include <ctype.h>
#include <string.h>
#include "fat.h"
#include "filespec.h"
#include "alloc.h"
#include "directory.h"
#include "util.h"
 
/* Defaults to all zeros */
WorkingDirectory *cwd[MAXPARTITION] = { 0 };
int DefaultPartition = 0;
 
void delete_working_directory_stack(WorkingDirectory * wd)
{
WorkingDirectory *parent;
 
while (wd) {
parent = wd->parent;
free_wd(wd);
wd = parent;
}
 
return;
}
 
#define WD_BUFSIZE 10
#define WD_EXT_BUFSIZE 5
 
WorkingDirectory *_build_working_directory_stack(const char *path,
int is_dir, int create)
{
char buf[WD_BUFSIZE];
char ext_buf[WD_EXT_BUFSIZE];
field_type type = PATH_START;
WorkingDirectory *wd = 0;
WorkingDirectory *child;
int i = 0;
int partition = DefaultPartition;
#if defined(CONFIG_WRITE) && defined(CONFIG_DIR_SUPPORT)
char leaf_buf[WD_BUFSIZE];
#endif
 
while (type != PATH_DONE) {
i += parse_path(path + i, buf, WD_BUFSIZE, is_dir, &type);
 
switch (type) {
case DEVICE_NAME:
/* Cannot support server spec */
if (strlen(buf) > 1) {
delete_working_directory_stack(wd);
return 0;
}
/* interpret drive letter */
if ((partition = tolower(buf[0]) - 'a') < 0
|| partition >= MAXPARTITION) {
delete_working_directory_stack(wd);
return 0;
}
break;
 
case DIR_NAME:
if (wd == 0 && !strcmp(buf, DIRSEPSTRING)) {
/* The specification is absolute - this is the root directory */
if ((wd = make_root_directory(partition)) == 0)
return 0;
break;
}
 
if (wd == 0) {
/* This is a relative pathname - see if there is a CWD for this partition.
* If not, default to the root directory for the partition. Then duplicate
* the default stack so that the child can be appended. */
if (cwd[partition] == 0)
cwd[partition] =
make_root_directory(partition);
if (cwd[partition] == 0)
return 0;
wd = copy_directory_stack(cwd[partition]);
if (wd == 0)
return 0;
}
 
/* Add the child directory to the path */
if ((child = make_child_directory(buf, NULL, wd)) == 0) {
#if defined(CONFIG_WRITE) && defined(CONFIG_DIR_SUPPORT)
if ((!is_dir) || (is_dir && !create))
#endif
{
delete_working_directory_stack(wd);
return 0;
}
}
 
#if defined(CONFIG_WRITE) && defined(CONFIG_DIR_SUPPORT)
/* request to create a directory */
if (is_dir && create && (child == 0)) {
/* create only if we are at the leaf */
parse_path(path + i, leaf_buf, WD_BUFSIZE, is_dir, &type);
if (type != PATH_DONE) {
/* we are not at the leaf, but couldn't go further
* so invalid path */
return 0;
} else /* we are at the leaf, so we need to create the directory */
return create_file_entry(buf, "", wd, ATTR_DIRECTORY);
}
#endif
 
wd = child;
break;
 
case FILE_NAME:
/* Buf contains a filename - now see if there is an extension there */
parse_path(path + i, ext_buf, WD_EXT_BUFSIZE,
is_dir, &type);
if (type == PATH_DONE) { /* The extension is empty */
ext_buf[0] = 0;
} else if (type != FILE_EXT) { /* There was an error */
delete_working_directory_stack(wd);
return 0;
}
 
if (wd == 0) { /* There is no directory, so copy over the cwd */
if (cwd[partition] == 0)
cwd[partition] = make_root_directory(partition);
if (cwd[partition] == 0)
return 0;
wd = copy_directory_stack(cwd[partition]);
if (wd == 0)
return 0;
}
 
/* See if this file exists */
if ((child = make_child_directory(buf, ext_buf, wd)) == 0) {
#ifdef CONFIG_WRITE
if (!create) /* no such file, and no request to create one */
#endif
{
delete_working_directory_stack(wd);
return 0;
}
}
 
/* if this is a request to create an entry, then
* create an entry if none exists
*/
#ifdef CONFIG_WRITE
if (create && child == 0) {
/* search for a free directory entry
* make a new entry with size 0
*/
child = create_file_entry(buf, ext_buf, wd, 0);
}
#endif
return child;
 
case PATH_DONE:
return wd;
 
default:
/* Error condition */
delete_working_directory_stack(wd);
return 0;
}
}
 
return wd;
}
 
WorkingDirectory *build_working_directory_stack(const char *path,
int is_dir, int write)
{
WorkingDirectory *wd = NULL;
 
if (write == 0) /* create for read mode */
return _build_working_directory_stack(path, is_dir, 0);
 
#ifdef CONFIG_WRITE
/* when created in write mode, the file has to be
* truncated if already present
* created if absent
*/
wd = _build_working_directory_stack(path, is_dir, 1);
if (!wd)
return 0;
if (is_dir)
return wd;
 
/* if this is a pre-existing file (size != 0), then truncate it */
if (wd->v.child.FileSize != 0) {
debug_xil_printf("File already exists..size = %d\n\r",
(unsigned int)wd->v.child.FileSize);
if (truncate_file(wd->v.child.FirstCluster, wd->pi) < 0)
return 0;
 
/* change filesize to 0.
* the directory entry is not changed yet
*/
wd->v.child.FileSize = 0;
debug_xil_printf("%s @ %d, file truncated\n\r", __FUNCTION__, __LINE__);
} else {
debug_print("File doesn't exist (Created now) or size 0.\n\r");
}
#endif
 
return wd;
}
 
void set_child_details(WorkingDirectory *wd, UINT32 firstcluster,
UINT32 filesize, UINT32 de_sector, UINT32 de_offset,
WorkingDirectory *parent)
{
wd->v.child.FirstCluster = firstcluster;
wd->v.child.FileSize = filesize;
wd->v.child.DirLocation.sector = de_sector;
wd->v.child.DirLocation.offset = de_offset;
wd->parent = parent;
wd->pi = parent->pi;
}
 
WorkingDirectory *make_child_directory(const char *name, const char *ext,
WorkingDirectory * parent)
{
WorkingDirectory *wd;
UINT32 firstcluster;
UINT32 filesize;
UINT32 de_sector;
UINT32 de_offset;
 
/* find if child is present in given parent directory */
if (!find_in_directory(parent, name, ext, &firstcluster,
&filesize, &de_sector, &de_offset))
return 0;
 
/* create child wd */
if ((wd = malloc_wd(name)) == 0)
return 0;
set_child_details(wd, firstcluster, filesize, de_sector,
de_offset, parent);
return wd;
}
 
void set_root_details(WorkingDirectory *wd, PartitionInfo *pi)
{
switch(pi->FatType) {
case FAT12:
case FAT16:
wd->v.root.StartSector = pi->RootDirSector;
wd->v.root.DirCount = pi->RootDirCount;
return;
case FAT32:
wd->v.child.FirstCluster = pi->RootCluster;
return;
}
}
 
WorkingDirectory *make_root_directory(int partition)
{
WorkingDirectory *wd;
PartitionInfo *pi;
 
if ((pi = get_partition_info(partition)) == 0)
return 0;
 
if ((wd = malloc_wd(DIRSEPSTRING)) == 0)
return 0;
wd->parent = 0;
wd->pi = pi;
 
/* copy over the information about root directory */
set_root_details(wd, pi);
 
return wd;
}
 
#ifdef CONFIG_WRITE
/* names are truncated to 8.3 format when writing */
void initialize_de(DirectoryEntry *de,
char *name,
char *ext,
UINT32 firstcluster,
UINT32 filesize,
PartitionInfo *pi,
BYTE attrib)
{
int i;
 
for (i = 0; i < 8; i++) {
if (*name) {
de->Name[i] = toupper(*name);
name++;
} else
de->Name[i] = ' ';
}
 
for (i = 0; i < 3; i++) {
if (*ext) {
de->Extension[i] = toupper(*ext);
ext++;
} else
de->Extension[i] = ' ';
}
 
de->Attributes = attrib;
memset(de->Reserved, 0, 8);
memset(de->Date, 0, 2);
 
update_de_firstcluster(de, firstcluster, pi);
 
update_de_filesize(de, filesize);
 
return;
}
#endif
 
WorkingDirectory *copy_directory_stack(WorkingDirectory * stack)
{
WorkingDirectory *src, *dest, *first, *previous;
 
first = 0;
previous = 0;
src = stack;
 
/* Copy child directories */
while (src) {
dest = malloc_wd(src->name);
if (dest == 0) {
delete_working_directory_stack(first);
return 0;
}
 
if (first == 0)
first = dest;
 
if (previous)
previous->parent = dest;
 
dest->parent = 0;
dest->pi = src->pi;
 
if (src->parent || src->pi->FatType == FAT32) {
/* Child directory */
dest->v.child.FirstCluster = src->v.child.FirstCluster;
dest->v.child.FileSize = src->v.child.FileSize;
} else {
/* Root directory */
dest->v.root.StartSector = src->v.root.StartSector;
dest->v.root.DirCount = src->v.root.DirCount;
}
 
src = src->parent;
previous = dest;
}
 
return first;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_direct.c
0,0 → 1,21
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
/* All functions have been moved to other files */
/xilfatfs_v1_00_a/src/src/xilfatfs_fat.c
0,0 → 1,229
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include "fat.h"
#include "directory.h"
#include "util.h"
 
/* given a cluster, look into the FAT to find the next
* cluster in the link list */
UINT32 next_cluster(UINT32 cluster, PartitionInfo * pi)
{
if (cluster < 2)
return BAD_CLUSTER;
 
return pi->op->next_cluster(cluster, pi);
}
 
/* return the first sector corresponding to a cluster */
UINT32 starting_sector(UINT32 cluster, PartitionInfo * pi)
{
if (cluster == 0)
return 0;
return (((cluster - 2) * (UINT32) pi->SectorsPerCluster) +
pi->DataSector);
}
 
/* next_cluster_generic: given a cluster number, return the
* cluster that is next in this cluster chain by looking
* into the FAT data structure for this partition
*
* generic for FAT16 & FAT32
*/
UINT32 next_cluster_generic(UINT32 cluster, PartitionInfo * pi)
{
BYTE buf[SECTORSIZE];
UINT32 TempNextCluster;
UINT32 Fat0SectorNum;
UINT32 Fat1SectorNum;
int NextClusterPosition;
 
if (!pi->op->is_valid_cluster(cluster, pi))
return BAD_CLUSTER;
 
Fat0SectorNum = pi->op->get_fat_sector_for_cluster(cluster, pi);
NextClusterPosition = pi->op->get_fat_offset_for_cluster(cluster, pi);
 
if (read_sector(Fat0SectorNum, buf) != SECTORSIZE)
return BAD_CLUSTER;
 
TempNextCluster = pi->op->get_next_cluster(buf + NextClusterPosition, pi);
 
/* check for FAT misMatch !!! */
if (pi->NumberOfFats > 1) {
Fat1SectorNum = Fat0SectorNum + pi->SectorsPerFat;
 
if (read_sector(Fat1SectorNum, buf) != SECTORSIZE)
return BAD_CLUSTER;
 
if (TempNextCluster != pi->op->get_next_cluster(buf + NextClusterPosition, pi))
return BAD_CLUSTER; /* FAT tables don't match bail */
}
 
return (TempNextCluster);
}
 
/* Follow the cluster chain in FAT16/32 and free all allotted
* clusters.
*/
int free_cluster_chain_generic(UINT32 cluster, PartitionInfo *pi)
{
UINT32 sector_in_buf = 0;
UINT32 sector, offset;
int modified = 0; /* denotes if the sector_in_buf has been modified */
char buf[SECTORSIZE];
 
while (!pi->op->is_eoc(cluster, pi)) {
sector = pi->op->get_fat_sector_for_cluster(cluster, pi);
if (sector != sector_in_buf) { /* have to read in a new sector from FAT */
/* write to disk if the old sector was modified */
if (modified) {
if (write_sector(sector_in_buf, buf) != SECTORSIZE)
return -1;
 
/* update FAT 2 */
if (pi->NumberOfFats > 1)
if (write_sector(sector_in_buf + pi->SectorsPerFat, buf)
!= SECTORSIZE)
return -1;
modified = 0;
}
 
/* read in the new sector */
if (read_sector(sector, buf) != SECTORSIZE)
return -1;
 
sector_in_buf = sector;
}
 
offset = pi->op->get_fat_offset_for_cluster(cluster, pi);
 
/* obtain the current value & reset it to zero */
cluster = pi->op->get_next_cluster(buf + offset, pi);
pi->op->set_next_cluster(buf + offset, 0, pi);
modified = 1;
}
 
if (modified) {
if (write_sector(sector_in_buf, buf) != SECTORSIZE)
return -1;
/* update FAT 2 */
if (pi->NumberOfFats > 1)
if (write_sector(sector_in_buf + pi->SectorsPerFat, buf)
!= SECTORSIZE)
return -1;
modified = 0;
}
return 0;
}
 
/* truncate a file to size 0: done by following the cluster chain
* and freeing all allotted clsuters for this file
*/
int truncate_file(UINT32 cluster, PartitionInfo *pi)
{
if (cluster < 2)
return -1;
 
return pi->op->free_cluster_chain(cluster, pi);
}
 
/* find a free cluster, set the next entry of that cluster to EOC
* and return that cluster.
* A request to allocate_one_cluster automatically sets the entry
* in FAT for that cluster to point to EOC. This is because we want
* to reduce the # of read and write calls to the disk
*/
UINT32 allocate_one_cluster_generic(PartitionInfo *pi)
{
BYTE buf[SECTORSIZE];
int FatEntrySize;
UINT32 cluster = 0, sector, i;
UINT32 eoc;
 
if (pi->FatType == FAT16) {
FatEntrySize = 2;
eoc = FAT16_EOC;
} else if (pi->FatType == FAT32) {
FatEntrySize = 4;
eoc = FAT32_EOC;
} else { /* works only for FAT16/32 */
return 0;
}
 
for (sector = pi->FatSector;
sector < pi->FatSector + pi->SectorsPerFat;
sector++) {
/* read in the sector */
if (read_sector(sector, buf) != SECTORSIZE)
return 0;
 
/* find if an entry is free */
for (i = 0; i < SECTORSIZE; i+= FatEntrySize) {
UINT32 cluster_val = pi->op->get_next_cluster(buf + i, pi);
if (cluster_val == 0) { /* this cluster is free */
BYTE buf2[SECTORSIZE];
UINT32 cluster_val_2;
 
if (read_sector(sector + pi->SectorsPerFat, buf2) != SECTORSIZE)
return 0;
cluster_val_2 = pi->op->get_next_cluster(buf2 + i, pi);
 
if (cluster_val_2 != cluster_val)
return 0; /* FAT mismatch */
 
/* write EOC as the entry for this cluster
* in both the FATs */
pi->op->set_next_cluster(buf2 + i, eoc, pi);
if (write_sector(sector + pi->SectorsPerFat, buf2) != SECTORSIZE)
return 0;
 
pi->op->set_next_cluster(buf + i, eoc, pi);
if (write_sector(sector, buf) != SECTORSIZE)
return 0;
 
return cluster;
}
cluster++;
}
}
 
return 0;
}
 
int link_cluster_generic(UINT32 from_cluster, UINT32 to_cluster, PartitionInfo *pi)
{
UINT32 sector = pi->op->get_fat_sector_for_cluster(from_cluster, pi);
UINT32 offset = pi->op->get_fat_offset_for_cluster(from_cluster, pi);
BYTE buf[SECTORSIZE];
if (read_sector(sector, buf) != SECTORSIZE)
return -1;
 
/* set the next cluster for from_cluster to to_cluster */
pi->op->set_next_cluster(buf + offset, to_cluster, pi);
 
if (write_sector(sector, buf) != SECTORSIZE)
return -1;
 
return 0;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_read.c
0,0 → 1,128
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include <string.h>
 
#include "filestatus.h"
#include "sysace_stdio.h"
#include "fat.h"
 
#if defined( DUMMY_DISK )
static char *dummy_data = "Are we there yet?\n";
#endif
 
int read_from_file(FileStatus * fs, char *buf, int count)
{
int readcount, n;
int remaining;
BYTE sectorbuf[SECTORSIZE];
UINT32 sector;
UINT32 filesize;
UINT32 nsectors;
UINT32 sector_offset;
int byte_offset;
 
/* Safety check */
if (fs == 0 || !fs->read || count < 0)
return 0;
 
filesize = fs->wd->v.child.FileSize;
 
if (fs->PositionInFile >= filesize)
return 0;
 
readcount = 0;
 
/* Compute number of bytes left to read - may be limited
* by size of users buf or by file size */
remaining = filesize - fs->PositionInFile;
if (count < remaining)
remaining = count;
 
while (fs->PositionInFile < filesize) {
/* Which sector of this cluster did we leave off at last time ? */
sector_offset = fs->PositionInCluster / SECTORSIZE;
 
/* Which byte of that sector did we leave off at last time ? */
byte_offset = fs->PositionInCluster % SECTORSIZE;
 
/* Sector address to start reading this time */
sector = starting_sector(fs->CurrentCluster, fs->wd->pi);
if (sector == 0) {
/* FAT problem ? */
return 0;
}
sector += sector_offset;
 
/* How many sectors left to read in this cluster */
nsectors = fs->wd->pi->SectorsPerCluster - sector_offset;
 
while (nsectors) {
if (read_sector(sector, sectorbuf) != SECTORSIZE)
return -1;
if (remaining <= (SECTORSIZE - byte_offset)) {
/* End of file or end of buffer occurs in this sector
* Read what's left and quit */
memcpy(buf + readcount,
(char *) (sectorbuf + byte_offset),
remaining);
fs->PositionInFile += remaining;
fs->PositionInCluster += remaining;
return (remaining + readcount);
}
/* End of file is beyond this sector */
n = SECTORSIZE - byte_offset;
memcpy(buf + readcount,
(char *) (sectorbuf + byte_offset), n);
fs->PositionInFile += n;
fs->PositionInCluster += n;
readcount += n;
remaining -= n;
 
/* Point to start of next sector in cluster */
byte_offset = 0;
sector += 1;
nsectors -= 1;
} /* end of while */
 
/* Done with that cluster, advance to the next one */
fs->CurrentCluster = next_cluster(fs->CurrentCluster, fs->wd->pi);
if (fs->CurrentCluster == BAD_CLUSTER) {
/* Bad cluster address - this means that there is a FAT problem,
* because we should have dtected that this was the last cluster
* based on filesize. The file system is hosed. */
return 0;
}
/* We are at the start of this new cluster */
fs->PositionInCluster = 0;
}
 
return readcount;
}
 
int sysace_fread(void *buffer, int size, int count, SYSACE_FILE *stream)
{
FileStatus *fs = find_file_status(stream);
 
if (fs == 0)
return -1;
 
return read_from_file(fs, (char *) buffer, size * count);
}
/xilfatfs_v1_00_a/src/src/xilfatfs_fat12.c
0,0 → 1,314
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
#include "fat.h"
#include "directory.h"
#include "util.h"
 
/* given the cluster #, find the sector in the partition where
* the FAT entry for that cluster is present
*/
UINT32 get_fat12_sector_for_cluster(UINT32 cluster, PartitionInfo *pi)
{
/* Each FAT entry takes 1.5 bytes in FAT 12 */
return ((cluster + cluster/2) / SECTORSIZE) + pi->FatSector;
}
 
/* given the cluster #, find the offset in the sector in the partition where
* the FAT entry for that cluster is present
*/
UINT32 get_fat12_offset_for_cluster(UINT32 cluster, PartitionInfo *pi)
{
return ((cluster + cluster/2) % SECTORSIZE);
}
 
/* given the address (fat_entry) where the FAT entry for a cluster
* is present, return the next cluster for that entry
*/
UINT32 get_next_cluster_fat12(BYTE *fat_entry, PartitionInfo *pi, UINT32 cluster)
{
UINT32 tmp_next_cluster;
 
/* We need 12 bits from the 2 bytes - so first read in the 2 bytes */
tmp_next_cluster = (UINT32) make_UINT16(*(fat_entry + 1), *(fat_entry));
if (cluster & 0x1) /* if cluster is odd, we take the higher 12 bits */
tmp_next_cluster >>= 4;
else /* else we take the lower 12 bits */
tmp_next_cluster &= 0xFFF;
 
return tmp_next_cluster;
}
 
/* given the address (fat_entry) where the FAT entry for a cluster
* is present, set the next cluster entry to next_cluster
*/
void set_next_cluster_fat12(BYTE *fat_entry,
UINT32 next_cluster,
PartitionInfo *pi,
UINT32 cluster)
{
UINT16 old_entry = make_UINT16(*(fat_entry+1), *(fat_entry));
UINT32 new_entry;
 
if (cluster & 0x1) { /* if cluster is odd, we need to update the higher 12 bits */
new_entry = (next_cluster << 4) | (old_entry & 0xF);
write_UINT16(fat_entry, new_entry);
} else { /* else write the lower order 12 bits */
new_entry = (next_cluster & 0xFFF) | (old_entry & 0xF000);
write_UINT16(fat_entry, new_entry);
}
}
 
/* find if this is the end of cluster mark */
int is_eoc_fat12(UINT32 cluster, PartitionInfo *pi)
{
return (cluster >= FAT12_EOC);
}
 
int is_valid_cluster_fat12(UINT32 cluster, PartitionInfo *pi)
{
return (cluster < MAX_FAT12_CLUSTERS);
}
 
/* next_cluster_fat12: given a cluster number, return the
* cluster that is next in this cluster chain by looking
* into the FAT data structure for this partition
*
* For FAT12, each entry in the FAT is 1.5 bytes = 12 bits.
* This results in two complications:
* 1. A single FAT entry may span two sectors.
* 2. After reading in 16 bits, 12 bits must be extracted
* depending on whether the cluster # is even or odd.
*/
UINT32 next_cluster_fat12(UINT32 cluster, PartitionInfo * pi)
{
BYTE buf[SECTORSIZE*2];
UINT32 TempNextCluster;
UINT32 Fat0SectorNum;
UINT32 Fat1SectorNum;
int NextClusterPosition;
 
if (cluster > MAX_FAT12_CLUSTERS)
return BAD_CLUSTER;
 
Fat0SectorNum = pi->op->get_fat_sector_for_cluster(cluster, pi);
NextClusterPosition = pi->op->get_fat_offset_for_cluster(cluster, pi);
 
if (read_sector(Fat0SectorNum, buf) != SECTORSIZE)
return BAD_CLUSTER;
 
/* Additionally (as compared to FAT 16/32 we have to see if the entry
* spans a sector boundary, and if so read in the next sector.
*/
if (NextClusterPosition == SECTORSIZE - 1)
if (read_sector(Fat0SectorNum + 1, buf + SECTORSIZE) != SECTORSIZE)
return BAD_CLUSTER;
 
TempNextCluster = get_next_cluster_fat12(buf + NextClusterPosition, pi, cluster);
 
/* check for FAT misMatch !!! */
if (pi->NumberOfFats > 1) {
UINT32 FAT1_TempNextCluster = 0;
 
Fat1SectorNum = Fat0SectorNum + pi->SectorsPerFat;
 
if (read_sector(Fat1SectorNum, buf) != SECTORSIZE)
return 0;
if (NextClusterPosition == SECTORSIZE - 1)
if (read_sector(Fat0SectorNum + 1, buf + SECTORSIZE) != SECTORSIZE)
return BAD_CLUSTER;
 
FAT1_TempNextCluster = get_next_cluster_fat12(buf + NextClusterPosition, pi, cluster);
 
if (TempNextCluster != FAT1_TempNextCluster)
return BAD_CLUSTER; /* FAT tables don't match bail */
}
 
return (TempNextCluster);
}
 
/* Follow the cluster chain in FAT12 and free all allotted clusters. */
int free_cluster_chain_fat12(UINT32 cluster, PartitionInfo *pi)
{
UINT32 sector_in_buf = 0;
UINT32 sector, offset, old_cluster;
int modified = 0; /* denotes if the sector_in_buf has been modified */
int used_second_sector = 0; /* denotes if a 2nd sector was read & modified */
char buf[SECTORSIZE*2];
 
while (!pi->op->is_eoc(cluster, pi)) {
sector = pi->op->get_fat_sector_for_cluster(cluster, pi);
debug_xil_printf("%d: cluster: %d is at sector: %d\n\r", __LINE__,
(int)cluster, (int)sector);
if (sector != sector_in_buf) { /* have to read in a new sector from FAT */
/* write to disk if the old sector was modified */
if (modified) {
if (write_sector(sector_in_buf, buf) != SECTORSIZE)
return -1;
 
/* update FAT 2 */
if (pi->NumberOfFats > 1)
if (write_sector(sector_in_buf + pi->SectorsPerFat, buf)
!= SECTORSIZE)
return -1;
 
/* if the writes had spanned 2 sectors, then write out
* the 2nd sector too
*/
if (used_second_sector) {
if (write_sector(sector_in_buf,
buf + SECTORSIZE) != SECTORSIZE)
return -1;
 
/* update FAT 2 */
if (pi->NumberOfFats > 1)
if (write_sector(sector_in_buf + pi->SectorsPerFat,
buf + SECTORSIZE) != SECTORSIZE)
return -1;
 
used_second_sector = 0;
}
debug_xil_printf("written modified sec %d\n", (unsigned int)sector_in_buf);
modified = 0;
}
 
debug_xil_printf("%s @ %d, reading in new sector\n\r",
__FUNCTION__, __LINE__);
/* read in the new sector */
if (read_sector(sector, buf) != SECTORSIZE)
return -1;
 
sector_in_buf = sector;
}
 
offset = pi->op->get_fat_offset_for_cluster(cluster, pi);
if (offset == SECTORSIZE - 1) { /* FAT entry spans sector boundary */
if (read_sector(sector, buf + SECTORSIZE) != SECTORSIZE)
return 0;
used_second_sector = 1;
}
 
/* obtain the current value & reset it to zero */
old_cluster = cluster;
cluster = get_next_cluster_fat12(buf + offset, pi, cluster);
set_next_cluster_fat12(buf + offset, 0, pi, old_cluster);
modified = 1;
}
 
if (modified) {
if (write_sector(sector_in_buf, buf) != SECTORSIZE)
return -1;
/* update FAT 2 */
if (pi->NumberOfFats > 1)
if (write_sector(sector_in_buf + pi->SectorsPerFat, buf)
!= SECTORSIZE)
return -1;
 
/* if the writes had spanned 2 sectors, then write out
* the 2nd sector too
*/
if (used_second_sector) {
if (write_sector(sector_in_buf,
buf + SECTORSIZE) != SECTORSIZE)
return -1;
 
/* update FAT 2 */
if (pi->NumberOfFats > 1)
if (write_sector(sector_in_buf + pi->SectorsPerFat,
buf + SECTORSIZE) != SECTORSIZE)
return -1;
 
used_second_sector = 0;
}
 
debug_xil_printf("written modified sec %d\n", (unsigned int)sector_in_buf);
modified = 0;
}
return 0;
}
 
int link_cluster_fat12(UINT32 from_cluster, UINT32 to_cluster, PartitionInfo *pi)
{
UINT32 sector = pi->op->get_fat_sector_for_cluster(from_cluster, pi);
UINT32 offset = pi->op->get_fat_offset_for_cluster(from_cluster, pi);
BYTE buf[SECTORSIZE*2];
if (read_sector(sector, buf) != SECTORSIZE)
return -1;
if (offset == SECTORSIZE - 1) {
/* read in next sector if this FAT entry spans two sectors */
if (read_sector(sector + 1, buf + SECTORSIZE) != SECTORSIZE)
return -1;
}
 
/* set the next cluster for from_cluster to to_cluster */
set_next_cluster_fat12(buf + offset, to_cluster, pi, from_cluster);
 
if (write_sector(sector, buf) != SECTORSIZE)
return -1;
if (offset == SECTORSIZE - 1)
if (write_sector(sector + 1, buf + SECTORSIZE) != SECTORSIZE)
return -1;
/* update 2nd FAT if present */
if (pi->NumberOfFats > 1) {
if (write_sector(sector + pi->SectorsPerFat, buf) != SECTORSIZE)
return -1;
if (offset == SECTORSIZE - 1)
if (write_sector(sector + 1 + pi->SectorsPerFat, buf + SECTORSIZE)
!= SECTORSIZE)
return -1;
 
}
 
return 0;
}
 
/* find a free cluster, set the next entry of that cluster to EOC
* and return that cluster.
*/
UINT32 allocate_one_cluster_fat12(PartitionInfo *pi)
{
UINT32 cluster = 0;
 
for (cluster = 2;
cluster < (pi->TotalSectors/pi->SectorsPerCluster);
cluster++)
if (next_cluster(cluster, pi) == 0) {
link_cluster_fat12(cluster, FAT12_EOC, pi);
return cluster;
}
 
return 0;
}
 
fat_ops fat12_ops = {
get_fat12_sector_for_cluster,
get_fat12_offset_for_cluster,
0,
0,
is_eoc_fat12,
is_valid_cluster_fat12,
next_cluster_fat12,
free_cluster_chain_fat12,
allocate_one_cluster_fat12,
link_cluster_fat12,
};
/xilfatfs_v1_00_a/src/src/xilfatfs_fat32.c
0,0 → 1,85
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
#include "fat.h"
#include "directory.h"
#include "util.h"
 
/* given the cluster #, find the sector in the partition where
* the FAT entry for that cluster is present
*/
 
UINT32 get_fat32_sector_for_cluster(UINT32 cluster, PartitionInfo *pi)
{
/* Each FAT entry takes 4 bytes in FAT 32 */
return ((cluster * 4) / SECTORSIZE) + pi->FatSector;
}
 
UINT32 get_fat32_offset_for_cluster(UINT32 cluster, PartitionInfo *pi)
{
/* Each FAT entry takes 4 bytes in FAT 32 */
return ((cluster * 4) % SECTORSIZE);
}
 
UINT32 get_next_cluster_fat32(BYTE *fat_entry, PartitionInfo *pi)
{
return 0x0FFFFFFF & make_UINT32(*(fat_entry + 3),
*(fat_entry + 2),
*(fat_entry + 1),
*(fat_entry));
}
 
void set_next_cluster_fat32(BYTE *fat_entry, UINT32 next_cluster, PartitionInfo *pi)
{
UINT32 old_entry;
 
/* extract the higher order 4 bits from old entry */
old_entry = 0xf0000000 & make_UINT32(*(fat_entry + 3),
*(fat_entry + 2),
*(fat_entry + 1),
*(fat_entry));
 
next_cluster &= 0x0fffffff;
next_cluster |= old_entry;
 
write_UINT32(fat_entry, next_cluster);
}
 
int is_eoc_fat32(UINT32 cluster, PartitionInfo *pi)
{
return (cluster >= FAT32_EOC);
}
 
int is_valid_cluster_fat32(UINT32 cluster, PartitionInfo *pi)
{
return (cluster < MAX_FAT32_CLUSTERS);
}
 
fat_ops fat32_ops = {
get_fat32_sector_for_cluster,
get_fat32_offset_for_cluster,
get_next_cluster_fat32,
set_next_cluster_fat32,
is_eoc_fat32,
is_valid_cluster_fat32,
next_cluster_generic,
free_cluster_chain_generic,
allocate_one_cluster_generic,
link_cluster_generic,
};
/xilfatfs_v1_00_a/src/src/xilfatfs_fat16.c
0,0 → 1,69
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
#include "fat.h"
#include "directory.h"
#include "util.h"
 
UINT32 get_fat16_sector_for_cluster(UINT32 cluster, PartitionInfo *pi)
{
/* Each FAT entry takes 2 bytes in FAT 16 */
return ((cluster * 2) / SECTORSIZE) + pi->FatSector;
}
 
UINT32 get_fat16_offset_for_cluster(UINT32 cluster, PartitionInfo *pi)
{
/* Each FAT entry takes 2 bytes in FAT 16 */
return ((cluster * 2) % SECTORSIZE);
}
 
UINT32 get_next_cluster_fat16(BYTE *fat_entry, PartitionInfo *pi)
{
return (UINT32)(0xffff & make_UINT16(*(fat_entry + 1), *(fat_entry)));
}
 
void set_next_cluster_fat16(BYTE *fat_entry, UINT32 next_cluster, PartitionInfo *pi)
{
write_UINT16(fat_entry, next_cluster);
}
 
int is_eoc_fat16(UINT32 cluster, PartitionInfo *pi)
{
return (cluster >= FAT16_EOC);
}
 
int is_valid_cluster_fat16(UINT32 cluster, PartitionInfo *pi)
{
return (cluster < MAX_FAT16_CLUSTERS);
}
 
fat_ops fat16_ops = {
get_fat16_sector_for_cluster,
get_fat16_offset_for_cluster,
get_next_cluster_fat16,
set_next_cluster_fat16,
is_eoc_fat16,
is_valid_cluster_fat16,
next_cluster_generic,
free_cluster_chain_generic,
allocate_one_cluster_generic,
link_cluster_generic,
};
 
 
/xilfatfs_v1_00_a/src/src/xilfatfs_filestatus.c
0,0 → 1,98
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include "filestatus.h"
#include "alloc.h"
 
/* global static for linked list start pointer */
static FileStatus *FileListHead = 0;
 
/* find the filestatus corresponding to a given stream */
FileStatus *find_file_status(SYSACE_FILE *stream)
{
FileStatus *fs;
 
for (fs = FileListHead; fs; fs = fs->next)
if (fs == stream)
return fs;
 
return 0;
}
 
 
/* Create a new FILEINFO and add to list.
* Fail if file is already open for write
*/
FileStatus *create_file_status(WorkingDirectory * wd,
BYTE read, BYTE write)
{
FileStatus *ps;
 
/* See it this file is already opened */
for (ps = FileListHead; ps; ps = ps->next) {
if (ps->wd->v.child.FirstCluster ==
wd->v.child.FirstCluster && (write || ps->write))
return 0;
}
 
if ((ps = malloc_fs()) == 0)
return 0;
 
ps->wd = wd;
ps->read = read;
ps->write = write;
ps->CurrentCluster = wd->v.child.FirstCluster;
ps->PositionInCluster = 0;
ps->PositionInFile = 0;
 
ps->next = FileListHead;
FileListHead = ps;
 
return ps;
}
 
int delete_file_status(FileStatus * status)
{
FileStatus *ps;
 
/* First unlink this item */
if (FileListHead == status) {
/* It's the first item, just step over it */
FileListHead = status->next;
} else {
/* It's further down the list - keep looking */
for (ps = FileListHead; ps; ps = ps->next) {
if (ps->next == status) {
/* found it - remove from list */
ps->next = status->next;
/* Stop search */
break;
}
}
if (ps == 0) {
/* Went through whole list and it wasn't there!! */
return -1;
}
}
 
delete_working_directory_stack(status->wd);
free_fs(status);
return 0;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_readdisk.c
0,0 → 1,21
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
/* All functions have been moved to other files */
/xilfatfs_v1_00_a/src/src/xilfatfs_standalone-utils.c
0,0 → 1,61
/////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
/////////////////////////////////////////////////////////////////////////////
 
/* Define the same functions present in sysace.c & sysace_stdio.c
* only these now work on a file (virtualized disk) rather than
* the compact flash
*/
 
#include <stdio.h>
#include <sysace.h>
 
/* pointer to the virtual disk */
FILE *disk_fp;
char *diskpath = "../cfdisk";
 
int init_ace()
{
disk_fp = fopen(diskpath, "r+");
if (!disk_fp) {
printf("%s: Error opening virtual disk: %s\n", __FUNCTION__, diskpath);
return -1;
}
 
return 0;
}
 
int read_sector(UINT32 sector, BYTE *sector_buf)
{
/* fseek to the correct position & return the sector */
if (fseek(disk_fp, sector * SECTORSIZE, SEEK_SET) < 0) {
printf("error while seeking..\n");
return -1;
}
return fread(sector_buf, 1, SECTORSIZE, disk_fp);
}
 
int write_sector(UINT32 sector, BYTE *sector_buf)
{
/* fseek to the correct position & write the sector */
if (fseek(disk_fp, sector * SECTORSIZE, SEEK_SET) < 0) {
printf("error while seeking..\n");
return -1;
}
return fwrite(sector_buf, 1, SECTORSIZE, disk_fp);
}
/xilfatfs_v1_00_a/src/src/xilfatfs_sysace.c
0,0 → 1,85
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include "xparameters.h"
 
#include "sysace.h"
#include "xsysace_l.h"
#include "xsysace.h"
#include "xstatus.h"
#include "xbasic_types.h"
#include "xio.h"
#include "bufcache.h"
#include "stats.h"
 
static Xuint32 sysace_base_addr = 0;
 
int read_sector_cf(UINT32 sector, BYTE *pSectorBuffer)
{
xilfatfs_stats_read++;
return XSysAce_ReadSector(sysace_base_addr,
sector, pSectorBuffer);
}
 
int write_sector_cf(UINT32 sector, BYTE *pSectorBuffer)
{
xilfatfs_stats_write++;
return XSysAce_WriteSector(sysace_base_addr,
sector, pSectorBuffer);
}
 
/***** initalize system ace for reading and writing *****/
int init_ace()
{
XSysAce Ace;
XStatus Result;
XStatus status_init;
 
/* This code assumes only one systemace interface in the build and its Device ID is 0*/
status_init = XSysAce_Initialize(&Ace, 0);
sysace_base_addr = Ace.BaseAddress;
while ((Result = XSysAce_Lock(&Ace, XFALSE)) != XST_SUCCESS)
;
XSysAce_RegWrite32(sysace_base_addr + XSA_CR_OFFSET,
XSA_CR_FORCECFGMODE_MASK);
 
init_bufcache(write_sector_cf);
 
return (int) (status_init);
}
 
int read_sector(UINT32 sector, BYTE *sector_buf)
{
if (is_buffered(sector) < 0) { /* sector not buffered */
int n = read_sector_cf(sector, sector_buf);
if (n == SECTORSIZE) { /* if valid data read */
if (update_bufcache(sector, sector_buf, 0) < 0)
return -1;
}
return n;
} else { /* sector already present in buffer */
return read_bufcache(sector, sector_buf);
}
}
 
int write_sector(UINT32 sector, BYTE *sector_buf)
{
return update_bufcache(sector, sector_buf, 1);
}
/xilfatfs_v1_00_a/src/src/xilfatfs_chdir.c
0,0 → 1,143
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include "fat.h"
#include "filespec.h"
#include "directory.h"
#include "util.h"
 
/* Limited to 8 character filenames */
int sysace_chdir(const char *path)
{
WorkingDirectory *wd;
int partition;
 
wd = build_working_directory_stack(path, 1, 0);
 
if (wd) {
/* This is a valid directory path */
partition = wd->pi->PartitionNum;
if (cwd[partition])
delete_working_directory_stack(cwd[partition]);
cwd[partition] = wd;
DefaultPartition = partition;
return 0;
}
 
return -1;
}
 
#ifdef GET_CWD
 
#define GETDCWDBUFSIZE 100
 
char *my_getdcwd(int drive, char *path, int pathsize)
{
int length, level;
int i, j;
char *s, *buf_t;
char buf[GETDCWDBUFSIZE];
WorkingDirectory *wd;
 
if (drive == 0) {
/* Use the default drive */
drive = DefaultPartition;
} else
drive -= 1;
 
if (drive < 0 || drive >= MAXPARTITION)
return 0;
 
if (cwd[drive] == 0) {
/* Set the default */
cwd[drive] =
build_working_directory_stack(DIRSEPSTRING, 1, 0);
if (cwd[drive] == 0)
return 0;
}
/* Determine the total length needed */
level = 0;
length = 3; /* Drive specification, terminating 0 */
 
wd = cwd[drive];
while (wd) {
length += strlen(wd->name);
++level;
wd = wd->parent;
}
 
if (level > 2)
length += level - 2; /* Allow for separating characters */
 
if (path) {
/* Use the users buffer */
if (pathsize < length)
return 0;
s = path;
} else {
if (GETDCWDBUFSIZE < length)
return 0;
s = buf;
}
 
/* Drive letter */
s[0] = 'a' + drive;
s[1] = ':';
 
/* terminate the string */
i = length;
s[--i] = 0;
 
wd = cwd[drive];
while (wd) {
j = strlen(wd->name);
 
/* Copy the directory name */
while (j > 0) {
if (i < 2) { /* Something went wrong - we re about to run out of room */
return 0;
}
s[--i] = wd->name[--j];
}
 
/* Add separator. Note that root and 2nd level directory do not need separators. */
if (level > 2)
s[--i] = DIRSEPCHAR;
--level;
wd = wd->parent;
}
 
if (i != 2) {
/* Something went wrong - at this point there should be space remaining for
* the drive spec (2 characters). */
return 0;
}
 
if (s == path)
return path;
 
/* Make a new string - user is responsible for free()ing this string */
buf_t = (char *)malloc(strlen(buf) + 1);
if (!buf_t)
return 0;
return strcpy(buf_t, buf);
}
 
#endif /*GET_CWD */
/xilfatfs_v1_00_a/src/src/xilfatfs_sysace_stdio.c
0,0 → 1,22
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
/* All functions have been moved to other files */
 
/xilfatfs_v1_00_a/src/src/xilfatfs_filespec.c
0,0 → 1,300
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
 
#include <ctype.h>
#include "filespec.h"
 
/* Routines to parse out path names. The only characters that are
* checked for are \ (backslash), . (period) and : (colon). The
* rest are treated as valid characters for names.
*
* Examine path to see if it starts with a directory name.
* If so, copy it to buf and return number of characters
* consumed. If buf is too short, 0 is returned. The is_dir
* flags says that we expect this to be a directory specifier, i.e.
* a trailing name with no file extension is a directory name,
* not a file name. The root flag says that this might be the root
* directory, i.e if it starts with backslash, return just that.
*/
static int find_dir(const char *path, char *buf, int length, int is_dir,
int root)
{
int i = 0;
int relative = 0;
 
if (root && path[0] == DIRSEPCHAR) {
/* This is the root */
if (length < 2)
return 0;
buf[0] = DIRSEPCHAR;
buf[1] = 0;
return 1;
}
 
while (i < length) {
if (path[i] == 0) {
/* End of string - could be a directory or a file
* name that has no extension */
if (is_dir) {
/* Last field is a directory */
buf[i] = 0;
return i;
} else {
/* Last field is a file */
return 0;
}
}
 
if (path[i] == DIRSEPCHAR) {
if (i > 0) {
/* hierarchy separator */
buf[i] = 0;
return i + 1; /* eat the directory separator too */
} else
return 0;
}
/* Look for bad characters */
if (path[i] == '.') {
if (i == 0)
relative = 1;
else if (i > 1 || !relative)
return 0;
}
 
if (path[i] == ':')
return 0;
 
/* Keep copying - so far so good */
buf[i] = path[i];
++i;
}
 
/* Never found the end of this name */
return 0;
}
 
/* Examine path to see if it starts with a device spec.
* If so, copy it to buf and return the number of chars
* consumed. If buf is too short, 0 is returned.
* Device spec can be a DOS style (e.g. a:) or network
* style (e.g. \\server).
*/
static int find_device(const char *path, char *buf, int length)
{
char c;
int i;
 
/* look for server form */
if (path[0] == DIRSEPCHAR && path[1] == DIRSEPCHAR) {
/* Find the server name - it looks just like a directory name */
i = 0;
while (i < length) {
if (path[i + 2] == 0 || path[i + 2] == DIRSEPCHAR) {
/* hit end of server name */
buf[i] = 0;
return i + 2; /* eat the double backslash too */
}
/* Watch for illegal characters */
if (path[i + 2] == '.' || path[i + 2] == ':')
return 0;
 
buf[i] = path[i + 2];
++i;
}
return 0;
}
/* Must be a plain old DOS disk (letter colon) */
if (length < 2 || path[0] == 0 || path[1] != ':')
return 0;
c = tolower(path[0]);
if (c < 'a' || c > 'z')
return 0;
 
/* It was a device */
buf[0] = c;
buf[1] = 0;
 
return 2;
}
 
/* Examine path to see if it starts with a file name.
* If so, copy it to buf and return number of characters
* consumed. If buf is too short, 0 is returned. The is_dir
* flags says that we expect this to be a directory specifier, i.e.
* a trailing name with no file extension is a directory name,
* not a file name.
*/
static int find_file(const char *path, char *buf, int length, int is_dir)
{
int i = 0;
 
/* Do not apply file name rules if this is known to be a directory path */
if (is_dir)
return 0;
 
while (i < length) {
if (path[i] == 0) {
/* End of string - file has no extension */
buf[i] = 0;
return i;
}
 
if (path[i] == '.') {
/* Hit the file extension */
buf[i] = 0;
return i;
}
/* Look for bad characters */
if (path[i] == DIRSEPCHAR || path[i] == ':')
return 0;
 
/* Keep copying - so far so good */
buf[i] = path[i];
++i;
}
 
/* Never found the end of this name */
return 0;
}
 
static int find_ext(const char *path, char *buf, int length)
{
int i = 0;
 
/* Must start with a dot */
if (path[0] != '.')
return 0;
 
while (i < length) {
/* 3 character max */
if (i > 3)
return 0;
 
if (path[i + 1] == 0) {
buf[i] = 0;
return i + 1;
}
/* Look for bad characters */
if (path[i + 1] == '.' || path[i + 1] == DIRSEPCHAR
|| path[i + 1] == ':')
return 0;
 
/* Keep copying - so far so good */
buf[i] = path[i + 1];
++i;
}
 
/* Never found the end of this name */
return 0;
}
 
/* Find the next field in the path. Returns the number of characters
* consumed by this field. The field type pointed to by type should
* Be set initially to 'START' and will be updated after the field
* has been found. The identified field will be stored in buf (up to l
* characters) - if it does not fit, there will be an error.
* The flag is_dir says that the path is a directory path, i.e. the
* last field will be treated as a directory, not a file with no
* extension.
*/
int parse_path(const char *path, char *buf, int length,
int is_dir, field_type * type)
{
int i = 0;
 
switch (*type) {
case PATH_START:
/* String cannot be empty */
if (*path == 0) {
*type = PATH_ERROR;
break;
}
 
/* Can start with device, directory or file */
if ((i = find_device(path, buf, length)) > 0)
*type = DEVICE_NAME;
else if ((i = find_dir(path, buf, length, is_dir, 1)) > 0)
*type = DIR_NAME;
else if ((i = find_file(path, buf, length, is_dir)) > 0)
*type = FILE_NAME;
else
*type = PATH_ERROR;
break;
 
case DEVICE_NAME:
/* String cannot be empty if we are looking for a file name */
if (*path == 0) {
if (!is_dir)
*type = PATH_ERROR;
else
*type = PATH_DONE;
break;
}
/* Device can be followed by directory or file */
if ((i = find_dir(path, buf, length, is_dir, 1)) > 0)
*type = DIR_NAME;
else if ((i = find_file(path, buf, length, is_dir)) > 0)
*type = FILE_NAME;
else
*type = PATH_ERROR;
break;
 
case DIR_NAME:
/* String cannot be empty if we are looking for a file name */
if (*path == 0) {
if (!is_dir)
*type = PATH_ERROR;
else
*type = PATH_DONE;
break;
}
/* Directory can be followed by directory or file */
if ((i = find_dir(path, buf, length, is_dir, 0)) > 0)
*type = DIR_NAME;
else if ((i = find_file(path, buf, length, is_dir)) > 0)
*type = FILE_NAME;
else
*type = PATH_ERROR;
break;
 
case FILE_NAME:
if (*path == 0)
*type = PATH_DONE;
else if ((i = find_ext(path, buf, length)) > 0)
*type = FILE_EXT;
else
*type = PATH_ERROR;
break;
 
case FILE_EXT:
if (*path == 0)
*type = PATH_DONE;
else
*type = PATH_ERROR;
break;
 
default:
*type = PATH_ERROR;
break;
}
 
return i;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_alloc.c
0,0 → 1,83
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include <string.h>
#include "alloc.h"
#include "fat.h"
 
/* Create and release WDs */
static WorkingDirectory wd_buf[MAXWD];
static int wd_init_flag = 1;
WorkingDirectory *
malloc_wd(const char *name)
{
int i;
 
/* Do initialization because MBlaze seems not to initialize statics per K&R */
if(wd_init_flag) {
wd_init_flag = 0;
for(i=0; i<MAXWD; i++ )
wd_buf[i].name[0] = 0;
}
 
for(i=0; i<MAXWD; i++)
if(wd_buf[i].name[0] == 0) {
strncpy(wd_buf[i].name, name, MAXFILENAMESIZE);
return wd_buf + i;
}
 
return 0;
}
 
void
free_wd(WorkingDirectory *wd)
{
wd->name[0] = 0;
}
 
static FileStatus fs_buf[MAXFILES];
static int fs_init_flag = 1;
 
FileStatus *
malloc_fs(void)
{
int i;
 
if(fs_init_flag) {
fs_init_flag = 0;
for(i=0; i<MAXFILES; i++)
fs_buf[i].reserved = 0;
}
 
for(i=0; i<MAXFILES; i++)
if( fs_buf[i].reserved == 0 ) {
fs_buf[i].reserved = 1;
return fs_buf + i;
}
 
return 0;
}
 
void
free_fs(FileStatus *fs)
{
fs->reserved = 0;
}
/xilfatfs_v1_00_a/src/src/xilfatfs_write.c
0,0 → 1,309
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
 
#include <string.h>
 
#include "alloc.h"
#include "fat.h"
#include "filestatus.h"
#include "sysace.h"
#include "sysace_stdio.h"
#include "util.h"
 
/* write_to_file:
* Write from the current position in chunks of sectors.
* Update the file size in the directory entry
* Update FAT if a new cluster is added
*/
int write_to_file(FileStatus *fs, char *buf, int count)
{
int writecount, n;
int remaining;
BYTE sectorbuf[SECTORSIZE], dir_buf[SECTORSIZE];
UINT32 sector;
UINT32 nsectors;
UINT32 sector_offset;
UINT32 filesize;
int byte_offset;
PartitionInfo *pi = fs->wd->pi;
UINT32 next_cluster;
DirectoryEntry *de;
 
/* Safety check */
if (fs == 0 || !fs->write || count <= 0)
return 0;
 
filesize = fs->wd->v.child.FileSize;
debug_xil_printf("Original file size: %d\n\r", (int)filesize);
writecount = 0; /* written til now */
remaining = count; /* remaining left to write */
 
/* read directory entry for this file. the directory entry
* is updated at the end with the new file size
*/
if (read_sector(fs->wd->v.child.DirLocation.sector, dir_buf) != SECTORSIZE)
return -1;
de = (DirectoryEntry *) (dir_buf + fs->wd->v.child.DirLocation.offset);
 
/* if this is the first byte of the file, then the firstcluster
* entry for it should be set in its directory entry
*/
if (filesize == 0) {
fs->wd->v.child.FirstCluster = pi->op->allocate_one_cluster(pi);
if (fs->wd->v.child.FirstCluster == 0)
return 0; /* out of space */
 
fs->CurrentCluster = fs->wd->v.child.FirstCluster;
fs->PositionInCluster = fs->PositionInFile = 0;
 
/* set the first cluster entry in the directory entry */
debug_xil_printf("First cluster set to: %d\n\r", (int)fs->CurrentCluster);
update_de_firstcluster(de, fs->CurrentCluster, pi);
}
 
/* if we are currently in the middle of a sector, then read in
* the contents before writing into it.
*/
 
/* Which byte of that sector did we leave off at last time ? */
byte_offset = fs->PositionInCluster % SECTORSIZE;
 
if (byte_offset) {
debug_xil_printf("%s @ %d: byte_offset = %d\n\r", __FUNCTION__,
__LINE__, byte_offset);
/* Which sector of this cluster did we leave off at last time ? */
sector_offset = fs->PositionInCluster / SECTORSIZE;
 
/* Sector address to start writing this time */
sector = starting_sector(fs->CurrentCluster, pi);
if (sector == 0) { /* FAT problem ? */
return 0;
}
sector += sector_offset;
 
if (read_sector(sector, sectorbuf) != SECTORSIZE)
return -1;
 
n = SECTORSIZE - byte_offset;
if (remaining < n)
n = remaining;
memcpy(sectorbuf + byte_offset, buf + writecount, n);
 
if (write_sector(sector, sectorbuf) != SECTORSIZE) {
/* nothing has changed. return error */
return -1;
}
 
/* we have written n bytes. update all fields accordingly */
filesize += n;
writecount += n;
remaining -= n;
fs->PositionInCluster += n;
}
 
/* now we are sector aligned. keep writing sector
* sized chunks. allocate a new cluster when needed
*/
while (remaining > 0) {
/* Which sector of this cluster did we leave off at last time ? */
sector_offset = fs->PositionInCluster / SECTORSIZE;
 
/* Sector address to start writing this time */
sector = starting_sector(fs->CurrentCluster, pi);
if (sector == 0) {
/* FAT problem ? */
return 0;
}
sector += sector_offset;
 
/* How many sectors left to write in this cluster */
nsectors = pi->SectorsPerCluster - sector_offset;
 
while (nsectors) {
if (remaining <= SECTORSIZE) {
debug_xil_printf("%s @ %d: last write of file data, remaining = %d\n\r",
__FUNCTION__, __LINE__, remaining);
/* the remaining data fits in this sector */
memcpy((char *) sectorbuf,
buf + writecount, remaining);
if (write_sector(sector, sectorbuf) != SECTORSIZE)
goto update_dentry;
 
fs->PositionInFile += remaining;
fs->PositionInCluster += remaining;
filesize += remaining;
writecount += remaining;
remaining = 0;
 
/* go and update the directory entry */
goto update_dentry;
}
 
/* End of file is beyond this sector */
n = SECTORSIZE;
if (write_sector(sector, buf + writecount) != SECTORSIZE)
goto update_dentry;
 
fs->PositionInFile += n;
fs->PositionInCluster += n;
filesize += n;
writecount += n;
remaining -= n;
 
/* Point to start of next sector in cluster */
sector += 1;
nsectors -= 1;
}
 
/* Done with that cluster, advance to the next one */
if ((next_cluster = pi->op->allocate_one_cluster(pi)) == 0) {
/* no more free clusters, update directory
* with whatever was written */
goto update_dentry;
}
 
/* link the current cluster to the next cluster in FAT */
if (pi->op->link_cluster(fs->CurrentCluster, next_cluster, pi) < 0)
goto update_dentry; /* error linking cluster chain */
 
/* start using the new cluster */
fs->CurrentCluster = next_cluster;
fs->PositionInCluster = 0;
}
 
update_dentry:
/* update the file size in the directory entry */
update_de_filesize(de, filesize);
 
/* update filesize in file status */
fs->wd->v.child.FileSize = filesize;
 
/* write back the directory entry */
if (write_sector(fs->wd->v.child.DirLocation.sector, dir_buf) != SECTORSIZE) {
/* in this case, we were able to read the directory entry
* but not write to it. the fs is in an inconsistent state
* since the FAT has been altered, but filesize not updated
* in the directory entry */
return -1;
}
 
return writecount;
}
 
int sysace_fwrite(void *buffer, int size, int count, SYSACE_FILE * stream)
{
FileStatus *fs = find_file_status(stream);
 
if (fs == 0)
return -1;
return write_to_file(fs, (char *) buffer, size * count);
}
 
/* create an entry for the file name.ext in parent directory */
WorkingDirectory *create_file_entry(const char *name, const char *ext,
WorkingDirectory *parent, BYTE attributes)
{
char buf[SECTORSIZE];
WorkingDirectory *wd;
int de;
UINT32 firstcluster;
UINT32 filesize;
UINT32 de_sector;
UINT32 de_offset;
DirectoryEntry dir_entry;
PartitionInfo *pi = parent->pi;
 
/* find a free directory entry */
if ((de = find_in_directory(parent, NULL, NULL, &firstcluster,
&filesize, &de_sector, &de_offset)) == 0)
return 0; /* no free entries available */
 
filesize = firstcluster = 0;
 
#ifdef CONFIG_DIR_SUPPORT
/* when creating a directory, two special directories (. & ..) within
* that directory should always be created
*/
if ((attributes & ATTR_DIRECTORY) == ATTR_DIRECTORY) {
UINT32 sector, parent_cluster;
int i;
 
firstcluster = pi->op->allocate_one_cluster(pi);
debug_xil_printf("firstcluster for dir: %ld\n", firstcluster);
if (firstcluster == 0)
return 0; /* no free space */
 
/* zero out all sectors in the allotted cluster */
memset(buf, 0, sizeof buf);
sector = starting_sector(firstcluster, pi);
debug_xil_printf("sectors starting from: %ld\n", sector);
for (i = 1, sector++; /* the first sector needs to have dot, dotdot entries
* and will be filled in later */
i < pi->SectorsPerCluster;
i++, sector++)
if (write_sector(sector, buf) != SECTORSIZE)
return 0; /* disk error */
 
/* create dot & dotdot entries for the directory */
 
/* the dot entry points to itself */
initialize_de(dotdot_entry, ".", "", firstcluster, 0, pi, ATTR_DIRECTORY);
 
/* the dotdot entry should point to the parent of the new directory */
parent_cluster = parent->v.child.FirstCluster;
if (parent->parent == NULL) /* root */
parent_cluster = 0;
debug_xil_printf("parent cluster = %ld\n", parent_cluster);
initialize_de(dotdot_entry+1, "..", "", parent_cluster, 0, pi, ATTR_DIRECTORY);
memcpy(buf, dotdot_entry, sizeof(DirectoryEntry)*2);
sector = starting_sector(firstcluster, pi);
if (write_sector(sector, buf) != SECTORSIZE)
return 0;
}
#endif
 
initialize_de(&dir_entry, (char *)name, (char *)ext, firstcluster, filesize,
pi, attributes);
 
/* allocate a wd structure to hold the working directory info*/
if ((wd = malloc_wd(name)) == 0)
return 0;
 
/* 1. read in the whole sector */
if (read_sector(de_sector, buf) != SECTORSIZE)
return 0;
 
/* 2. write the new directory entry */
memcpy(buf + de_offset, (char*)&dir_entry, sizeof dir_entry);
 
/* 3. write out the whole sector */
if (write_sector(de_sector, buf) != SECTORSIZE)
return 0;
 
wd->v.child.FirstCluster = firstcluster;
wd->v.child.FileSize = filesize;
wd->v.child.DirLocation.sector = de_sector;
wd->v.child.DirLocation.offset = de_offset;
wd->pi = parent->pi;
wd->parent = parent;
return wd;
}
/xilfatfs_v1_00_a/src/Makefile
0,0 → 1,96
####################################/-*-Makefile-*-
#
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
######################################################
 
include Makefile.config
 
DEBUG_OUTPUT = n
STANDALONE = n
 
#include all common source files
SRCS = xilfatfs_alloc.c xilfatfs_close.c xilfatfs_directory.c \
xilfatfs_fat.c xilfatfs_fat16.c xilfatfs_fat32.c xilfatfs_filespec.c \
xilfatfs_filestatus.c xilfatfs_open.c xilfatfs_part.c xilfatfs_read.c xilfatfs_wd.c \
xilfatfs_stats.c xilfatfs_bufcache.c
 
CFLAGS = -Wall -O2
 
# parse options
ifeq ($(CONFIG_WRITE), y)
CFLAGS += -DCONFIG_WRITE
SRCS += xilfatfs_write.c
ifeq ($(CONFIG_DIR_SUPPORT), y)
CFLAGS += -DCONFIG_DIR_SUPPORT
SRCS += xilfatfs_chdir.c xilfatfs_mkdir.c
endif
endif
 
ifeq ($(CONFIG_FAT12), y)
CFLAGS += -DCONFIG_FAT12
SRCS += xilfatfs_fat12.c
endif
 
ifeq ($(DEBUG_OUTPUT), y)
CFLAGS += -DDEBUG
endif
 
ifeq ($(STANDALONE), y)
SRCS += xilfatfs_standalone-utils.c
else
SRCS += xilfatfs_sysace.c
endif
 
ifdef CONFIG_MAXFILES
CFLAGS += -DMAXFILES=$(CONFIG_MAXFILES)
else
CFLAGS += -DMAXFILES=5
endif
 
OBJS = ${SRCS:.c=.o}
 
COMPILER=
ARCHIVER=
CP=cp
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
LEVEL=0
 
RELEASEDIR=../../../lib/
INCLUDEDIR=../../../include/
INCLUDES=-I./include/ -I${INCLUDEDIR}
 
INCLUDEFILES= ./include/sysace_stdio.h
LIBSOURCES= $(SRCS:%.c=src/%.c)
OUTS = *.o
 
libs:
for i in $(LIBSOURCES); do \
echo "Compiling " $$i ;\
$(COMPILER) $(COMPILER_FLAGS) $(CFLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $$i; \
done
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
echo make clean
 
include: dummy
${CP} -rf ${INCLUDEFILES} ${INCLUDEDIR}
 
dummy:
clean:
rm -rf ${OUTS}
 
/cpu_v1_00_a/src/xio.c
0,0 → 1,233
/* $Id: xio.c,v 1.1 2006-06-23 19:01:05 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2003 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.c
*
* Contains I/O functions for memory-mapped or non-memory-mapped I/O
* architectures. These functions encapsulate generic CPU I/O requirements.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* </pre>
*
* @note
*
* This file may contain architecture-dependent code.
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xio.h"
#include "xbasic_types.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
 
/*****************************************************************************/
/**
*
* Performs a 16-bit endian converion.
*
* @param Source contains the value to be converted.
* @param DestPtr contains a pointer to the location to put the
* converted value.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XIo_EndianSwap16(Xuint16 Source, Xuint16* DestPtr)
{
*DestPtr = (Xuint16)(((Source & 0xFF00) >> 8) | ((Source & 0x00FF) << 8));
}
 
/*****************************************************************************/
/**
*
* Performs a 32-bit endian converion.
*
* @param Source contains the value to be converted.
* @param DestPtr contains a pointer to the location to put the
* converted value.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XIo_EndianSwap32(Xuint32 Source, Xuint32* DestPtr)
{
/* get each of the half words from the 32 bit word */
 
Xuint16 LoWord = (Xuint16)(Source & 0x0000FFFF);
Xuint16 HiWord = (Xuint16)((Source & 0xFFFF0000) >> 16);
 
/* byte swap each of the 16 bit half words */
 
LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
 
/* swap the half words before returning the value */
 
*DestPtr = (Xuint32)((LoWord << 16) | HiWord);
}
 
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the byte-swapped value read from that
* address.
*
* @param InAddress contains the address to perform the input operation at.
*
* @return
*
* The byte-swapped value read from the specified input address.
*
* @note
*
* None.
*
******************************************************************************/
Xuint16 XIo_InSwap16(XIo_Address InAddress)
{
Xuint16 InData;
/* get the data then swap it */
InData = XIo_In16(InAddress);
return (Xuint16)(((InData & 0xFF00) >> 8) | ((InData & 0x00FF) << 8));
}
 
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the byte-swapped value read from that
* address.
*
* @param InAddress contains the address to perform the input operation at.
*
* @return
*
* The byte-swapped value read from the specified input address.
*
* @note
*
* None.
*
******************************************************************************/
Xuint32 XIo_InSwap32(XIo_Address InAddress)
{
Xuint32 InData;
Xuint32 SwapData;
/* get the data then swap it */
InData = XIo_In32(InAddress);
XIo_EndianSwap32(InData, &SwapData);
return SwapData;
}
 
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address. The value is byte-swapped
* before being written.
*
* @param OutAddress contains the address to perform the output operation at.
* @param Value contains the value to be output at the specified address.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XIo_OutSwap16(XIo_Address OutAddress, Xuint16 Value)
{
Xuint16 OutData;
/* swap the data then output it */
OutData = (Xuint16)(((Value & 0xFF00) >> 8) | ((Value & 0x00FF) << 8));
XIo_Out16(OutAddress, OutData);
}
 
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address. The value is byte-swapped
* before being written.
*
* @param OutAddress contains the address to perform the output operation at.
* @param Value contains the value to be output at the specified address.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XIo_OutSwap32(XIo_Address OutAddress, Xuint32 Value)
{
Xuint32 OutData;
/* swap the data then output it */
XIo_EndianSwap32(Value, &OutData);
XIo_Out32(OutAddress, OutData);
}
 
/cpu_v1_00_a/src/xio.h
0,0 → 1,214
/* $Id: xio.h,v 1.1 2006-06-23 19:01:05 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2003 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xio.h
*
* This file contains the interface for the XIo component, which encapsulates
* the Input/Output functions for processors that do not require any special
* I/O handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added InSwap/OutSwap routines for endian conversion
* 1.00a xd 11/04/04 Improved support for doxygen
* </pre>
*
* @note
*
* This file may contain architecture-dependent items (memory-mapped or
* non-memory-mapped I/O).
*
******************************************************************************/
 
#ifndef XIO_H /* prevent circular inclusions */
#define XIO_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
/**
* Typedef for an I/O address. Typically correlates to the width of the
* address bus.
*/
typedef Xuint32 XIo_Address;
 
/***************** Macros (Inline Functions) Definitions *********************/
 
/*
* The following macros allow optimized I/O operations for memory mapped I/O.
* It should be noted that macros cannot be used if synchronization of the I/O
* operation is needed as it will likely break some code.
*/
 
/*****************************************************************************/
/**
*
* Performs an input operation for an 8-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
******************************************************************************/
#define XIo_In8(InputPtr) (*(volatile Xuint8 *)(InputPtr))
 
/*****************************************************************************/
/**
*
* Performs an input operation for a 16-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
******************************************************************************/
#define XIo_In16(InputPtr) (*(volatile Xuint16 *)(InputPtr))
 
/*****************************************************************************/
/**
*
* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param InputPtr contains the address to perform the input operation at.
*
* @return The value read from the specified input address.
*
******************************************************************************/
#define XIo_In32(InputPtr) (*(volatile Xuint32 *)(InputPtr))
 
 
/*****************************************************************************/
/**
*
* Performs an output operation for an 8-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation at.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
******************************************************************************/
#define XIo_Out8(OutputPtr, Value) \
{ (*(volatile Xuint8 *)(OutputPtr) = Value); }
 
/*****************************************************************************/
/**
*
* Performs an output operation for a 16-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation at.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
******************************************************************************/
#define XIo_Out16(OutputPtr, Value) \
{ (*(volatile Xuint16 *)(OutputPtr) = Value); }
 
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address.
*
* @param OutputPtr contains the address to perform the output operation at.
* @param Value contains the value to be output at the specified address.
*
* @return None.
*
******************************************************************************/
#define XIo_Out32(OutputPtr, Value) \
{ (*(volatile Xuint32 *)(OutputPtr) = Value); }
 
 
/* The following macros allow the software to be transportable across
* processors which use big or little endian memory models.
*
* Defined first is a no-op endian conversion macro. This macro is not to
* be used directly by software. Instead, the XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX macros below are to be used to allow the endian
* conversion to only be performed when necessary
*/
#define XIo_EndianNoop(Source, Destination) (*DestPtr = Source)
 
#ifdef XLITTLE_ENDIAN
 
#define XIo_ToLittleEndian16 XIo_EndianNoop
#define XIo_ToLittleEndian32 XIo_EndianNoop
#define XIo_FromLittleEndian16 XIo_EndianNoop
#define XIo_FromLittleEndian32 XIo_EndianNoop
 
#define XIo_ToBigEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToBigEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromBigEndian16 XIo_ToBigEndian16
#define XIo_FromBigEndian32 XIo_ToBigEndian32
 
#else
 
#define XIo_ToLittleEndian16(Source, DestPtr) XIo_EndianSwap16(Source, DestPtr)
#define XIo_ToLittleEndian32(Source, DestPtr) XIo_EndianSwap32(Source, DestPtr)
#define XIo_FromLittleEndian16 XIo_ToLittleEndian16
#define XIo_FromLittleEndian32 XIo_ToLittleEndian32
 
#define XIo_ToBigEndian16 XIo_EndianNoop
#define XIo_ToBigEndian32 XIo_EndianNoop
#define XIo_FromBigEndian16 XIo_EndianNoop
#define XIo_FromBigEndian32 XIo_EndianNoop
 
#endif
 
/************************** Function Prototypes ******************************/
 
/* The following functions allow the software to be transportable across
* processors which use big or little endian memory models. These functions
* should not be directly called, but the macros XIo_To/FromLittleEndianXX and
* XIo_To/FromBigEndianXX should be used to allow the endian conversion to only
* be performed when necessary.
*/
void XIo_EndianSwap16(Xuint16 Source, Xuint16* DestPtr);
void XIo_EndianSwap32(Xuint32 Source, Xuint32* DestPtr);
 
/* The following functions handle IO addresses where data must be swapped
* They cannot be implemented as macros
*/
Xuint16 XIo_InSwap16(XIo_Address InAddress);
Xuint32 XIo_InSwap32(XIo_Address InAddress);
void XIo_OutSwap16(XIo_Address OutAddress, Xuint16 Value);
void XIo_OutSwap32(XIo_Address OutAddress, Xuint32 Value);
 
#endif /* end of protection macro */
/cpu_v1_00_a/src/Makefile
0,0 → 1,27
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
 
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
 
OUTS = *.o
 
LIBSOURCES=*.c
INCLUDEFILES=xio.h
 
libs:
echo "Compiling cpu"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
 
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
 
clean:
rm -rf ${OUTS}
/sysace_v1_00_a/src/xsysace.c
0,0 → 1,377
/* $Id: xsysace.c,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysace.c
*
* The Xilinx System ACE driver component. This driver supports the Xilinx
* System Advanced Configuration Environment (ACE) controller. It currently
* supports only the CompactFlash solution. See xsysace.h for a detailed
* description of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rpm 06/17/02 work in progress
* 1.00a rmm 05/14/03 Fixed diab compiler warnings relating to asserts
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xparameters.h"
#include "xsysace.h"
#include "xsysace_l.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
static void StubEventHandler(void *CallBackRef, int Event);
 
/************************** Variable Definitions *****************************/
 
 
/*****************************************************************************/
/**
*
* Initialize a specific XSysAce instance. The configuration information for
* the given device ID is found and the driver instance data is initialized
* appropriately.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param DeviceId is the unique id of the device controlled by this XSysAce
* instance.
*
* @return
*
* XST_SUCCESS if successful, or XST_DEVICE_NOT_FOUND if the device was not
* found in the configuration table in xsysace_g.c.
*
* @note
*
* We do not want to reset the configuration controller here since this could
* cause a reconfiguration of the JTAG target chain, depending on how the
* CFGMODEPIN of the device is wired.
*
******************************************************************************/
XStatus XSysAce_Initialize(XSysAce *InstancePtr, Xuint16 DeviceId)
{
XSysAce_Config *ConfigPtr;
 
XASSERT_NONVOID(InstancePtr != XNULL);
 
InstancePtr->IsReady = 0;
 
/*
* Lookup configuration data in the device configuration table.
* Use this configuration info down below when initializing this component.
*/
ConfigPtr = XSysAce_LookupConfig(DeviceId);
 
if (ConfigPtr == (XSysAce_Config *)XNULL)
{
return XST_DEVICE_NOT_FOUND;
}
 
/*
* Set some default values for the instance data
*/
InstancePtr->BaseAddress = ConfigPtr->BaseAddress;
InstancePtr->EventHandler = StubEventHandler;
InstancePtr->NumRequested = 0;
InstancePtr->NumRemaining = 0;
InstancePtr->BufferPtr = XNULL;
 
/*
* Put the device into 16-bit mode or 8-bit mode depending on compile-time
* parameter
*/
#if (XPAR_XSYSACE_MEM_WIDTH == 16)
XSysAce_RegWrite16(InstancePtr->BaseAddress + XSA_BMR_OFFSET,
XSA_BMR_16BIT_MASK);
#else
XSysAce_RegWrite16(InstancePtr->BaseAddress + XSA_BMR_OFFSET, 0);
#endif
 
/*
* Disable interrupts. Interrupts must be enabled by the user using
* XSysAce_EnableInterrupt(). Put the interrupt request line in reset and
* clear the interrupt enable bits.
*/
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_RESETIRQ_MASK);
XSysAce_mAndControlReg(InstancePtr->BaseAddress, ~(XSA_CR_DATARDYIRQ_MASK |
XSA_CR_ERRORIRQ_MASK | XSA_CR_CFGDONEIRQ_MASK));
 
/*
* Indicate the instance is now ready to use, initialized without error
*/
InstancePtr->IsReady = XCOMPONENT_IS_READY;
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Attempt to lock access to the CompactFlash. The CompactFlash may be accessed
* by the MPU port as well as the JTAG configuration port within the System ACE
* device. This function requests exclusive access to the CompactFlash for the
* MPU port. This is a non-blocking request. If access cannot be locked
* (because the configuration controller has the lock), an appropriate status is
* returned. In this case, the user should call this function again until
* successful.
*
* If the user requests a forced lock, the JTAG configuration controller will
* be put into a reset state in case it currently has a lock on the CompactFlash.
* This effectively aborts any operation the configuration controller had in
* progress and makes the configuration controller restart its process the
* next time it is able to get a lock.
*
* A lock must be granted to the user before attempting to read or write the
* CompactFlash device.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param Force is a boolean value that, when set to XTRUE, will force the MPU
* lock to occur in the System ACE. When set to XFALSE, the lock is
* requested and the device arbitrates between the MPU request and
* JTAG requests. Forcing the MPU lock resets the configuration
* controller, thus aborting any configuration operations in progress.
*
* @return
*
* XST_SUCCESS if the lock was granted, or XST_DEVICE_BUSY if the lock was
* not granted because the configuration controller currently has access to
* the CompactFlash.
*
* @note
*
* If the lock is not granted to the MPU immediately, this function removes its
* request for a lock so that a lock is not later granted at a time when the
* application is (a) not ready for the lock, or (b) cannot be informed
* asynchronously about the granted lock since there is no such interrupt event.
*
******************************************************************************/
XStatus XSysAce_Lock(XSysAce *InstancePtr, Xboolean Force)
{
Xboolean IsLocked;
 
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/*
* Check to see if the configuration controller currently has the lock
*/
IsLocked = (XSysAce_mGetStatusReg(InstancePtr->BaseAddress) &
XSA_SR_CFGLOCK_MASK);
 
if (Force)
{
/*
* Reset the configuration controller if it has the lock. Per ASIC
* designer, this eliminates a potential deadlock if the FORCELOCK and
* LOCKREQ bits are both set and the RDYFORCFCMD is not set.
*/
if (IsLocked)
{
/* Reset the configuration controller */
XSysAce_mOrControlReg(InstancePtr->BaseAddress,
XSA_CR_CFGRESET_MASK);
}
 
/* Force the MPU lock. The lock will occur immediately. */
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_LOCKREQ_MASK |
XSA_CR_FORCELOCK_MASK);
}
else
{
/*
* Check to see if the configuration controller has the lock. If so,
* return a busy status.
*/
if (IsLocked)
{
return XST_DEVICE_BUSY;
}
 
/* Request the lock, but do not force it */
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_LOCKREQ_MASK);
}
 
/*
* See if the lock was granted. Note that it is guaranteed to occur if
* the user forced it.
*/
if (!XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
/* Lock was not granted, so remove request and return a busy */
XSysAce_mAndControlReg(InstancePtr->BaseAddress,
~(XSA_CR_LOCKREQ_MASK | XSA_CR_FORCELOCK_MASK));
 
return XST_DEVICE_BUSY;
}
 
/*
* Lock has been granted.
*
* If the configuration controller had the lock and has been reset,
* go ahead and release it from reset as it will not be able to get
* the lock again until the MPU lock is released.
*/
if (IsLocked && Force)
{
/* Release the reset of the configuration controller */
XSysAce_mAndControlReg(InstancePtr->BaseAddress, ~XSA_CR_CFGRESET_MASK);
}
 
return XST_SUCCESS;
}
 
 
/*****************************************************************************/
/**
*
* Release the MPU lock to the CompactFlash. If a lock is not currently granted
* to the MPU port, this function has no effect.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XSysAce_Unlock(XSysAce *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/*
* Blindly clear the lock and force-lock request bits of the control
* register
*/
XSysAce_mAndControlReg(InstancePtr->BaseAddress,
~(XSA_CR_LOCKREQ_MASK | XSA_CR_FORCELOCK_MASK));
}
 
/*****************************************************************************/
/**
*
* Get all outstanding errors. Errors include the inability to read or write
* CompactFlash and the inability to successfully configure FPGA devices along
* the target FPGA chain.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* A 32-bit mask of error values. See xsysace_l.h for a description of possible
* values. The error identifiers are prefixed with XSA_ER_*.
*
* @note
*
* None.
*
******************************************************************************/
Xuint32 XSysAce_GetErrors(XSysAce *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
return XSysAce_mGetErrorReg(InstancePtr->BaseAddress);
}
 
/*****************************************************************************/
/**
*
* Stub for the asynchronous event callback. The stub is here in case the upper
* layers forget to set the handler.
*
* @param CallBackRef is a pointer to the upper layer callback reference
* @param Event is the event that occurs
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
static void StubEventHandler(void *CallBackRef, int Event)
{
XASSERT_VOID_ALWAYS();
}
 
/*****************************************************************************/
/**
*
* Looks up the device configuration based on the unique device ID. The table
* XSysAce_ConfigTable contains the configuration info for each device in the
* system.
*
* @param DeviceId is the unique device ID to look for.
*
* @return
*
* A pointer to the configuration data for the device, or XNULL if no match is
* found.
*
* @note
*
* None.
*
******************************************************************************/
XSysAce_Config *XSysAce_LookupConfig(Xuint16 DeviceId)
{
extern XSysAce_Config XSysAce_ConfigTable[];
XSysAce_Config *CfgPtr = XNULL;
int i;
 
for (i=0; i < XPAR_XSYSACE_NUM_INSTANCES; i++)
{
if (XSysAce_ConfigTable[i].DeviceId == DeviceId)
{
CfgPtr = &XSysAce_ConfigTable[i];
break;
}
}
 
return CfgPtr;
}
 
/sysace_v1_00_a/src/xsysace_l.h
0,0 → 1,503
/* $Id: xsysace_l.h,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysace_l.h
*
* Defines identifiers and low-level macros/functions for the XSysAce driver.
* These identifiers include register offsets and bit masks. A high-level driver
* interface is defined in xsysace.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rpm 06/14/02 work in progress
* </pre>
*
******************************************************************************/
 
#ifndef XSYSACE_L_H /* prevent circular inclusions */
#define XSYSACE_L_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
#include "xio.h"
 
/************************** Constant Definitions *****************************/
 
/*
* Constant used to align the register offsets to the proper address. This was
* used during development to handle both byte-addressable (alignment=1) and
* word addressable (alignment=4) registers. The #ifndef allows the user to
* modify this at compile-time.
*/
#ifndef XSA_ADDR_ALIGN
#define XSA_ADDR_ALIGN 1
#endif
 
/** @name Register Offsets
* System ACE register offsets
* @{
*/
#define XSA_BMR_OFFSET (XSA_ADDR_ALIGN * 0) /**< Bus mode (BUSMODEREG) */
#define XSA_SR_OFFSET (XSA_ADDR_ALIGN * 4) /**< Status (STATUSREG) */
#define XSA_ER_OFFSET (XSA_ADDR_ALIGN * 8) /**< Error (ERRORREG) */
#define XSA_CLR_OFFSET (XSA_ADDR_ALIGN * 12) /**< Config LBA (CFGLBAREG) */
#define XSA_MLR_OFFSET (XSA_ADDR_ALIGN * 16) /**< MPU LBA (MPULBAREG) */
#define XSA_SCCR_OFFSET (XSA_ADDR_ALIGN * 20) /**< Sector cnt (SECCNTCMDREG) */
#define XSA_VR_OFFSET (XSA_ADDR_ALIGN * 22) /**< Version (VERSIONREG) */
#define XSA_CR_OFFSET (XSA_ADDR_ALIGN * 24) /**< Control (CONTROLREG) */
#define XSA_FSR_OFFSET (XSA_ADDR_ALIGN * 28) /**< FAT status (FATSTATREG) */
#define XSA_DBR_OFFSET (XSA_ADDR_ALIGN * 64) /**< Data buffer (DATABUFREG) */
/*@}*/
 
/*
* Bus Mode Register masks
*/
#define XSA_BMR_16BIT_MASK 0x0101 /**< 16-bit access to ACE controller */
 
 
/** @name Status Values
* Status Register masks
* @{
*/
#define XSA_SR_CFGLOCK_MASK 0x00000001 /**< Config port lock status */
#define XSA_SR_MPULOCK_MASK 0x00000002 /**< MPU port lock status */
#define XSA_SR_CFGERROR_MASK 0x00000004 /**< Config port error status */
#define XSA_SR_CFCERROR_MASK 0x00000008 /**< CF error status */
#define XSA_SR_CFDETECT_MASK 0x00000010 /**< CF detect flag */
#define XSA_SR_DATABUFRDY_MASK 0x00000020 /**< Data buffer ready status */
#define XSA_SR_DATABUFMODE_MASK 0x00000040 /**< Data buffer mode status */
#define XSA_SR_CFGDONE_MASK 0x00000080 /**< Configuration done status */
#define XSA_SR_RDYFORCMD_MASK 0x00000100 /**< Ready for CF command */
#define XSA_SR_CFGMODE_MASK 0x00000200 /**< Configuration mode status */
#define XSA_SR_CFGADDR_MASK 0x0000E000 /**< Configuration address */
#define XSA_SR_CFBSY_MASK 0x00020000 /**< CF busy (BSY bit) */
#define XSA_SR_CFRDY_MASK 0x00040000 /**< CF ready (RDY bit) */
#define XSA_SR_CFDWF_MASK 0x00080000 /**< CF data write fault (DWF bit) */
#define XSA_SR_CFDSC_MASK 0x00100000 /**< CF ready (DSC bit) */
#define XSA_SR_CFDRQ_MASK 0x00200000 /**< CF data request (DRQ) */
#define XSA_SR_CFCORR_MASK 0x00400000 /**< CF correctable error (CORR bit) */
#define XSA_SR_CFERR_MASK 0x00800000 /**< CF error (ERR bit) */
/*@}*/
 
 
/** @name Error Values
* Error Register masks.
* @{
*/
#define XSA_ER_CARD_RESET 0x00000001 /**< CF card failed to reset */
#define XSA_ER_CARD_READY 0x00000002 /**< CF card failed to ready */
#define XSA_ER_CARD_READ 0x00000004 /**< CF read command failed */
#define XSA_ER_CARD_WRITE 0x00000008 /**< CF write command failed */
#define XSA_ER_SECTOR_READY 0x00000010 /**< CF sector failed to ready */
#define XSA_ER_CFG_ADDR 0x00000020 /**< Cfg address is invalid */
#define XSA_ER_CFG_FAIL 0x00000040 /**< Failed to configure a device */
#define XSA_ER_CFG_READ 0x00000080 /**< Cfg read of CF failed */
#define XSA_ER_CFG_INSTR 0x00000100 /**< Invalid instruction during cfg */
#define XSA_ER_CFG_INIT 0x00000200 /**< CFGINIT pin error - did not
* go high within 500ms of start */
#define XSA_ER_RESERVED 0x00000400 /**< reserved */
#define XSA_ER_BAD_BLOCK 0x00000800 /**< CF bad block detected */
#define XSA_ER_UNCORRECTABLE 0x00001000 /**< CF uncorrectable error */
#define XSA_ER_SECTOR_ID 0x00002000 /**< CF sector ID not found */
#define XSA_ER_ABORT 0x00004000 /**< CF command aborted */
#define XSA_ER_GENERAL 0x00008000 /**< CF general error */
/*@}*/
 
 
/**
* Config LBA Register - address mask
*/
#define XSA_CLR_LBA_MASK 0x0FFFFFFF /* Logical Block Address mask */
 
/**
* MPU LBA Register - address mask
*/
#define XSA_MLR_LBA_MASK 0x0FFFFFFF /* Logical Block Address mask */
 
 
/** @name Sector Cound/Command Values
* Sector Count Command Register masks
* @{
*/
#define XSA_SCCR_COUNT_MASK 0x00FF /**< Sector count mask */
#define XSA_SCCR_RESET_MASK 0x0100 /**< Reset CF card command */
#define XSA_SCCR_IDENTIFY_MASK 0x0200 /**< Identify CF card command */
#define XSA_SCCR_READDATA_MASK 0x0300 /**< Read CF card command */
#define XSA_SCCR_WRITEDATA_MASK 0x0400 /**< Write CF card command */
#define XSA_SCCR_ABORT_MASK 0x0600 /**< Abort CF command */
#define XSA_SCCR_CMD_MASK 0x0700 /**< Command mask */
/*@}*/
 
 
/*
* Version Register masks
*/
#define XSA_VR_BUILD_MASK 0x00FF /* Revision/build number */
#define XSA_VR_MINOR_MASK 0x0F00 /* Minor version number */
#define XSA_VR_MAJOR_MASK 0xF000 /* Major version number */
 
 
/** @name Control Values
* Control Register masks
* @{
*/
#define XSA_CR_FORCELOCK_MASK 0x00000001 /**< Force lock request */
#define XSA_CR_LOCKREQ_MASK 0x00000002 /**< MPU lock request */
#define XSA_CR_FORCECFGADDR_MASK 0x00000004 /**< Force CFG address */
#define XSA_CR_FORCECFGMODE_MASK 0x00000008 /**< Force CFG mode */
#define XSA_CR_CFGMODE_MASK 0x00000010 /**< CFG mode */
#define XSA_CR_CFGSTART_MASK 0x00000020 /**< CFG start */
#define XSA_CR_CFGSEL_MASK 0x00000040 /**< CFG select */
#define XSA_CR_CFGRESET_MASK 0x00000080 /**< CFG reset */
#define XSA_CR_DATARDYIRQ_MASK 0x00000100 /**< Enable data ready IRQ */
#define XSA_CR_ERRORIRQ_MASK 0x00000200 /**< Enable error IRQ */
#define XSA_CR_CFGDONEIRQ_MASK 0x00000400 /**< Enable CFG done IRQ */
#define XSA_CR_RESETIRQ_MASK 0x00000800 /**< Reset IRQ line */
#define XSA_CR_CFGPROG_MASK 0x00001000 /**< Inverted CFGPROG pin */
#define XSA_CR_CFGADDR_MASK 0x0000E000 /**< Config address mask */
#define XSA_CR_CFGADDR_SHIFT 13 /**< Config address shift */
/*@}*/
 
 
/** @name FAT Status
*
* FAT filesystem status masks. The first valid partition of the CF
* is a FAT partition.
* @{
*/
#define XSA_FAT_VALID_BOOT_REC 0x0001 /**< Valid master boot record */
#define XSA_FAT_VALID_PART_REC 0x0002 /**< Valid partition boot record */
#define XSA_FAT_12_BOOT_REC 0x0004 /**< FAT12 in master boot rec */
#define XSA_FAT_12_PART_REC 0x0008 /**< FAT12 in parition boot rec */
#define XSA_FAT_16_BOOT_REC 0x0010 /**< FAT16 in master boot rec */
#define XSA_FAT_16_PART_REC 0x0020 /**< FAT16 in partition boot rec */
#define XSA_FAT_12_CALC 0x0040 /**< Calculated FAT12 from clusters */
#define XSA_FAT_16_CALC 0x0080 /**< Calculated FAT16 from clusters */
/*@}*/
 
 
#define XSA_DATA_BUFFER_SIZE 32 /**< Size of System ACE data buffer */
#define XSA_CF_SECTOR_SIZE 512 /**< Number of bytes in a CF sector */
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
/*****************************************************************************
*
* Low-level driver macros and functions. The list below provides signatures
* to help the user use the macros.
*
* Xuint32 XSysAce_mGetControlReg(Xuint32 BaseAddress)
* void XSysAce_mSetControlReg(Xuint32 BaseAddress, Xuint32 Data)
* void XSysAce_mOrControlReg(Xuint32 BaseAddress, Xuint32 Data)
* void XSysAce_mAndControlReg(Xuint32 BaseAddress, Xuint32 Data)
* Xuint32 XSysAce_mGetErrorReg(Xuint32 BaseAddress)
* Xuint32 XSysAce_mGetStatusReg(Xuint32 BaseAddress)
*
* void XSysAce_mSetCfgAddr(Xuint32 BaseAddress, unsigned int Address)
* void XSysAce_mWaitForLock(Xuint32 BaseAddress)
* void XSysAce_mEnableIntr(Xuint32 BaseAddress, Xuint32 Mask)
* void XSysAce_mDisableIntr(Xuint32 BaseAddress, Xuint32 Mask)
*
* Xboolean XSysAce_mIsReadyForCmd(Xuint32 BaseAddress)
* Xboolean XSysAce_mIsCfgDone(Xuint32 BaseAddress)
* Xboolean XSysAce_mIsMpuLocked(Xuint32 BaseAddress)
* Xboolean XSysAce_mIsIntrEnabled(Xuint32 BaseAddress)
*
*****************************************************************************/
 
 
/*****************************************************************************/
/**
*
* Get the contents of the control register.
*
* @param BaseAddress is the base address of the device.
*
* @return The 32-bit value of the control register.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mGetControlReg(BaseAddress) \
XSysAce_RegRead32((BaseAddress) + XSA_CR_OFFSET)
 
 
/*****************************************************************************/
/**
*
* Set the contents of the control register.
*
* @param BaseAddress is the base address of the device.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mSetControlReg(BaseAddress, Data) \
XSysAce_RegWrite32((BaseAddress) + XSA_CR_OFFSET, (Data))
 
 
/*****************************************************************************/
/**
*
* Set the contents of the control register to the value specified OR'ed with
* its current contents.
*
* @param BaseAddress is the base address of the device.
* @param Data is the 32-bit value to OR with the register.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mOrControlReg(BaseAddress, Data) \
XSysAce_mSetControlReg((BaseAddress), \
XSysAce_mGetControlReg(BaseAddress) | (Data))
 
 
/*****************************************************************************/
/**
*
* Set the contents of the control register to the value specified AND'ed with
* its current contents.
*
* @param BaseAddress is the base address of the device.
* @param Data is the 32-bit value to AND with the register.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mAndControlReg(BaseAddress, Data) \
XSysAce_mSetControlReg((BaseAddress), \
XSysAce_mGetControlReg(BaseAddress) & (Data))
 
 
/*****************************************************************************/
/**
*
* Get the contents of the error register.
*
* @param BaseAddress is the base address of the device.
*
* @return The 32-bit value of the register.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mGetErrorReg(BaseAddress) \
XSysAce_RegRead32((BaseAddress) + XSA_ER_OFFSET)
 
 
/*****************************************************************************/
/**
*
* Get the contents of the status register.
*
* @param BaseAddress is the base address of the device.
*
* @return The 32-bit value of the register.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mGetStatusReg(BaseAddress) \
XSysAce_RegRead32((BaseAddress) + XSA_SR_OFFSET)
 
 
/*****************************************************************************/
/**
*
* Set the configuration address, or file, of the CompactFlash. This address
* indicates which .ace bitstream to use to configure the target FPGA chain.
*
* @param BaseAddress is the base address of the device.
* @param Address ranges from 0 to 7 and represents the eight possible .ace
* bitstreams that can reside on the CompactFlash.
*
* @return None.
*
* @note Used cryptic var names to avoid conflict with caller's var names.
*
******************************************************************************/
#define XSysAce_mSetCfgAddr(BaseAddress, Address) \
{ \
Xuint32 A66rMask = ((Address) << XSA_CR_CFGADDR_SHIFT) & XSA_CR_CFGADDR_MASK; \
Xuint32 C0ntr0l = XSysAce_mGetControlReg(BaseAddress); \
C0ntr0l &= ~XSA_CR_CFGADDR_MASK; /* clear current address */ \
C0ntr0l |= (A66rMask | XSA_CR_FORCECFGADDR_MASK); \
XSysAce_mSetControlReg((BaseAddress), C0ntr0l); \
}
 
 
/*****************************************************************************/
/**
*
* Request then wait for the MPU lock. This is not a forced lock, so we must
* contend with the configuration controller.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mWaitForLock(BaseAddress) \
{ \
XSysAce_mOrControlReg((BaseAddress), XSA_CR_LOCKREQ_MASK); \
while ((XSysAce_mGetStatusReg(BaseAddress) & XSA_SR_MPULOCK_MASK) == 0); \
}
 
/*****************************************************************************/
/**
*
* Enable ACE controller interrupts.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mEnableIntr(BaseAddress, Mask) \
XSysAce_mOrControlReg((BaseAddress), (Mask));
 
 
/*****************************************************************************/
/**
*
* Disable ACE controller interrupts.
*
* @param BaseAddress is the base address of the device.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mDisableIntr(BaseAddress, Mask) \
XSysAce_mAndControlReg((BaseAddress), ~(Mask));
 
 
/*****************************************************************************/
/**
*
* Is the CompactFlash ready for a command?
*
* @param BaseAddress is the base address of the device.
*
* @return XTRUE if it is ready, XFALSE otherwise.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mIsReadyForCmd(BaseAddress) \
(XSysAce_mGetStatusReg(BaseAddress) & XSA_SR_RDYFORCMD_MASK)
 
 
/*****************************************************************************/
/**
*
* Is the ACE controller locked for MPU access?
*
* @param BaseAddress is the base address of the device.
*
* @return XTRUE if it is locked, XFALSE otherwise.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mIsMpuLocked(BaseAddress) \
(XSysAce_mGetStatusReg(BaseAddress) & XSA_SR_MPULOCK_MASK)
 
 
/*****************************************************************************/
/**
*
* Is the CompactFlash configuration of the target FPGA chain complete?
*
* @param BaseAddress is the base address of the device.
*
* @return XTRUE if it is ready, XFALSE otherwise.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mIsCfgDone(BaseAddress) \
(XSysAce_mGetStatusReg(BaseAddress) & XSA_SR_CFGDONE_MASK)
 
 
/*****************************************************************************/
/**
*
* Have interrupts been enabled by the user? We look for the interrupt reset
* bit to be clear (meaning interrupts are armed, even though none may be
* individually enabled).
*
* @param BaseAddress is the base address of the device.
*
* @return XTRUE if it is enabled, XFALSE otherwise.
*
* @note None.
*
******************************************************************************/
#define XSysAce_mIsIntrEnabled(BaseAddress) \
((XSysAce_mGetControlReg(BaseAddress) & XSA_CR_RESETIRQ_MASK) == 0)
 
 
/************************** Function Prototypes ******************************/
 
int XSysAce_ReadSector(Xuint32 BaseAddress, Xuint32 SectorId,
Xuint8 *BufferPtr);
int XSysAce_WriteSector(Xuint32 BaseAddress, Xuint32 SectorId,
Xuint8 *BufferPtr);
 
/*
* Utility functions to read and write registers and data buffer
*/
Xuint32 XSysAce_RegRead32(Xuint32 Address);
Xuint16 XSysAce_RegRead16(Xuint32 Address);
void XSysAce_RegWrite32(Xuint32 Address, Xuint32 Data);
void XSysAce_RegWrite16(Xuint32 Address, Xuint16 Data);
 
int XSysAce_ReadDataBuffer(Xuint32 BaseAddress, Xuint8 *BufferPtr,
int NumBytes);
int XSysAce_WriteDataBuffer(Xuint32 BaseAddress, Xuint8 *BufferPtr,
int NumBytes);
 
#endif /* end of protection macro */
 
/sysace_v1_00_a/src/xsysace_compactflash.c
0,0 → 1,809
/* $Id: xsysace_compactflash.c,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysace_compactflash.c
*
* Contains functions to reset, read, and write the CompactFlash device via
* the System ACE controller.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rpm 06/17/02 work in progress
* 1.00a ecm 09/17/04 Fixed the endianism issue with the string copies.
* Replaced the ByteCopy with WordCopySwap which
* copies the bytes and swaps to correct the endianism.
* CR 194182
*
* 1.00a ecm 09/27/04 Fixed the lack of reset during read and write in
* L1 functions.
* CR 194423
*
* 1.00a ecm 12/09/04 Removed the above fix, breaks MVL.
* CR 200015
*
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xsysace.h"
#include "xsysace_l.h"
 
/************************** Constant Definitions *****************************/
 
/*
* Indices into the parameter information from the CompactFlash. When the
* user calls XSysAce_IdentifyCF(), the parameter information is read into a
* byte buffer. The byte buffer is then mapped to a XSysAce_CFParameters
* structure using these indices into the byte buffer.
*/
#define XSA_CFPARM_SIGNATURE 0
#define XSA_CFPARM_NUMCYLS 2
#define XSA_CFPARM_RESERVED1 4
#define XSA_CFPARM_NUMHEADS 6
#define XSA_CFPARM_BYTES_TRACK 8
#define XSA_CFPARM_BYTES_SECT 10
#define XSA_CFPARM_SECTS_TRK 12
#define XSA_CFPARM_SECTS_HI 14
#define XSA_CFPARM_SECTS_LO 16
#define XSA_CFPARM_VENDOR1 18
#define XSA_CFPARM_SERIAL_NO 20
#define XSA_CFPARM_BUFFER_TYPE 40
#define XSA_CFPARM_BUFFER_SIZE 42
#define XSA_CFPARM_ECC_BYTES 44
#define XSA_CFPARM_FW_VERSION 46
#define XSA_CFPARM_MODEL_NO 54
#define XSA_CFPARM_MAX_SECTORS 94
#define XSA_CFPARM_DBL_WORD 96
#define XSA_CFPARM_CAPS 98
#define XSA_CFPARM_RESERVED2 100
#define XSA_CFPARM_PIO_MODE 102
#define XSA_CFPARM_DMA_MODE 104
#define XSA_CFPARM_TRANSLATE 106
#define XSA_CFPARM_CURCYLS 108
#define XSA_CFPARM_CURHEADS 110
#define XSA_CFPARM_CURSECTS_TRK 112
#define XSA_CFPARM_CURSECTS 114
#define XSA_CFPARM_MULTIPLE 118
#define XSA_CFPARM_LBA_SECTS 120
#define XSA_CFPARM_RESERVED3 124
#define XSA_CFPARM_SECURITY 256
#define XSA_CFPARM_VENDOR2 258
#define XSA_CFPARM_POWER 320
#define XSA_CFPARM_RESERVED4 322
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
static void WordCopySwap(Xuint8 *SourcePtr, Xuint8 *DestPtr, int NumBytes);
static void FillParam(XSysAce_CFParameters *ParamPtr, Xuint8 *BufPtr);
 
/************************** Variable Definitions *****************************/
 
 
/*****************************************************************************/
/**
*
* Reset the CompactFlash device. This function does not reset the System ACE
* controller. An ATA soft-reset of the CompactFlash is performed.
*
* An MPU lock, obtained using XSysAce_Lock(), must be granted before calling
* this function. If a lock has not been granted, no action is taken and an
* error is returned.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* - XST_SUCCESS if the reset was done successfully
* - XST_SYSACE_NO_LOCK if no MPU lock has yet been granted
* - XST_DEVICE_BUSY if the CompactFlash is not ready for a command
*
* @note
*
* None.
*
******************************************************************************/
XStatus XSysAce_ResetCF(XSysAce *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* If a lock has not been granted, return an error */
if (!XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
return XST_SYSACE_NO_LOCK;
}
 
/* See if the CF is ready for a command */
if (!XSysAce_mIsReadyForCmd(InstancePtr->BaseAddress))
{
return XST_DEVICE_BUSY;
}
 
/*
* If interrupts are enabled, enable the error interrupt. A reset clears
* the error status, so we're going to re-enable the interrupt here so any
* new errors will be caught.
*/
if (XSysAce_mIsIntrEnabled(InstancePtr->BaseAddress))
{
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_ERRORIRQ_MASK);
}
 
/*
* Send the reset command
*/
XSysAce_RegWrite16(InstancePtr->BaseAddress + XSA_SCCR_OFFSET,
XSA_SCCR_RESET_MASK);
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Abort the CompactFlash operation currently in progress.
*
* An MPU lock, obtained using XSysAce_Lock(), must be granted before calling
* this function. If a lock has not been granted, no action is taken and an
* error is returned.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* - XST_SUCCESS if the abort was done successfully
* - XST_SYSACE_NO_LOCK if no MPU lock has yet been granted
* - XST_DEVICE_BUSY if the CompactFlash is not ready for a command
*
* @note
*
* According to the ASIC designer, the abort command has not been well tested.
*
******************************************************************************/
XStatus XSysAce_AbortCF(XSysAce *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* If a lock has not been granted, return an error */
if (!XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
return XST_SYSACE_NO_LOCK;
}
 
/*
* See if the CF is ready for a command
*
* TODO: make sure this check works, or possibly the abort can be done
* if it is not ready for a command (e.g., that's what we're aborting)?
*/
if (!XSysAce_mIsReadyForCmd(InstancePtr->BaseAddress))
{
return XST_DEVICE_BUSY;
}
 
/*
* Send the abort command
*/
XSysAce_RegWrite16(InstancePtr->BaseAddress + XSA_SCCR_OFFSET,
XSA_SCCR_ABORT_MASK);
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Identify the CompactFlash device. Retrieves the parameters for the
* CompactFlash storage device. Note that this is a polled read of one sector
* of data. The data is read from the CompactFlash into a byte buffer, which
* is then copied into the XSysAce_CFParameters structure passed in by the
* user. The copy is necessary since we don't know how the compiler packs
* the XSysAce_CFParameters structure.
*
* An MPU lock, obtained using XSysAce_Lock(), must be granted before calling
* this function. If a lock has not been granted, no action is taken and an
* error is returned.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param ParamPtr is a pointer to a XSysAce_CFParameters structure where the
* information for the CompactFlash device will be stored. See xsysace.h
* for details on the XSysAce_CFParameters structure.
*
* @return
*
* - XST_SUCCESS if the identify was done successfully
* - XST_FAILURE if an error occurs. Use XSysAce_GetErrors() to determine cause.
* - XST_SYSACE_NO_LOCK if no MPU lock has yet been granted
* - XST_DEVICE_BUSY if the CompactFlash is not ready for a command
*
* @note
*
* None.
*
* @internal
*
* The identify command has the same protocol as the read sector command
* according to the CompactFlash specification. However, there is a discepency
* in that same specification on the size of the parameter structure. The word
* addresses defined in the spec indicate the parameter information is a full
* 512 bytes, the same size as a sector. The total bytes defined in the spec,
* however, indicate that the parameter information is only 500 bytes. We
* defined the parameter structure in xsysace.h assuming the parameters are the
* full 512 bytes since that makes sense, and therefore ignored the "Total
* Bytes" column in the spec.
*
* The SectorData variable was made static to avoid putting 512 bytes on the
* stack every time this function is called.
*
******************************************************************************/
XStatus XSysAce_IdentifyCF(XSysAce *InstancePtr, XSysAce_CFParameters *ParamPtr)
{
int NumRead;
Xboolean InterruptsOn;
static Xuint8 SectorData[XSA_CF_SECTOR_SIZE];
 
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(ParamPtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* If a lock has not been granted, return an error */
if (!XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
return XST_SYSACE_NO_LOCK;
}
 
/* See if the CF is ready for a command */
if (!XSysAce_mIsReadyForCmd(InstancePtr->BaseAddress))
{
return XST_DEVICE_BUSY;
}
 
/*
* If interrupts are enabled, we disable them because we want to do this
* identify in polled mode - due to the buffer endian conversion and copy
* that takes place.
*/
InterruptsOn = XSysAce_mIsIntrEnabled(InstancePtr->BaseAddress);
if (InterruptsOn)
{
XSysAce_DisableInterrupt(InstancePtr);
}
 
/*
* Send the identify command
*/
XSysAce_RegWrite16(InstancePtr->BaseAddress + XSA_SCCR_OFFSET,
XSA_SCCR_IDENTIFY_MASK);
 
/* Reset configuration controller (be sure to keep the lock) */
/* This breaks mvl, beware! */
/* XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_CFGRESET_MASK);*/
 
/*
* Read a sector of data from the data buffer. The parameter info is
* the same size as a sector.
*/
NumRead = XSysAce_ReadDataBuffer(InstancePtr->BaseAddress, SectorData,
XSA_CF_SECTOR_SIZE);
 
/* Clear reset of configuration controller */
/* This breaks mvl, beware! */
/*XSysAce_mAndControlReg(InstancePtr->BaseAddress, ~(XSA_CR_CFGRESET_MASK));*/
 
/* If interrupts were on, re-enable interrupts (regardless of error) */
if (InterruptsOn)
{
XSysAce_EnableInterrupt(InstancePtr);
}
 
if (NumRead == 0)
{
/* an error occurred */
return XST_FAILURE;
}
 
/*
* Copy the byte buffer to the parameter structure
*/
FillParam(ParamPtr, SectorData);
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Check to see if the CompactFlash is ready for a command. The CompactFlash
* may delay after one operation before it is ready for the next. This function
* helps the user determine when it is ready before invoking a CompactFlash
* operation such as XSysAce_SectorRead() or XSysAce_SectorWrite();
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* XTRUE if the CompactFlash is ready for a command, and XFALSE otherwise.
*
* @note
*
* None.
*
******************************************************************************/
Xboolean XSysAce_IsCFReady(XSysAce *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
return XSysAce_mIsReadyForCmd(InstancePtr->BaseAddress);
}
 
/*****************************************************************************/
/**
*
* Read at least one sector of data from the CompactFlash. The user specifies
* the starting sector ID and the number of sectors to be read. The minimum unit
* that can be read from the CompactFlash is a sector, which is 512 bytes.
*
* In polled mode, this read is blocking. If there are other tasks in the system
* that must run, it is best to keep the number of sectors to be read to a
* minimum (e.g., 1). In interrupt mode, this read is non-blocking and an event,
* XSA_EVENT_DATA_DONE, is returned to the user in the asynchronous event
* handler when the read is complete. The user must call
* XSysAce_EnableInterrupt() to put the driver/device into interrupt mode.
*
* An MPU lock, obtained using XSysAce_Lock(), must be granted before calling
* this function. If a lock has not been granted, no action is taken and an
* error is returned.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param StartSector is the starting sector ID from where data will be read.
* Sector IDs range from 0 (first sector) to 0x10000000.
* @param NumSectors is the number of sectors to read. The range can be from
* 1 to 256.
* @param BufferPtr is a pointer to a buffer where the data will be stored.
* The user must ensure it is big enough to hold (512 * NumSectors) bytes.
*
* @return
*
* - XST_SUCCESS if the read was successful. In interrupt mode, this does not
* mean the read is complete, only that it has begun. An event is returned
* to the user when the read is complete.
* - XST_SYSACE_NO_LOCK if no MPU lock has yet been granted
* - XST_DEVICE_BUSY if the ACE controller is not ready for a command
* - XST_FAILURE if an error occurred during the read. The user should call
* XSysAce_GetErrors() to determine the cause of the error.
*
* @note
*
* None.
*
* @internal
*
* Polled mode is blocking under the assumption that a single sector can be
* transferred at a very fast rate (>20 Mbps). So, the user can choose to
* transfer only single sectors when in polled mode, thus allowing time for
* other work to be done. The biggest issue is that although data transfer
* rates are high, seek time for CompactFlash cards is slow (5-20 ms on
* average, depending on the type of device). We could move to a non-blocking
* solution that transfers 32 bytes at a time (the entire data buffer) and
* then returns. The user would then need to increment its buffer pointer
* appropriately and call the read/write again. The driver would need some way
* to know not to issue a new command to the CompactFlash, but instead continue
* with the previous command. This can be done either with a NumSectors argument
* of zero to indicate that there is already an operation in progress, or by
* having the driver keep state to know there is an operation in progress. The
* interface for either seems a bit awkward. Also, the hit for seek time needs
* to be taken regardless of the blocking or non-blocking nature of the call, so
* the additional few microseconds to transfer a sector of data seems acceptable.
*
******************************************************************************/
XStatus XSysAce_SectorRead(XSysAce *InstancePtr, Xuint32 StartSector,
int NumSectors, Xuint8 *BufferPtr)
{
Xuint16 SectorCmd;
int BytesToRecv;
 
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(NumSectors > 0 && NumSectors <= (XSA_SCCR_COUNT_MASK + 1));
XASSERT_NONVOID(BufferPtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* If a lock has not been granted, return an error */
if (!XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
return XST_SYSACE_NO_LOCK;
}
 
/* See if the CF is ready for a command */
if (!XSysAce_mIsReadyForCmd(InstancePtr->BaseAddress))
{
return XST_DEVICE_BUSY;
}
 
BytesToRecv = XSA_CF_SECTOR_SIZE * NumSectors;
 
/*
* If in interrupt mode, set up the state variables and enable the
* data-buffer-ready interrupt. This needs to be done before the command
* is sent to the ACE, which will cause the interrupt to occur.
*/
if (XSysAce_mIsIntrEnabled(InstancePtr->BaseAddress))
{
InstancePtr->NumRequested = BytesToRecv;
InstancePtr->NumRemaining = BytesToRecv;
InstancePtr->BufferPtr = BufferPtr;
 
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_DATARDYIRQ_MASK);
}
 
/* Write the sector ID (LBA) */
XSysAce_RegWrite32(InstancePtr->BaseAddress + XSA_MLR_OFFSET, StartSector);
 
/*
* Send the read command for the number of sectors specified
*/
SectorCmd = (NumSectors & XSA_SCCR_COUNT_MASK) | XSA_SCCR_READDATA_MASK;
XSysAce_RegWrite16(InstancePtr->BaseAddress + XSA_SCCR_OFFSET, SectorCmd);
 
/*
* If in polled mode, receive the entire amount requested
*/
if (!XSysAce_mIsIntrEnabled(InstancePtr->BaseAddress))
{
int NumRead;
 
/* Reset configuration controller (be sure to keep the lock) */
/* This breaks mvl, beware! */
/*XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_CFGRESET_MASK);*/
 
NumRead = XSysAce_ReadDataBuffer(InstancePtr->BaseAddress, BufferPtr,
BytesToRecv);
/* Clear reset of configuration controller */
/* This breaks mvl, beware! */
/*XSysAce_mAndControlReg(InstancePtr->BaseAddress, ~(XSA_CR_CFGRESET_MASK));*/
 
if (NumRead != BytesToRecv)
{
/* an error occurred, report this to the user */
return XST_FAILURE;
}
}
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Write data to the CompactFlash. The user specifies the starting sector ID
* and the number of sectors to be written. The minimum unit that can be written
* to the CompactFlash is a sector, which is 512 bytes.
*
* In polled mode, this write is blocking. If there are other tasks in the
* system that must run, it is best to keep the number of sectors to be written
* to a minimum (e.g., 1). In interrupt mode, this write is non-blocking and an
* event, XSA_EVENT_DATA_DONE, is returned to the user in the asynchronous
* event handler when the write is complete. The user must call
* XSysAce_EnableInterrupt() to put the driver/device into interrupt mode.
*
* An MPU lock, obtained using XSysAce_Lock(), must be granted before calling
* this function. If a lock has not been granted, no action is taken and an
* error is returned.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param StartSector is the starting sector ID from where data will be written.
* Sector IDs range from 0 (first sector) to 0x10000000.
* @param NumSectors is the number of sectors to write. The range can be from
* 1 to 256.
* @param BufferPtr is a pointer to the data buffer to be written. This buffer
* must have at least (512 * NumSectors) bytes.
*
* @return
*
* - XST_SUCCESS if the write was successful. In interrupt mode, this does not
* mean the write is complete, only that it has begun. An event is returned
* to the user when the write is complete.
* - XST_SYSACE_NO_LOCK if no MPU lock has yet been granted
* - XST_DEVICE_BUSY if the ACE controller is not ready for a command
* - XST_FAILURE if an error occurred during the write. The user should call
* XSysAce_GetErrors() to determine the cause of the error.
*
* @note
*
* None.
*
* @internal
*
* Polled mode is blocking under the assumption that a single sector can be
* transferred at a very fast rate (>20 Mbps). So, the user can choose to
* transfer only single sectors when in polled mode, thus allowing time for
* other work to be done. The biggest issue is that although data transfer
* rates are high, seek time for CompactFlash cards is slow (5-20 ms on
* average, depending on the type of device). We could move to a non-blocking
* solution that transfers 32 bytes at a time (the entire data buffer) and
* then returns. The user would then need to increment its buffer pointer
* appropriately and call the read/write again. The driver would need some way
* to know not to issue a new command to the CompactFlash, but instead continue
* with the previous command. This can be done either with a NumSectors argument
* of zero to indicate that there is already an operation in progress, or by
* having the driver keep state to know there is an operation in progress. The
* interface for either seems a bit awkward. Also, the hit for seek time needs
* to be taken regardless of the blocking or non-blocking nature of the call, so
* the additional few microseconds to transfer a sector of data seems acceptable.
*
******************************************************************************/
XStatus XSysAce_SectorWrite(XSysAce *InstancePtr, Xuint32 StartSector,
int NumSectors, Xuint8 *BufferPtr)
{
Xuint16 SectorCmd;
int NumSent;
int BytesToSend;
 
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(NumSectors > 0 && NumSectors <= (XSA_SCCR_COUNT_MASK + 1));
XASSERT_NONVOID(BufferPtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* If a lock has not been granted, return an error */
if (!XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
return XST_SYSACE_NO_LOCK;
}
 
/* See if the CF is ready for a command */
if (!XSysAce_mIsReadyForCmd(InstancePtr->BaseAddress))
{
return XST_DEVICE_BUSY;
}
 
/* Write the sector ID (LBA) */
XSysAce_RegWrite32(InstancePtr->BaseAddress + XSA_MLR_OFFSET, StartSector);
 
/*
* Send the write command for the number of sectors specified
*/
SectorCmd = (NumSectors & XSA_SCCR_COUNT_MASK) | XSA_SCCR_WRITEDATA_MASK;
XSysAce_RegWrite16(InstancePtr->BaseAddress + XSA_SCCR_OFFSET, SectorCmd);
 
BytesToSend = XSA_CF_SECTOR_SIZE * NumSectors;
 
/*
* If in interrupt mode, set up the state variables and enable the
* data-buffer-ready interrupt. We do this after the write command above
* is done in order to guarantee that the interrupt occurs only after the
* first data buffer write is done below (an interrupt may or may not occur
* after the write command is issued)
*/
if (XSysAce_mIsIntrEnabled(InstancePtr->BaseAddress))
{
/*
* Set the state variables. We're going to send one data buffer here in
* this routine, so adjust the buffer pointer and number remaining to
* reflect this.
*/
InstancePtr->NumRequested = BytesToSend;
InstancePtr->NumRemaining = BytesToSend - XSA_DATA_BUFFER_SIZE;
InstancePtr->BufferPtr = BufferPtr + XSA_DATA_BUFFER_SIZE;
 
/* Send only one data buffer in interrupt mode */
BytesToSend = XSA_DATA_BUFFER_SIZE;
 
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_DATARDYIRQ_MASK);
}
 
NumSent = XSysAce_WriteDataBuffer(InstancePtr->BaseAddress, BufferPtr,
BytesToSend);
if (NumSent != BytesToSend)
{
/* an error occurred, report this to the user */
return XST_FAILURE;
}
 
return XST_SUCCESS;
}
 
 
/*****************************************************************************/
/**
*
* Get the status of the FAT filesystem on the first valid partition of the
* CompactFlash device such as the boot record and FAT types found.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* A 16-bit mask of status values. These values are defined in xsysace_l.h
* with the prefix XSA_FAT_*.
*
* @note
*
* None.
*
******************************************************************************/
Xuint16 XSysAce_GetFatStatus(XSysAce *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
return XSysAce_RegRead16(InstancePtr->BaseAddress + XSA_FSR_OFFSET);
}
 
/*****************************************************************************/
/**
*
* This bit of ugliness allows us to present a structure to the user. The
* byte buffer which was read from the CompactFlash is converted into the
* XSysAce_CFParameters structure. The byte buffer is accessed by the indices
* of the fields as defined at the top of this file. We do not read from
* CompactFlash directly into the CF Parameter structure because of structure
* packing problems.
*
* Note that we also need to perform endian conversion here since the System
* ACE device gives us little endian data and we're (possibly) on a big endian
* processor.
*
* @param ParamPtr is the structure to fill
* @param BufPtr is the byte buffer containing the CF parameter data
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
static void FillParam(XSysAce_CFParameters *ParamPtr, Xuint8 *BufPtr)
{
Xuint16 HiWord;
Xuint16 LoWord;
 
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_SIGNATURE]),
&ParamPtr->Signature);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_NUMCYLS]),
&ParamPtr->NumCylinders);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_RESERVED1]),
&ParamPtr->Reserved);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_NUMHEADS]),
&ParamPtr->NumHeads);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_BYTES_TRACK]),
&ParamPtr->NumBytesPerTrack);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_BYTES_SECT]),
&ParamPtr->NumBytesPerSector);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_SECTS_TRK]),
&ParamPtr->NumSectorsPerTrack);
 
/* NumSectorsPerCard is stored as two half-words, MSW first */
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_SECTS_HI]),
&HiWord);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_SECTS_LO]),
&LoWord);
ParamPtr->NumSectorsPerCard = ((Xuint32)HiWord << 16) | (Xuint32)LoWord;
 
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_VENDOR1]),
&ParamPtr->VendorUnique);
 
WordCopySwap(&BufPtr[XSA_CFPARM_SERIAL_NO], ParamPtr->SerialNo, 20);
 
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_BUFFER_TYPE]),
&ParamPtr->BufferType);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_BUFFER_SIZE]),
&ParamPtr->BufferSize);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_ECC_BYTES]),
&ParamPtr->NumEccBytes);
 
WordCopySwap(&BufPtr[XSA_CFPARM_FW_VERSION], ParamPtr->FwVersion, 8);
WordCopySwap(&BufPtr[XSA_CFPARM_MODEL_NO], ParamPtr->ModelNo, 40);
 
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_MAX_SECTORS]),
&ParamPtr->MaxSectors);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_DBL_WORD]),
&ParamPtr->DblWord);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_CAPS]),
&ParamPtr->Capabilities);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_RESERVED2]),
&ParamPtr->Reserved2);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_PIO_MODE]),
&ParamPtr->PioMode);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_DMA_MODE]),
&ParamPtr->DmaMode);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_TRANSLATE]),
&ParamPtr->TranslationValid);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_CURCYLS]),
&ParamPtr->CurNumCylinders);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_CURHEADS]),
&ParamPtr->CurNumHeads);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_CURSECTS_TRK]),
&ParamPtr->CurSectorsPerTrack);
XIo_FromLittleEndian32(*((Xuint32 *)&BufPtr[XSA_CFPARM_CURSECTS]),
&ParamPtr->CurSectorsPerCard);
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_MULTIPLE]),
&ParamPtr->MultipleSectors);
XIo_FromLittleEndian32(*((Xuint32 *)&BufPtr[XSA_CFPARM_LBA_SECTS]),
&ParamPtr->LbaSectors);
 
WordCopySwap(&BufPtr[XSA_CFPARM_RESERVED3], ParamPtr->Reserved3, 132);
 
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_SECURITY]),
&ParamPtr->SecurityStatus);
 
WordCopySwap(&BufPtr[XSA_CFPARM_VENDOR2], ParamPtr->VendorUniqueBytes, 62);
 
XIo_FromLittleEndian16(*((Xuint16 *)&BufPtr[XSA_CFPARM_POWER]),
&ParamPtr->PowerDesc);
 
WordCopySwap(&BufPtr[XSA_CFPARM_RESERVED4], ParamPtr->Reserved4, 190);
 
}
 
/*****************************************************************************/
/**
*
* Utility to copy words and swap the endianism on the fly.
*
* @param SourcePtr is a pointer to the source byte buffer
* @param DestPtr is a pointer to the destination byte buffer
* @param NumBytes is the number of bytes to copy
*
* @return
*
* None.
*
* @note
*
* NumBytes should be even but if it isn't, the function increases by 1
* to correct.
*
******************************************************************************/
static void WordCopySwap(Xuint8 *SourcePtr, Xuint8 *DestPtr, int NumBytes)
{
int i;
 
/* make sure the requested length is even, if not, increase by 1 */
 
if ((NumBytes & 0x00000001) != 0)
{
NumBytes += 1;
}
 
for (i=0; i < NumBytes; i+=2)
{
DestPtr[i+1] = SourcePtr[i];
DestPtr[i] = SourcePtr[i+1];
}
}
/sysace_v1_00_a/src/xsysace.h
0,0 → 1,320
/* $Id: xsysace.h,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysace.h
*
* The Xilinx System ACE driver. This driver supports the Xilinx System Advanced
* Configuration Environment (ACE) controller. It currently supports only the
* CompactFlash solution. The driver makes use of the Microprocessor (MPU)
* interface to communicate with the device.
*
* The driver provides a user the ability to access the CompactFlash through
* the System ACE device. The user can read and write CompactFlash sectors,
* identify the flash device, and reset the flash device. Also, the driver
* provides a user the ability to configure FPGA devices by selecting a
* configuration file (.ace file) resident on the CompactFlash, or directly
* configuring the FPGA devices via the MPU port and the configuration JTAG
* port of the controller.
*
* <b>Bus Mode</b>
*
* The System ACE device supports both 8-bit and 16-bit access to its registers.
* The driver defaults to 8-bit access, but can be changed to use 16-bit access
* at compile-time. The compile-time constant XPAR_XSYSACE_MEM_WIDTH must be
* defined equal to 16 to make the driver use 16-bit access. This constant is
* typically defined in xparameters.h.
*
* <b>Endianness</b>
*
* The System ACE device is little-endian. If being accessed by a big-endian
* processor, the endian conversion will be done by the device driver. The
* endian conversion is encapsulated inside the XSysAce_RegRead/Write functions
* so that it can be removed if the endian conversion is moved to hardware.
*
* <b>Hardware Access</b>
*
* The device driver expects the System ACE controller to be a memory-mapped
* device. Access to the System ACE controller is typically achieved through
* the External Memory Controller (EMC) IP core. The EMC is simply a pass-through
* device that allows access to the off-chip System ACE device. There is no
* software-based setup or configuration necessary for the EMC.
*
* The System ACE registers are expected to be byte-addressable. If for some
* reason this is not possible, the register offsets defined in xsysace_l.h must
* be changed accordingly.
*
* <b>Reading or Writing CompactFlash</b>
*
* The smallest unit that can be read from or written to CompactFlash is one
* sector. A sector is 512 bytes. The functions provided by this driver allow
* the user to specify a starting sector ID and the number of sectors to be read
* or written. At most 256 sectors can be read or written in one operation. The
* user must ensure that the buffer passed to the functions is big enough to
* hold (512 * NumSectors), where NumSectors is the number of sectors specified.
*
* <b>Interrupt Mode</b>
*
* By default, the device and driver are in polled mode. The user is required to
* enable interrupts using XSysAce_EnableInterrupt(). In order to use interrupts,
* it is necessary for the user to connect the driver's interrupt handler,
* XSysAce_InterruptHandler(), to the interrupt system of the application. This
* function does not save and restore the processor context. An event handler
* must also be set by the user, using XSysAce_SetEventHandler(), for the driver
* such that the handler is called when interrupt events occur. The handler is
* called from interrupt context and allows application-specific processing to
* be performed.
*
* In interrupt mode, the only available interrupt is data buffer ready, so
* the size of a data transfer between interrupts is 32 bytes (the size of the
* data buffer).
*
* <b>Polled Mode</b>
*
* The sector read and write functions are blocking when in polled mode. This
* choice was made over non-blocking since sector transfer rates are high
* (>20Mbps) and the user can limit the number of sectors transferred in a single
* operation to 1 when in polled mode, plus the API for non-blocking polled
* functions was a bit awkward. Below is some more information on the sector
* transfer rates given the current state of technology (year 2002). Although
* the seek times for CompactFlash cards is high, this average hit needs to be
* taken every time a new read/write operation is invoked by the user. So the
* additional few microseconds to transfer an entire sector along with seeking
* is miniscule.
*
* - Microdrives are slower than CompactFlash cards by a significant factor,
* especially if the MD is asleep.
* - Microdrive:
* - Power-up/wake-up time is approx. 150 to 1000 ms.
* - Average seek time is approx. 15 to 20 ms.
* - CompactFlash:
* - Power-up/reset time is approx. 50 to 400 ms and wake-up time is
* approx. 3 ms.
* - "Seek time" here means how long it takes the internal controller
* to process the command until the sector data is ready for transfer
* by the ACE controller. This time is approx. 2 ms per sector.
*
* - Once the sector data is ready in the CF device buffer (i.e., "seek time" is
* over) the ACE controller can read 2 bytes from the MD/CF device every 11
* clock cycles, assuming no wait cycles happen. For instance, if the clock
* is 33 MHz, then then the max. rate that the ACE controller can transfer is
* 6 MB/sec. However, due to other overhead (e.g., time for data buffer
* transfers over MPU port, etc.), a better estimate is 3-5 MB/sec.
*
* <b>Mutual Exclusion</b>
*
* This driver is not thread-safe. The System ACE device has a single data
* buffer and therefore only one operation can be active at a time. The device
* driver does not prevent the user from starting an operation while a previous
* operation is still in progress. It is up to the user to provide this mutual
* exclusion.
*
* <b>Errors</b>
*
* Error causes are defined in xsysace_l.h using the prefix XSA_ER_*. The
* user can use XSysAce_GetErrors() to retrieve all outstanding errors.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rpm 06/17/02 work in progress
* </pre>
*
******************************************************************************/
 
#ifndef XSYSACE_H /* prevent circular inclusions */
#define XSYSACE_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
#include "xstatus.h"
#include "xsysace_l.h"
 
/************************** Constant Definitions *****************************/
 
/** @name Asynchronous Events
*
* Asynchronous events passed to the event handler when in interrupt mode.
*
* Note that when an error event occurs, the only way to clear this condition
* is to reset the CompactFlash or the System ACE configuration controller,
* depending on where the error occurred. The driver does not reset either
* and leaves this task to the user.
* @{
*/
#define XSA_EVENT_CFG_DONE 1 /**< Configuration of JTAG chain is done */
#define XSA_EVENT_DATA_DONE 2 /**< Data transfer to/from CompactFlash is done */
#define XSA_EVENT_ERROR 3 /**< An error occurred. Use XSysAce_GetErrors()
* to determine the cause of the error(s).
*/
/*@}*/
 
 
/**************************** Type Definitions *******************************/
 
/**
* Typedef for CompactFlash identify drive parameters. Use XSysAce_IdentifyCF()
* to retrieve this information from the CompactFlash storage device.
*/
typedef struct
{
Xuint16 Signature; /**< CompactFlash signature is 0x848a */
Xuint16 NumCylinders; /**< Default number of cylinders */
Xuint16 Reserved;
Xuint16 NumHeads; /**< Default number of heads */
Xuint16 NumBytesPerTrack; /**< Number of unformatted bytes per track */
Xuint16 NumBytesPerSector; /**< Number of unformatted bytes per sector */
Xuint16 NumSectorsPerTrack; /**< Default number of sectors per track */
Xuint32 NumSectorsPerCard; /**< Default number of sectors per card */
Xuint16 VendorUnique; /**< Vendor unique */
Xuint8 SerialNo[20]; /**< ASCII serial number */
Xuint16 BufferType; /**< Buffer type */
Xuint16 BufferSize; /**< Buffer size in 512-byte increments */
Xuint16 NumEccBytes; /**< Number of ECC bytes on R/W Long cmds */
Xuint8 FwVersion[8]; /**< ASCII firmware version */
Xuint8 ModelNo[40]; /**< ASCII model number */
Xuint16 MaxSectors; /**< Max sectors on R/W Multiple cmds */
Xuint16 DblWord; /**< Double Word not supported */
Xuint16 Capabilities; /**< Device capabilities */
Xuint16 Reserved2;
Xuint16 PioMode; /**< PIO data transfer cycle timing mode */
Xuint16 DmaMode; /**< DMA data transfer cycle timing mode */
Xuint16 TranslationValid; /**< Translation parameters are valid */
Xuint16 CurNumCylinders; /**< Current number of cylinders */
Xuint16 CurNumHeads; /**< Current number of heads */
Xuint16 CurSectorsPerTrack; /**< Current number of sectors per track */
Xuint32 CurSectorsPerCard; /**< Current capacity in sectors */
Xuint16 MultipleSectors; /**< Multiple sector setting */
Xuint32 LbaSectors; /**< Number of addressable sectors in LBA mode */
Xuint8 Reserved3[132];
Xuint16 SecurityStatus; /**< Security status */
Xuint8 VendorUniqueBytes[62]; /**< Vendor unique bytes */
Xuint16 PowerDesc; /**< Power requirement description */
Xuint8 Reserved4[190];
 
} XSysAce_CFParameters;
 
 
/**
* Callback when an asynchronous event occurs during interrupt mode.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the upper
* layer when the callback is invoked.
* @param Event is the event that occurred. See xsysace.h and the event
* identifiers prefixed with XSA_EVENT_* for a description of possible
* events.
*/
typedef void (*XSysAce_EventHandler)(void *CallBackRef, int Event);
 
/**
* This typedef contains configuration information for the device.
*/
typedef struct
{
Xuint16 DeviceId; /**< Unique ID of device */
Xuint32 BaseAddress; /**< Register base address */
 
} XSysAce_Config;
 
/**
* The XSysAce driver instance data. The user is required to allocate a
* variable of this type for every System ACE device in the system. A
* pointer to a variable of this type is then passed to the driver API
* functions.
*/
typedef struct
{
Xuint32 BaseAddress; /* Base address of ACE device */
Xuint32 IsReady; /* Device is initialized and ready */
 
/* interrupt-related data */
int NumRequested; /* Number of bytes to read/write */
int NumRemaining; /* Number of bytes left to read/write */
Xuint8 *BufferPtr; /* Buffer being read/written */
XSysAce_EventHandler EventHandler; /* Callback for asynchronous events */
void *EventRef; /* Callback reference */
 
} XSysAce;
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
/*
* Required functions in xsysace.c
*/
XStatus XSysAce_Initialize(XSysAce *InstancePtr, Xuint16 DeviceId);
XStatus XSysAce_Lock(XSysAce *InstancePtr, Xboolean Force);
void XSysAce_Unlock(XSysAce *InstancePtr);
Xuint32 XSysAce_GetErrors(XSysAce *InstancePtr);
XSysAce_Config *XSysAce_LookupConfig(Xuint16 DeviceId);
 
/*
* CompactFlash access functions in xsysace_compactflash.c
*/
XStatus XSysAce_ResetCF(XSysAce *InstancePtr);
XStatus XSysAce_AbortCF(XSysAce *InstancePtr);
XStatus XSysAce_IdentifyCF(XSysAce *InstancePtr,
XSysAce_CFParameters *ParamPtr);
Xboolean XSysAce_IsCFReady(XSysAce *InstancePtr);
XStatus XSysAce_SectorRead(XSysAce *InstancePtr, Xuint32 StartSector,
int NumSectors, Xuint8 *BufferPtr);
XStatus XSysAce_SectorWrite(XSysAce *InstancePtr, Xuint32 StartSector,
int NumSectors, Xuint8 *BufferPtr);
Xuint16 XSysAce_GetFatStatus(XSysAce *InstancePtr);
 
/*
* JTAG configuration interface functions in xsysace_jtagcfg.c
*/
void XSysAce_ResetCfg(XSysAce *InstancePtr);
void XSysAce_SetCfgAddr(XSysAce *InstancePtr, unsigned int Address);
void XSysAce_SetStartMode(XSysAce *InstancePtr, Xboolean ImmedOnReset,
Xboolean SetStart);
Xboolean XSysAce_IsCfgDone(XSysAce *InstancePtr);
Xuint32 XSysAce_GetCfgSector(XSysAce *InstancePtr);
XStatus XSysAce_ProgramChain(XSysAce *InstancePtr, Xuint8 *BufferPtr, int NumBytes);
 
/*
* General interrupt-related functions in xsysace_intr.c
*/
void XSysAce_EnableInterrupt(XSysAce *InstancePtr);
void XSysAce_DisableInterrupt(XSysAce *InstancePtr);
void XSysAce_SetEventHandler(XSysAce *InstancePtr, XSysAce_EventHandler FuncPtr,
void *CallBackRef);
void XSysAce_InterruptHandler(void *InstancePtr); /* interrupt handler */
 
/*
* Diagnostic functions in xsysace_selftest.c
*/
XStatus XSysAce_SelfTest(XSysAce *InstancePtr);
Xuint16 XSysAce_GetVersion(XSysAce *InstancePtr);
 
 
#endif /* end of protection macro */
 
/sysace_v1_00_a/src/xsysace_jtagcfg.c
0,0 → 1,457
/* $Id: xsysace_jtagcfg.c,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysace_jtagcfg.c
*
* Contains functions to control the configuration of the target FPGA chain on
* the System ACE via the JTAG configuration port.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rpm 06/17/02 work in progress
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xsysace.h"
#include "xsysace_l.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
 
/************************** Variable Definitions *****************************/
 
 
/*****************************************************************************/
/**
*
* Reset the JTAG configuration controller. This comprises a reset of the JTAG
* configuration controller and the CompactFlash controller (if it is currently
* being accessed by the configuration controller). Note that the MPU controller
* is not reset, meaning the MPU registers remain unchanged. The configuration
* controller is reset then released from reset in this function.
*
* The CFGDONE status (and therefore interrupt) is cleared when the configuration
* controller is reset. If interrupts have been enabled, we go ahead and enable
* the CFGDONE interrupt here. This means that if and when a configuration
* process starts as a result of this reset, an interrupt will be received when
* it is complete.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* This function is not thread-safe.
*
******************************************************************************/
void XSysAce_ResetCfg(XSysAce *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Reset the configuration controller */
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_CFGRESET_MASK);
 
/*
* If in interrupt mode, enable the CFGDONE and error interrupts.
* A reset clears the CFGDONE and error statuses, so we're going to
* re-enable the interrupts here so any new errors or CFGDONEs will be
* caught.
*/
if (XSysAce_mIsIntrEnabled(InstancePtr->BaseAddress))
{
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_CFGDONEIRQ_MASK |
XSA_CR_ERRORIRQ_MASK);
}
 
/* Release the reset of the configuration controller */
XSysAce_mAndControlReg(InstancePtr->BaseAddress, ~XSA_CR_CFGRESET_MASK);
}
 
/*****************************************************************************/
/**
*
* Select the configuration address (or file) from the CompactFlash to be used
* for configuration of the target FPGA chain.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param Address is the address or file number to be used as the bitstream to
* configure the target FPGA devices. There are 8 possible files, so
* the value of this parameter can range from 0 to 7.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XSysAce_SetCfgAddr(XSysAce *InstancePtr, unsigned int Address)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(Address < 8);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/*
* Set the control register with the address and the bit that forces
* the use of the control register address bits instead of the address
* pins on the device.
*/
XSysAce_mSetCfgAddr(InstancePtr->BaseAddress, Address);
}
 
/*****************************************************************************/
/**
*
* Set the start mode for configuration of the target FPGA chain from
* CompactFlash. The configuration process only starts after a reset. The
* user can indicate that the configuration should start immediately after a
* reset, or the configuration process can be delayed until the user commands
* it to start (using this function). The configuration controller can be
* reset using XSysAce_ResetCfg().
*
* The user can select which configuration file on the CompactFlash to use using
* the XSysAce_SetCfgAddr() function. If the user intends to configure the target
* FPGA chain directly from the MPU port, this function is not needed. Instead,
* the user would simply call XSysAce_ProgramChain().
*
* The user can use XSysAce_IsCfgDone() when in polled mode to determine if
* the configuration is complete. If in interrupt mode, the event
* XSA_EVENT_CFG_DONE will be returned asynchronously to the user when the
* configuration is complete. The user must call XSysAce_EnableInterrupt() to put
* the device/driver into interrupt mode.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param ImmedOnReset can be set to XTRUE to indicate the configuration process
* will start immediately after a reset of the ACE configuration
* controller, or it can be set to XFALSE to indicate the configuration
* process is delayed after a reset until the user starts it (using this
* function).
* @param StartCfg is a boolean indicating whether to start the configuration
* process or not. When ImmedOnReset is set to XTRUE, this value is
* ignored. When ImmedOnReset is set to XFALSE, then this value controls
* when the configuration process is started. When set to XTRUE the
* configuration process starts (assuming a reset of the device has
* occurred), and when set to XFALSE the configuration process does not
* start.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XSysAce_SetStartMode(XSysAce *InstancePtr, Xboolean ImmedOnReset,
Xboolean StartCfg)
{
Xuint32 Control;
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Get the current contents of the control register */
Control = XSysAce_mGetControlReg(InstancePtr->BaseAddress);
 
/*
* Since the user has called this function, we want to tell the ACE
* controller to look at the CFGMODE bit of the control register rather
* than the CFGMODE pin of the device to determine when to start a
* configuration process.
*/
Control |= XSA_CR_FORCECFGMODE_MASK;
 
/* Set or clear the CFGMODE bit of the control register */
if (ImmedOnReset)
{
Control |= XSA_CR_CFGMODE_MASK; /* immediate on reset */
}
else
{
Control &= ~XSA_CR_CFGMODE_MASK; /* wait for start bit */
}
 
 
/* Set or clear the CFGSTART bit of the control register */
if (StartCfg)
{
Control |= XSA_CR_CFGSTART_MASK;
}
else
{
Control &= ~XSA_CR_CFGSTART_MASK;
}
 
XSysAce_mSetControlReg(InstancePtr->BaseAddress, Control);
}
 
 
/*****************************************************************************/
/**
*
* Program the target FPGA chain through the configuration JTAG port. This
* allows the user to program the devices on the target FPGA chain from the MPU
* port instead of from CompactFlash. The user specifies a buffer and the number
* of bytes to write. The buffer should be equivalent to an ACE (.ace) file.
*
* Note that when loading the ACE file via the MPU port, the first sector of the
* ACE file is discarded. The CF filesystem controller in the System ACE device
* knows to skip the first sector when the ACE file comes from the CF, but the
* CF filesystem controller is bypassed when the ACE file comes from the MPU
* port. For this reason, this function skips the first sector of the buffer
* passed in.
*
* In polled mode, the write is blocking. In interrupt mode, the write is
* non-blocking and an event, XSA_EVENT_CFG_DONE, is returned to the user in
* the asynchronous event handler when the configuration is complete.
*
* An MPU lock, obtained using XSysAce_Lock(), must be granted before calling
* this function. If a lock has not been granted, no action is taken and an
* error is returned.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param BufferPtr is a pointer to a buffer that will be used to program
* the configuration JTAG devices.
* @param NumBytes is the number of bytes in the buffer. We assume that there
* is at least one sector of data in the .ace file, which is the
* information sector.
*
* @return
*
* - XST_SUCCESS if the write was successful. In interrupt mode, this does not
* mean the write is complete, only that it has begun. An event is returned
* to the user when the write is complete.
* - XST_SYSACE_NO_LOCK if no MPU lock has yet been granted
* - XST_FAILURE if an error occurred during the write. The user should call
* XSysAce_GetErrors() to determine the cause of the error.
*
* @note
*
* None.
*
* @internal
*
* The System ACE controller has a 32-byte buffer which holds data. The entire
* buffer must be written to ensure that it gets sent to the configuration
* JTAG port. If the number of bytes specified by the user is not a multiple
* of 32, the driver will pad the remaining bytes of the System ACE buffer with
* zeroes in order to write the entire buffer.
*
******************************************************************************/
XStatus XSysAce_ProgramChain(XSysAce *InstancePtr, Xuint8 *BufferPtr,
int NumBytes)
{
Xuint32 ControlMask;
int BytesToSend;
int NumSent;
 
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(BufferPtr != XNULL);
XASSERT_NONVOID(NumBytes > XSA_CF_SECTOR_SIZE);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* If a lock has not been granted, return an error */
if (!XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
return XST_SYSACE_NO_LOCK;
}
 
/*
* Set up the configuration controller to use the MPU port as the
* source of configuration data (instead of the CF). The following
* control flow comes directly from the System ACE specification, except
* the reset was moved to after the other control register bits are set.
* Putting it into reset before the bits are set seemed to produce
* configuration errors occasionally.
*/
ControlMask = XSysAce_mGetControlReg(InstancePtr->BaseAddress);
 
/* Select MPU as the source */
ControlMask |= XSA_CR_CFGSEL_MASK;
XSysAce_mSetControlReg(InstancePtr->BaseAddress, ControlMask);
 
/* Tell controller to wait for start bit from MPU */
ControlMask |= XSA_CR_FORCECFGMODE_MASK;
ControlMask &= ~XSA_CR_CFGMODE_MASK;
XSysAce_mSetControlReg(InstancePtr->BaseAddress, ControlMask);
 
/* Set the start bit */
ControlMask |= XSA_CR_CFGSTART_MASK;
XSysAce_mSetControlReg(InstancePtr->BaseAddress, ControlMask);
 
/* Put the configuration controller into a reset condition */
ControlMask |= XSA_CR_CFGRESET_MASK;
XSysAce_mSetControlReg(InstancePtr->BaseAddress, ControlMask);
 
/* Clear the reset condition, which starts the process */
ControlMask &= ~XSA_CR_CFGRESET_MASK;
XSysAce_mSetControlReg(InstancePtr->BaseAddress, ControlMask);
 
/*
* Set up number of bytes to send. Default to the entire buffer, which
* will be true in polled mode. In interrupt mode, modify this value to
* send only one data buffer of data. Always skip the first sector per
* the comment above.
*/
BytesToSend = NumBytes - XSA_CF_SECTOR_SIZE;
 
/*
* The number of bytes to write depends on interrupt or polled mode
*/
if (XSysAce_mIsIntrEnabled(InstancePtr->BaseAddress))
{
/*
* In interrupt mode, so enable the data-buffer-ready and
* configuration-done interrupts. Also, set up the state variables for
* the interrupt handler to transfer the remaining data after the
* initial write below. We need to write one data buffer here in this
* function in order to cause the data-buffer-ready interrupt to occur
* for subsequent writes.
*/
ControlMask |= XSA_CR_DATARDYIRQ_MASK | XSA_CR_CFGDONEIRQ_MASK;
XSysAce_mSetControlReg(InstancePtr->BaseAddress, ControlMask);
 
/* Send only one data buffer to begin with (if there is that much) */
if (BytesToSend > XSA_DATA_BUFFER_SIZE)
{
BytesToSend = XSA_DATA_BUFFER_SIZE;
}
 
/*
* Setup state variables for the interrupt handler. Skip the first
* sector per the comment above, and also skip the first data buffer
* since it is written below.
*/
InstancePtr->NumRequested = NumBytes - XSA_CF_SECTOR_SIZE;
InstancePtr->BufferPtr = BufferPtr + XSA_CF_SECTOR_SIZE + BytesToSend;
InstancePtr->NumRemaining = NumBytes - XSA_CF_SECTOR_SIZE - BytesToSend;
}
 
NumSent = XSysAce_WriteDataBuffer(InstancePtr->BaseAddress,
BufferPtr + XSA_CF_SECTOR_SIZE,
BytesToSend);
if (NumSent != BytesToSend)
{
/* an error occurred, report this to the user */
return XST_FAILURE;
}
 
/*
* If in polled mode, restore the control register to the way it was
*/
if (!XSysAce_mIsIntrEnabled(InstancePtr->BaseAddress))
{
/*
* Unselect MPU as the source, tell controller to use CFGMODE pin,
* and clear the start bit.
*/
ControlMask &= ~(XSA_CR_CFGSEL_MASK | XSA_CR_FORCECFGMODE_MASK |
XSA_CR_CFGSTART_MASK);
XSysAce_mSetControlReg(InstancePtr->BaseAddress, ControlMask);
}
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Check to see if the configuration of the target FPGA chain is complete. This
* function is typically only used in polled mode. In interrupt mode, an event
* (XSA_EVENT_CFG_DONE) is returned to the user in the asynchronous event
* handler.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* XTRUE if the configuration is complete. XFALSE otherwise.
*
* @note
*
* None.
*
******************************************************************************/
Xboolean XSysAce_IsCfgDone(XSysAce *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Use the layer 0 macro by the same name */
 
return XSysAce_mIsCfgDone(InstancePtr->BaseAddress);
}
 
 
/*****************************************************************************/
/**
*
* Get the sector ID of the CompactFlash sector being used for configuration of
* the target FPGA chain. This sector ID (or logical block address) only affects
* transfers between the ACE configuration logic and the CompactFlash card.
* This function is typically used for debug purposes to determine which sector
* was being accessed when an error occurred.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* The sector ID (logical block address) being used for data transfers between
* the ACE configuration logic and the CompactFlash. Sector IDs range from 0
* to 0x10000000.
*
* @note
*
* None.
*
******************************************************************************/
Xuint32 XSysAce_GetCfgSector(XSysAce *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
return XSysAce_RegRead32(InstancePtr->BaseAddress + XSA_CLR_OFFSET);
}
/sysace_v1_00_a/src/xsysace_g.c
0,0 → 1,29
 
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Driver configuration
*
*******************************************************************/
 
#include "xparameters.h"
#include "xsysace.h"
 
/*
* The configuration table for devices
*/
 
XSysAce_Config XSysAce_ConfigTable[] =
{
{
XPAR_SYSACE_COMPACTFLASH_DEVICE_ID,
XPAR_SYSACE_COMPACTFLASH_BASEADDR
}
};
 
 
/sysace_v1_00_a/src/xsysace_selftest.c
0,0 → 1,152
/* $Id: xsysace_selftest.c,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysace_selftest.c
*
* Contains diagnostic functions for the System ACE device and driver. This
* includes a self-test to make sure communication to the device is possible
* and the ability to retrieve the ACE controller version.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rpm 06/17/02 work in progress
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xsysace.h"
#include "xsysace_l.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
 
/************************** Variable Definitions *****************************/
 
 
/*****************************************************************************/
/**
*
* A self-test that simply proves communication to the ACE controller from the
* device driver by obtaining an MPU lock, verifying it, then releasing it.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* XST_SUCCESS if self-test passes, or XST_FAILURE if an error occurs.
*
* @note
*
* None.
*
******************************************************************************/
XStatus XSysAce_SelfTest(XSysAce *InstancePtr)
{
XStatus Result;
 
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/*
* Grab a lock (expect immediate success)
*/
Result = XSysAce_Lock(InstancePtr, XTRUE);
if (Result != XST_SUCCESS)
{
return Result;
}
 
/*
* Verify the lock was retrieved
*/
if (!XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
return XST_FAILURE;
}
 
/*
* Release the lock
*/
XSysAce_Unlock(InstancePtr);
 
/*
* Verify the lock was released
*/
if (XSysAce_mIsMpuLocked(InstancePtr->BaseAddress))
{
return XST_FAILURE;
}
 
/*
* If there are currently any errors on the device, fail self-test
*/
if (XSysAce_mGetErrorReg(InstancePtr->BaseAddress) != 0)
{
return XST_FAILURE;
}
 
return XST_SUCCESS;
}
 
 
/*****************************************************************************/
/**
*
* Retrieve the version of the System ACE device.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* A 16-bit version where the 4 most significant bits are the major version
* number, the next four bits are the minor version number, and the least
* significant 8 bits are the revision or build number.
*
* @note
*
* None.
*
******************************************************************************/
Xuint16 XSysAce_GetVersion(XSysAce *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
return XSysAce_RegRead16(InstancePtr->BaseAddress + XSA_VR_OFFSET);
}
 
/sysace_v1_00_a/src/xsysace_l.c
0,0 → 1,590
/* $Id: xsysace_l.c,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysace_l.c
*
* This file contains low-level functions to read and write CompactFlash
* sectors and ACE controller registers. These functions can be used when only
* the low-level functionality of the driver is desired. The user would
* typically use the high-level driver functions defined in xsysace.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rpm 06/14/02 work in progress
* 1.00a rpm 09/16/03 Added include of xparameters.h in order to get
* the XPAR_XSYSACE_MEM_WIDTH definition.
* 1.00a rpm 02/17/04 Fixed WriteSector function command
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xparameters.h"
#include "xsysace_l.h"
 
/************************** Constant Definitions *****************************/
 
/*
* Set up the access width of the MPU registers based on compile-time constants.
* If hardware requires 32-bit aligned addresses (XSA_ADDR_ALIGN=4) to access
* the MPU registers, then access all of them as 32 bits. If hardware allows
* 8-bit aligned addresses (XSA_ADDR_ALIGN=1, or not 4) to access the MPU
* registers, access them as 8 or 16 bits depending on the bus mode of the ACE
* controller.
*/
#if (XSA_ADDR_ALIGN == 4)
 
#define XIo_In XIo_In32
#define XIo_Out XIo_Out32
 
#else
 
#if (XPAR_XSYSACE_MEM_WIDTH == 16)
#define XIo_In XIo_In16
#define XIo_Out XIo_Out16
#else /* XPAR_XSYSACE_MEM_WIDTH */
#define XIo_In XIo_In8
#define XIo_Out XIo_Out8
#endif /* XPAR_XSYSACE_MEM_WIDTH */
 
#endif /* (XSA_ADDR_ALIGN == 4) */
 
/**************************** Type Definitions *******************************/
 
/***************** Macros (Inline Functions) Definitions *********************/
 
/************************** Function Prototypes ******************************/
 
/************************** Variable Definitions *****************************/
 
/*****************************************************************************/
/**
*
* Read a 32-bit value from the given address. Based on a compile-time
* constant, do the read in two 16-bit reads or four 8-bit reads.
*
* @param Address is the address to read from.
*
* @return The 32-bit value of the address.
*
* @note No need for endian conversion in 8-bit mode since this function
* gets the bytes into their proper lanes in the 32-bit word.
*
******************************************************************************/
#if (XPAR_XSYSACE_MEM_WIDTH == 16)
Xuint32 XSysAce_RegRead32(Xuint32 Address)
{
Xuint16 Data;
Xuint16 ConvertedData;
Xuint32 Value = 0;
 
/*
* Need to endian convert each 32-bit value. The ACE registers are little-
* endian, so we read the two LSBs first, endian convert, then put them
* in the LSB lanes of the 32-bit word. etc...
*/
Data = (Xuint16)XIo_In(Address);
XIo_FromLittleEndian16(Data, &ConvertedData);
Value = (Xuint32)ConvertedData;
 
Data = (Xuint16)XIo_In(Address + (2 * XSA_ADDR_ALIGN));
XIo_FromLittleEndian16(Data, &ConvertedData);
Value |= ((Xuint32)ConvertedData << 16);
 
return Value;
}
#else
Xuint32 XSysAce_RegRead32(Xuint32 Address)
{
Xuint32 Value = 0;
 
/*
* The ACE registers are little-endian always. This code reads each 8-bit
* register value, in order from LSB to MSB, and shifts it to the correct
* byte lane of the 32-bit word. This code should work on both
* little-endian and big-endian processors.
*/
Value = (Xuint32)XIo_In(Address);
Value |= ((Xuint32)XIo_In(Address + (1 * XSA_ADDR_ALIGN)) << 8);
Value |= ((Xuint32)XIo_In(Address + (2 * XSA_ADDR_ALIGN)) << 16);
Value |= ((Xuint32)XIo_In(Address + (3 * XSA_ADDR_ALIGN)) << 24);
 
return Value;
}
#endif
 
 
/*****************************************************************************/
/**
*
* Read a 16-bit value from the given address. Based on a compile-time
* constant, do the read in one 16-bit read or two 8-bit reads.
*
* @param Address is the address to read from.
*
* @return The 16-bit value of the address.
*
* @note No need for endian conversion in 8-bit mode since this function
* gets the bytes into their proper lanes in the 16-bit word.
*
******************************************************************************/
#if (XPAR_XSYSACE_MEM_WIDTH == 16)
Xuint16 XSysAce_RegRead16(Xuint32 Address)
{
Xuint16 Data;
Xuint16 ConvertedData;
 
/*
* Need to endian convert the 16-bit value. The ACE registers are little-
* endian.
*/
Data = (Xuint16)XIo_In(Address);
XIo_FromLittleEndian16(Data, &ConvertedData);
return ConvertedData;
}
#else
Xuint16 XSysAce_RegRead16(Xuint32 Address)
{
Xuint16 Value = 0;
 
/*
* The ACE registers are little-endian always. This code reads each 8-bit
* register value, in order from LSB to MSB, and shifts it to the correct
* byte lane of the 32-bit word. This code should work on both
* little-endian and big-endian processors.
*/
Value = (Xuint16)XIo_In(Address);
Value |= ((Xuint16)XIo_In(Address + (1 * XSA_ADDR_ALIGN)) << 8);
 
return Value;
}
#endif
 
 
/*****************************************************************************/
/**
*
* Write a 32-bit value to the given address. Based on a compile-time
* constant, do the write in two 16-bit writes or four 8-bit writes.
*
* @param Address is the address to write to.
* @param Data is the value to write
*
* @return None.
*
* @note No need for endian conversion in 8-bit mode since this function
* writes the bytes into their proper lanes based on address.
*
******************************************************************************/
#if (XPAR_XSYSACE_MEM_WIDTH == 16)
void XSysAce_RegWrite32(Xuint32 Address, Xuint32 Data)
{
Xuint16 Hword;
Xuint16 ConvertedData;
 
/*
* The ACE registers are little-endian always. This code takes each 16-bit
* value of the incoming 32-bit word and endian converts it, then writes it
* to the ACE register.
*/
Hword = (Xuint16)Data;
XIo_ToLittleEndian16(Hword, &ConvertedData);
XIo_Out(Address, ConvertedData);
 
Hword = (Xuint16)(Data >> 16);
XIo_ToLittleEndian16(Hword, &ConvertedData);
XIo_Out(Address + (2 * XSA_ADDR_ALIGN), ConvertedData);
}
#else
void XSysAce_RegWrite32(Xuint32 Address, Xuint32 Data)
{
/*
* The ACE registers are little-endian always. This code reads each 8-bit
* register value, in order from LSB to MSB, and shifts it to the correct
* byte lane of the 32-bit word. This code should work on both
* little-endian and big-endian processors.
*/
XIo_Out(Address, (Xuint8)Data);
XIo_Out(Address + (1 * XSA_ADDR_ALIGN), (Xuint8)(Data >> 8));
XIo_Out(Address + (2 * XSA_ADDR_ALIGN), (Xuint8)(Data >> 16));
XIo_Out(Address + (3 * XSA_ADDR_ALIGN), (Xuint8)(Data >> 24));
}
#endif
 
 
/*****************************************************************************/
/**
*
* Write a 16-bit value to the given address. Based on a compile-time
* constant, do the write in one 16-bit write or two 8-bit writes.
*
* @param Address is the address to write to.
* @param Data is the value to write
*
* @return None.
*
* @note No need for endian conversion in 8-bit mode since this function
* writes the bytes into their proper lanes based on address.
*
******************************************************************************/
#if (XPAR_XSYSACE_MEM_WIDTH == 16)
void XSysAce_RegWrite16(Xuint32 Address, Xuint16 Data)
{
Xuint16 ConvertedData;
 
/*
* The ACE registers are little-endian always. This code takes the incoming
* 16-bit and endian converts it, then writes it to the ACE register.
*/
XIo_ToLittleEndian16(Data, &ConvertedData);
XIo_Out(Address, ConvertedData);
}
#else
void XSysAce_RegWrite16(Xuint32 Address, Xuint16 Data)
{
/*
* The ACE registers are little-endian always. This code reads each 8-bit
* register value, in order from LSB to MSB, and shifts it to the correct
* byte lane of the 32-bit word. This code should work on both
* little-endian and big-endian processors.
*/
XIo_Out(Address, (Xuint8)Data);
XIo_Out(Address + (1 * XSA_ADDR_ALIGN), (Xuint8)(Data >> 8));
}
#endif
 
 
/*****************************************************************************/
/**
*
* Read a CompactFlash sector. This is a blocking, low-level function which
* does not return until the specified sector is read.
*
* @param BaseAddress is the base address of the device
* @param SectorId is the id of the sector to read
* @param BufferPtr is a pointer to a buffer where the data will be stored.
*
* @return
*
* The number of bytes read. If this number is not equal to the sector size,
* 512 bytes, then an error occurred.
*
* @note
*
* None.
*
******************************************************************************/
int XSysAce_ReadSector(Xuint32 BaseAddress, Xuint32 SectorId, Xuint8 *BufferPtr)
{
int NumRead;
 
/* Request and wait for the lock */
XSysAce_mWaitForLock(BaseAddress);
 
/* See if the CF is ready for a command */
if (!XSysAce_mIsReadyForCmd(BaseAddress))
{
return 0;
}
 
/* Write the sector ID (LBA) */
XSysAce_RegWrite32(BaseAddress + XSA_MLR_OFFSET, SectorId);
 
/* Send a read command of one sector to the controller */
XSysAce_RegWrite16(BaseAddress + XSA_SCCR_OFFSET,
XSA_SCCR_READDATA_MASK | 1);
 
/* Reset configuration controller (be sure to keep the lock) */
XSysAce_mOrControlReg(BaseAddress, XSA_CR_CFGRESET_MASK);
 
/* Read a sector of data from the data buffer */
NumRead = XSysAce_ReadDataBuffer(BaseAddress, BufferPtr,
XSA_CF_SECTOR_SIZE);
 
/* Clear reset of configuration controller and locks */
XSysAce_mAndControlReg(BaseAddress, ~(XSA_CR_CFGRESET_MASK |
XSA_CR_LOCKREQ_MASK));
 
return NumRead;
}
 
/*****************************************************************************/
/**
*
* Write a CompactFlash sector. This is a blocking, low-level function which
* does not return until the specified sector is written in its entirety.
*
* @param BaseAddress is the base address of the device
* @param SectorId is the id of the sector to write
* @param BufferPtr is a pointer to a buffer used to write the sector.
*
* @return
*
* The number of bytes written. If this number is not equal to the sector size,
* 512 bytes, then an error occurred.
*
* @note
*
* None.
*
******************************************************************************/
int XSysAce_WriteSector(Xuint32 BaseAddress, Xuint32 SectorId, Xuint8 *BufferPtr)
{
int NumSent;
 
/* Get the lock */
XSysAce_mWaitForLock(BaseAddress);
 
/* See if the CF is ready for a command */
if (!XSysAce_mIsReadyForCmd(BaseAddress))
{
return 0;
}
 
/* Write the sector ID (LBA) */
XSysAce_RegWrite32(BaseAddress + XSA_MLR_OFFSET, SectorId);
 
/* Send a write command of one sector to the controller */
XSysAce_RegWrite16(BaseAddress + XSA_SCCR_OFFSET,
XSA_SCCR_WRITEDATA_MASK | 1);
 
/* Reset configuration controller (be sure to keep the lock) */
XSysAce_mOrControlReg(BaseAddress, XSA_CR_CFGRESET_MASK);
 
/* Write a sector of data to the data buffer */
NumSent = XSysAce_WriteDataBuffer(BaseAddress, BufferPtr,
XSA_CF_SECTOR_SIZE);
 
/* Clear reset of configuration controller and locks */
XSysAce_mAndControlReg(BaseAddress, ~(XSA_CR_CFGRESET_MASK |
XSA_CR_LOCKREQ_MASK));
 
return NumSent;
}
 
 
/*****************************************************************************/
/**
*
* Read the specified number of bytes from the data buffer of the ACE
* controller. The data buffer, which is 32 bytes, can only be read two bytes
* at a time. Once the data buffer is read, we wait for it to be filled again
* before reading the next buffer's worth of data.
*
* @param BaseAddress is the base address of the device
* @param BufferPtr is a pointer to a buffer in which to store data.
* @param Size is the number of bytes to read
*
* @return
*
* The total number of bytes read, or 0 if an error occurred.
*
* @note
*
* If Size is not aligned with the size of the data buffer (32 bytes), this
* function will read the entire data buffer, dropping the extra bytes on the
* floor since the user did not request them. This is necessary to get the
* data buffer to be ready again.
*
******************************************************************************/
int XSysAce_ReadDataBuffer(Xuint32 BaseAddress, Xuint8 *BufferPtr, int Size)
{
int DataBytes; /* number of data bytes written */
int BufferBytes;
Xuint16 Data;
 
/*
* Read data two bytes at a time. We need to wait for the data
* buffer to be ready before reading the buffer.
*/
BufferBytes = 0;
for (DataBytes = 0; DataBytes < Size;)
{
/*
* If at any point during this read an error occurs, exit early
*/
if (XSysAce_mGetErrorReg(BaseAddress) != 0)
{
return 0;
}
 
if (BufferBytes == 0)
{
/*
* Wait for CF data buffer to ready, then reset buffer byte count
*/
while ((XSysAce_mGetStatusReg(BaseAddress)
& XSA_SR_DATABUFRDY_MASK) == 0);
 
BufferBytes = XSA_DATA_BUFFER_SIZE;
}
 
/*
* Need to read two bytes. Put the first one in the output buffer
* because if we're here we know one more is needed. Put the second one
* in the output buffer if there is still room, or just drop it on the
* floor if the requested number of bytes have already been read.
*/
Data = XSysAce_RegRead16(BaseAddress + XSA_DBR_OFFSET);
*BufferPtr++ = (Xuint8)Data;
DataBytes++;
 
if (DataBytes < Size)
{
/* Still more room in the output buffer */
*BufferPtr++ = (Xuint8)(Data >> 8);
DataBytes++;
}
 
BufferBytes -= 2;
}
 
/*
* If a complete data buffer was not read, read and ignore the remaining
* bytes
*/
while (BufferBytes != 0)
{
/*
* If at any point during this read an error occurs, exit early
*/
if (XSysAce_mGetErrorReg(BaseAddress) != 0)
{
return 0;
}
 
(void)XSysAce_RegRead16(BaseAddress + XSA_DBR_OFFSET);
BufferBytes -= 2;
}
 
return DataBytes;
}
 
/*****************************************************************************/
/**
*
* Write the specified number of bytes to the data buffer of the ACE controller.
* The data buffer, which is 32 bytes, can only be written two bytes at a time.
* Once the data buffer is written, we wait for it to be empty again before
* writing the next buffer's worth of data. If the size of the incoming buffer
* is not aligned with the System ACE data buffer size (32 bytes), then this
* routine pads out the data buffer with zeros so the entire data buffer is
* written. This is necessary for the ACE controller to process the data buffer.
*
* @param BaseAddress is the base address of the device
* @param BufferPtr is a pointer to a buffer used to write to the controller.
* @param Size is the number of bytes to write
*
* @return
*
* The total number of bytes written (not including pad bytes), or 0 if an
* error occurs.
*
* @note
*
* None.
*
******************************************************************************/
int XSysAce_WriteDataBuffer(Xuint32 BaseAddress, Xuint8 *BufferPtr, int Size)
{
int DataBytes; /* number of data bytes written */
int BufferBytes;
Xuint16 Data;
 
/*
* Write a sector two bytes at a time. We need to wait for the data
* buffer to be ready before writing the buffer.
*/
BufferBytes = 0;
for (DataBytes = 0; DataBytes < Size;)
{
/*
* If at any point during this write an error occurs, exit early
*/
if (XSysAce_mGetErrorReg(BaseAddress) != 0)
{
return 0;
}
 
if (BufferBytes == 0)
{
/*
* Wait for CF read data buffer to ready, then reset buffer byte
* count
*/
while ((XSysAce_mGetStatusReg(BaseAddress)
& XSA_SR_DATABUFRDY_MASK) == 0);
 
BufferBytes = XSA_DATA_BUFFER_SIZE;
}
 
/*
* Need to send two bytes. Grab the first one from the incoming buffer
* because if we're here we know one more exists. Grab the second one
* from the incoming buffer if there are still any bytes remaining, or
* send a pad byte if the incoming buffer has been expired.
*/
Data = *BufferPtr++;
DataBytes++;
 
if (DataBytes < Size)
{
/* Still more data in the incoming buffer */
Data |= ((Xuint16)*BufferPtr++ << 8);
DataBytes++;
}
else
{
/* No more data in the incoming buffer, send a pad byte of 0 */
Data |= ((Xuint16)0 << 8);
}
 
XSysAce_RegWrite16(BaseAddress + XSA_DBR_OFFSET, Data);
 
BufferBytes -= 2;
}
 
/*
* If a complete data buffer was not filled, fill it with pad bytes (zeros)
*/
while (BufferBytes != 0)
{
/*
* If at any point during this write an error occurs, exit early
*/
if (XSysAce_mGetErrorReg(BaseAddress) != 0)
{
return 0;
}
 
XSysAce_RegWrite16(BaseAddress + XSA_DBR_OFFSET, 0);
BufferBytes -= 2;
}
 
return DataBytes;
}
/sysace_v1_00_a/src/xsysace_intr.c
0,0 → 1,418
/* $Id: xsysace_intr.c,v 1.1 2006-06-23 19:03:45 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsysace_intr.c
*
* Contains functions related to System ACE interrupt mode. The driver's
* interrupt handler, XSysAce_InterruptHandler(), must be connected by the
* user to the interrupt controller.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rpm 06/17/02 work in progress
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xsysace.h"
#include "xsysace_l.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Variable Definitions *****************************/
 
 
/************************** Function Prototypes ******************************/
 
static void HandleDataBuffer(XSysAce *InstancePtr, Xuint32 StatusReg);
static void DataComplete(XSysAce *InstancePtr);
 
 
/*****************************************************************************/
/**
*
* Enable System ACE interrupts. There are three interrupts that can be enabled.
* The error interrupt enable serves as the driver's means to determine whether
* interrupts have been enabled or not. The configuration-done interrupt is not
* enabled here, instead it is enabled during a reset - which can cause a
* configuration process to start. The data-buffer-ready interrupt is not enabled
* here either. It is enabled when a read or write operation is started. The
* reason for not enabling the latter two interrupts are because the status bits
* may be set as a leftover of an earlier occurrence of the interrupt.
*
* @param InstancePtr is a pointer to the XSysAce instance to work on.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XSysAce_EnableInterrupt(XSysAce *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* By default, enable only the error interrupt */
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_ERRORIRQ_MASK);
 
/* Clear the reset on the interrupt line if it was in reset */
XSysAce_mAndControlReg(InstancePtr->BaseAddress, ~XSA_CR_RESETIRQ_MASK);
}
 
 
/*****************************************************************************/
/**
*
* Disable all System ACE interrupts and hold the interrupt request line of
* the device in reset.
*
* @param InstancePtr is a pointer to the XSysAce instance that just interrupted.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XSysAce_DisableInterrupt(XSysAce *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
/* Put the interrupt request line in reset */
XSysAce_mOrControlReg(InstancePtr->BaseAddress, XSA_CR_RESETIRQ_MASK);
 
/* Clear the interrupt enable bits */
XSysAce_mAndControlReg(InstancePtr->BaseAddress, ~(XSA_CR_DATARDYIRQ_MASK |
XSA_CR_ERRORIRQ_MASK | XSA_CR_CFGDONEIRQ_MASK));
}
 
 
/*****************************************************************************/
/**
*
* The interrupt handler for the System ACE driver. This handler must be
* connected by the user to an interrupt controller or source. This function
* does not save or restore context.
*
* This function continues reading or writing to the compact flash if such an
* operation is in progress, and notifies the upper layer software through
* the event handler once the operation is complete or an error occurs. On an
* error, any command currently in progress is aborted.
*
* @param InstancePtr is a pointer to the XSysAce instance that just interrupted.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XSysAce_InterruptHandler(void *InstancePtr)
{
Xuint32 StatusReg;
XSysAce *AcePtr = (XSysAce *)InstancePtr;
 
XASSERT_VOID(InstancePtr != XNULL);
 
/*
* Get the status in order to process each interrupt that has occurred
*/
StatusReg = XSysAce_mGetStatusReg(AcePtr->BaseAddress);
 
/*
* Reset the interrupt line to effectively clear the interrupt conditions.
* We need to set the bit to clear the interrupts, then clear the bit so
* that new interrupts can be generated.
*/
XSysAce_mOrControlReg(AcePtr->BaseAddress, XSA_CR_RESETIRQ_MASK);
XSysAce_mAndControlReg(AcePtr->BaseAddress, ~XSA_CR_RESETIRQ_MASK);
 
/*
* Check for data buffer ready, which means an operation (either read or
* write) is in progress.
*/
if (StatusReg & XSA_SR_DATABUFRDY_MASK)
{
/*
* Handles the data buffer, and invokes the callback to the user for
* data transfer completion.
*/
HandleDataBuffer(AcePtr, StatusReg);
}
 
/*
* Check for completion of JTAG configuration and report the event up.
* We only do this if the CFGDONE interrupt is enabled since the CFGDONE
* status only gets cleared when the confguration controller is reset,
* which we do not do unless requested by the user because it may cause
* a configuration process to start. We could have gotten into this
* interrupt handler by another interrupt, yet have a leftover CFGDONE
* status from an earlier configuration process.
*/
if ((StatusReg & XSA_SR_CFGDONE_MASK) &&
(XSysAce_mGetControlReg(AcePtr->BaseAddress) & XSA_CR_CFGDONEIRQ_MASK))
{
/*
* Clear the bit indicating MPU is the source of configuration data
* since we're done configuring from the MPU for now. Also clear the
* force CFGMODE bit and the CFGSTART bit, basically undoing what was
* done in XSysAce_ProgramChain(). Disable the interrupts since the
* CFGDONE status does not get cleared unless a reset occurs - and in
* the meantime we may get into this interrupt handler again.
*/
XSysAce_mAndControlReg(AcePtr->BaseAddress, ~(XSA_CR_CFGSEL_MASK |
XSA_CR_CFGSTART_MASK | XSA_CR_CFGDONEIRQ_MASK |
XSA_CR_DATARDYIRQ_MASK | XSA_CR_FORCECFGMODE_MASK));
 
AcePtr->EventHandler(AcePtr->EventRef, XSA_EVENT_CFG_DONE);
}
 
/*
* Check for errors and report the event (the user is responsible for
* retrieving and interpreting the errors). We only do this if the error
* interrupt is enabled since the error status only gets cleared when the
* CompactFlash or confguration controller is reset, which we do not do
* because it may cause a configuration process to start. We could have
* entered this interrupt handler by another interrupt and have a leftover
* error status from a previous error.
*/
if ((StatusReg & (XSA_SR_CFGERROR_MASK | XSA_SR_CFCERROR_MASK)) &&
(XSysAce_mGetControlReg(AcePtr->BaseAddress) & XSA_CR_ERRORIRQ_MASK))
{
/* Clear the transfer state to effectively abort the operation */
AcePtr->NumRequested = 0;
AcePtr->NumRemaining = 0;
AcePtr->BufferPtr = XNULL;
 
/*
* Disable the error interrupt since the only way to clear the
* error status is to reset the CF or the configuration controller,
* neither of which we want to do here since the consequences may
* be undesirable (i.e., may cause a reconfiguration). The user
* will need to perform the reset based on the error event.
*/
XSysAce_mAndControlReg(AcePtr->BaseAddress, ~XSA_CR_ERRORIRQ_MASK);
 
AcePtr->EventHandler(AcePtr->EventRef, XSA_EVENT_ERROR);
}
}
 
/*****************************************************************************/
/**
*
* Set the callback function for handling events. The upper layer software
* should call this function during initialization. The events are passed
* asynchronously to the upper layer software. The events are described in
* xsysace.h and are named XSA_EVENT_*.
*
* Note that the callback is invoked by the driver within interrupt context, so
* it needs to do its job quickly. If there are potentially slow operations
* within the callback, these should be done at task-level.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param FuncPtr is the pointer to the callback function.
* @param CallBackRef is a reference pointer to be passed back to the upper
* layer.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XSysAce_SetEventHandler(XSysAce *InstancePtr, XSysAce_EventHandler FuncPtr,
void *CallBackRef)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(FuncPtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 
InstancePtr->EventHandler = FuncPtr;
InstancePtr->EventRef = CallBackRef;
}
 
/*****************************************************************************/
/**
*
* Handle a data-buffer-ready interrupt. If we get the interrupt when reading,
* it means there is still data to read since the interrupt does not occur after
* reading the last data buffer. If we get the interrupt when writing, there
* may or may not be data left to write since the interrupt does occur after the
* last data buffer is written.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
* @param StatusReg is the contents of the status register, read at the start
* of the interrupt service routine.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
static void HandleDataBuffer(XSysAce *InstancePtr, Xuint32 StatusReg)
{
/* By default, transfer a whole data buffer */
int BytesToTransfer = XSA_DATA_BUFFER_SIZE;
 
/*
* Check to see if number of bytes remaining is less than the data buffer
* size. If it is, we need to adjust the remaining bytes to transfer.
*/
if (InstancePtr->NumRemaining < XSA_DATA_BUFFER_SIZE)
{
BytesToTransfer = InstancePtr->NumRemaining;
}
 
/*
* Transfer only one data buffer at a time, which is 32 bytes. Note that
* errors will be handled by an error interrupt occurring, so no need to
* check for them here.
*/
if (StatusReg & XSA_SR_DATABUFMODE_MASK)
{
/*
* A write operation in progress, so if there is data remaining then
* write the buffer. If no data is remaining, clean up.
*/
if (InstancePtr->NumRemaining > 0)
{
(void)XSysAce_WriteDataBuffer(InstancePtr->BaseAddress,
InstancePtr->BufferPtr,
BytesToTransfer);
 
/*
* Decrement the number of bytes remaining to be transferred and
* adjust the buffer pointer appropriately.
*/
InstancePtr->NumRemaining -= BytesToTransfer;
InstancePtr->BufferPtr += BytesToTransfer;
}
else
{
/* Done writing data, so clean up */
DataComplete(InstancePtr);
}
}
else
{
/* A read operation in progress, so read the buffer */
(void)XSysAce_ReadDataBuffer(InstancePtr->BaseAddress,
InstancePtr->BufferPtr,
BytesToTransfer);
 
/*
* Decrement the number of bytes remaining to be transferred and
* adjust the buffer pointer appropriately. If it was the last buffer,
* we're done and we can cleanup.
*/
InstancePtr->NumRemaining -= BytesToTransfer;
InstancePtr->BufferPtr += BytesToTransfer;
 
if (InstancePtr->NumRemaining == 0)
{
/* Done reading data, so clean up */
DataComplete(InstancePtr);
}
}
}
 
/*****************************************************************************/
/**
*
* Handle cleanup when a data transfer is complete. This means intializing the
* state variables, disabling the data-buffer-ready interrupt, and sending the
* event to the user.
*
* @param InstancePtr is a pointer to the XSysAce instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
static void DataComplete(XSysAce *InstancePtr)
{
InstancePtr->NumRequested = 0;
InstancePtr->NumRemaining = 0;
InstancePtr->BufferPtr = XNULL;
 
/*
* Disable the data-buffer-ready interrupt. This isn't necessary when
* reading since the DATABUFRDY status bit is cleared by the ACE after
* the last data buffer is read. However, the ACE isn't currently
* smart enough to clear the DATABUFRDY status bit after the last data
* buffer is written during a write operation. So, we need to use the
* enable/disable interrupt bit to control its usefulness.
*/
XSysAce_mAndControlReg(InstancePtr->BaseAddress, ~XSA_CR_DATARDYIRQ_MASK);
 
/*
* The same code is executed for JTAG configuration as well as CompactFlash
* transfers, so we need to distinguish between JTAG config done and CF
* data transfer done. We look at the CFGSEL value in the control register
* to determine if an MPU JTAG config process has just completed. The
* CFG_DONE event is passed up later by the main interrupt handler.
*/
if ((XSysAce_mGetControlReg(InstancePtr->BaseAddress)
& XSA_CR_CFGSEL_MASK) == 0)
{
/* no JTAG configuration in progress */
InstancePtr->EventHandler(InstancePtr->EventRef, XSA_EVENT_DATA_DONE);
}
}
 
/sysace_v1_00_a/src/Makefile
0,0 → 1,28
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
 
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
 
INCLUDEFILES=xsysace.h xsysace_l.h
LIBSOURCES=*.c
OUTS = *.o
 
 
libs:
echo "Compiling sysace"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
 
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
 
clean:
rm -rf ${OUTS}
 
/common_v1_00_a/src/xparameters.h
0,0 → 1,517
/* $Id: xparameters.h,v 1.1 2006-06-23 19:00:01 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xparameters.h
*
* This file contains system parameters for the Xilinx device driver environment.
* It is a representation of the system in that it contains the number of each
* device in the system as well as the parameters and memory map for each
* device. The user can view this file to obtain a summary of the devices in
* their system and the device parameters.
*
* This file may be automatically generated by a design tool such as System
* Generator.
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#ifndef XPARAMETERS_H /* prevent circular inclusions */
#define XPARAMETERS_H /* by using protection macros */
 
/* unifying driver changes
 
added XPAR_INTC_0_ACK_BEFORE, XPAR_INTC_1_ACK_BEFORE
changed XPAR_INTC_MAX_ID to XPAR_INTC_MAX_NUM_INTR_INPUTS
deleted XPAR_INTC_0_MAX_ID, XPAR_INTC_1_MAX_ID
 
*/
 
/************************** Constant Definitions *****************************/
 
/*
* The following constants are for each device.
*
* An instance must exist for each physical device that exists in the system.
* The device IDs in the following constants are unique between all devices to
* allow device IDs to be searched in the future.
*/
 
/*****************************************************************************
*
* System Level defines. These constants are for devices that do not require
* a device driver. Examples of these types of devices include volatile RAM
* devices.
*/
#define XPAR_ZBT_NUM_INSTANCES 1
#define XPAR_ZBT_0_BASE 0x00000000
#define XPAR_ZBT_0_SIZE 0x00100000
 
#define XPAR_SRAM_NUM_INSTANCES 1
#define XPAR_SRAM_0_BASE 0x00100000
#define XPAR_SRAM_0_SIZE 0x00200000
 
#define XPAR_DDR_NUM_INSTANCES 1
#define XPAR_DDR_0_BASE 0xF0000000
#define XPAR_DDR_0_SIZE 0x01000000
 
#define XPAR_CORE_CLOCK_FREQ_HZ 12500000
 
#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ XPAR_CORE_CLOCK_FREQ_HZ
 
/*****************************************************************************
*
* Interrupt Controller (Intc) defines.
* DeviceID starts at 0
*/
#define XPAR_XINTC_NUM_INSTANCES 2 /* Number of instances */
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 31 /* max # inputs of all */
#define XPAR_INTC_SINGLE_BASEADDR 0x70800000 /* low level driver base */
#define XPAR_INTC_SINGLE_DEVICE_ID 0 /* single instance ID */
#define XPAR_INTC_SINGLE_ACK_BEFORE 0xFFFF00FF /* low level driver */
 
#define XPAR_INTC_0_DEVICE_ID 1 /* Device ID for instance */
#define XPAR_INTC_0_ACK_BEFORE 0xFFFF00FF /* Ack timing, before/after */
#define XPAR_INTC_0_BASEADDR 0x70800000 /* Register base address */
 
#define XPAR_INTC_0_UARTLITE_0_VEC_ID 4 /* Interrupt source for vector */
#define XPAR_INTC_0_WDTTB_0_VEC_ID 5 /* Interrupt source for vector */
#define XPAR_INTC_0_WD_0_VEC_ID 6 /* Interrupt source for vector */
#define XPAR_INTC_0_TMRCTR_0_VEC_ID 7 /* Interrupt source for vector */
#define XPAR_INTC_0_SPI_0_VEC_ID 11 /* Interrupt source for vector */
#define XPAR_INTC_0_IIC_0_VEC_ID 12 /* Interrupt source for vector */
#define XPAR_INTC_0_UARTNS550_0_VEC_ID 13 /* Interrupt source for vector */
#define XPAR_INTC_0_UARTNS550_1_VEC_ID 14 /* Interrupt source for vector */
#define XPAR_INTC_0_EMAC_0_VEC_ID 15 /* Interrupt source for vector */
 
#define XPAR_INTC_1_DEVICE_ID 2 /* Device ID for instance */
#define XPAR_INTC_1_ACK_BEFORE 0xFFFF00FF /* Ack timing, before/after */
#define XPAR_INTC_1_BASEADDR 0x70800020 /* Register base address */
 
#define XPAR_INTC_1_OPB_TO_PLB_ERR_VEC_ID 0 /* Interrupt source for vector */
#define XPAR_INTC_1_PLB_TO_OPB_ERR_VEC_ID 1 /* Interrupt source for vector */
 
/*****************************************************************************
*
* Ethernet 10/100 MAC defines.
* DeviceID starts at 10
*/
#define XPAR_XEMAC_NUM_INSTANCES 1 /* Number of instances */
 
#define XPAR_EMAC_0_DEVICE_ID 10 /* Device ID for instance */
#define XPAR_EMAC_0_BASEADDR 0x60000000 /* Device base address */
#define XPAR_EMAC_0_DMA_PRESENT XFALSE /* Does device have DMA? */
#define XPAR_EMAC_0_ERR_COUNT_EXIST XTRUE /* Does device have counters? */
#define XPAR_EMAC_0_MII_EXIST XTRUE /* Does device support MII? */
 
/*****************************************************************************
*
* NS16550 UART defines.
* DeviceID starts at 20
*/
#define XPAR_XUARTNS550_NUM_INSTANCES 1 /* Number of instances */
 
#define XPAR_UARTNS550_0_DEVICE_ID 20 /* Device ID for instance */
#define XPAR_UARTNS550_0_BASEADDR 0xA0010000 /* IPIF base address */
#define XPAR_UARTNS550_0_CLOCK_HZ (66000000L)/* 66 MHz clock */
 
#define XPAR_UARTNS550_1_DEVICE_ID 21 /* Device ID for instance */
#define XPAR_UARTNS550_1_BASEADDR 0xA0000000 /* IPIF base address */
#define XPAR_UARTNS550_1_CLOCK_HZ (66000000L)/* 66 MHz clock */
 
/*****************************************************************************
*
* UartLite defines.
* DeviceID starts at 30
*/
#define XPAR_XUARTLITE_NUM_INSTANCES 1 /* Number of instances */
 
#define XPAR_UARTLITE_0_DEVICE_ID 30 /* Device ID for instance */
#define XPAR_UARTLITE_0_BASEADDR 0xA0020000 /* Device base address */
#define XPAR_UARTLITE_0_BAUDRATE 19200 /* Baud rate */
#define XPAR_UARTLITE_0_USE_PARITY XFALSE /* Parity generator enabled */
#define XPAR_UARTLITE_0_ODD_PARITY XFALSE /* Type of parity generated */
#define XPAR_UARTLITE_0_DATA_BITS 8 /* Data bits */
 
/*****************************************************************************
*
* ATM controller defines.
* DeviceID starts at 40
*/
#define XPAR_XATMC_NUM_INSTANCES 1 /* Number of instances */
 
#define XPAR_ATMC_0_DEVICE_ID 40 /* Device ID for instance */
#define XPAR_ATMC_0_BASEADDR 0x70000000 /* Device base address */
#define XPAR_ATMC_0_DMA_PRESENT XFALSE /* Does device have DMA? */
 
/*****************************************************************************
*
* Serial Peripheral Interface (SPI) defines.
* DeviceID starts at 50
*/
#define XPAR_XSPI_NUM_INSTANCES 2 /* Number of instances */
 
#define XPAR_SPI_0_DEVICE_ID 50 /* Device ID for instance */
#define XPAR_SPI_0_BASEADDR 0x50000000 /* Device base address */
#define XPAR_SPI_0_FIFO_EXIST XTRUE /* Does device have FIFOs? */
#define XPAR_SPI_0_SLAVE_ONLY XFALSE /* Is the device slave only? */
#define XPAR_SPI_0_NUM_SS_BITS 32 /* Number of slave select bits */
 
#define XPAR_SPI_1_DEVICE_ID 51 /* Device ID for instance */
#define XPAR_SPI_1_BASEADDR 0x50000100 /* IPIF base address */
#define XPAR_SPI_1_FIFO_EXIST XTRUE /* Does device have FIFOs? */
#define XPAR_SPI_1_SLAVE_ONLY XFALSE /* Is the device slave only? */
#define XPAR_SPI_1_NUM_SS_BITS 32 /* Number of slave select bits */
 
/*****************************************************************************
*
* OPB Arbiter defines.
* DeviceID starts at 60
*/
#define XPAR_XOPBARB_NUM_INSTANCES 1 /* Number of instances */
 
#define XPAR_OPBARB_0_DEVICE_ID 60 /* Device ID for instance */
#define XPAR_OPBARB_0_BASEADDR 0x80000000 /* Register base address */
#define XPAR_OPBARB_0_NUM_MASTERS 8 /* Number of masters on bus */
 
/*****************************************************************************
*
* Watchdog timer/timebase (WdtTb) defines.
* DeviceID starts at 70
*/
#define XPAR_XWDTTB_NUM_INSTANCES 1 /* Number of instances */
 
#define XPAR_WDTTB_0_DEVICE_ID 70 /* Device ID for instance */
#define XPAR_WDTTB_0_BASEADDR 0x70800040 /* Register base address */
 
/*****************************************************************************
*
* Timer Counter (TmrCtr) defines.
* DeviceID starts at 80
*/
#define XPAR_XTMRCTR_NUM_INSTANCES 2 /* Number of instances */
 
#define XPAR_TMRCTR_0_DEVICE_ID 80 /* Device ID for instance */
#define XPAR_TMRCTR_0_BASEADDR 0x70800100 /* Register base address */
 
/*****************************************************************************
*
* IIC defines.
* DeviceID starts at 90
*/
#define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */
 
#define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */
#define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */
#define XPAR_IIC_0_TEN_BIT_ADR XTRUE /* Supports 10 bit addresses */
 
#define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance */
#define XPAR_IIC_1_BASEADDR 0xA8000000 /* Device base address */
#define XPAR_IIC_1_TEN_BIT_ADR XTRUE /* Supports 10 bit addresses */
 
/*****************************************************************************
*
* Flash defines.
* DeviceID starts at 100
*/
#define XPAR_XFLASH_NUM_INSTANCES 1 /* Number of instances */
#define XPAR_FLASH_INTEL_SUPPORT /* Include intel flash support */
 
#define XPAR_FLASH_0_DEVICE_ID 100 /* Device ID for first instance */
#define XPAR_FLASH_0_BASEADDR 0xFF000000 /* Base address of parts */
#define XPAR_FLASH_0_NUM_PARTS 2 /* Number of parts in array */
#define XPAR_FLASH_0_PART_WIDTH 2 /* Width of each part in bytes */
#define XPAR_FLASH_0_PART_MODE 2 /* Mode of each part in bytes */
 
/*****************************************************************************
*
* GPIO defines.
* DeviceID starts at 110
*/
#define XPAR_XGPIO_NUM_INSTANCES 1
 
#define XPAR_GPIO_0_DEVICE_ID 110 /* Device ID for instance */
#define XPAR_GPIO_0_BASEADDR 0x90000000 /* Register base address */
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0 /* Interrupts supported? */
#define XPAR_GPIO_0_IS_DUAL 0 /* Dual channels supported? */
 
/*****************************************************************************
*
* EMC defines.
* DeviceID starts at 120
*/
#define XPAR_XEMC_NUM_INSTANCES 1
 
#define XPAR_EMC_0_DEVICE_ID 120 /* Device ID for instance */
#define XPAR_EMC_0_BASEADDR 0xE0000000 /* Register base address */
#define XPAR_EMC_0_NUM_BANKS_MEM 3 /* Number of banks */
 
/*****************************************************************************
*
* PLB Arbiter defines.
* DeviceID starts at 130
*/
#define XPAR_XPLBARB_NUM_INSTANCES 1
 
#define XPAR_PLBARB_0_DEVICE_ID 130 /* Device ID for instance */
#define XPAR_PLBARB_0_BASEADDR 0x300 /* Register base address */
#define XPAR_PLBARB_0_NUM_MASTERS 1 /* Number of masters on bus */
 
/*****************************************************************************
*
* PLB To OPB Bridge defines.
* DeviceID starts at 140
*/
#define XPAR_XPLB2OPB_NUM_INSTANCES 1
 
#define XPAR_PLB2OPB_0_DEVICE_ID 140 /* Device ID for instance */
#define XPAR_PLB2OPB_0_DCR_BASEADDR 0x0 /* DCR Register base address */
#define XPAR_PLB2OPB_0_NUM_MASTERS 1 /* Number of masters on bus */
 
 
/*****************************************************************************
*
* OPB To PLB Bridge defines.
* DeviceID starts at 150
*/
#define XPAR_XOPB2PLB_NUM_INSTANCES 1
#define XPAR_XOPB2PLB_ANY_OPB_REG_INTF /* Accessible from OPB, not DCR */
 
#define XPAR_OPB2PLB_0_DEVICE_ID 150 /* Device ID for instance */
#define XPAR_OPB2PLB_0_OPB_BASEADDR 0x0 /* Register base address */
#define XPAR_OPB2PLB_0_DCR_BASEADDR 0x0 /* DCR Register base address */
 
 
/*****************************************************************************
*
* System ACE defines.
* DeviceID starts at 160
*/
#define XPAR_XSYSACE_NUM_INSTANCES 1
 
#define XPAR_SYSACE_0_DEVICE_ID 160 /* Device ID for instance */
#define XPAR_SYSACE_0_BASEADDR 0xCF000000 /* Register base address */
 
 
/*****************************************************************************
*
* HDLC defines.
* DeviceID starts at 170
*/
#define XPAR_XHDLC_NUM_INSTANCES 1
 
#define XPAR_HDLC_0_DEVICE_ID 170 /* Device ID for instance */
#define XPAR_HDLC_0_BASEADDR 0x60010000 /* Register base address */
#define XPAR_HDLC_0_TX_MEM_DEPTH 2048 /* Tx FIFO depth (bytes) */
#define XPAR_HDLC_0_RX_MEM_DEPTH 2048 /* Rx FIFO depth (bytes) */
#define XPAR_HDLC_0_DMA_PRESENT 3 /* DMA SG in hardware */
 
 
/*****************************************************************************
*
* PS2 Reference driver defines.
* DeviceID starts at 180
*/
#define XPAR_XPS2_NUM_INSTANCES 2
 
#define XPAR_PS2_0_DEVICE_ID 180 /* Device ID for instance */
#define XPAR_PS2_0_BASEADDR 0x40010000 /* Register base address */
 
#define XPAR_PS2_1_DEVICE_ID 181 /* Device ID for instance */
#define XPAR_PS2_1_BASEADDR 0x40020000 /* Register base address */
 
/*****************************************************************************
*
* Rapid IO defines.
* DeviceID starts at 190
*/
#define XPAR_XRAPIDIO_NUM_INSTANCES 1
 
#define XPAR_RAPIDIO_0_DEVICE_ID 190 /* Device ID for instance */
#define XPAR_RAPIDIO_0_BASEADDR 0x60000000 /* Register base address */
 
 
/*****************************************************************************
*
* PCI defines.
* DeviceID starts at 200
*/
#define XPAR_XPCI_NUM_INSTANCES 1
#define XPAR_OPB_PCI_1_DEVICE_ID 200
#define XPAR_OPB_PCI_1_BASEADDR 0x86000000
#define XPAR_OPB_PCI_1_HIGHADDR 0x860001FF
#define XPAR_OPB_PCI_1_PCIBAR_0 0x10000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_0 27
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_0 0xF0000000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_0 0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_0 1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_0 1
#define XPAR_OPB_PCI_1_PCIBAR_1 0x3F000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_1 15
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_1 0xC0FF8000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_1 1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_1 1
#define XPAR_OPB_PCI_1_PCIBAR_2 0x5F000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_2 16
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_2 0x00000000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_2 1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_2 1
#define XPAR_OPB_PCI_1_IPIFBAR_0 0x80000000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_0 0x81FFFFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_0 0xF0000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_0 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_0 1
#define XPAR_OPB_PCI_1_IPIFBAR_1 0x82000000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1 0x820007FF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_1 0xCE000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_1 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1 1
#define XPAR_OPB_PCI_1_IPIFBAR_2 0x82320000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2 0x8232FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_2 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_2 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2 1
#define XPAR_OPB_PCI_1_IPIFBAR_3 0x82330000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3 0x8233FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_3 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_3 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_3 0
#define XPAR_OPB_PCI_1_IPIFBAR_4 0x82340000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4 0x8234FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_4 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_4 0
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4 0
#define XPAR_OPB_PCI_1_IPIFBAR_5 0x82350000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5 0x8235FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_5 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_5 1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5 1
#define XPAR_OPB_PCI_1_DMA_BASEADDR 0x87000000
#define XPAR_OPB_PCI_1_DMA_HIGHADDR 0x8700007F
#define XPAR_OPB_PCI_1_DMA_CHAN_TYPE 0
#define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH 11
 
/*****************************************************************************
*
* GEmac defines.
* DeviceID starts at 210
*/
#define XPAR_XGEMAC_NUM_INSTANCES 1
#define XPAR_GEMAC_0_DEVICE_ID 210
#define XPAR_GEMAC_0_BASEADDR 0x61000000
#define XPAR_GEMAC_0_DMA_TYPE 9
#define XPAR_GEMAC_0_MIIM_EXIST 0
#define XPAR_GEMAC_0_INCLUDE_STATS 0
 
 
/*****************************************************************************
*
* Touchscreen defines .
* DeviceID starts at 220
*/
#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
#define XPAR_TOUCHSCREEN_0_DEVICE_ID 220
#define XPAR_TOUCHSCREEN_0_BASEADDR 0x70000000
 
 
/*****************************************************************************
*
* DDR defines .
* DeviceID starts at 230
*/
#define XPAR_XDDR_NUM_INSTANCES 1
#define XPAR_DDR_0_DEVICE_ID 230
#define XPAR_DDR_0_BASEADDR 0
#define XPAR_DDR_0_INTERRUPT_PRESENT 0
 
/*****************************************************************************
*
* EmacLite defines .
* DeviceID starts at 240
*/
#define XPAR_XEMACLITE_NUM_INSTANCES 1
#define XPAR_EMACLITE_0_DEVICE_ID 240
#define XPAR_EMACLITE_0_BASEADDR 0
#define XPAR_EMACLITE_0_TX_PING_PONG 0
#define XPAR_EMACLITE_0_RX_PING_PONG 0
 
/*****************************************************************************
*
* DSDAC defines .
* DeviceID starts at 250
*/
#define XPAR_XDSDAC_NUM_INSTANCES 1
#define XPAR_DSDAC_0_DEVICE_ID 250
#define XPAR_DSDAC_0_BASEADDR 0
 
/*****************************************************************************
*
* DSADC defines .
* DeviceID starts at 260
*/
#define XPAR_XDSADC_NUM_INSTANCES 1
#define XPAR_DSADC_0_DEVICE_ID 260
#define XPAR_DSADC_0_BASEADDR 0
 
/*****************************************************************************
*
* PCI Arbiter defines.
* DeviceID starts at 270
*/
#define XPAR_XPCIARB_NUM_INSTANCES 1
#define XPAR_OPB_PCI_ARBITER_0_DEVICE_ID 270
#define XPAR_OPB_PCI_ARBITER_0_BASEADDR 0
#define XPAR_OPB_PCI_ARBITER_0_NUM_PCI_MSTRS 2
 
/*****************************************************************************
*
* TEMAC defines .
* DeviceID starts at 280
*/
#define XPAR_XTEMAC_NUM_INSTANCES 1
#define XPAR_TEMAC_0_DEVICE_ID 280
#define XPAR_TEMAC_0_BASEADDR 0
#define XPAR_TEMAC_0_DMA_TYPE 3
#define XPAR_TEMAC_0_RDFIFO_DEPTH 131072
#define XPAR_TEMAC_0_WRFIFO_DEPTH 131072
#define XPAR_TEMAC_0_MAC_FIFO_DEPTH 16
#define XPAR_TEMAC_0_TEMAC_DCR_HOST 0
#define XPAR_TEMAC_0_DRE 0
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/xstatus.h
0,0 → 1,350
/* $Id: xstatus.h,v 1.1 2006-06-23 19:00:01 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xstatus.h
*
* This file contains Xilinx software status codes. Status codes have their
* own data type called XStatus. These codes are used throughout the Xilinx
* device drivers.
*
******************************************************************************/
 
#ifndef XSTATUS_H /* prevent circular inclusions */
#define XSTATUS_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
 
/************************** Constant Definitions *****************************/
 
/*********************** Common statuses 0 - 500 *****************************/
 
#define XST_SUCCESS 0L
#define XST_FAILURE 1L
#define XST_DEVICE_NOT_FOUND 2L
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
#define XST_INVALID_VERSION 4L
#define XST_DEVICE_IS_STARTED 5L
#define XST_DEVICE_IS_STOPPED 6L
#define XST_FIFO_ERROR 7L /* an error occurred during an
operation with a FIFO such as
an underrun or overrun, this
error requires the device to
be reset */
#define XST_RESET_ERROR 8L /* an error occurred which requires
the device to be reset */
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
typically requires the device
using the DMA to be reset */
#define XST_NOT_POLLED 10L /* the device is not configured for
polled mode operation */
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
the specified data into */
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
to hold the expected data */
#define XST_NO_DATA 13L /* there was no data available */
#define XST_REGISTER_ERROR 14L /* a register did not contain the
expected value */
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
into the function */
#define XST_NOT_SGDMA 16L /* the device is not configured for
scatter-gather DMA operation */
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
#define XST_NO_CALLBACK 18L /* a callback has not yet been
registered */
#define XST_NO_FEATURE 19L /* device is not configured with
the requested feature */
#define XST_NOT_INTERRUPT 20L /* device is not configured for
interrupt mode operation */
#define XST_DEVICE_BUSY 21L /* device is busy */
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
have maxed out */
#define XST_IS_STARTED 23L /* used when part of device is
already started i.e.
sub channel */
#define XST_IS_STOPPED 24L /* used when part of device is
already stopped i.e.
sub channel */
#define XST_DATA_LOST 26L /* driver defined error */
#define XST_RECV_ERROR 27L /* generic receive error */
#define XST_SEND_ERROR 28L /* generic transmit error */
#define XST_NOT_ENABLED 29L /* a requested service is not
available because it has not
been enabled */
 
/***************** Utility Component statuses 401 - 500 *********************/
 
#define XST_MEMTEST_FAILED 401L /* memory test failed */
 
 
/***************** Common Components statuses 501 - 1000 *********************/
 
/********************* Packet Fifo statuses 501 - 510 ************************/
 
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
was invalid after reset */
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
* empty and full simultaneously
*/
 
/************************** DMA statuses 511 - 530 ***************************/
 
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
failed */
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
was invalid after reset */
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
no buffer descriptors ready
to be processed */
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
the scatter gather list are
being used */
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
descriptor which is to be
copied over in the scatter
list is locked */
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
put into the scatter gather
list to be commited */
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
specified was larger than the
total # of buffer descriptors
in the scatter gather list */
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
already been created */
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
been created */
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
being started was not committed
to the list */
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
has already been used by the
hardware so it can't be reused
*/
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
error */
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
error */
 
/************************** IPIF statuses 531 - 550 ***************************/
 
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
was passed into the function */
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
reset was not valid */
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
status register did not read
back correctly */
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
register did not reset when
acked */
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
register was not updated when
other registers changed */
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
status register did not read
back correctly */
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
did not reset when acked */
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
not updated correctly when other
registers changed */
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
register did not indicate the
expected value */
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
did not indicate the expected
value */
#define XST_IPIF_ERROR 541L /* generic ipif error */
 
/****************** Device specific statuses 1001 - 4095 *********************/
 
/********************* Ethernet statuses 1001 - 1050 *************************/
 
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
* to hold the minimum number of
* buffers or descriptors */
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Adapter is out of buffers */
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid adapter init string */
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
* collision on polled send */
 
/*********************** UART statuses 1051 - 1075 ***************************/
#define XST_UART
 
#define XST_UART_INIT_ERROR 1051L
#define XST_UART_START_ERROR 1052L
#define XST_UART_CONFIG_ERROR 1053L
#define XST_UART_TEST_FAIL 1054L
#define XST_UART_BAUD_ERROR 1055L
#define XST_UART_BAUD_RANGE 1056L
 
 
/************************ IIC statuses 1076 - 1100 ***************************/
 
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
/* general call address */
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
/* value after reset not valid */
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
/* value after reset not valid */
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
/* value after reset not valid */
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
/* value after reset not valid */
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register*/
/* didn't return value written */
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg*/
/* didn't return value written */
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
/* didn't return written value */
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
 
/*********************** ATMC statuses 1101 - 1125 ***************************/
 
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
controller hit the max value
which requires the statistics
to be cleared */
 
/*********************** Flash statuses 1126 - 1150 **************************/
 
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming */
#define XST_FLASH_READY 1127L /* Flash is ready for commands */
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
error. Use XFlash_DeviceControl
to retrieve device specific codes */
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state */
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state */
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
driver */
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
aborted due to a timeout */
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
addressible range */
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
write/erase function with
XFL_NON_BLOCKING_WRITE/ERASE
option cleared */
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
 
/*********************** SPI statuses 1151 - 1175 ****************************/
 
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
* selected */
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only */
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
 
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
 
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
* one master assigned to two or more
* priorities, or one master not
* assigned to any priority
*/
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
* priority levels without first
* suspending the use of priority
* levels
*/
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
* bus parking was not enabled
*/
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
* priority mode to allow the
* priorities to be changed
*/
 
/************************ Intc statuses 1201 - 1225 **************************/
 
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
 
/********************** TmrCtr statuses 1226 - 1250 **************************/
 
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
 
/********************** WdtTb statuses 1251 - 1275 ***************************/
 
#define XST_WDTTB_TIMER_FAILED 1251L
 
/********************** PlbArb statuses 1276 - 1300 **************************/
 
#define XST_PLBARB_FAIL_SELFTEST 1276L
 
/********************** Plb2Opb statuses 1301 - 1325 *************************/
 
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
 
/********************** Opb2Plb statuses 1326 - 1350 *************************/
 
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
 
/********************** SysAce statuses 1351 - 1360 **************************/
 
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
 
/********************** PCI Bridge statuses 1361 - 1375 **********************/
 
#define XST_PCI_INVALID_ADDRESS 1361L
 
/**************************** Type Definitions *******************************/
 
/**
* The status typedef.
*/
typedef Xuint32 XStatus;
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/xbasic_types.h
0,0 → 1,268
/* $Id: xbasic_types.h,v 1.1 2006-06-23 19:00:01 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
* This file contains basic types for Xilinx software IP. These types do not
* follow the standard naming convention with respect to using the component
* name in front of each name because they are considered to be primitives.
*
* @note
*
* This file contains items which are architecture dependent.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rmm 12/14/01 First release
* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab
* compiler warnings
* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
* 1.00a rpm 07/21/04 Added XExceptionHandler typedef for processor exceptions
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
******************************************************************************/
 
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
 
/************************** Constant Definitions *****************************/
 
/** Xboolean true */
#define XTRUE 1
/** Xboolean false */
#define XFALSE 0
 
#ifndef NULL
#define NULL 0
#endif
/** Null */
#define XNULL NULL
 
#define XCOMPONENT_IS_READY 0x11111111 /**< component has been initialized */
#define XCOMPONENT_IS_STARTED 0x22222222 /**< component has been started */
 
/* the following constants and declarations are for unit test purposes and are
* designed to be used in test applications.
*/
#define XTEST_PASSED 0
#define XTEST_FAILED 1
 
#define XASSERT_NONE 0
#define XASSERT_OCCURRED 1
 
extern unsigned int XAssertStatus;
extern void XAssert(char *, int);
 
/**************************** Type Definitions *******************************/
 
/** @name Primitive types
* These primitive types are created for transportability.
* They are dependent upon the target architecture.
* @{
*/
typedef unsigned char Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef unsigned short Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef unsigned long Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision floating point */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
 
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
 
/*@}*/
 
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler)(void *InstancePtr);
 
/**
* This data type defines an exception handler for a processor.
* The argument points to the instance of the component
*/
typedef void (*XExceptionHandler)(void *InstancePtr);
 
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*XAssertCallback)(char* FilenamePtr, int LineNumber);
 
/***************** Macros (Inline Functions) Definitions *********************/
 
/*****************************************************************************/
/**
* Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
 
/*****************************************************************************/
/**
* Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
 
 
#ifndef NDEBUG
 
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do not return anything
* (void). This in conjunction with the XWaitInAssert boolean can be used to
* accomodate tests so that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the XWaitInAssert variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_VOID(expression) \
{ \
if (expression) \
{ \
XAssertStatus = XASSERT_NONE; \
} \
else \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return; \
} \
}
 
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do return a value. This in
* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
* that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_NONVOID(expression) \
{ \
if (expression) \
{ \
XAssertStatus = XASSERT_NONE; \
} \
else \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return 0; \
} \
}
 
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do not
* return anything (void). Use for instances where an assert should always
* occur.
*
* @return Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_VOID_ALWAYS() \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return; \
}
 
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do return
* a value. Use for instances where an assert should always occur.
*
* @return Returns void unless the XWaitInAssert variable is true, in which case
* no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define XASSERT_NONVOID_ALWAYS() \
{ \
XAssert(__FILE__, __LINE__); \
XAssertStatus = XASSERT_OCCURRED; \
return 0; \
}
 
 
#else
 
#define XASSERT_VOID(expression)
#define XASSERT_VOID_ALWAYS()
#define XASSERT_NONVOID(expression)
#define XASSERT_NONVOID_ALWAYS()
#endif
 
/************************** Function Prototypes ******************************/
 
void XAssertSetCallback(XAssertCallback Routine);
void XNullHandler(void *NullParameter);
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/xversion.h
0,0 → 1,91
/* $Id: xversion.h,v 1.1 2006-06-23 19:00:01 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xversion.h
*
* This file contains the interface for the XVersion component. This
* component represents a version ID. It is encapsulated within a component
* so that it's type and implementation can change without affecting users of
* it.
*
* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
* X is the major revision, YY is the minor revision, and Z is the
* compatability revision.
*
* Packed versions are also utilized for the configuration ROM such that
* memory is minimized. A packed version consumes only 16 bits and is
* formatted as follows.
*
* <pre>
* Revision Range Bit Positions
*
* Major Revision 0 - 9 Bits 15 - 12
* Minor Revision 0 - 99 Bits 11 - 5
* Compatability Revision a - z Bits 4 - 0
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
******************************************************************************/
 
#ifndef XVERSION_H /* prevent circular inclusions */
#define XVERSION_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
#include "xstatus.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
/* the following data type is used to hold a null terminated version string
* consisting of the following format, "X.YYX"
*/
typedef Xint8 XVersion[6];
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
void XVersion_UnPack(XVersion *InstancePtr, Xuint16 PackedVersion);
 
XStatus XVersion_Pack(XVersion *InstancePtr, Xuint16 *PackedVersion);
 
Xboolean XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr);
 
void XVersion_ToString(XVersion *InstancePtr, Xint8 *StringPtr);
 
XStatus XVersion_FromString(XVersion *InstancePtr, Xint8 *StringPtr);
 
void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr);
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/xutil_memtest.c
0,0 → 1,1254
/* $Id: xutil_memtest.c,v 1.1 2006-06-23 19:00:01 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xutil_memtest.c
*
* Contains the memory test utility functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 11/01/01 First release
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
*****************************************************************************/
 
/***************************** Include Files ********************************/
#include "xbasic_types.h"
#include "xstatus.h"
#include "xutil.h"
 
/************************** Constant Definitions ****************************/
/************************** Function Prototypes *****************************/
 
static Xuint32 RotateLeft(Xuint32 Input, Xuint8 Width);
 
/* define ROTATE_RIGHT to give access to this functionality */
/* #define ROTATE_RIGHT */
#ifdef ROTATE_RIGHT
static Xuint32 RotateRight(Xuint32 Input, Xuint8 Width);
#endif /* ROTATE_RIGHT*/
 
 
/*****************************************************************************/
/**
*
* Performs a destructive 32-bit wide memory test.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Words is the length of the block.
* @param Pattern is the constant used for the constant pattern test, if 0,
* 0xDEADBEEF is used.
* @param Subtest is the test selected. See xutil.h for possible values.
*
* @return
*
* - XST_MEMTEST_FAILED is returned for a failure
* - XST_SUCCESS is returned for a pass
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
* boundry of a power of two making it more difficult to detect addressing
* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
* problem. Ideally, if large blocks of memory are to be tested, break
* them up into smaller regions of memory to allow the test patterns used
* not to repeat over the region tested.
*
*****************************************************************************/
XStatus XUtil_MemoryTest32(Xuint32 *Addr,Xuint32 Words,Xuint32 Pattern,
Xuint8 Subtest)
{
Xuint32 i;
Xuint32 j;
Xuint32 Val = XUT_MEMTEST_INIT_VALUE;
Xuint32 FirstVal = XUT_MEMTEST_INIT_VALUE;
Xuint32 Word;
 
XASSERT_NONVOID(Words != 0);
XASSERT_NONVOID(Subtest <= XUT_MAXTEST);
 
/*
* Select the proper Subtest
*/
 
 
switch (Subtest)
{
 
case XUT_ALLMEMTESTS:
 
/* this case executes all of the Subtests */
 
/* fall through case statement */
 
case XUT_INCREMENT:
{
 
/*
* Fill the memory with incrementing
* values starting from 'FirstVal'
*/
for (i = 0L; i < Words; i++)
{
Addr[i] = Val;
 
/* write memory location */
 
Val++;
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
 
Val = FirstVal;
 
/*
* Check every word within the Words
* of tested memory and compare it
* with the incrementing reference
* Val
*/
 
for (i = 0L; i < Words; i++)
{
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
 
Val++;
}
 
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
 
} /* end of case 1 */
 
/* fall through case statement */
 
case XUT_WALKONES:
{
/*
* set up to cycle through all possible initial
* test Patterns for walking ones test
*/
 
for (j = 0L; j < 32; j++)
{
/*
* Generate an initial value for walking ones test to test for bad
* data bits
*/
 
Val = 1 << j;
 
/*
* START walking ones test
* Write a one to each data bit indifferent locations
*/
 
for (i = 0L; i < 32; i++)
{
 
/* write memory location */
 
Addr[i] = Val;
Val = (Xuint32) RotateLeft(Val, 32);
 
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = 1 << j;
 
/* Read the values from each location that was written */
 
for (i = 0L; i < 32; i++)
{
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
 
Val = (Xuint32) RotateLeft(Val, 32);
 
}
 
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
 
} /* end of case 2 */
 
/* fall through case statement */
 
case XUT_WALKZEROS:
{
/*
* set up to cycle through all possible
* initial test Patterns for walking zeros test
*/
 
for (j = 0L; j < 32; j++)
{
 
/*
* Generate an initial value for walking ones test to test for
* bad data bits
*/
 
Val = ~(1 << j);
 
/*
* START walking zeros test
* Write a one to each data bit indifferent locations
*/
 
for (i = 0L; i < 32; i++)
{
 
/* write memory location */
 
Addr[i] = Val;
Val = ~((Xuint32) RotateLeft(~Val, 32));
 
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
 
Val = ~(1 << j);
 
/* Read the values from each location that was written */
 
for (i = 0L; i < 32; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
 
Val = ~((Xuint32) RotateLeft(~Val, 32));
 
}
 
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
} /* end of case 3 */
 
/* fall through case statement */
 
case XUT_INVERSEADDR:
{
 
/* Fill the memory with inverse of address */
 
for (i = 0L; i < Words; i++)
{
 
/* write memory location */
 
Val = (Xuint32) (~((Xuint32)(&Addr[i])));
 
Addr[i] = Val;
 
}
 
/*
* Check every word within the Words
* of tested memory
*/
 
for (i = 0L; i < Words; i++)
{
 
/* Read the location */
 
Word = Addr[i];
 
Val = (Xuint32) (~((Xuint32)(&Addr[i])));
 
if ((Word ^ Val) != 0x00000000)
{
return XST_MEMTEST_FAILED;
}
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
 
} /* end of case 4 */
 
 
/* fall through case statement */
 
case XUT_FIXEDPATTERN:
{
 
/*
* Generate an initial value for
* memory testing
*/
 
if (Pattern == 0)
{
Val = 0xDEADBEEF;
 
}
else
{
Val = Pattern;
 
}
 
/*
* Fill the memory with fixed pattern
*/
 
for (i = 0L; i < Words; i++)
{
/* write memory location */
 
Addr[i] = Val;
 
}
 
/*
* Check every word within the Words
* of tested memory and compare it
* with the fixed pattern
*/
 
for (i = 0L; i < Words; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
} /* end of case 5 */
 
/* this break is for the prior fall through case statements */
 
break ;
 
default:
{
return XST_MEMTEST_FAILED;
}
 
} /* end of switch */
 
/* Successfully passed memory test ! */
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Performs a destructive 16-bit wide memory test.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Words is the length of the block.
* @param Pattern is the constant used for the constant pattern test, if 0,
* 0xDEADBEEF is used.
* @param Subtest is the test selected. See xutil.h for possible values.
*
* @return
*
* - XST_MEMTEST_FAILED is returned for a failure
* - XST_SUCCESS is returned for a pass
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
* boundry of a power of two making it more difficult to detect addressing
* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
* problem. Ideally, if large blocks of memory are to be tested, break
* them up into smaller regions of memory to allow the test patterns used
* not to repeat over the region tested.
*
*****************************************************************************/
XStatus XUtil_MemoryTest16(Xuint16 *Addr,Xuint32 Words, Xuint16 Pattern,
Xuint8 Subtest)
{
Xuint32 i;
Xuint32 j;
Xuint16 Val= XUT_MEMTEST_INIT_VALUE;
Xuint16 FirstVal= XUT_MEMTEST_INIT_VALUE;
Xuint16 Word;
 
XASSERT_NONVOID(Words != 0);
XASSERT_NONVOID(Subtest <= XUT_MAXTEST);
 
/*
* selectthe proper Subtest(s)
*/
 
switch (Subtest)
{
 
case XUT_ALLMEMTESTS:
 
/* this case executes all of the Subtests */
 
/* fall through case statement */
 
case XUT_INCREMENT:
{
 
/*
* Fill the memory with incrementing
* values starting from 'FirstVal'
*/
for (i = 0L; i < Words; i++)
{
/* write memory location */
 
Addr[i] = Val;
 
Val++;
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
 
Val = FirstVal;
 
/*
* Check every word within the Words
* of tested memory and compare it
* with the incrementing reference
* Val
*/
 
for (i = 0L; i < Words; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
Val++;
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
} /* end of case 1 */
 
/* fall through case statement */
 
case XUT_WALKONES:
{
/*
* set up to cycle through all possible initial test
* Patterns for walking ones test
*/
 
for (j = 0L; j < 16; j++)
{
/*
* Generate an initial value for walking ones test to test for bad
* data bits
*/
 
Val = 1 << j;
 
/*
* START walking ones test
* Write a one to each data bit indifferent locations
*/
 
for (i = 0L; i < 16; i++)
{
 
/* write memory location */
 
Addr[i] = Val;
 
Val = (Xuint16) RotateLeft(Val, 16);
 
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
 
Val = 1 << j;
 
/* Read the values from each location that was written */
 
for (i = 0L; i < 16; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
 
Val = (Xuint16) RotateLeft(Val, 16);
 
}
 
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
 
} /* end of case 2 */
 
/* fall through case statement */
 
case XUT_WALKZEROS:
{
/*
* set up to cycle through all possible initial
* test Patterns for walking zeros test
*/
 
for (j = 0L; j < 16; j++)
{
 
/*
* Generate an initial value for walking ones
* test to test for bad
* data bits
*/
 
Val = ~(1 << j);
 
/*
* START walking zeros test
* Write a one to each data bit indifferent locations
*/
 
for (i = 0L; i < 16; i++)
{
 
 
/* write memory location */
 
Addr[i] = Val;
Val = ~((Xuint16) RotateLeft(~Val, 16));
 
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
 
Val = ~(1 << j);
 
/* Read the values from each location that was written */
 
for (i = 0L; i < 16; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
 
Val = ~((Xuint16) RotateLeft(~Val, 16));
 
}
 
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
} /* end of case 3 */
 
/* fall through case statement */
 
case XUT_INVERSEADDR:
{
 
/* Fill the memory with inverse of address */
 
for (i = 0L; i < Words; i++)
{
/* write memory location */
 
Val = (Xuint16) (~((Xuint32)(&Addr[i])));
Addr[i] = Val;
 
}
 
/*
* Check every word within the Words
* of tested memory
*/
 
for (i = 0L; i < Words; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
Val = (Xuint16) (~((Xuint32)(&Addr[i])));
 
if ((Word ^ Val) != 0x0000)
{
return XST_MEMTEST_FAILED;
}
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
 
} /* end of case 4 */
 
 
/* fall through case statement */
 
case XUT_FIXEDPATTERN:
{
 
/*
* Generate an initial value for
* memory testing
*/
 
if (Pattern == 0)
{
Val = 0xDEAD;
 
}
else
{
Val = Pattern;
 
}
 
/*
* Fill the memory with fixed pattern
*/
 
for (i = 0L; i < Words; i++)
{
 
/* write memory location */
 
Addr[i] = Val;
 
}
 
/*
* Check every word within the Words
* of tested memory and compare it
* with the fixed pattern
*/
 
for (i = 0L; i < Words; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
} /* end of case 5 */
 
/* this break is for the prior fall through case statements */
 
break ;
 
default:
{
return XST_MEMTEST_FAILED;
}
 
} /* end of switch */
 
/* Successfully passed memory test ! */
 
return XST_SUCCESS;
}
 
 
/*****************************************************************************/
/**
*
* Performs a destructive 8-bit wide memory test.
*
* @param Addr is a pointer to the region of memory to be tested.
* @param Words is the length of the block.
* @param Pattern is the constant used for the constant pattern test, if 0,
* 0xDEADBEEF is used.
* @param Subtest is the test selected. See xutil.h for possible values.
*
* @return
*
* - XST_MEMTEST_FAILED is returned for a failure
* - XST_SUCCESS is returned for a pass
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
* boundry of a power of two making it more difficult to detect addressing
* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
* problem. Ideally, if large blocks of memory are to be tested, break
* them up into smaller regions of memory to allow the test patterns used
* not to repeat over the region tested.
*
*****************************************************************************/
XStatus XUtil_MemoryTest8(Xuint8 *Addr,Xuint32 Words, Xuint8 Pattern,
Xuint8 Subtest)
{
Xuint32 i;
Xuint32 j;
Xuint8 Val= XUT_MEMTEST_INIT_VALUE;
Xuint8 FirstVal= XUT_MEMTEST_INIT_VALUE;
Xuint8 Word;
 
XASSERT_NONVOID(Words != 0);
XASSERT_NONVOID(Subtest <= XUT_MAXTEST);
 
/*
* select the proper Subtest(s)
*/
 
switch (Subtest)
{
 
case XUT_ALLMEMTESTS:
 
/* this case executes all of the Subtests */
 
/* fall through case statement */
 
case XUT_INCREMENT:
{
 
/*
* Fill the memory with incrementing
* values starting from 'FirstVal'
*/
for (i = 0L; i < Words; i++)
{
 
/* write memory location */
 
Addr[i] = Val;
Val++;
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
 
Val = FirstVal;
 
/*
* Check every word within the Words
* of tested memory and compare it
* with the incrementing reference
* Val
*/
 
for (i = 0L; i < Words; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
Val++;
}
 
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
 
} /* end of case 1 */
 
/* fall through case statement */
 
case XUT_WALKONES:
{
/*
* set up to cycle through all possible initial
* test Patterns for walking ones test
*/
 
for (j = 0L; j < 8; j++)
{
/*
* Generate an initial value for walking ones test to test
* for bad data bits
*/
 
Val = 1 << j;
 
/*
* START walking ones test
* Write a one to each data bit indifferent locations
*/
 
for (i = 0L; i < 8; i++)
{
 
/* write memory location */
 
Addr[i] = Val;
Val = (Xuint8) RotateLeft(Val, 8);
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
Val = 1 << j;
 
/* Read the values from each location that was written */
 
for (i = 0L; i < 8; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
 
Val = (Xuint8) RotateLeft(Val, 8);
 
}
 
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
 
} /* end of case 2 */
 
/* fall through case statement */
 
case XUT_WALKZEROS:
{
/*
* set up to cycle through all possible initial test
* Patterns for walking zeros test
*/
 
for (j = 0L; j < 8; j++)
{
 
/*
* Generate an initial value for walking ones test to test
* for bad data bits
*/
 
Val = ~(1 << j);
 
/*
* START walking zeros test
* Write a one to each data bit indifferent locations
*/
 
for (i = 0L; i < 8; i++)
{
 
 
/* write memory location */
 
Addr[i] = Val;
Val = ~((Xuint8) RotateLeft(~Val, 8));
 
}
 
/*
* Restore the reference 'Val' to the
* initial value
*/
 
Val = ~(1 << j);
 
/* Read the values from each location that was written */
 
for (i = 0L; i < 8; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
 
Val = ~((Xuint8) RotateLeft(~Val, 8));
 
}
 
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
} /* end of case 3 */
 
/* fall through case statement */
 
case XUT_INVERSEADDR:
{
 
/* Fill the memory with inverse of address */
 
for (i = 0L; i < Words; i++)
{
 
/* write memory location */
 
Val = (Xuint8) (~((Xuint32)(&Addr[i])));
Addr[i] = Val;
 
}
 
/*
* Check every word within the Words
* of tested memory
*/
 
for (i = 0L; i < Words; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
Val = (Xuint8) (~((Xuint32)(&Addr[i])));
 
if ((Word ^ Val) != 0x00)
{
return XST_MEMTEST_FAILED;
}
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
 
} /* end of case 4 */
 
 
/* fall through case statement */
 
case XUT_FIXEDPATTERN:
{
 
/*
* Generate an initial value for
* memory testing
*/
 
if (Pattern == 0)
{
Val = 0xA5;
 
}
else
{
Val = Pattern;
 
}
 
/*
* Fill the memory with fixed pattern
*/
 
for (i = 0L; i < Words; i++)
{
 
/* write memory location */
 
Addr[i] = Val;
 
}
 
/*
* Check every word within the Words
* of tested memory and compare it
* with the fixed pattern
*/
 
for (i = 0L; i < Words; i++)
{
 
/* read memory location */
 
Word = Addr[i];
 
if (Word != Val)
{
return XST_MEMTEST_FAILED;
}
}
 
if (Subtest != XUT_ALLMEMTESTS)
{
return XST_SUCCESS;
}
 
} /* end of case 5 */
 
/* this break is for the prior fall through case statements */
 
break ;
 
default:
{
return XST_MEMTEST_FAILED;
}
 
} /* end of switch */
 
/* Successfully passed memory test ! */
 
return XST_SUCCESS;
}
 
 
/*****************************************************************************/
/**
*
* Rotates the provided value to the left one bit position
*
* @param Input is value to be rotated to the left
* @param Width is the number of bits in the input data
*
* @return
*
* The resulting unsigned long value of the rotate left
*
* @note
*
* None.
*
*****************************************************************************/
static Xuint32 RotateLeft(Xuint32 Input, Xuint8 Width)
{
Xuint32 Msb;
Xuint32 ReturnVal;
Xuint32 WidthMask;
Xuint32 MsbMask;
 
/*
* set up the WidthMask and the MsbMask
*/
 
MsbMask = 1 << (Width-1);
 
WidthMask = (MsbMask << 1) - 1;
 
/*
* set the width of the Input to the correct width
*/
 
Input = Input & WidthMask;
 
Msb = Input & MsbMask;
 
ReturnVal = Input << 1;
 
if (Msb != 0x00000000)
{
ReturnVal = ReturnVal | 0x00000001;
}
 
ReturnVal = ReturnVal & WidthMask;
 
return (ReturnVal);
 
}
 
#ifdef ROTATE_RIGHT
/*****************************************************************************/
/**
*
* Rotates the provided value to the right one bit position
*
* @param Input is value to be rotated to the right
* @param Width is the number of bits in the input data
*
* @return
*
* The resulting Xuint32 value of the rotate right
*
* @note
*
* None.
*
*****************************************************************************/
static Xuint32 RotateRight(Xuint32 Input, Xuint8 Width)
{
Xuint32 Lsb;
Xuint32 ReturnVal;
Xuint32 WidthMask;
Xuint32 MsbMask;
 
/*
* set up the WidthMask and the MsbMask
*/
 
MsbMask = 1 << (Width-1);
 
WidthMask = (MsbMask << 1) - 1;
 
/*
* set the width of the Input to the correct width
*/
 
Input = Input & WidthMask;
 
ReturnVal = Input >> 1;
 
Lsb = Input & 0x00000001;
 
if (Lsb != 0x00000000)
{
ReturnVal = ReturnVal | MsbMask;
}
 
ReturnVal = ReturnVal & WidthMask;
 
return (ReturnVal);
 
}
#endif /* ROTATE_RIGHT */
 
/common_v1_00_a/src/xenv_linux.h
0,0 → 1,181
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_linux.h
*
* Defines common services specified by xenv.h. Some of these services are
* defined as not performing any action. The implementation of these services
* are left to the user.
*
* @note
*
* This file is not intended to be included directly by driver code. Instead,
* the generic xenv.h file is intended to be included by driver code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ch 10/24/02 First release
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
*
******************************************************************************/
 
#ifndef XENV_LINUX_H /* prevent circular inclusions */
#define XENV_LINUX_H /* by using protection macros */
 
/***************************** Include Files *********************************/
#include "sleep.h"
 
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None.
*
* @note
*
* Signature: void XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
{ \
char *Dest = (char*)(DestPtr); \
char *Src = (char*)(SrcPtr); \
unsigned BytesLeft = (Bytes); \
\
while (BytesLeft--) *Dest++ = *Src++; \
}
 
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None.
*
* @note
*
* Signature: void XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
{ \
char *Dest = (char*)(DestPtr); \
char c = (Data); \
unsigned BytesLeft = (Bytes); \
\
while (BytesLeft--) *Dest++ = c; \
}
 
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef int XENV_TIME_STAMP;
 
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
 
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
 
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
 
/*****************************************************************************/
/**
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XENV_USLEEP(delay) \
{ \
usleep(delay); \
}
 
 
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/xenv_none.h
0,0 → 1,179
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_none.h
*
* Defines common services specified by xenv.h. Some of these services are
* defined as not performing any action. The implementation of these services
* are left to the user.
*
* @note
*
* This file is not intended to be included directly by driver code. Instead,
* the generic xenv.h file is intended to be included by driver code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/21/02 First release
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
*
******************************************************************************/
 
#ifndef XENV_NONE_H /* prevent circular inclusions */
#define XENV_NONE_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None.
*
* @note
*
* Signature: void XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
{ \
char *Dest = (char*)(DestPtr); \
char *Src = (char*)(SrcPtr); \
unsigned BytesLeft = (Bytes); \
\
while (BytesLeft--) *Dest++ = *Src++; \
}
 
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None.
*
* @note
*
* Signature: void XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
{ \
char *Dest = (char*)(DestPtr); \
char c = (Data); \
unsigned BytesLeft = (Bytes); \
\
while (BytesLeft--) *Dest++ = c; \
}
 
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef int XENV_TIME_STAMP;
 
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
 
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
 
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
 
/*****************************************************************************/
/**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay is the number of microseconds to delay.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XENV_USLEEP(delay)
 
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/xenv.h
0,0 → 1,169
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
 
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
 
/*
* Select which target environment we are operating under
*/
 
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
 
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
 
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
 
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
 
/* No environment selected */
#else
#include "xenv_none.h"
#endif
 
 
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
 
/**************************** Type Definitions *******************************/
 
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
 
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
 
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
 
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
 
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/xenv_vxworks.h
0,0 → 1,185
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_vxworks.h
*
* Defines common services that are typically found in a VxWorks target
* environment.
*
* @note
*
* This file is not intended to be included directly by driver code. Instead,
* the generic xenv.h file is intended to be included by driver code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a xd 11/03/04 Improved support for doxygen.
* rmm 09/13/03 CR 177068: Fix compiler warning in XENV_MEM_FILL
* rmm 10/24/02 Added XENV_USLEEP macro
* 1.00a rmm 07/16/01 First release
* </pre>
*
*
******************************************************************************/
 
#ifndef XENV_VXWORKS_H /* prevent circular inclusions */
#define XENV_VXWORKS_H /* by using protection macros */
 
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "vxWorks.h"
#include "vxLib.h"
#include <string.h>
 
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None.
*
* @note
*
* Signature: void XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
{ \
void *Dest = (DestPtr); \
void *Src = (SrcPtr); \
unsigned LengthBytes = (Bytes); \
\
memcpy(Dest, Src, (size_t)LengthBytes); \
}
 
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None.
*
* @note
*
* Signature: void XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
{ \
void *Dest = (DestPtr); \
unsigned LengthBytes = (Bytes); \
\
memset(Dest, (int)Data, (size_t)LengthBytes); \
}
 
#if (CPU_FAMILY==PPC)
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef struct
{
Xuint32 TimeBaseUpper;
Xuint32 TimeBaseLower;
} XENV_TIME_STAMP;
#endif
 
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr) \
{ \
vxTimeBaseGet((UINT32*)&(StampPtr)->TimeBaseUpper, \
(UINT32*)&(StampPtr)->TimeBaseLower); \
}
 
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note None.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
 
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* None.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
 
/*****************************************************************************/
/**
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#define XENV_USLEEP(delay) sysUsDelay(delay)
 
 
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/xutil.h
0,0 → 1,151
/* $Id: xutil.h,v 1.1 2006-06-23 19:00:01 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xutil.h
*
* This file contains utility functions such as memory test functions.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* Subtest descriptions:
* <pre>
* XUT_ALLMEMTESTS:
* Runs all of the following tests
*
* XUT_INCREMENT:
* Incrementing Value Test.
* This test starts at 'XUT_MEMTEST_INIT_VALUE' and uses the incrementing
* value as the test value for memory.
*
* XUT_WALKONES:
* Walking Ones Test.
* This test uses a walking '1' as the test value for memory.
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
*
* XUT_WALKZEROS:
* Walking Zero's Test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*
* XUT_INVERSEADDR:
* Inverse Address Test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* XUT_FIXEDPATTERN:
* Fixed Pattern Test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
* </pre>
*
* <i>WARNING</i>
*
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
*
* The address, Addr, provided to the memory tests is not checked for
* validity except for the XNULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
* boundry of a power of two making it more difficult to detect addressing
* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
* problem. Ideally, if large blocks of memory are to be tested, break
* them up into smaller regions of memory to allow the test patterns used
* not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 11/01/01 First release
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
******************************************************************************/
 
#ifndef XUTIL_H /* prevent circular inclusions */
#define XUTIL_H /* by using protection macros */
 
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xstatus.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
/* xutil_memtest defines */
 
#define XUT_MEMTEST_INIT_VALUE 1
 
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XUT_ALLMEMTESTS 0
#define XUT_INCREMENT 1
#define XUT_WALKONES 2
#define XUT_WALKZEROS 3
#define XUT_INVERSEADDR 4
#define XUT_FIXEDPATTERN 5
#define XUT_MAXTEST XUT_FIXEDPATTERN
/* @} */
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
/* xutil_memtest prototypes */
 
XStatus XUtil_MemoryTest32(Xuint32 *Addr, Xuint32 Words, Xuint32 Pattern,
Xuint8 Subtest);
XStatus XUtil_MemoryTest16(Xuint16 *Addr, Xuint32 Words, Xuint16 Pattern,
Xuint8 Subtest);
XStatus XUtil_MemoryTest8(Xuint8 *Addr, Xuint32 Words, Xuint8 Pattern,
Xuint8 Subtest);
 
 
#endif /* end of protection macro */
 
/common_v1_00_a/src/Makefile
0,0 → 1,28
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
 
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I${INCLUDEDIR}
 
OUTS = *.o
 
LIBSOURCES=*.c
INCLUDEFILES=xbasic_types.h xenv.h xenv_none.h xenv_vxworks.h xstatus.h xutil.h xversion.h
 
libs:
echo "Compiling common"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
 
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
 
clean:
rm -rf $(OUTS)
 
/common_v1_00_a/src/xbasic_types.c
0,0 → 1,138
/* $Id $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002-2003 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.c
*
* This file contains basic functions for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
* 1.00a xd 11/03/04 Improved support for doxygen.
* </pre>
*
******************************************************************************/
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
 
/************************** Constant Definitions *****************************/
 
/**************************** Type Definitions *******************************/
 
/***************** Macros (Inline Functions) Definitions *********************/
 
/************************** Variable Definitions *****************************/
 
/**
* This variable allows testing to be done easier with asserts. An assert
* sets this variable such that a driver can evaluate this variable
* to determine if an assert occurred.
*/
unsigned int XAssertStatus;
 
/**
* This variable allows the assert functionality to be changed for testing
* such that it does not wait infinitely. Use the debugger to disable the
* waiting during testing of asserts.
*/
Xboolean XWaitInAssert = XTRUE;
 
/* The callback function to be invoked when an assert is taken */
static XAssertCallback XAssertCallbackRoutine = (XAssertCallback)XNULL;
 
/************************** Function Prototypes ******************************/
 
/*****************************************************************************/
/**
*
* Implements assert. Currently, it calls a user-defined callback function
* if one has been set. Then, it potentially enters an infinite loop depending
* on the value of the XWaitInAssert variable.
*
* @param File is the name of the filename of the source
* @param Line is the linenumber within File
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XAssert(char *File, int Line)
{
/* if the callback has been set then invoke it */
if (XAssertCallbackRoutine != XNULL)
{
(*XAssertCallbackRoutine)(File, Line);
}
 
/* if specified, wait indefinitely such that the assert will show up
* in testing
*/
while (XWaitInAssert)
{
}
}
 
/*****************************************************************************/
/**
*
* Sets up a callback function to be invoked when an assert occurs. If there
* was already a callback installed, then it is replaced.
*
* @param Routine is the callback to be invoked when an assert is taken
*
* @return None.
*
* @note This function has no effect if NDEBUG is set
*
******************************************************************************/
void XAssertSetCallback(XAssertCallback Routine)
{
XAssertCallbackRoutine = Routine;
}
 
 
/*****************************************************************************/
/**
*
* Null handler function. This follows the XInterruptHandler signature for
* interrupt handlers. It can be used to assign a null handler (a stub) to an
* interrupt controller vector table.
*
* @param NullParameter is an arbitrary void pointer and not used.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XNullHandler(void *NullParameter)
{
}
 
/common_v1_00_a/src/xversion.c
0,0 → 1,347
/* $Id: xversion.c,v 1.1 2006-06-23 19:00:01 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xversion.c
*
* This file contains the implementation of the XVersion component. This
* component represents a version ID. It is encapsulated within a component
* so that it's type and implementation can change without affecting users of
* it.
*
* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
* X is the major revision, YY is the minor revision, and Z is the
* compatability revision.
*
* Packed versions are also utilized for the configuration ROM such that
* memory is minimized. A packed version consumes only 16 bits and is
* formatted as follows.
*
* <pre>
* Revision Range Bit Positions
*
* Major Revision 0 - 9 Bits 15 - 12
* Minor Revision 0 - 99 Bits 11 - 5
* Compatability Revision a - z Bits 4 - 0
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a xd 11/03/04 Improved support for doxygen.
</pre>
*
******************************************************************************/
 
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
#include "xversion.h"
 
/************************** Constant Definitions *****************************/
 
/* the following constants define the masks and shift values to allow the
* revisions to be packed and unpacked, a packed version is packed into a 16
* bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the
* major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability
* revision
*/
#define XVE_MAJOR_SHIFT_VALUE 12
#define XVE_MINOR_ONLY_MASK 0x0FE0
#define XVE_MINOR_SHIFT_VALUE 5
#define XVE_COMP_ONLY_MASK 0x001F
 
/* the following constants define the specific characters of a version string
* for each character of the revision, a version string is in the following
* format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor
* revision (00 - 99), and Z is the compatability revision (a - z)
*/
#define XVE_MAJOR_CHAR 0 /* major revision 0 - 9 */
#define XVE_MINOR_TENS_CHAR 2 /* minor revision tens 0 - 9 */
#define XVE_MINOR_ONES_CHAR 3 /* minor revision ones 0 - 9 */
#define XVE_COMP_CHAR 4 /* compatability revision a - z */
#define XVE_END_STRING_CHAR 5
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
static Xboolean IsVersionStringValid(Xint8* StringPtr);
 
/*****************************************************************************/
/**
*
* Unpacks a packed version into the specified version. Versions are packed
* into the configuration ROM to reduce the amount storage. A packed version
* is a binary format as oppossed to a non-packed version which is implemented
* as a string.
*
* @param InstancePtr points to the version to unpack the packed version into.
* @param PackedVersion contains the packed version to unpack.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XVersion_UnPack(XVersion *InstancePtr, Xuint16 PackedVersion)
{
/* not implemented yet since CROM related */
}
 
/*****************************************************************************/
/**
*
* Packs a version into the specified packed version. Versions are packed into
* the configuration ROM to reduce the amount storage.
*
* @param InstancePtr points to the version to pack.
* @param PackedVersionPtr points to the packed version which will receive
* the new packed version.
*
* @return
*
* A status, XST_SUCCESS, indicating the packing was accomplished
* successfully, or an error, XST_INVALID_VERSION, indicating the specified
* input version was not valid such that the pack did not occur
* <br><br>
* The packed version pointed to by PackedVersionPtr is modified with the new
* packed version if the status indicates success.
*
* @note
*
* None.
*
******************************************************************************/
XStatus XVersion_Pack(XVersion *InstancePtr, Xuint16 *PackedVersionPtr)
{
/* not implemented yet since CROM related */
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Determines if two versions are equal.
*
* @param InstancePtr points to the first version to be compared.
* @param VersionPtr points to a second version to be compared.
*
* @return
*
* XTRUE if the versions are equal, XFALSE otherwise.
*
* @note
*
* None.
*
******************************************************************************/
Xboolean XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr)
{
Xuint8 *Version1 = (Xuint8 *)InstancePtr;
Xuint8 *Version2 = (Xuint8 *)VersionPtr;
int Index;
 
/* assert to verify input arguments */
 
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(VersionPtr != XNULL);
 
/* check each byte of the versions to see if they are the same,
* return at any point a byte differs between them
*/
for (Index = 0; Index < sizeof(XVersion); Index++)
{
if (Version1[Index] != Version2[Index])
{
return XFALSE;
}
}
 
/* No byte was found to be different between the versions, so indicate
* the versions are equal
*/
return XTRUE;
}
 
/*****************************************************************************/
/**
*
* Converts a version to a null terminated string.
*
* @param InstancePtr points to the version to convert.
* @param StringPtr points to the string which will be the result of the
* conversion. This does not need to point to a null terminated
* string as an input, but must point to storage which is an adequate
* amount to hold the result string.
*
* @return
*
* The null terminated string is inserted at the location pointed to by
* StringPtr if the status indicates success.
*
* @note
*
* It is necessary for the caller to have already allocated the storage to
* contain the string. The amount of memory necessary for the string is
* specified in the version header file.
*
******************************************************************************/
void XVersion_ToString(XVersion *InstancePtr, Xint8 *StringPtr)
{
/* assert to verify input arguments */
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(StringPtr != XNULL);
 
/* since version is implemented as a string, just copy the specified
* input into the specified output
*/
XVersion_Copy(InstancePtr, (XVersion *)StringPtr);
}
 
/*****************************************************************************/
/**
*
* Initializes a version from a null terminated string. Since the string may not
* be a format which is compatible with the version, an error could occur.
*
* @param InstancePtr points to the version which is to be initialized.
* @param StringPtr points to a null terminated string which will be
* converted to a version. The format of the string must match the
* version string format which is X.YYX where X = 0 - 9, YY = 00 - 99,
* Z = a - z.
*
* @return
*
* A status, XST_SUCCESS, indicating the conversion was accomplished
* successfully, or XST_INVALID_VERSION indicating the version string format
* was not valid.
*
* @note
*
* None.
*
******************************************************************************/
XStatus XVersion_FromString(XVersion *InstancePtr, Xint8 *StringPtr)
{
/* assert to verify input arguments */
 
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(StringPtr != XNULL);
 
/* if the version string specified is not valid, return an error */
 
if (!IsVersionStringValid(StringPtr))
{
return XST_INVALID_VERSION;
}
 
/* copy the specified string into the specified version and indicate the
* conversion was successful
*/
XVersion_Copy((XVersion *)StringPtr, InstancePtr);
 
return XST_SUCCESS;
}
 
/*****************************************************************************/
/**
*
* Copies the contents of a version to another version.
*
* @param InstancePtr points to the version which is the source of data for
* the copy operation.
* @param VersionPtr points to another version which is the destination of
* the copy operation.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr)
{
Xuint8 *Source = (Xuint8 *)InstancePtr;
Xuint8 *Destination = (Xuint8 *)VersionPtr;
int Index;
 
/* assert to verify input arguments */
 
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(VersionPtr != XNULL);
 
/* copy each byte of the source version to the destination version */
 
for (Index = 0; Index < sizeof(XVersion); Index++)
{
Destination[Index] = Source[Index];
}
}
 
/*****************************************************************************/
/**
*
* Determines if the specified version is valid.
*
* @param StringPtr points to the string to be validated.
*
* @return
*
* XTRUE if the version string is a valid format, XFALSE otherwise.
*
* @note
*
* None.
*
******************************************************************************/
static Xboolean IsVersionStringValid(Xint8* StringPtr)
{
/* if the input string is not a valid format, "X.YYZ" where X = 0 - 9,
* YY = 00 - 99, and Z = a - z, then indicate it's not valid
*/
if ((StringPtr[XVE_MAJOR_CHAR] < '0') ||
(StringPtr[XVE_MAJOR_CHAR] > '9') ||
(StringPtr[XVE_MINOR_TENS_CHAR] < '0') ||
(StringPtr[XVE_MINOR_TENS_CHAR] > '9') ||
(StringPtr[XVE_MINOR_ONES_CHAR] < '0') ||
(StringPtr[XVE_MINOR_ONES_CHAR] > '9') ||
(StringPtr[XVE_COMP_CHAR] < 'a') ||
(StringPtr[XVE_COMP_CHAR] > 'z'))
{
return XFALSE;
}
 
return XTRUE;
}
 
/standalone_v1_00_a/src/microblaze_exceptions_g.c
0,0 → 1,17
 
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Exception Handler Table for MicroBlaze Processor
*
*******************************************************************/
 
#include "microblaze_exceptions_i.h"
#include "xparameters.h"
 
 
/standalone_v1_00_a/src/microblaze_update_dcache.s
0,0 → 1,76
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_update_dcache.s
# Date : 2003, September 24
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Update dcache on the microblaze.
# Takes in three parameters
# r5 : Cache Tag Line
# r6 : Cache Data
# r7 : Lock/Valid information
# Bit 30 is Lock [ 1 indicates locked ]
# Bit 31 is Valid [ 1 indicates valid ]
#
# --------------------------------------------------------------
# | Lock | Valid | Effect
# --------------------------------------------------------------
# | 0 | 0 | Invalidate Cache
# | 0 | 1 | Valid, but unlocked cacheline
# | 1 | 0 | Invalidate Cache, No effect of lock
# | 1 | 1 | Valid cache. Locked to a
# | | | particular addrees
# --------------------------------------------------------------
#
# $Id: microblaze_update_dcache.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_update_dcache
.ent microblaze_update_dcache
.align 2
microblaze_update_dcache:
 
#Read the MSR register into a temp register
mfs r18, rmsr
 
#Clear the dcache enable bit to disable the cache
# Register r10,r18 are volatile registers and hence do not need to be saved before use
andi r10, r18, ~128
mts rmsr, r10
 
# Update the lock and valid info
andi r5,r5,0xfffffffc
or r5,r5,r7
# Update dcache
wdc r5,r6
 
#Return
rtsd r15, 8
 
# Restore the MSR back
mts rmsr,r18
.end microblaze_update_dcache
 
/standalone_v1_00_a/src/microblaze_interrupt_handler.c
0,0 → 1,108
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_interrupt_handler.c,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
////////////////////////////////////////////////////////////////////////////////
 
/*****************************************************************************/
/**
*
* @file microblaze_interrupt_handler.c
*
* This file contains the standard interrupt handler for the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
 
 
/***************************** Include Files *********************************/
 
#include "microblaze_interrupts_i.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
void __interrupt_handler () __attribute__ ((interrupt_handler));
 
/************************** Variable Definitions *****************************/
 
extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
/*****************************************************************************/
/**
*
* This function is the standard interrupt handler used by the MicroBlaze processor.
* It saves all volatile registers, calls the users top level interrupt handler.
* When this returns, it restores all registers, and returns using a rtid instruction.
*
* @param
*
* None
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void __interrupt_handler(void)
{
/* The compiler saves all volatiles and the MSR */
MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef);
/* The compiler restores all volatiles and MSR, and returns from interrupt */
}
 
/****************************************************************************//*****************************************************************************/
/**
*
* Registers a top-level interrupt handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
 
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
{
MB_InterruptVectorTable.Handler = Handler;
MB_InterruptVectorTable.CallBackRef = DataPtr;
}
 
/standalone_v1_00_a/src/config.make
0,0 → 1,3
LIBSOURCES = *.s *.c *.S
PROFILE_ARCH_OBJS = profile_mcount_mb.o
LIBS = standalone_libs
/standalone_v1_00_a/src/microblaze_init_icache_range.s
0,0 → 1,64
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_init_icache_range.s
# Date : 2003, September 24
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Update icache on the microblaze.
# Takes in two parameters
# r5 : Cache Base Address
# (start address in the cache where invalidation begins)
# r6 : Size of Cache to be invalidated
#
# $Id: microblaze_init_icache_range.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_init_icache_range
.ent microblaze_init_icache_range
.align 2
microblaze_init_icache_range:
 
# Read the MSR register into a temp register
mfs r9, rmsr
 
# Clear the icache enable bit to disable the cache
# Register r10,r18 are volatile registers and hence do not need to be saved before use
andi r10, r9, ~32
mts rmsr, r10
 
## Start the loop
add r6,r5,r6 # One address beyond last address
L_start:
cmp r18,r5,r6
bleid r18, L_done # Jump out of the loop if done
addi r6,r6,-4 # Decrement the addrees by 4 [ delay slot]
brid L_start # Branch to the beginning of the loop
wic r6,r0 # Invalidate the Cache [ delay slot]
L_done:
# Return
rtsd r15, 8
 
# Restore the MSR back
mts rmsr,r9
.end microblaze_init_icache_range
 
/standalone_v1_00_a/src/microblaze_exception_handler.c
0,0 → 1,82
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_exception_handler.c,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
////////////////////////////////////////////////////////////////////////////////
 
/*****************************************************************************/
/**
*
* @file microblaze_exception_handler.c
*
* This file contains exception handler registration routines for
* the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 06/24/04 First release
* </pre>
*
******************************************************************************/
 
 
/***************************** Include Files *********************************/
 
#include "microblaze_exceptions_i.h"
 
/************************** Constant Definitions *****************************/
 
 
/**************************** Type Definitions *******************************/
 
 
/***************** Macros (Inline Functions) Definitions *********************/
 
 
/************************** Function Prototypes ******************************/
 
/************************** Variable Definitions *****************************/
extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
/****************************************************************************/
 
/*****************************************************************************/
/**
*
* Registers an exception handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param ExceptionId is the id of the exception to register this handler
* for.
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr)
{
MB_ExceptionVectorTable[ExceptionId - 1].Handler = Handler;
MB_ExceptionVectorTable[ExceptionId - 1].CallBackRef = DataPtr;
}
 
/standalone_v1_00_a/src/microblaze_interrupts_i.h
0,0 → 1,54
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_interrupts_i.h,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
////////////////////////////////////////////////////////////////////////////////
 
/*****************************************************************************/
/**
*
* @file microblaze_interrupts_i.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xintc.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
 
#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
 
typedef struct
{
XInterruptHandler Handler;
void *CallBackRef;
} MB_InterruptVectorTableEntry;
 
 
#endif /* end of protection macro */
/standalone_v1_00_a/src/microblaze_exceptions_g.h
0,0 → 1,13
 
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Exception Handling Header for MicroBlaze Processor
*
*******************************************************************/
 
/standalone_v1_00_a/src/microblaze_enable_dcache.s
0,0 → 1,53
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_dcache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable dcache on the microblaze.
#
# $Id: microblaze_enable_dcache.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_enable_dcache
.ent microblaze_enable_dcache
.align 2
microblaze_enable_dcache:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 128
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_dcache
 
/standalone_v1_00_a/src/microblaze_update_icache.s
0,0 → 1,74
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_update_icache.s
# Date : 2003, September 24
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Update icache on the microblaze.
# Takes in three parameters
# r5 : Cache Tag Line
# r6 : Cache Data
# r7 : Lock/Valid information
# Bit 30 is Lock [ 1 indicates locked ]
# Bit 31 is Valid [ 1 indicates valid ]
#
# --------------------------------------------------------------
# | Lock | Valid | Effect
# --------------------------------------------------------------
# | 0 | 0 | Invalidate Cache
# | 0 | 1 | Valid, but unlocked cacheline
# | 1 | 0 | Invalidate Cache, No effect of lock
# | 1 | 1 | Valid cache. Locked to a
# | | | particular addrees
# --------------------------------------------------------------
#
# $Id: microblaze_update_icache.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_update_icache
.ent microblaze_update_icache
.align 2
microblaze_update_icache:
 
# Read the MSR register into a temp register
mfs r18, rmsr
 
# Clear the icache enable bit to disable the cache
# Register r10,r18 are volatile registers and hence do not need to be saved before use
andi r10, r18, ~32
mts rmsr, r10
 
# Update the lock and valid info
andi r5,r5,0xfffffffc
or r5,r5,r7
 
# Update icache
wic r5,r6
 
# Return
rtsd r15, 8
 
# Restore the MSR back
mts rmsr,r18
.end microblaze_update_icache
 
/standalone_v1_00_a/src/microblaze_exceptions_i.h
0,0 → 1,61
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_exceptions_i.h,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
////////////////////////////////////////////////////////////////////////////////
 
/*****************************************************************************/
/**
*
* @file microblaze_exceptions_i.h
*
* This header file contains defines for structures used by the microblaze
* hardware exception handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00a 06/24/04 First release
* </pre>
*
******************************************************************************/
 
#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
 
/***************************** Include Files *********************************/
 
#include "xbasic_types.h"
 
typedef struct
{
XExceptionHandler Handler;
void *CallBackRef;
} MB_ExceptionVectorTableEntry;
 
/* Exception IDs */
#define XEXC_ID_UNALIGNED_ACCESS 1
#define XEXC_ID_ILLEGAL_OPCODE 2
#define XEXC_ID_IOPB_EXCEPTION 3
#define XEXC_ID_DOPB_EXCEPTION 4
#define XEXC_ID_DIV_BY_ZERO 5
#define XEXC_ID_FPU 6
 
void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr);
 
#endif /* end of protection macro */
/standalone_v1_00_a/src/hw_exception_handler.S
0,0 → 1,383
/*///////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: hw_exception_handler.S,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
//
//////////////////////////////////////////////////////////////////////////////*/
 
/*
* Microblaze HW Exception Handler
* - Non self-modifying exception handler for the following exception conditions
* - Unalignment
* - Instruction bus error
* - Data bus error
* - Illegal instruction opcode
* - Divide-by-zero
*/
 
#include "microblaze_exceptions_g.h"
/* Helpful Macros */
#define EX_HANDLER_STACK_SIZ (4*19)
#define RMSR_OFFSET 0
#define REG_OFFSET(regnum) (4*regnum)
#define NUM_TO_REG(num) r ## num
 
#define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum)
#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum)
 
#define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
#define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
/* Uses r5 */
#define PUSH_MSR \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET;
 
#define PUSH_MSR_AND_ENABLE_EXC \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET; \
ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
mts rmsr, r5;
/* Uses r5 */
#define POP_MSR \
lwi r5, r1, RMSR_OFFSET; \
mts rmsr, r5;
 
#define LWREG_NOP \
bri ex_handler_unhandled; \
nop;
 
#define SWREG_NOP \
bri ex_handler_unhandled; \
nop;
/* r3 is the source */
#define R3_TO_LWREG_V(regnum) \
R3_TO_STACK (regnum); \
bri ex_handler_done;
 
/* r3 is the source */
#define R3_TO_LWREG(regnum) \
or NUM_TO_REG (regnum), r0, r3; \
bri ex_handler_done;
 
/* r3 is the target */
#define SWREG_TO_R3_V(regnum) \
R3_FROM_STACK (regnum); \
bri ex_sw_tail;
/* r3 is the target */
#define SWREG_TO_R3(regnum) \
or r3, r0, NUM_TO_REG (regnum); \
bri ex_sw_tail;
 
/* Extern declarations */
.extern MB_ExceptionVectorTable
 
 
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/*
* hw_exception_handler - Handler for unaligned exceptions
* Exception handler notes:
* - Does not handle exceptions other than unaligned exceptions
* - Does not handle exceptions during load into r17, r1, r0.
* - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
*
* Relevant register structures
*
* EAR - |----|----|----|----|----|----|----|----|
* - < ## 32 bit faulting address ## >
*
* ESR - |----|----|----|----|----| - | - |-----|-----|
* - W S REG EXC
*
*
* STACK FRAME STRUCTURE
* ---------------------
*
* +-------------+ + 0
* | MSR |
* +-------------+ + 4
* | r1 |
* | . |
* | . |
* | . |
* | . |
* | r18 |
* +-------------+ + 76
* | . |
* | . |
*/
 
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
_hw_exception_handler:
addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
PUSH_REG(3);
PUSH_REG(4);
PUSH_REG(5);
PUSH_REG(6);
PUSH_REG(17);
PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
mfs r3, resr;
andi r5, r3, 0x1F; /* Extract ESR[EXC] */
 
#if (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER))
xori r6, r5, 1; /* 00001 = Unaligned Exception */
beqi r6, handle_unaligned_ex ; /* Jump to unalignment exception handler*/
#endif /* (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER)) */
 
#if (! defined (NO_OTHER_EXCEPTIONS) || (defined(USER_SPEC_UNALIGNED_HANDLER)))
handle_other_ex: /* Handle Other exceptions here */
ori r6, r0, 7;
cmp r6, r5, r6; /* >= 7 are unknown exceptions. Do not handle these */
blei r6, ex_handler_done;
 
PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
PUSH_REG(8);
PUSH_REG(9);
PUSH_REG(10);
PUSH_REG(11);
PUSH_REG(12);
PUSH_REG(15);
PUSH_REG(18);
 
la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
addik r5, r5, -1 /* Interesting exception numbers start range from 1-6.
Convert to array index. */
addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */
addk r7, r7, r7;
addk r7, r7, r7;
addk r7, r7, r4; /* Get pointer to exception vector */
lwi r5, r7, 4; /* Load argument to exception handler from table */
lw r7, r7, r0; /* Load vector itself here */
 
brald r15, r7; /* Branch to handler */
nop;
POP_REG(7); /* Restore other volatiles */
POP_REG(8);
POP_REG(9);
POP_REG(10);
POP_REG(11);
POP_REG(12);
POP_REG(15);
POP_REG(18);
#endif /* (! defined (NO_OTHER_EXCEPTIONS) || (defined(USER_SPEC_UNALIGNED_HANDLER))) */
 
#if (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER))
bri ex_handler_done; /* Complete exception handling */
handle_unaligned_ex:
andi r6, r3, 0x3E0; /* Mask and extract the register operand */
srl r6, r6; /* r6 >> 5 */
srl r6, r6;
srl r6, r6;
srl r6, r6;
srl r6, r6;
sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
mfs r4, rear;
andi r6, r3, 0x400; /* Extract ESR[S] */
bnei r6, ex_sw;
ex_lw:
andi r6, r3, 0x800; /* Extract ESR[W] */
beqi r6, ex_lhw;
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lbui r5, r4, 2;
sbi r5, r0, ex_tmp_data_loc_2;
lbui r5, r4, 3;
sbi r5, r0, ex_tmp_data_loc_3;
lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
bri ex_lw_tail;
ex_lhw:
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
ex_lw_tail:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r6;
bra r5;
ex_lw_end: /* Exception handling of load word, ends */
ex_sw:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r6;
bra r5;
ex_sw_tail:
mfs r6, resr;
andi r6, r6, 0x800; /* Extract ESR[W] */
beqi r6, ex_shw;
swi r3, r0, ex_tmp_data_loc_0;
lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
sbi r3, r4, 0;
lbui r3, r0, ex_tmp_data_loc_1;
sbi r3, r4, 1;
lbui r3, r0, ex_tmp_data_loc_2;
sbi r3, r4, 2;
lbui r3, r0, ex_tmp_data_loc_3;
sbi r3, r4, 3;
bri ex_handler_done;
ex_shw:
swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
lbui r3, r0, ex_tmp_data_loc_2;
sbi r3, r4, 0;
lbui r3, r0, ex_tmp_data_loc_3;
sbi r3, r4, 1;
ex_sw_end: /* Exception handling of store word, ends. */
#endif /* (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER)) */
ex_handler_done:
POP_MSR;
POP_REG(3);
POP_REG(4);
POP_REG(5);
POP_REG(6);
POP_REG(17);
rted r17, 0
addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
ex_handler_unhandled:
bri 0 /* UNHANDLED. TRAP HERE */
.end _hw_exception_handler
 
#if (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER))
/*
* hw_exception_handler Jump Table
* - Contains code snippets for each register that caused the unaligned exception.
* - Hence exception handler is NOT self-modifying
* - Separate table for load exceptions and store exceptions.
* - Each table is of size: (8 * 32) = 256 bytes
*/
.section .text
.align 4
lw_table:
lw_r0: R3_TO_LWREG (0);
lw_r1: LWREG_NOP;
lw_r2: R3_TO_LWREG (2);
lw_r3: R3_TO_LWREG_V (3);
lw_r4: R3_TO_LWREG_V (4);
lw_r5: R3_TO_LWREG_V (5);
lw_r6: R3_TO_LWREG_V (6);
lw_r7: R3_TO_LWREG (7);
lw_r8: R3_TO_LWREG (8);
lw_r9: R3_TO_LWREG (9);
lw_r10: R3_TO_LWREG (10);
lw_r11: R3_TO_LWREG (11);
lw_r12: R3_TO_LWREG (12);
lw_r13: R3_TO_LWREG (13);
lw_r14: R3_TO_LWREG (14);
lw_r15: R3_TO_LWREG (15);
lw_r16: R3_TO_LWREG (16);
lw_r17: LWREG_NOP;
lw_r18: R3_TO_LWREG (18);
lw_r19: R3_TO_LWREG (19);
lw_r20: R3_TO_LWREG (20);
lw_r21: R3_TO_LWREG (21);
lw_r22: R3_TO_LWREG (22);
lw_r23: R3_TO_LWREG (23);
lw_r24: R3_TO_LWREG (24);
lw_r25: R3_TO_LWREG (25);
lw_r26: R3_TO_LWREG (26);
lw_r27: R3_TO_LWREG (27);
lw_r28: R3_TO_LWREG (28);
lw_r29: R3_TO_LWREG (29);
lw_r30: R3_TO_LWREG (30);
lw_r31: R3_TO_LWREG (31);
 
sw_table:
sw_r0: SWREG_TO_R3 (0);
sw_r1: SWREG_NOP;
sw_r2: SWREG_TO_R3 (2);
sw_r3: SWREG_TO_R3_V (3);
sw_r4: SWREG_TO_R3_V (4);
sw_r5: SWREG_TO_R3_V (5);
sw_r6: SWREG_TO_R3_V (6);
sw_r7: SWREG_TO_R3 (7);
sw_r8: SWREG_TO_R3 (8);
sw_r9: SWREG_TO_R3 (9);
sw_r10: SWREG_TO_R3 (10);
sw_r11: SWREG_TO_R3 (11);
sw_r12: SWREG_TO_R3 (12);
sw_r13: SWREG_TO_R3 (13);
sw_r14: SWREG_TO_R3 (14);
sw_r15: SWREG_TO_R3 (15);
sw_r16: SWREG_TO_R3 (16);
sw_r17: SWREG_NOP;
sw_r18: SWREG_TO_R3 (18);
sw_r19: SWREG_TO_R3 (19);
sw_r20: SWREG_TO_R3 (20);
sw_r21: SWREG_TO_R3 (21);
sw_r22: SWREG_TO_R3 (22);
sw_r23: SWREG_TO_R3 (23);
sw_r24: SWREG_TO_R3 (24);
sw_r25: SWREG_TO_R3 (25);
sw_r26: SWREG_TO_R3 (26);
sw_r27: SWREG_TO_R3 (27);
sw_r28: SWREG_TO_R3 (28);
sw_r29: SWREG_TO_R3 (29);
sw_r30: SWREG_TO_R3 (30);
sw_r31: SWREG_TO_R3 (31);
 
/* Temporary data structures used in the handler */
.section .data
.align 2
ex_tmp_data_loc_0:
.byte 0
ex_tmp_data_loc_1:
.byte 0
ex_tmp_data_loc_2:
.byte 0
ex_tmp_data_loc_3:
.byte 0
ex_reg_op:
.byte 0
#endif /* (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER)) */
#else /* Dummy exception handler, in case exceptions are not present in the processor */
 
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
_hw_exception_handler:
bri 0;
.end _hw_exception_handler
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
 
 
 
/standalone_v1_00_a/src/microblaze_enable_icache.s
0,0 → 1,53
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable icache on the microblaze.
#
# $Id: microblaze_enable_icache.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_enable_icache
.ent microblaze_enable_icache
.align 2
microblaze_enable_icache:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 32
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_icache
 
/standalone_v1_00_a/src/microblaze_enable_interrupts.s
0,0 → 1,53
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable interrupts on the microblaze.
#
# $Id: microblaze_enable_interrupts.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_enable_interrupts
.ent microblaze_enable_interrupts
.align 2
microblaze_enable_interrupts:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 2
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_interrupts
 
/standalone_v1_00_a/src/microblaze_enable_exceptions.s
0,0 → 1,37
##############################################################-*-asm-*-
#
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# Enable exceptions on microblaze.
#
# $Id: microblaze_enable_exceptions.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
 
.section .text
.globl microblaze_enable_exceptions
.ent microblaze_enable_exceptions
.align 2
microblaze_enable_exceptions:
mfs r4, rmsr;
ori r4, r4, 0x100; /* Turn ON the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
.end microblaze_enable_exceptions
 
/standalone_v1_00_a/src/profile/_profile_clean.c
0,0 → 1,31
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: _profile_clean.c,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
 
#include "profile.h"
#include "_profile_timer_hw.h"
 
/*
* This function is the exit routine and is called by the crtinit, when the
* program terminates. The name needs to be changed later..
*/
void _profile_clean( void )
{
disable_timer();
}
 
/standalone_v1_00_a/src/profile/_profile_init.c
0,0 → 1,64
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: _profile_init.c,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
// _program_init.c:
// Initialize the Profiling Structures.
//
//////////////////////////////////////////////////////////////////////
 
#include "profile.h"
 
// XMD Initializes the following Global Variables Value during Program
// Download with appropriate values.
 
int profile_version = 1; // Version of S/W Intrusive Profiling library
 
int binsize = BINSIZE; // Histogram Bin Size
unsigned int cpu_clk_freq = CPU_FREQ_HZ ; // CPU Clock Frequency
unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ; // Histogram Sampling Frequency
unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer
 
// Structure for Storing the Profiling Data
struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff;
int n_gmon_sections = 1;
 
// This is the initialization code, which is called from the crtinit.
//
void _profile_init( void )
{
int i;
 
/* print("Gmon Init called....\r\n") ; */
/* putnum(n_gmon_sections) ; print("\r\n") ; */
/* if( _gmonparam == 0xffffffff ) */
/* printf("Gmonparam is NULL !!\r\n"); */
/* for( i = 0; i < n_gmon_sections; i++ ){ */
/* putnum(_gmonparam[i].lowpc) ; print("\t") ; */
/* putnum(_gmonparam[i].highpc) ; print("\r\n") ; */
/* putnum( _gmonparam[i].textsize ); print("\r\n") ; */
/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */
/* } */
 
#ifdef PROC_MICROBLAZE
microblaze_init();
#else
powerpc405_init();
#endif
}
 
/standalone_v1_00_a/src/profile/_profile_timer_hw.h
0,0 → 1,177
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/profile/_profile_timer_hw.h,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
// $Id: _profile_timer_hw.h,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
// _program_timer_hw.h:
// Timer related functions
//
//////////////////////////////////////////////////////////////////////
 
#ifndef _PROFILE_TIMER_HW_H
#define _PROFILE_TIMER_HW_H
 
#include "profile.h"
 
#ifdef PROC_PPC
#include "xexception_l.h"
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
 
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
 
#ifndef PPC_PIT_INTERRUPT
#include "xtmrctr_l.h"
#endif
 
extern unsigned int timer_clk_ticks ;
 
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC
#ifdef PPC_PIT_INTERRUPT
unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG
#endif
 
//--------------------------------------------------------------------
// Disable the Timer - During Profiling
//
// For PIT Timer -
// 1. XTime_PITDisableInterrupt() ;
// 2. Store the remaining timer clk tick
// 3. Stop the PIT Timer
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define disable_timer() \
{ \
unsigned long val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \
timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
mtspr(XREG_SPR_PIT, 0); \
}
#else
#define disable_timer() \
{ \
XTmrCtr_mDisable(PROFILE_TIMER_BASEADDR, 0 ); \
}
#endif
 
 
 
//--------------------------------------------------------------------
// Enable the Timer
//
// For PIT Timer -
// 1. Load the remaining timer clk ticks
// 2. XTime_PITEnableInterrupt() ;
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define enable_timer() \
{ \
unsigned long val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
}
#else
#define enable_timer() \
{ \
XTmrCtr_mEnable(PROFILE_TIMER_BASEADDR, 0 ); \
}
#endif
 
 
 
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
// For PIT Timer -
// 1. Load the timer clk ticks
// 2. Enable AutoReload and Interrupt
// 3. Clear PIT Timer Status bits
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
#define timer_ack() \
{ \
unsigned long val; \
mtspr(XREG_SPR_PIT, timer_clk_ticks); \
mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
}
#else
#define timer_ack() \
{ \
unsigned int csr; \
csr = XTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
XTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
#endif
 
//--------------------------------------------------------------------
#endif // PROC_PPC
//--------------------------------------------------------------------
 
 
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_MICROBLAZE
 
//--------------------------------------------------------------------
// Disable the Timer during Call-Graph Data collection
//
//--------------------------------------------------------------------
#define disable_timer() \
{ \
XTmrCtr_mDisable(PROFILE_TIMER_BASEADDR, 0 ); \
}
 
 
//--------------------------------------------------------------------
// Enable the Timer after Call-Graph Data collection
//
//--------------------------------------------------------------------
#define enable_timer() \
{ \
XTmrCtr_mEnable(PROFILE_TIMER_BASEADDR, 0 ); \
}
 
 
//--------------------------------------------------------------------
// Send Ack to Timer Interrupt
//
//--------------------------------------------------------------------
#define timer_ack() \
{ \
unsigned int csr; \
csr = XTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
XTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
 
//--------------------------------------------------------------------
#endif // PROC_MICROBLAZE
//--------------------------------------------------------------------
 
#endif
/standalone_v1_00_a/src/profile/profile_mcount_mb.S
0,0 → 1,51
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_mcount_mb.S,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
.globl _mcount
.text
.align 2
.ent _mcount
 
#ifndef PROFILE_NO_GRAPH
_mcount:
addi r1, r1, -40
swi r5, r1, 36
swi r6, r1, 32
swi r7, r1, 28
swi r8, r1, 24
swi r9, r1, 20
swi r10, r1, 16
swi r16, r1, 12
add r5, r0, r15
brlid r15, mcount
add r6, r0, r16
lwi r5, r1, 36
lwi r6, r1, 32
lwi r7, r1, 28
lwi r8, r1, 24
lwi r9, r1, 20
lwi r10, r1, 16
lwi r16, r1, 12
rtbd r16, 4
addi r1, r1, 40
 
#endif /* PROFILE_NO_GRAPH */
.end _mcount
/standalone_v1_00_a/src/profile/mblaze_nt_types.h
0,0 → 1,44
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/profile/mblaze_nt_types.h,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
// $Id: mblaze_nt_types.h,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
//////////////////////////////////////////////////////////////////////
 
#ifndef _MBLAZE_NT_TYPES_H
#define _MBLAZE_NT_TYPES_H
 
typedef char byte;
typedef short half;
typedef int word;
typedef unsigned char ubyte;
typedef unsigned short uhalf;
typedef unsigned int uword;
typedef ubyte boolean;
 
//typedef unsigned char u_char;
//typedef unsigned short u_short;
//typedef unsigned int u_int;
//typedef unsigned long u_long;
 
typedef short int16_t;
typedef unsigned short uint16_t;
typedef int int32_t;
typedef unsigned int uint32_t;
 
#endif
/standalone_v1_00_a/src/profile/profile.h
0,0 → 1,121
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/profile/profile.h,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
// $Id: profile.h,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
//////////////////////////////////////////////////////////////////////
 
#ifndef _PROFILE_H
#define _PROFILE_H 1
 
#include <stdio.h>
#include "mblaze_nt_types.h"
#include "profile_config.h"
 
void _system_init( void ) ;
void _system_clean( void ) ;
void mcount(unsigned long frompc, unsigned long selfpc);
void profile_intr_handler( void ) ;
 
 
 
/****************************************************************************
* Profiling on hardware - Hash table maintained on hardware and data sent
* to xmd for gmon.out generation.
****************************************************************************/
/*
* histogram counters are unsigned shorts (according to the kernel).
*/
#define HISTCOUNTER unsigned short
 
struct tostruct {
unsigned long selfpc;
long count;
short link;
unsigned short pad;
};
 
struct fromstruct {
unsigned long frompc ;
short link ;
unsigned short pad ;
} ;
 
/*
* general rounding functions.
*/
#define ROUNDDOWN(x,y) (((x)/(y))*(y))
#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
 
/*
* The profiling data structures are housed in this structure.
*/
struct gmonparam {
long int state;
 
// Histogram Information
unsigned short *kcount; /* No. of bins in histogram */
unsigned long kcountsize; /* Histogram samples */
 
// Call-graph Information
struct fromstruct *froms;
unsigned long fromssize;
struct tostruct *tos;
unsigned long tossize;
 
// Initialization I/Ps
unsigned long lowpc;
unsigned long highpc;
unsigned long textsize;
//unsigned long cg_froms;
//unsigned long cg_tos;
};
extern struct gmonparam *_gmonparam;
extern int n_gmon_sections;
 
/*
* Possible states of profiling.
*/
#define GMON_PROF_ON 0
#define GMON_PROF_BUSY 1
#define GMON_PROF_ERROR 2
#define GMON_PROF_OFF 3
 
/*
* Sysctl definitions for extracting profiling information from the kernel.
*/
#define GPROF_STATE 0 /* int: profiling enabling variable */
#define GPROF_COUNT 1 /* struct: profile tick count buffer */
#define GPROF_FROMS 2 /* struct: from location hash bucket */
#define GPROF_TOS 3 /* struct: destination/count structure */
#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
 
 
#endif /* _PROFILE_H */
 
 
 
 
 
 
 
 
 
 
 
 
/standalone_v1_00_a/src/profile/profile_hist.c
0,0 → 1,50
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_hist.c,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
#include "profile.h"
#include "mblaze_nt_types.h"
#include "_profile_timer_hw.h"
 
#ifdef PROC_PPC
#include "xpseudo_asm.h"
#define SPR_SRR0 0x01A
#endif
 
extern int binsize ;
uint32_t pc ;
 
void profile_intr_handler( void )
{
unsigned int csr, j ;
 
#ifdef PROC_MICROBLAZE
asm( "swi r14, r0, pc" ) ;
#else
pc = mfspr(SPR_SRR0);
#endif
//print("PC: "); putnum(pc); print("\r\n");
for(j = 0; j < n_gmon_sections; j++ ){
if((pc >= _gmonparam[j].lowpc) && (pc < _gmonparam[j].highpc)) {
_gmonparam[j].kcount[(pc-_gmonparam[j].lowpc)/(4 * binsize)]++;
break;
}
}
// Ack the Timer Interrupt
timer_ack();
}
 
/standalone_v1_00_a/src/profile/profile_mcount_ppc.S
0,0 → 1,54
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_mcount_ppc.S,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
.globl _mcount
#define _MCOUNT_STACK_FRAME 40
.section .text
.align 2
.type _mcount@function
 
 
_mcount:
stwu 1, -_MCOUNT_STACK_FRAME(1)
stw 3, 8(1)
stw 4, 12(1)
stw 5, 16(1)
stw 6, 20(1)
stw 7, 24(1)
stw 8, 28(1)
stw 9, 32(1)
stw 10, 36(1)
mflr 4
stw 4, (_MCOUNT_STACK_FRAME+4)(1)
lwz 3, (_MCOUNT_STACK_FRAME)(1)
lwz 3, 4(3)
bl mcount
lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
mtlr 4
lwz 10, 36(1)
lwz 9, 32(1)
lwz 8, 28(1)
lwz 7, 24(1)
lwz 6, 20(1)
lwz 5, 16(1)
lwz 4, 12(1)
lwz 3, 8(1)
addi 1,1, _MCOUNT_STACK_FRAME
blr
/standalone_v1_00_a/src/profile/profile_cg.c
0,0 → 1,144
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: profile_cg.c,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
 
#include "mblaze_nt_types.h"
#include "profile.h"
#include "_profile_timer_hw.h"
 
/*
* The mcount fucntion is excluded from the library, if the user defines
* PROFILE_NO_GRAPH.
*/
#ifndef PROFILE_NO_GRAPH
 
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
 
extern struct gmonparam *_gmonparam;
 
void mcount( unsigned long frompc, unsigned long selfpc )
{
register struct gmonparam *p;
register long toindex, fromindex;
int i, j;
 
disable_timer();
 
//print("CG: "); putnum(frompc); print("->"); putnum(selfpc); print("\r\n");
// check that frompcindex is a reasonable pc value.
// for example: signal catchers get called from the stack,
// not from text space. too bad.
//
for(j = 0; j < n_gmon_sections; j++ ){
if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
p = &_gmonparam[j];
break;
}
}
if( j == n_gmon_sections )
goto done;
 
#ifdef PROFILE_NO_FUNCPTR
fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
if( fromindex == -1 ) {
fromindex = p->cgtable_size ;
p->cgtable_size++ ;
p->cgtable[fromindex].frompc = frompc ;
p->cgtable[fromindex].selfpc = selfpc ;
p->cgtable[fromindex].count = 1 ;
goto done ;
}
p->cgtable[fromindex].count++ ;
#else
fromindex = searchpc( p->froms, p->fromssize, frompc ) ;
if( fromindex == -1 ) {
fromindex = p->fromssize ;
p->fromssize++ ;
//if( fromindex >= N_FROMS ) {
//print("Error : From PC table overflow\r\n") ;
//goto overflow ;
//}
p->froms[fromindex].frompc = frompc ;
p->froms[fromindex].link = -1 ;
}else {
toindex = p->froms[fromindex].link ;
while(toindex != -1) {
toindex = (p->tossize - toindex)-1 ;
if( p->tos[toindex].selfpc == selfpc ) {
p->tos[toindex].count++ ;
goto done ;
}
toindex = p->tos[toindex].link ;
}
}
//if( toindex == -1 ) {
p->tos-- ;
p->tossize++ ;
//if( toindex >= N_TOS ) {
//print("Error : To PC table overflow\r\n") ;
//goto overflow ;
//}
p->tos[0].selfpc = selfpc ;
p->tos[0].count = 1 ;
p->tos[0].link = p->froms[fromindex].link ;
p->froms[fromindex].link = p->tossize-1 ;
#endif
 
done:
p->state = GMON_PROF_ON;
goto enable_timer ;
overflow:
p->state = GMON_PROF_ERROR;
enable_timer:
enable_timer();
return ;
}
 
#ifdef PROFILE_NO_FUNCPTR
int searchpc( struct fromto_struct *cgtable, int cgtable_size, unsigned long frompc )
{
int index = 0 ;
while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
index++ ;
}
if( index == cgtable_size )
return -1 ;
else
return index ;
}
#else
int searchpc( struct fromstruct *froms, int fromssize, unsigned long frompc )
{
int index = 0 ;
while( (index < fromssize) && (froms[index].frompc != frompc) ){
index++ ;
}
if( index == fromssize )
return -1 ;
else
return index ;
}
#endif /* PROFILE_NO_FUNCPTR */
 
#endif /* PROFILE_NO_GRAPH */
 
/standalone_v1_00_a/src/profile/profile_config.h
0,0 → 1,38
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/profile/profile_config.h,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
// $Id: profile_config.h,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
//////////////////////////////////////////////////////////////////////
 
#ifndef _PROFILE_CONFIG_H
#define _PROFILE_CONFIG_H
 
#define BINSIZE 4
#define SAMPLE_FREQ_HZ 100000
#define TIMER_CLK_TICKS 1000
 
#define PROFILE_NO_FUNCPTR_FLAG 0
 
//#define PROFILE_TIMER_BASEADDR 0x0c000500
#define PROFILE_TIMER_BASEADDR 0x00608000
#define PROFILE_TIMER_INTR_ID 0
 
#define TIMER_CONNECT_INTC
 
#endif
/standalone_v1_00_a/src/profile/dummy.S
0,0 → 1,40
//
// Copyright (c) 2002 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: dummy.S,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
.globl dummy_f
 
#ifdef PROC_MICROBLAZE
.text
.align 2
.ent dummy_f
 
dummy_f:
nop
 
.end dummy_f
#endif
 
#ifdef PROC_PPC
.section .text
.align 2
.type dummy_f@function
dummy_f:
b dummy_f
#endif
/standalone_v1_00_a/src/profile/Makefile
0,0 → 1,65
#######################################################################
#
# Copyright (c) 2002 Xilinx, Inc. All rights reserved.
# Xilinx, Inc.
#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# $Id: Makefile,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
#
# Makefile for profiler
#
#######################################################################
 
# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
include ../config.make
 
AS=mb-as
COMPILER = mb-gcc
ARCHIVER = mb-ar
CP = cp
COMPILER_FLAGS=-O2
EXTRA_COMPILER_FLAGS=
LIB = libxil.a
DUMMYLIB = libxilprofile.a
 
CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
 
RELEASEDIR = ../../../../lib
INCLUDEDIR = ../../../../include
INCLUDES = -I./. -I${INCLUDEDIR}
 
OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
DUMMYOBJ = dummy.o
INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
 
libs : reallibs dummylibs
 
reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
$(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
 
dummylibs : $(DUMMYOBJ)
$(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
 
%.o:%.c
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
 
%.o:%.S
$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
 
include:
$(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
 
clean:
rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
/standalone_v1_00_a/src/profile/_profile_timer_hw.c
0,0 → 1,182
//////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
// Xilinx, Inc.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/profile/_profile_timer_hw.c,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
// $Id: _profile_timer_hw.c,v 1.1 2006-06-23 19:03:44 quickwayne Exp $
//
// _program_timer_hw.c:
// Timer related functions
//
//////////////////////////////////////////////////////////////////////
 
#include "profile.h"
 
#ifdef PROC_PPC
#include "xexception_l.h"
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
 
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif // TIMER_CONNECT_INTC
 
#ifndef PPC_PIT_INTERRUPT
#include "xtmrctr_l.h"
#endif
 
extern unsigned int timer_clk_ticks ;
 
//--------------------------------------------------------------------
// PowerPC Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_PPC
 
 
//--------------------------------------------------------------------
// PowerPC PIT Timer Init.
// Defined only if PIT Timer is used for Profiling
//
//--------------------------------------------------------------------
#ifdef PPC_PIT_INTERRUPT
int ppc_pit_init( void )
{
// 1. Register Profile_intr_handler as Interrupt handler
// 2. Set PIT Timer Interrupt and Enable it.
XExc_RegisterHandler( XEXC_ID_PIT_INT,
(XExceptionHandler)profile_intr_handler,(void *)0);
XTime_PITSetInterval( timer_clk_ticks ) ;
XTime_PITEnableAutoReload() ;
return 0;
}
#endif
 
 
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, PIT and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init()
{
XExc_Init() ;
XExc_mDisableExceptions( XEXC_NON_CRITICAL ) ;
 
// Initialize the Timer.
// 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_pit_init();
#else
#ifdef TIMER_CONNECT_INTC
XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT,
(XExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT,
(XExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
 
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_PITEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_mMasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_mEnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
XExc_mEnableExceptions( XEXC_NON_CRITICAL ) ;
#endif
}
 
#endif // PROC_PPC
 
 
 
//--------------------------------------------------------------------
// opb_timer Initialization for PowerPC and MicroBlaze. This function
// is not needed if PIT timer is used in PowerPC
//
//--------------------------------------------------------------------
#ifndef PPC_PIT_INTERRUPT
int opb_timer_init( void )
{
// set the number of cycles the timer counts before interrupting
XTmrCtr_mSetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks);
 
// reset the timers, and clear interrupts
XTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0,
XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
 
// start the timers
XTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK
| XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
return 0;
}
#endif
 
 
//--------------------------------------------------------------------
// MicroBlaze Target - Timer related functions
//--------------------------------------------------------------------
#ifdef PROC_MICROBLAZE
 
//--------------------------------------------------------------------
// Initialize the Profile Timer for MicroBlaze Target.
// For MicroBlaze, opb_timer is used. The opb_timer can be directly
// connected to MicroBlaze or connected through Interrupt Controller.
//
//--------------------------------------------------------------------
int microblaze_init()
{
// Register profile_intr_handler
// 1. If timer is connected to Interrupt Controller, register the handler
// to Interrupt Controllers vector table.
// 2. If timer is directly connected to MicroBlaze, register the handler
// as Interrupt handler
#ifdef TIMER_CONNECT_INTC
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
microblaze_register_handler( (XInterruptHandler)profile_intr_handler,
(void *)0) ;
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
 
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
XIntc_mMasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_mEnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
microblaze_enable_interrupts();
#endif
}
 
#endif // PROC_MICROBLAZE
/standalone_v1_00_a/src/microblaze_disable_dcache.s
0,0 → 1,53
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_disable_dcache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable dcache on the microblaze.
#
# $Id: microblaze_disable_dcache.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_disable_dcache
.ent microblaze_disable_dcache
.align 2
microblaze_disable_dcache:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Clear the dcache enable bit
andi r12, r12, ~128
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_dcache
 
/standalone_v1_00_a/src/mb_interface.h
0,0 → 1,66
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// File : mb_interface.h
// Date : 2002, March 20.
// Company: Xilinx
// Group : Emerging Software Technologies
//
// Summary:
// Header file for mb_interface
//
// $Id: mb_interface.h,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
//
////////////////////////////////////////////////////////////////////////////////
 
#ifndef _MICROBLAZE_INTERFACE_H_
#define _MICROBLAZE_INTERFACE_H_
 
#include "xbasic_types.h"
extern void microblaze_enable_interrupts(void); // Enable Interrupts
extern void microblaze_disable_interrupts(void); // Disable Interrupts
extern void microblaze_enable_icache(void); // Enable Instruction Cache
extern void microblaze_disable_icache(void); // Disable Instruction Cache
extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); // Register top level interrupt handler
extern void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr); // Register exception handler
 
 
extern void microblaze_update_icache (int , int , int );
extern void microblaze_init_icache_range (int , int );
extern void microblaze_update_dcache (int , int , int );
extern void microblaze_init_dcache_range (int , int );
 
 
// FSL Access Macros
 
// Blocking Data Read and Write to FSL no. id
#define microblaze_bread_datafsl(val, id) asm volatile ("get %0, rfsl" #id : "=d" (val))
#define microblaze_bwrite_datafsl(val, id) asm volatile ("put %0, rfsl" #id :: "d" (val))
 
// Non-blocking Data Read and Write to FSL no. id
#define microblaze_nbread_datafsl(val, id) asm volatile ("nget %0, rfsl" #id : "=d" (val))
#define microblaze_nbwrite_datafsl(val, id) asm volatile ("nput %0, rfsl" #id :: "d" (val))
 
// Blocking Control Read and Write to FSL no. id
#define microblaze_bread_cntlfsl(val, id) asm volatile ("cget %0, rfsl" #id : "=d" (val))
#define microblaze_bwrite_cntlfsl(val, id) asm volatile ("cput %0, rfsl" #id :: "d" (val))
 
// Non-blocking Control Read and Write to FSL no. id
#define microblaze_nbread_cntlfsl(val, id) asm volatile ("ncget %0, rfsl" #id : "=d" (val))
#define microblaze_nbwrite_cntlfsl(val, id) asm volatile ("ncput %0, rfsl" #id :: "d" (val))
 
 
#endif // _MICROBLAZE_INTERFACE_H_
/standalone_v1_00_a/src/microblaze_disable_icache.s
0,0 → 1,53
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_disable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable icache on the microblaze.
#
# $Id: microblaze_disable_icache.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_disable_icache
.ent microblaze_disable_icache
.align 2
microblaze_disable_icache:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Clear the icache enable bit
andi r12, r12, ~32
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_icache
 
/standalone_v1_00_a/src/microblaze_disable_interrupts.s
0,0 → 1,53
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_disable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable interrupts on the microblaze.
#
# $Id: microblaze_disable_interrupts.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_disable_interrupts
.ent microblaze_disable_interrupts
.align 2
microblaze_disable_interrupts:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Clear the interrupt enable bit
andi r12, r12, ~2
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_interrupts
 
/standalone_v1_00_a/src/inbyte.c
0,0 → 1,6
#include "xparameters.h"
#include "xuartlite_l.h"
 
char inbyte(void) {
return XUartLite_RecvByte(STDIN_BASEADDRESS);
}
/standalone_v1_00_a/src/microblaze_disable_exceptions.s
0,0 → 1,37
##############################################################-*-asm-*-
#
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# Disable exceptions on microblaze.
#
# $Id: microblaze_disable_exceptions.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
 
.section .text
.globl microblaze_disable_exceptions
.ent microblaze_disable_exceptions
.align 2
microblaze_disable_exceptions:
mfs r4, rmsr;
andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
.end microblaze_disable_exceptions
 
/standalone_v1_00_a/src/outbyte.c
0,0 → 1,6
#include "xparameters.h"
#include "xuartlite_l.h"
 
void outbyte(char c) {
XUartLite_SendByte(STDOUT_BASEADDRESS, c);
}
/standalone_v1_00_a/src/Makefile
0,0 → 1,61
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
######################################################################
 
# The following are defined in config.make
# LIBSOURCES - Based on if MicroBlaze support Exceptions
# LIBS - Do Build Profile Libraries
include config.make
 
AS=mb-as
COMPILER=mb-gcc
ARCHIVER=mb-ar
CP=cp
COMPILER_FLAGS=-O2 -c
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
 
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
 
OUTS = *.o
 
INCLUDEFILES=*.h
 
libs: $(LIBS)
 
standalone_libs:
for i in $(LIBSOURCES); do \
echo "Compiling " $$i ;\
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $$i; \
done
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
 
profile_libs:
(cd profile; $(MAKE) COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(COMPILER)" ARCHIVER="$(ARCHIVER)" libs)
 
include: standalone_includes profile_includes
 
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
 
profile_includes:
(cd profile; $(MAKE) COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(COMPILER)" ARCHIVER="$(ARCHIVER)" include)
 
clean:
rm -rf ${OUTS}
(cd profile; $(MAKE) COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(COMPILER)" ARCHIVER="$(ARCHIVER)" clean)
/standalone_v1_00_a/src/microblaze_interrupts_g.c
0,0 → 1,29
 
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Interrupt Handler Table for MicroBlaze Processor
*
*******************************************************************/
 
#include "microblaze_interrupts_i.h"
#include "xparameters.h"
 
 
extern void XNullHandler (void *);
 
/*
* The interrupt handler table for microblaze processor
*/
 
MB_InterruptVectorTableEntry MB_InterruptVectorTable[] =
{
XNullHandler,
(void*) XNULL
};
 
/standalone_v1_00_a/src/microblaze_init_dcache_range.s
0,0 → 1,64
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_init_dcache_range.s
# Date : 2003, September 24
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Update dcache on the microblaze.
# Takes in two parameters
# r5 : Cache Base Address
# (start address in the cache where invalidation begins)
# r6 : Size of Cache to be invalidated
#
# $Id: microblaze_init_dcache_range.s,v 1.1 2006-06-23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_init_dcache_range
.ent microblaze_init_dcache_range
.align 2
microblaze_init_dcache_range:
 
# Read the MSR register into a temp register
mfs r9, rmsr
 
# Clear the dcache enable bit to disable the cache
# Register r10,r18 are volatile registers and hence do not need to be saved before use
andi r10, r9, ~128
mts rmsr, r10
 
## Start the loop
add r6,r5,r6 # One address beyond last address
L_start:
cmp r18,r5,r6
bleid r18, L_done # Jump out of the loop if done
addi r6,r6,-4 # Decrement the addrees by 4 [ delay slot]
brid L_start # Branch to the beginning of the loop
wdc r6,r0 # Invalidate the Cache [ delay slot]
L_done:
# Return
rtsd r15, 8
 
# Restore the MSR back
mts rmsr,r9
.end microblaze_init_dcache_range
 

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