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    /mblite/trunk/designs/core_decoder_wb
    from Rev 6 to Rev 8
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  •

Rev 6 → Rev 8

/testbench.vhd
12,69 → 12,69
--
----------------------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
LIBRARY mblite;
USE mblite.config_Pkg.ALL;
USE mblite.core_Pkg.ALL;
USE mblite.std_Pkg.ALL;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
ENTITY testbench IS
END testbench;
entity testbench is
end testbench;
 
ARCHITECTURE arch OF testbench IS
architecture arch of testbench is
 
COMPONENT wb_stdio IS PORT
component wb_stdio is port
(
wb_o : OUT wb_slv_out_type;
wb_i : IN wb_slv_in_type
wb_o : out wb_slv_out_type;
wb_i : in wb_slv_in_type
);
END COMPONENT;
end component;
 
SIGNAL dmem_o : dmem_out_type;
SIGNAL dmem_i : dmem_in_type;
SIGNAL imem_o : imem_out_type;
SIGNAL imem_i : imem_in_type;
SIGNAL s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
SIGNAL s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal imem_o : imem_out_type;
signal imem_i : imem_in_type;
signal s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 downto 0);
signal s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 downto 0);
 
SIGNAL m_wb_i : wb_mst_in_type;
SIGNAL m_wb_o : wb_mst_out_type;
SIGNAL s_wb_i : wb_slv_in_type;
SIGNAL s_wb_o : wb_slv_out_type;
signal m_wb_i : wb_mst_in_type;
signal m_wb_o : wb_mst_out_type;
signal s_wb_i : wb_slv_in_type;
signal s_wb_o : wb_slv_out_type;
 
SIGNAL sys_clk_i : std_logic := '0';
SIGNAL sys_int_i : std_logic;
SIGNAL sys_rst_i : std_logic;
signal sys_clk_i : std_logic := '0';
signal sys_int_i : std_logic;
signal sys_rst_i : std_logic;
 
CONSTANT rom_size : integer := 16;
CONSTANT ram_size : integer := 16;
constant rom_size : integer := 16;
constant ram_size : integer := 16;
 
SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
SIGNAL ena_o : std_logic;
signal sel_o : std_logic_vector(3 downto 0);
signal ena_o : std_logic;
 
BEGIN
begin
 
sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
sys_clk_i <= not sys_clk_i after 10000 ps;
sys_rst_i <= '1' after 0 ps, '0' after 150000 ps;
sys_int_i <= '1' after 500000000 ps, '0' after 500040000 ps;
 
-- Warning: an infinite loop like while(1) {} triggers this timeout too!
-- disable this feature when a premature finish occur.
timeout: PROCESS(sys_clk_i)
BEGIN
IF NOW = 10 ms THEN
REPORT "TIMEOUT" SEVERITY FAILURE;
END IF;
timeout: process(sys_clk_i)
begin
if NOW = 10 ms then
report "TIMEOUT" severity FAILURE;
end if;
-- BREAK ON EXIT (0xB8000000)
IF compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' THEN
if compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' then
-- Make sure the simulator finishes when an error is encountered.
-- For modelsim: see menu Simulate -> Runtime options -> Assertions
REPORT "FINISHED" SEVERITY FAILURE;
END IF;
END PROCESS;
report "FINISHED" severity FAILURE;
end if;
end process;
 
s_wb_i.clk_i <= sys_clk_i;
s_wb_i.rst_i <= sys_rst_i;
91,13 → 91,13
m_wb_i.ack_i <= s_wb_o.ack_o;
m_wb_i.int_i <= s_wb_o.int_o;
 
stdio : wb_stdio PORT MAP
stdio : wb_stdio port map
(
wb_i => s_wb_i,
wb_o => s_wb_o
);
 
wb_adapter : core_wb_adapter PORT MAP
wb_adapter : core_wb_adapter port map
(
dmem_i => s_dmem_i(1),
wb_o => m_wb_o,
106,29 → 106,29
);
 
s_dmem_i(0).ena_i <= '1';
sel_o <= s_dmem_o(0).sel_o WHEN s_dmem_o(0).we_o = '1' ELSE (OTHERS => '0');
ena_o <= NOT sys_rst_i AND s_dmem_o(0).ena_o;
sel_o <= s_dmem_o(0).sel_o when s_dmem_o(0).we_o = '1' else (others => '0');
ena_o <= not sys_rst_i and s_dmem_o(0).ena_o;
 
dmem : sram_4en GENERIC MAP
dmem : sram_4en generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => ram_size - 2
SIZE => ram_size - 2
)
PORT MAP
port map
(
dat_o => s_dmem_i(0).dat_i,
dat_i => s_dmem_o(0).dat_o,
adr_i => s_dmem_o(0).adr_o(ram_size - 1 DOWNTO 2),
adr_i => s_dmem_o(0).adr_o(ram_size - 1 downto 2),
wre_i => sel_o,
ena_i => ena_o,
clk_i => sys_clk_i
);
 
decoder : core_address_decoder GENERIC MAP
decoder : core_address_decoder generic map
(
G_NUM_SLAVES => CFG_NUM_SLAVES
)
PORT MAP
port map
(
m_dmem_i => dmem_i,
s_dmem_o => s_dmem_o,
137,22 → 137,22
clk_i => sys_clk_i
);
 
imem : sram GENERIC MAP
imem : sram generic map
(
WIDTH => CFG_IMEM_WIDTH,
SIZE => rom_size - 2
SIZE => rom_size - 2
)
PORT MAP
port map
(
dat_o => imem_i.dat_i,
dat_i => "00000000000000000000000000000000",
adr_i => imem_o.adr_o(rom_size - 1 DOWNTO 2),
adr_i => imem_o.adr_o(rom_size - 1 downto 2),
wre_i => '0',
ena_i => imem_o.ena_o,
clk_i => sys_clk_i
);
 
core0 : core PORT MAP
core0 : core port map
(
imem_o => imem_o,
dmem_o => dmem_o,
163,4 → 163,4
clk_i => sys_clk_i
);
 
END arch;
end arch;
/config_Pkg.vhd
11,52 → 11,52
--
----------------------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
PACKAGE config_Pkg IS
package config_Pkg is
 
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
CONSTANT CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
constant CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
 
-- Implement hardware multiplier
CONSTANT CFG_USE_HW_MUL : boolean := true; -- Disable or enable multiplier [0,1]
constant CFG_USE_HW_MUL : boolean := true; -- Disable or enable multiplier [0,1]
 
-- Implement hardware barrel shifter
CONSTANT CFG_USE_BARREL : boolean := true; -- Disable or enable barrel shifter [0,1]
constant CFG_USE_BARREL : boolean := true; -- Disable or enable barrel shifter [0,1]
 
-- Debug mode
CONSTANT CFG_DEBUG : boolean := true; -- Resets some extra registers for better readability
constant CFG_DEBUG : boolean := true; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
 
-- Memory parameters
CONSTANT CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
CONSTANT CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
CONSTANT CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
constant CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
constant CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
constant CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
 
-- Register parameters
CONSTANT CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
CONSTANT CFG_REG_FWD_WB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
CONSTANT CFG_MEM_FWD_WB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
constant CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
constant CFG_REG_FWD_WRB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
constant CFG_MEM_FWD_WRB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
 
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
CONSTANT CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
CONSTANT CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
CONSTANT CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
constant CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
constant CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
constant CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
 
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
 
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
CONSTANT CFG_NUM_SLAVES : positive := 2;
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
type memory_map_type is array(natural range <>) of std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
constant CFG_NUM_SLAVES : positive := 2;
constant CFG_MEMORY_MAP : memory_map_type(0 to CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
 
END config_Pkg;
end config_Pkg;
/wb_stdio.vhd
11,84 → 11,84
--
----------------------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
LIBRARY mblite;
USE mblite.config_Pkg.ALL;
USE mblite.core_Pkg.ALL;
USE mblite.std_Pkg.ALL;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
USE std.textio.ALL;
use std.textio.all;
 
ENTITY wb_stdio IS PORT
entity wb_stdio is port
(
wb_o : OUT wb_slv_out_type;
wb_i : IN wb_slv_in_type
wb_o : out wb_slv_out_type;
wb_i : in wb_slv_in_type
);
END wb_stdio;
end wb_stdio;
 
ARCHITECTURE arch OF wb_stdio IS
CONSTANT ack_assert_delay : TIME := 2 ns;
CONSTANT ack_deassert_delay : TIME := 2 ns;
SIGNAL ack : std_logic;
SIGNAL chr_dat : std_logic_vector(31 DOWNTO 0);
SIGNAL chr_cnt : natural := 0;
BEGIN
architecture arch of wb_stdio is
constant ack_assert_delay : TIME := 2 ns;
constant ack_deassert_delay : TIME := 2 ns;
signal ack : std_logic;
signal chr_dat : std_logic_vector(31 downto 0);
signal chr_cnt : natural := 0;
begin
wb_o.int_o <= '0';
wb_o.dat_o <= chr_dat;
-- Character device
stdio: PROCESS(wb_i.clk_i)
VARIABLE s : line;
VARIABLE byte : std_logic_vector(7 DOWNTO 0);
VARIABLE char : character;
BEGIN
IF rising_edge(wb_i.clk_i) THEN
IF (wb_i.stb_i AND wb_i.cyc_i) = '1' THEN
IF wb_i.we_i = '1' AND ack = '0' THEN
stdio: process(wb_i.clk_i)
variable s : line;
variable byte : std_logic_vector(7 downto 0);
variable char : character;
begin
if rising_edge(wb_i.clk_i) then
if (wb_i.stb_i and wb_i.cyc_i) = '1' then
if wb_i.we_i = '1' and ack = '0' then
-- WRITE STDOUT
wb_o.ack_o <= '1' AFTER ack_assert_delay;
wb_o.ack_o <= '1' after ack_assert_delay;
ack <= '1';
CASE wb_i.sel_i IS
WHEN "0001" => byte := wb_i.dat_i( 7 DOWNTO 0);
WHEN "0010" => byte := wb_i.dat_i(15 DOWNTO 8);
WHEN "0100" => byte := wb_i.dat_i(23 DOWNTO 16);
WHEN "1000" => byte := wb_i.dat_i(31 DOWNTO 24);
WHEN OTHERS => NULL;
END CASE;
case wb_i.sel_i is
when "0001" => byte := wb_i.dat_i( 7 downto 0);
when "0010" => byte := wb_i.dat_i(15 downto 8);
when "0100" => byte := wb_i.dat_i(23 downto 16);
when "1000" => byte := wb_i.dat_i(31 downto 24);
when others => null;
end case;
char := character'val(my_conv_integer(byte));
IF byte = X"0D" THEN
if byte = X"0D" then
-- Ignore character 13
ELSIF byte = X"0A" THEN
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
ELSE
else
-- Write to buffer
write(s, char);
END IF;
ELSIF ack = '0' THEN
end if;
elsif ack = '0' then
-- READ stdout
ack <= '1';
wb_o.ack_o <= '1' AFTER ack_assert_delay;
IF chr_cnt = 0 THEN
wb_o.ack_o <= '1' after ack_assert_delay;
if chr_cnt = 0 then
chr_cnt <= 1;
chr_dat <= X"4C4C4C4C";
ELSIF chr_cnt = 1 THEN
elsif chr_cnt = 1 then
chr_cnt <= 2;
chr_dat <= X"4D4D4D4D";
ELSIF chr_cnt = 2 THEN
elsif chr_cnt = 2 then
chr_cnt <= 3;
chr_dat <= X"4E4E4E4E";
ELSIF chr_cnt = 3 THEN
elsif chr_cnt = 3 then
chr_cnt <= 0;
chr_dat <= X"0A0A0A0A";
END IF;
END IF;
ELSE
end if;
end if;
else
ack <= '0';
wb_o.ack_o <= '0' AFTER ack_deassert_delay;
END IF;
END IF;
END PROCESS;
END arch;
wb_o.ack_o <= '0' after ack_deassert_delay;
end if;
end if;
end process;
end arch;

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