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URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

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  • This comparison shows the changes necessary to convert path 
    /mblite/trunk/designs/core_syn
    from Rev 2 to Rev 6
    ↔ Reverse comparison
  •

Rev 2 → Rev 6

/testbench.vhd
42,14 → 42,14
);
END COMPONENT;
 
SIGNAL sys_clk_i : std_ulogic := '0';
SIGNAL sys_int_i : std_ulogic := '0';
SIGNAL sys_rst_i : std_ulogic := '0';
SIGNAL sys_ena_i : std_ulogic := '1';
SIGNAL sys_clk_i : std_logic := '0';
SIGNAL sys_int_i : std_logic := '0';
SIGNAL sys_rst_i : std_logic := '0';
SIGNAL sys_ena_i : std_logic := '1';
 
SIGNAL dmem_o : dmem_out_type;
 
CONSTANT std_out_adr : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
BEGIN
 
sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
79,7 → 79,7
-- Character device
stdio: PROCESS(sys_clk_i)
VARIABLE s : line;
VARIABLE byte : std_ulogic_vector(7 DOWNTO 0);
VARIABLE byte : std_logic_vector(7 DOWNTO 0);
VARIABLE char : character;
BEGIN
 
/mblite_soc.vhd
22,15 → 22,15
 
ENTITY mblite_soc IS PORT
(
sys_clk_i : IN std_ulogic;
dbg_dmem_o_we_o : OUT std_ulogic;
dbg_dmem_o_ena_o : OUT std_ulogic;
sys_rst_i : IN std_ulogic;
sys_ena_i : IN std_ulogic;
sys_int_i : IN std_ulogic;
dbg_dmem_o_adr_o : OUT std_ulogic_vector (31 DOWNTO 0);
dbg_dmem_o_dat_o : OUT std_ulogic_vector (31 DOWNTO 0);
dbg_dmem_o_sel_o : OUT std_ulogic_vector ( 3 DOWNTO 0)
sys_clk_i : IN std_logic;
dbg_dmem_o_we_o : OUT std_logic;
dbg_dmem_o_ena_o : OUT std_logic;
sys_rst_i : IN std_logic;
sys_ena_i : IN std_logic;
sys_int_i : IN std_logic;
dbg_dmem_o_adr_o : OUT std_logic_vector (31 DOWNTO 0);
dbg_dmem_o_dat_o : OUT std_logic_vector (31 DOWNTO 0);
dbg_dmem_o_sel_o : OUT std_logic_vector ( 3 DOWNTO 0)
);
END mblite_soc;
 
43,12 → 43,12
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_logic;
ena_i : IN std_logic;
clk_i : IN std_logic
);
END COMPONENT;
 
59,12 → 59,12
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic_vector(3 DOWNTO 0);
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_logic_vector(3 DOWNTO 0);
ena_i : IN std_logic;
clk_i : IN std_logic
);
END COMPONENT;
 
73,10 → 73,10
SIGNAL dmem_i : dmem_in_type;
SIGNAL imem_i : imem_in_type;
 
SIGNAL mem_enable : std_ulogic;
SIGNAL sel_o : std_ulogic_vector(3 DOWNTO 0);
SIGNAL mem_enable : std_logic;
SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
 
CONSTANT std_out_adr : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
CONSTANT rom_size : integer := 13;
CONSTANT ram_size : integer := 13;
 
/sram_init.vhd
25,17 → 25,17
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_logic;
ena_i : IN std_logic;
clk_i : IN std_logic
);
END sram_init;
 
ARCHITECTURE arch OF sram_init IS
TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type := (
X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
/config_Pkg.vhd
55,7 → 55,7
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
 
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
CONSTANT CFG_NUM_SLAVES : positive := 2;
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
 
/sram_4en_init.vhd
27,17 → 27,17
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic_vector(3 DOWNTO 0);
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_logic_vector(3 DOWNTO 0);
ena_i : IN std_logic;
clk_i : IN std_logic
);
END sram_4en_init;
 
ARCHITECTURE arch OF sram_4en_init IS
TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type := (
X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
296,7 → 296,7
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
 
SIGNAL di0, di1, di2, di3 : std_ulogic_vector(WIDTH/4 - 1 DOWNTO 0);
SIGNAL di0, di1, di2, di3 : std_logic_vector(WIDTH/4 - 1 DOWNTO 0);
BEGIN
process(wre_i, dat_i, adr_i)
begin

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