URL
https://opencores.org/ocsvn/mesi_isc/mesi_isc/trunk
Subversion Repositories mesi_isc
Compare Revisions
- This comparison shows the changes necessary to convert path
/mesi_isc/trunk
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/sim/iverilog.log
0,0 → 1,32
Using language generation: IEEE1364-2005,no-specify,xtypes,icarus-misc |
PARSING INPUT |
LOCATING TOP-LEVEL MODULES |
mesi_isc_tb |
ELABORATING DESIGN |
RUNNING FUNCTORS |
... 1 iterations deleted 372 dangling signals and 0 events. |
... 2 iterations deleted 372 dangling signals and 69 events. |
CALCULATING ISLANDS |
CODE GENERATION |
... invoking target_design |
STATISTICS |
lex_string: add_count=683 hit_count=3356 |
Icarus Verilog version 0.9.3 (v0_9_3) |
|
Copyright 1998-2010 Stephen Williams |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License along |
with this program; if not, write to the Free Software Foundation, Inc., |
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
|
translate: /usr/lib/ivl/ivlpp -v -L -F"/tmp/ivrlg238274735" -f"/tmp/ivrlg38274735" -p"/tmp/ivrli38274735" | /usr/lib/ivl/ivl -v -C"/tmp/ivrlh38274735" -C"/usr/lib/ivl/vvp.conf" -- - |
/sim/mesi_isc.out
0,0 → 1,6827
#! /usr/bin/vvp |
:ivl_version "0.9.3 " "(v0_9_3)"; |
:vpi_time_precision - 12; |
:vpi_module "system"; |
:vpi_module "v2005_math"; |
:vpi_module "va_math"; |
S_0x9aed928 .scope module, "mesi_isc_tb" "mesi_isc_tb" 2 58; |
.timescale -9 -12; |
P_0x9a84a34 .param/l "ADDR_WIDTH" 2 66, +C4<0100000>; |
P_0x9a84a48 .param/l "BREQ_FIFO_SIZE" 2 73, +C4<010>; |
P_0x9a84a5c .param/l "BREQ_FIFO_SIZE_LOG2" 2 74, +C4<01>; |
P_0x9a84a70 .param/l "BROAD_ID_WIDTH" 2 69, +C4<0101>; |
P_0x9a84a84 .param/l "BROAD_REQ_FIFO_SIZE" 2 70, +C4<0100>; |
P_0x9a84a98 .param/l "BROAD_REQ_FIFO_SIZE_LOG2" 2 71, +C4<010>; |
P_0x9a84aac .param/l "BROAD_TYPE_WIDTH" 2 68, +C4<010>; |
P_0x9a84ac0 .param/l "CBUS_CMD_WIDTH" 2 65, +C4<011>; |
P_0x9a84ad4 .param/l "DATA_WIDTH" 2 67, +C4<0100000>; |
P_0x9a84ae8 .param/l "MBUS_CMD_WIDTH" 2 72, +C4<011>; |
RS_0x9b0f454 .resolv tri, L_0x9b3f2e0, L_0x9b3f330, L_0x9b3f380, L_0x9b3f438; |
L_0x9aa2688 .functor OR 4, v0x9b2f280_0, RS_0x9b0f454, C4<0000>, C4<0000>; |
L_0x9b30eb0 .functor BUFZ 3, v0x9ace888_0, C4<000>, C4<000>, C4<000>; |
L_0x9b30f08 .functor BUFZ 3, v0x9aa02c8_0, C4<000>, C4<000>, C4<000>; |
L_0x9b30f60 .functor BUFZ 3, v0x9a852b8_0, C4<000>, C4<000>, C4<000>; |
L_0x9b30fb8 .functor BUFZ 3, v0x9abfbf0_0, C4<000>, C4<000>, C4<000>; |
L_0x9b31010 .functor BUFZ 32, v0x9ab7f98_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b31088 .functor BUFZ 32, v0x9aa0278_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b310e0 .functor BUFZ 32, v0x9a87238_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b31138 .functor BUFZ 32, v0x9adc1f0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b31170 .functor BUFZ 32, v0x9ae4498_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b31230 .functor BUFZ 32, v0x9ab17f0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b312a0 .functor BUFZ 32, v0x9a85828_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b31348 .functor BUFZ 32, v0x9acb5d0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
v0x9b30818_3 .array/port v0x9b30818, 3; |
L_0x9b313b8 .functor BUFZ 4, v0x9b30818_3, C4<0000>, C4<0000>, C4<0000>; |
v0x9b30818_2 .array/port v0x9b30818, 2; |
L_0x9b31310 .functor BUFZ 4, v0x9b30818_2, C4<0000>, C4<0000>, C4<0000>; |
v0x9b30818_1 .array/port v0x9b30818, 1; |
L_0x9b31460 .functor BUFZ 4, v0x9b30818_1, C4<0000>, C4<0000>, C4<0000>; |
v0x9b30818_0 .array/port v0x9b30818, 0; |
L_0x9b31518 .functor BUFZ 4, v0x9b30818_0, C4<0000>, C4<0000>, C4<0000>; |
v0x9b2e830_0 .net *"_s11", 0 0, C4<0>; 1 drivers |
v0x9b2e880_0 .net *"_s6", 0 0, C4<0>; 1 drivers |
v0x9b2e8d0_0 .net "broad_fifo_entry0", 41 0, L_0x9b30a70; 1 drivers |
v0x9b2e920_0 .net "broad_fifo_entry1", 41 0, L_0x9b30ce8; 1 drivers |
v0x9b2e970_0 .net "brroad_fifo_entry2", 0 0, L_0x9b30db0; 1 drivers |
v0x9b2e9c0_0 .net "brroad_fifo_entry3", 0 0, L_0x9b30e20; 1 drivers |
v0x9b2ea30_0 .net "cbus_ack0", 0 0, v0x9aeda88_0; 1 drivers |
v0x9b2ea80_0 .net "cbus_ack1", 0 0, v0x9a94c98_0; 1 drivers |
v0x9b2eb08_0 .net "cbus_ack2", 0 0, v0x9ab4888_0; 1 drivers |
v0x9b2eb90_0 .net "cbus_ack3", 0 0, v0x9a84e58_0; 1 drivers |
v0x9b2ec18_0 .net "cbus_addr", 31 0, L_0x9b2f7b0; 1 drivers |
v0x9b2ec68_0 .net "cbus_cmd0", 2 0, L_0x9b32388; 1 drivers |
v0x9b2ed28_0 .net "cbus_cmd1", 2 0, L_0x9b359f8; 1 drivers |
v0x9b2edb0_0 .net "cbus_cmd2", 2 0, L_0x9b359a8; 1 drivers |
v0x9b2ee00_0 .net "cbus_cmd3", 2 0, L_0x9b35958; 1 drivers |
v0x9b2ee88_0 .var "clk", 0 0; |
v0x9b2ef20_0 .var "cpu_priority", 1 0; |
v0x9b2ef70_0 .var "cpu_selected", 3 0; |
v0x9b2f010_0 .var/i "cur_stimulus_cpu", 31 0; |
v0x9b2f060_0 .var/i "i", 31 0; |
v0x9b2efc0_0 .var/i "j", 31 0; |
v0x9b2f108_0 .var/i "k", 31 0; |
v0x9b2f0b0_0 .var/i "l", 31 0; |
v0x9b2f1b8_0 .var/i "m", 31 0; |
v0x9b2f168_0 .net "mbus_ack", 3 0, L_0x9aa2688; 1 drivers |
v0x9b2f280_0 .var "mbus_ack_memory", 3 0; |
v0x9b2f218_0 .net8 "mbus_ack_mesi_isc", 3 0, RS_0x9b0f454; 4 drivers |
v0x9b2f350_0 .net "mbus_addr0", 31 0, L_0x9b31138; 1 drivers |
v0x9b2f2e0_0 .net "mbus_addr1", 31 0, L_0x9b310e0; 1 drivers |
v0x9b2f418_0 .net "mbus_addr2", 31 0, L_0x9b31088; 1 drivers |
v0x9b2f3b0_0 .net "mbus_addr3", 31 0, L_0x9b31010; 1 drivers |
v0x9b2f4e8 .array "mbus_addr_array", 0 3; |
v0x9b2f4e8_0 .net v0x9b2f4e8 0, 31 0, v0x9adc1f0_0; 1 drivers |
v0x9b2f4e8_1 .net v0x9b2f4e8 1, 31 0, v0x9a87238_0; 1 drivers |
v0x9b2f4e8_2 .net v0x9b2f4e8 2, 31 0, v0x9aa0278_0; 1 drivers |
v0x9b2f4e8_3 .net v0x9b2f4e8 3, 31 0, v0x9ab7f98_0; 1 drivers |
v0x9b2f630_0 .net "mbus_cmd0", 2 0, L_0x9b30fb8; 1 drivers |
v0x9b2f680_0 .net "mbus_cmd1", 2 0, L_0x9b30f60; 1 drivers |
v0x9b2f548_0 .net "mbus_cmd2", 2 0, L_0x9b30f08; 1 drivers |
v0x9b2f760_0 .net "mbus_cmd3", 2 0, L_0x9b30eb0; 1 drivers |
v0x9b2f6d0 .array "mbus_cmd_array", 0 3; |
v0x9b2f6d0_0 .net v0x9b2f6d0 0, 2 0, v0x9abfbf0_0; 1 drivers |
v0x9b2f6d0_1 .net v0x9b2f6d0 1, 2 0, v0x9a852b8_0; 1 drivers |
v0x9b2f6d0_2 .net v0x9b2f6d0 2, 2 0, v0x9aa02c8_0; 1 drivers |
v0x9b2f6d0_3 .net v0x9b2f6d0 3, 2 0, v0x9ace888_0; 1 drivers |
v0x9b2f8f0_0 .var "mbus_data_rd", 31 0; |
v0x9b2f9e0 .array "mbus_data_rd_word_array", 0 3; |
v0x9b2f9e0_0 .net v0x9b2f9e0 0, 7 0, L_0x9b31fe0; 1 drivers |
v0x9b2f9e0_1 .net v0x9b2f9e0 1, 7 0, L_0x9b31f70; 1 drivers |
v0x9b2f9e0_2 .net v0x9b2f9e0 2, 7 0, L_0x9b31ee0; 1 drivers |
v0x9b2f9e0_3 .net v0x9b2f9e0 3, 7 0, L_0x9b31e70; 1 drivers |
v0x9b2fa40_0 .net "mbus_data_wr0", 31 0, L_0x9b31348; 1 drivers |
v0x9b2f950_0 .net "mbus_data_wr1", 31 0, L_0x9b312a0; 1 drivers |
v0x9b2fb38_0 .net "mbus_data_wr2", 31 0, L_0x9b31230; 1 drivers |
v0x9b2fa90_0 .net "mbus_data_wr3", 31 0, L_0x9b31170; 1 drivers |
v0x9b2fc38 .array "mbus_data_wr_array", 0 3; |
v0x9b2fc38_0 .net v0x9b2fc38 0, 31 0, v0x9acb5d0_0; 1 drivers |
v0x9b2fc38_1 .net v0x9b2fc38 1, 31 0, v0x9a85828_0; 1 drivers |
v0x9b2fc38_2 .net v0x9b2fc38 2, 31 0, v0x9ab17f0_0; 1 drivers |
v0x9b2fc38_3 .net v0x9b2fc38 3, 31 0, v0x9ae4498_0; 1 drivers |
v0x9b2fb88 .array "mem", 0 9, 31 0; |
v0x9b2fb88_0 .array/port v0x9b2fb88, 0; |
v0x9b2fd40_0 .net "mem0", 31 0, v0x9b2fb88_0; 1 drivers |
v0x9b2fb88_1 .array/port v0x9b2fb88, 1; |
v0x9b2fc88_0 .net "mem1", 31 0, v0x9b2fb88_1; 1 drivers |
v0x9b2fb88_2 .array/port v0x9b2fb88, 2; |
v0x9b2fcd8_0 .net "mem2", 31 0, v0x9b2fb88_2; 1 drivers |
v0x9b2fb88_3 .array/port v0x9b2fb88, 3; |
v0x9b2fe58_0 .net "mem3", 31 0, v0x9b2fb88_3; 1 drivers |
v0x9b2fb88_4 .array/port v0x9b2fb88, 4; |
v0x9b2fea8_0 .net "mem4", 31 0, v0x9b2fb88_4; 1 drivers |
v0x9b2fb88_5 .array/port v0x9b2fb88, 5; |
v0x9b2fd90_0 .net "mem5", 31 0, v0x9b2fb88_5; 1 drivers |
v0x9b2fb88_6 .array/port v0x9b2fb88, 6; |
v0x9b2fdf0_0 .net "mem6", 31 0, v0x9b2fb88_6; 1 drivers |
v0x9b2fb88_7 .array/port v0x9b2fb88, 7; |
v0x9b2ffd0_0 .net "mem7", 31 0, v0x9b2fb88_7; 1 drivers |
v0x9b2fb88_8 .array/port v0x9b2fb88, 8; |
v0x9b30020_0 .net "mem8", 31 0, v0x9b2fb88_8; 1 drivers |
v0x9b2fb88_9 .array/port v0x9b2fb88, 9; |
v0x9b2fef8_0 .net "mem9", 31 0, v0x9b2fb88_9; 1 drivers |
v0x9b2ff58_0 .var "mem_access", 0 0; |
v0x9b30158_0 .var/i "n", 31 0; |
v0x9b301a8_0 .var/i "p", 31 0; |
v0x9b30080_0 .var "rst", 0 0; |
v0x9b300d0_0 .var/i "seed", 31 0; |
v0x9b302f0 .array "stat_cpu_access_nop", 0 3, 31 0; |
v0x9b30340 .array "stat_cpu_access_rd", 0 3, 31 0; |
v0x9b301f8 .array "stat_cpu_access_wr", 0 3, 31 0; |
v0x9b30248_0 .var "stimulus_addr", 7 0; |
v0x9b30498_0 .var "stimulus_nop_period", 7 0; |
v0x9b304e8_0 .var "stimulus_op", 1 0; |
v0x9b30390_0 .var "stimulus_rand_cpu_select", 1 0; |
v0x9b303f0 .array/i "stimulus_rand_numb", 0 9, 31 0; |
v0x9b30440_0 .net "tb_ins0", 3 0, L_0x9b31518; 1 drivers |
v0x9b30650_0 .net "tb_ins1", 3 0, L_0x9b31460; 1 drivers |
v0x9b30538_0 .net "tb_ins2", 3 0, L_0x9b31310; 1 drivers |
v0x9b30598_0 .net "tb_ins3", 3 0, L_0x9b313b8; 1 drivers |
RS_0x9b0f8ec .resolv tri, L_0x9b3fd50, L_0x9b40828, L_0x9b413e0, L_0x9b41ea8; |
v0x9b305f8_0 .net8 "tb_ins_ack", 3 0, RS_0x9b0f8ec; 4 drivers |
v0x9b30950_0 .array/port v0x9b30950, 0; |
v0x9b307c8_0 .net "tb_ins_addr0", 3 0, v0x9b30950_0; 1 drivers |
v0x9b30950_1 .array/port v0x9b30950, 1; |
v0x9b306a0_0 .net "tb_ins_addr1", 3 0, v0x9b30950_1; 1 drivers |
v0x9b30950_2 .array/port v0x9b30950, 2; |
v0x9b306f0_0 .net "tb_ins_addr2", 3 0, v0x9b30950_2; 1 drivers |
v0x9b30950_3 .array/port v0x9b30950, 3; |
v0x9b30740_0 .net "tb_ins_addr3", 3 0, v0x9b30950_3; 1 drivers |
v0x9b30950 .array "tb_ins_addr_array", 0 3, 3 0; |
v0x9b30818 .array "tb_ins_array", 0 3, 3 0; |
v0x9b30868 .array "tb_ins_nop_period", 0 3, 7 0; |
v0x9b30868_0 .array/port v0x9b30868, 0; |
v0x9b308c8_0 .net "tb_ins_nop_period0", 7 0, v0x9b30868_0; 1 drivers |
v0x9b30868_1 .array/port v0x9b30868, 1; |
v0x9b30ae8_0 .net "tb_ins_nop_period1", 7 0, v0x9b30868_1; 1 drivers |
v0x9b30868_2 .array/port v0x9b30868, 2; |
v0x9b309a0_0 .net "tb_ins_nop_period2", 7 0, v0x9b30868_2; 1 drivers |
v0x9b30868_3 .array/port v0x9b30868, 3; |
v0x9b30a00_0 .net "tb_ins_nop_period3", 7 0, v0x9b30868_3; 1 drivers |
E_0x99e4598/0 .event edge, v0x9b2a318_0, v0x9b2a2c8_0, v0x9aecad8_0, v0x9afcf38_0; |
E_0x99e4598/1 .event edge, v0x9a45e00_0, v0x9a45da0_0, v0x9b23e30_0, v0x9b23dd0_0; |
E_0x99e4598/2 .event edge, v0x9b249b0_0, v0x9b24950_0; |
E_0x99e4598 .event/or E_0x99e4598/0, E_0x99e4598/1, E_0x99e4598/2; |
v0x9b2a368_0 .array/port v0x9b2a368, 0; |
L_0x9b30a70 .concat [ 41 1 0 0], v0x9b2a368_0, C4<0>; |
v0x9b2a368_1 .array/port v0x9b2a368, 1; |
L_0x9b30ce8 .concat [ 41 1 0 0], v0x9b2a368_1, C4<0>; |
v0x9b2a368_2 .array/port v0x9b2a368, 2; |
L_0x9b30db0 .part v0x9b2a368_2, 0, 1; |
v0x9b2a368_3 .array/port v0x9b2a368, 3; |
L_0x9b30e20 .part v0x9b2a368_3, 0, 1; |
L_0x9b31e70 .part v0x9b2f8f0_0, 24, 8; |
L_0x9b31ee0 .part v0x9b2f8f0_0, 16, 8; |
L_0x9b31f70 .part v0x9b2f8f0_0, 8, 8; |
L_0x9b31fe0 .part v0x9b2f8f0_0, 0, 8; |
L_0x9b3f2e0 .part/pv L_0x9b3f138, 3, 1, 4; |
L_0x9b3f330 .part/pv L_0x9b3f188, 2, 1, 4; |
L_0x9b3f380 .part/pv L_0x9b3f240, 1, 1, 4; |
L_0x9b3f438 .part/pv L_0x9b3f290, 0, 1, 4; |
L_0x9b3fb98 .part L_0x9aa2688, 3, 1; |
L_0x9b3fd50 .part/pv v0x9accfa0_0, 3, 1, 4; |
L_0x9b40688 .part L_0x9aa2688, 2, 1; |
L_0x9b40828 .part/pv v0x9abe1e0_0, 2, 1, 4; |
L_0x9b411d8 .part L_0x9aa2688, 1, 1; |
L_0x9b413e0 .part/pv v0x9a847b0_0, 1, 1, 4; |
L_0x9b41d08 .part L_0x9aa2688, 0, 1; |
L_0x9b41ea8 .part/pv v0x9ab8958_0, 0, 1, 4; |
S_0x9b2e710 .scope task, "sanity_check_cache_status" "sanity_check_cache_status" 3 116, 3 116, S_0x9aed928; |
.timescale -9 -12; |
v0x9b2e790_0 .var "mbus_addr", 31 0; |
v0x9b2e7e0_0 .var "num_of_lines_in_m_e_state", 1 0; |
TD_mesi_isc_tb.sanity_check_cache_status ; |
%set/v v0x9b2e7e0_0, 0, 2; |
%ix/getv 3, v0x9b2e790_0; |
%load/av 8, v0x9adce38, 4; |
%cmpi/u 8, 5, 4; |
%mov 8, 4, 1; |
%ix/getv 3, v0x9b2e790_0; |
%load/av 9, v0x9adce38, 4; |
%cmpi/u 9, 9, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_0.0, 8; |
%load/v 8, v0x9b2e7e0_0, 2; |
%mov 10, 0, 30; |
%addi 8, 1, 32; |
%set/v v0x9b2e7e0_0, 8, 2; |
T_0.0 ; |
%ix/getv 3, v0x9b2e790_0; |
%load/av 8, v0x9a817f8, 4; |
%cmpi/u 8, 5, 4; |
%mov 8, 4, 1; |
%ix/getv 3, v0x9b2e790_0; |
%load/av 9, v0x9a817f8, 4; |
%cmpi/u 9, 9, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_0.2, 8; |
%load/v 8, v0x9b2e7e0_0, 2; |
%mov 10, 0, 30; |
%addi 8, 1, 32; |
%set/v v0x9b2e7e0_0, 8, 2; |
T_0.2 ; |
%ix/getv 3, v0x9b2e790_0; |
%load/av 8, v0x9aa9f48, 4; |
%cmpi/u 8, 5, 4; |
%mov 8, 4, 1; |
%ix/getv 3, v0x9b2e790_0; |
%load/av 9, v0x9aa9f48, 4; |
%cmpi/u 9, 9, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_0.4, 8; |
%load/v 8, v0x9b2e7e0_0, 2; |
%mov 10, 0, 30; |
%addi 8, 1, 32; |
%set/v v0x9b2e7e0_0, 8, 2; |
T_0.4 ; |
%ix/getv 3, v0x9b2e790_0; |
%load/av 8, v0x9aee678, 4; |
%cmpi/u 8, 5, 4; |
%mov 8, 4, 1; |
%ix/getv 3, v0x9b2e790_0; |
%load/av 9, v0x9aee678, 4; |
%cmpi/u 9, 9, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_0.6, 8; |
%load/v 8, v0x9b2e7e0_0, 2; |
%mov 10, 0, 30; |
%addi 8, 1, 32; |
%set/v v0x9b2e7e0_0, 8, 2; |
T_0.6 ; |
%movi 8, 1, 3; |
%load/v 11, v0x9b2e7e0_0, 2; |
%mov 13, 0, 1; |
%cmp/u 8, 11, 3; |
%jmp/0xz T_0.8, 5; |
%vpi_call 3 148 "$display", "Error 6. %d of cache lines are in M or E state. time:%d\012", v0x9b2e7e0_0, $time; |
%wait E_0x9aece10; |
%vpi_call 3 151 "$finish"; |
T_0.8 ; |
%end; |
S_0x9b2e550 .scope task, "sanity_check_rule1_rule2" "sanity_check_rule1_rule2" 3 79, 3 79, S_0x9aed928; |
.timescale -9 -12; |
v0x9b2e5d0_0 .var "cpu_id", 3 0; |
v0x9b2e620_0 .var "cur_mem_data", 31 0; |
v0x9b2e670_0 .var "mbus_addr", 31 0; |
v0x9b2e6c0_0 .var "mbus_wr_data", 31 0; |
TD_mesi_isc_tb.sanity_check_rule1_rule2 ; |
%ix/getv 3, v0x9b2e670_0; |
%load/av 8, v0x9b2fb88, 32; |
%set/v v0x9b2e620_0, 8, 32; |
%ix/load 1, 24, 0; |
%mov 4, 0, 1; |
%jmp/1 T_1.10, 4; |
%load/x1p 8, v0x9b2e6c0_0, 8; |
%jmp T_1.11; |
T_1.10 ; |
%mov 8, 2, 8; |
T_1.11 ; |
; Save base=8 wid=8 in lookaside. |
%ix/load 1, 24, 0; |
%mov 4, 0, 1; |
%jmp/1 T_1.12, 4; |
%load/x1p 16, v0x9b2e620_0, 8; |
%jmp T_1.13; |
T_1.12 ; |
%mov 16, 2, 8; |
T_1.13 ; |
; Save base=16 wid=8 in lookaside. |
%cmp/u 8, 16, 8; |
%mov 8, 5, 1; |
%ix/load 1, 16, 0; |
%mov 4, 0, 1; |
%jmp/1 T_1.14, 4; |
%load/x1p 9, v0x9b2e6c0_0, 8; |
%jmp T_1.15; |
T_1.14 ; |
%mov 9, 2, 8; |
T_1.15 ; |
; Save base=9 wid=8 in lookaside. |
%ix/load 1, 16, 0; |
%mov 4, 0, 1; |
%jmp/1 T_1.16, 4; |
%load/x1p 17, v0x9b2e620_0, 8; |
%jmp T_1.17; |
T_1.16 ; |
%mov 17, 2, 8; |
T_1.17 ; |
; Save base=17 wid=8 in lookaside. |
%cmp/u 9, 17, 8; |
%mov 9, 5, 1; |
%or 8, 9, 1; |
%ix/load 1, 8, 0; |
%mov 4, 0, 1; |
%jmp/1 T_1.18, 4; |
%load/x1p 9, v0x9b2e6c0_0, 8; |
%jmp T_1.19; |
T_1.18 ; |
%mov 9, 2, 8; |
T_1.19 ; |
; Save base=9 wid=8 in lookaside. |
%ix/load 1, 8, 0; |
%mov 4, 0, 1; |
%jmp/1 T_1.20, 4; |
%load/x1p 17, v0x9b2e620_0, 8; |
%jmp T_1.21; |
T_1.20 ; |
%mov 17, 2, 8; |
T_1.21 ; |
; Save base=17 wid=8 in lookaside. |
%cmp/u 9, 17, 8; |
%mov 9, 5, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9b2e6c0_0, 8; Only need 8 of 32 bits |
; Save base=9 wid=8 in lookaside. |
%load/v 17, v0x9b2e620_0, 8; Only need 8 of 32 bits |
; Save base=17 wid=8 in lookaside. |
%cmp/u 9, 17, 8; |
%mov 9, 5, 1; |
%or 8, 9, 1; |
%jmp/0xz T_1.22, 8; |
%vpi_call 3 95 "$display", "ERROR 7. The current memory data is bigger then the written data\012"; |
%vpi_call 3 96 "$display", " CPU: %h, Cur data: %h, Written data: %h, Address: %h, time:%d\012", v0x9b2e5d0_0, v0x9b2e620_0, v0x9b2e6c0_0, v0x9b2e670_0, $time; |
%wait E_0x9aece10; |
%vpi_call 3 102 "$finish"; |
T_1.22 ; |
%end; |
S_0x9aed7c0 .scope module, "mesi_isc" "mesi_isc" 2 425, 4 48, S_0x9aed928; |
.timescale -9 -12; |
P_0x9aec92c .param/l "ADDR_WIDTH" 4 79, +C4<0100000>; |
P_0x9aec940 .param/l "BREQ_FIFO_SIZE" 4 85, +C4<010>; |
P_0x9aec954 .param/l "BREQ_FIFO_SIZE_LOG2" 4 86, +C4<01>; |
P_0x9aec968 .param/l "BROAD_ID_WIDTH" 4 81, +C4<0101>; |
P_0x9aec97c .param/l "BROAD_REQ_FIFO_SIZE" 4 82, +C4<0100>; |
P_0x9aec990 .param/l "BROAD_REQ_FIFO_SIZE_LOG2" 4 83, +C4<010>; |
P_0x9aec9a4 .param/l "BROAD_TYPE_WIDTH" 4 80, +C4<010>; |
P_0x9aec9b8 .param/l "CBUS_CMD_WIDTH" 4 78, +C4<011>; |
P_0x9aec9cc .param/l "MBUS_CMD_WIDTH" 4 84, +C4<011>; |
v0x9b2d9f8_0 .net "broad_addr", 31 0, L_0x9b37fe8; 1 drivers |
v0x9b2da48_0 .net "broad_cpu_id", 1 0, L_0x9b397a0; 1 drivers |
v0x9b2da98_0 .net "broad_fifo_status_full", 0 0, L_0x9b32118; 1 drivers |
v0x9b2dae8_0 .net "broad_fifo_wr", 0 0, L_0x9b35ce0; 1 drivers |
v0x9b2dba0_0 .net "broad_id", 4 0, L_0x9b3a3c8; 1 drivers |
v0x9b2dbf0_0 .net "broad_type", 1 0, L_0x9b38ba0; 1 drivers |
v0x9b2dc40_0 .alias "cbus_ack0_i", 0 0, v0x9b2ea30_0; |
v0x9b2dc90_0 .alias "cbus_ack1_i", 0 0, v0x9b2ea80_0; |
v0x9b2dce0_0 .alias "cbus_ack2_i", 0 0, v0x9b2eb08_0; |
v0x9b2dd30_0 .alias "cbus_ack3_i", 0 0, v0x9b2eb90_0; |
v0x9b2dd80_0 .alias "cbus_addr_o", 31 0, v0x9b2ec18_0; |
v0x9b2ddd0_0 .alias "cbus_cmd0_o", 2 0, v0x9b2ec68_0; |
v0x9b2de20_0 .alias "cbus_cmd1_o", 2 0, v0x9b2ed28_0; |
v0x9b2de70_0 .alias "cbus_cmd2_o", 2 0, v0x9b2edb0_0; |
v0x9b2dee0_0 .alias "cbus_cmd3_o", 2 0, v0x9b2ee00_0; |
v0x9b2df50_0 .net "clk", 0 0, v0x9b2ee88_0; 1 drivers |
v0x9b2dfe8_0 .net "mbus_ack0_o", 0 0, L_0x9b3f290; 1 drivers |
v0x9b2e038_0 .net "mbus_ack1_o", 0 0, L_0x9b3f240; 1 drivers |
v0x9b2e0d8_0 .net "mbus_ack2_o", 0 0, L_0x9b3f188; 1 drivers |
v0x9b2e128_0 .net "mbus_ack3_o", 0 0, L_0x9b3f138; 1 drivers |
v0x9b2e088_0 .alias "mbus_addr0_i", 31 0, v0x9b2f4e8_0; |
v0x9b2e1d0_0 .alias "mbus_addr1_i", 31 0, v0x9b2f4e8_1; |
v0x9b2e178_0 .alias "mbus_addr2_i", 31 0, v0x9b2f4e8_2; |
v0x9b2e2a0_0 .alias "mbus_addr3_i", 31 0, v0x9b2f4e8_3; |
v0x9b2e358_0 .alias "mbus_cmd0_i", 2 0, v0x9b2f6d0_0; |
v0x9b2e3a8_0 .alias "mbus_cmd1_i", 2 0, v0x9b2f6d0_1; |
v0x9b2e2f0_0 .alias "mbus_cmd2_i", 2 0, v0x9b2f6d0_2; |
v0x9b2e488_0 .alias "mbus_cmd3_i", 2 0, v0x9b2f6d0_3; |
v0x9b2e418_0 .net "rst", 0 0, v0x9b30080_0; 1 drivers |
L_0x9b35908 .concat [ 1 1 1 1], v0x9aeda88_0, v0x9a94c98_0, v0x9ab4888_0, v0x9a84e58_0; |
RS_0x9b0f1b4 .resolv tri, L_0x9b321b8, L_0x9b32278, L_0x9b32338, L_0x9b32448; |
L_0x9b35958 .part RS_0x9b0f1b4, 9, 3; |
L_0x9b359a8 .part RS_0x9b0f1b4, 6, 3; |
L_0x9b359f8 .part RS_0x9b0f1b4, 3, 3; |
L_0x9b32388 .part RS_0x9b0f1b4, 0, 3; |
L_0x9b3ed58 .concat [ 3 3 3 3], v0x9abfbf0_0, v0x9a852b8_0, v0x9aa02c8_0, v0x9ace888_0; |
L_0x9b3ef48 .concat [ 32 32 32 32], v0x9adc1f0_0, v0x9a87238_0, v0x9aa0278_0, v0x9ab7f98_0; |
L_0x9b3f138 .part L_0x9b2d5d0, 3, 1; |
L_0x9b3f188 .part L_0x9b2d5d0, 2, 1; |
L_0x9b3f240 .part L_0x9b2d5d0, 1, 1; |
L_0x9b3f290 .part L_0x9b2d5d0, 0, 1; |
S_0x9b29d40 .scope module, "mesi_isc_broad" "mesi_isc_broad" 4 141, 5 48, S_0x9aed7c0; |
.timescale -9 -12; |
P_0x9b29dc4 .param/l "ADDR_WIDTH" 5 66, +C4<0100000>; |
P_0x9b29dd8 .param/l "BROAD_ID_WIDTH" 5 68, +C4<0101>; |
P_0x9b29dec .param/l "BROAD_REQ_FIFO_SIZE" 5 69, +C4<0100>; |
P_0x9b29e00 .param/l "BROAD_REQ_FIFO_SIZE_LOG2" 5 70, +C4<010>; |
P_0x9b29e14 .param/l "BROAD_TYPE_WIDTH" 5 67, +C4<010>; |
P_0x9b29e28 .param/l "CBUS_CMD_WIDTH" 5 65, +C4<011>; |
L_0x9b2f7b0 .functor BUFZ 32, L_0x9b35760, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b32118 .functor BUFZ 1, v0x9b2a838_0, C4<0>, C4<0>, C4<0>; |
v0x9b2d038_0 .alias "broad_addr_i", 31 0, v0x9b2d9f8_0; |
v0x9b2d088_0 .alias "broad_cpu_id_i", 1 0, v0x9b2da48_0; |
v0x9b2d110_0 .net "broad_fifo_rd", 0 0, v0x9b2c9a8_0; 1 drivers |
v0x9b2d3a0_0 .alias "broad_fifo_wr_i", 0 0, v0x9b2dae8_0; |
v0x9b2d3f0_0 .alias "broad_id_i", 4 0, v0x9b2dba0_0; |
v0x9b2d440_0 .net "broad_snoop_addr", 31 0, L_0x9b35760; 1 drivers |
v0x9b2d490_0 .net "broad_snoop_cpu_id", 1 0, L_0x9b35800; 1 drivers |
v0x9b2d4e0_0 .net "broad_snoop_id", 4 0, L_0x9b35850; 1 drivers |
v0x9b2d530_0 .net "broad_snoop_type", 1 0, L_0x9b357b0; 1 drivers |
v0x9b2d580_0 .alias "broad_type_i", 1 0, v0x9b2dbf0_0; |
v0x9b2d608_0 .net "cbus_ack_array_i", 3 0, L_0x9b35908; 1 drivers |
v0x9b2d658_0 .alias "cbus_addr_o", 31 0, v0x9b2ec18_0; |
v0x9b2d748_0 .net8 "cbus_cmd_array_o", 11 0, RS_0x9b0f1b4; 4 drivers |
v0x9b2d798_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9b2d7e8_0 .net "fifo_status_empty", 0 0, v0x9b2a778_0; 1 drivers |
v0x9b2d838_0 .net "fifo_status_full", 0 0, v0x9b2a838_0; 1 drivers |
v0x9b2d8d0_0 .alias "fifo_status_full_o", 0 0, v0x9b2da98_0; |
v0x9b2d958_0 .alias "rst", 0 0, v0x9b2e418_0; |
L_0x9b35570 .concat [ 5 2 2 32], L_0x9b3a3c8, L_0x9b397a0, L_0x9b38ba0, L_0x9b37fe8; |
L_0x9b35760 .part v0x9b2a278_0, 9, 32; |
L_0x9b357b0 .part v0x9b2a278_0, 7, 2; |
L_0x9b35800 .part v0x9b2a278_0, 5, 2; |
L_0x9b35850 .part v0x9b2a278_0, 0, 5; |
S_0x9b2a9c0 .scope module, "mesi_isc_broad_cntl" "mesi_isc_broad_cntl" 5 116, 6 48, S_0x9b29d40; |
.timescale -9 -12; |
P_0x9b2a88c .param/l "BROAD_ID_WIDTH" 6 66, +C4<0101>; |
P_0x9b2a8a0 .param/l "BROAD_TYPE_WIDTH" 6 65, +C4<010>; |
P_0x9b2a8b4 .param/l "CBUS_CMD_WIDTH" 6 64, +C4<011>; |
L_0x9b32208 .functor BUFZ 3, L_0x9b32f08, C4<000>, C4<000>, C4<000>; |
L_0x9b322c8 .functor BUFZ 3, L_0x9b339d8, C4<000>, C4<000>, C4<000>; |
L_0x9b2d920 .functor BUFZ 3, L_0x9b34228, C4<000>, C4<000>, C4<000>; |
L_0x9b324b8 .functor BUFZ 3, L_0x9b34d60, C4<000>, C4<000>, C4<000>; |
L_0x9b329f0 .functor AND 1, L_0x9b32918, L_0x9b329a0, C4<1>, C4<1>; |
L_0x9b32a98 .functor NOT 1, v0x9b2c9a8_0, C4<0>, C4<0>, C4<0>; |
L_0x9b32ad0 .functor AND 1, L_0x9b329f0, L_0x9b32a98, C4<1>, C4<1>; |
L_0x9b33388 .functor AND 1, L_0x9b333d8, L_0x9b33428, C4<1>, C4<1>; |
L_0x9b33568 .functor NOT 1, v0x9b2c9a8_0, C4<0>, C4<0>, C4<0>; |
L_0x9b33608 .functor AND 1, L_0x9b33388, L_0x9b33568, C4<1>, C4<1>; |
L_0x9b2faf0 .functor AND 1, L_0x9b33c10, L_0x9b33d98, C4<1>, C4<1>; |
L_0x9b33e68 .functor NOT 1, v0x9b2c9a8_0, C4<0>, C4<0>, C4<0>; |
L_0x9b33ed8 .functor AND 1, L_0x9b2faf0, L_0x9b33e68, C4<1>, C4<1>; |
L_0x9b33130 .functor AND 1, L_0x9b33320, L_0x9b34558, C4<1>, C4<1>; |
L_0x9b33ea0 .functor NOT 1, v0x9b2c9a8_0, C4<0>, C4<0>, C4<0>; |
L_0x9b349a0 .functor AND 1, L_0x9b33130, L_0x9b33ea0, C4<1>, C4<1>; |
L_0x9b34ea0 .functor NOT 4, L_0x9b35908, C4<0000>, C4<0000>, C4<0000>; |
L_0x9b34f10 .functor AND 4, v0x9b2ccd8_0, L_0x9b34ea0, C4<1111>, C4<1111>; |
v0x9b2aab0_0 .net *"_s100", 0 0, L_0x9b33b88; 1 drivers |
v0x9b2ab10_0 .net *"_s102", 2 0, C4<001>; 1 drivers |
v0x9b2ab70_0 .net *"_s104", 2 0, C4<010>; 1 drivers |
v0x9b2abd0_0 .net *"_s106", 2 0, L_0x9b33c80; 1 drivers |
v0x9b2ac20_0 .net *"_s109", 0 0, L_0x9b33cd0; 1 drivers |
v0x9b2ac80_0 .net *"_s11", 2 0, L_0x9b2d920; 1 drivers |
v0x9b2ace0_0 .net *"_s111", 0 0, L_0x9b33c10; 1 drivers |
v0x9b2ad40_0 .net *"_s113", 0 0, L_0x9b33d98; 1 drivers |
v0x9b2adc8_0 .net *"_s114", 0 0, L_0x9b2faf0; 1 drivers |
v0x9b2ae28_0 .net *"_s116", 0 0, L_0x9b33e68; 1 drivers |
v0x9b2ae88_0 .net *"_s118", 0 0, L_0x9b33ed8; 1 drivers |
v0x9b2aee8_0 .net *"_s120", 1 0, C4<01>; 1 drivers |
v0x9b2af80_0 .net *"_s122", 0 0, L_0x9b2cd88; 1 drivers |
v0x9b2afe0_0 .net *"_s124", 2 0, C4<011>; 1 drivers |
v0x9b2b040_0 .net *"_s126", 2 0, C4<100>; 1 drivers |
v0x9b2b0a0_0 .net *"_s128", 2 0, L_0x9b33f80; 1 drivers |
v0x9b2b148_0 .net *"_s130", 2 0, C4<000>; 1 drivers |
v0x9b2b1a8_0 .net *"_s132", 2 0, L_0x9b34130; 1 drivers |
v0x9b2b248_0 .net *"_s137", 0 0, L_0x9b34378; 1 drivers |
v0x9b2b298_0 .net *"_s138", 1 0, C4<01>; 1 drivers |
v0x9b2b1f8_0 .net *"_s140", 0 0, L_0x9b34010; 1 drivers |
v0x9b2b340_0 .net *"_s142", 2 0, C4<001>; 1 drivers |
v0x9b2b3f0_0 .net *"_s144", 2 0, C4<010>; 1 drivers |
v0x9b2b440_0 .net *"_s146", 2 0, L_0x9b342a0; 1 drivers |
v0x9b2b390_0 .net *"_s149", 0 0, L_0x9b34698; 1 drivers |
v0x9b2b4f8_0 .net *"_s15", 2 0, L_0x9b324b8; 1 drivers |
v0x9b2b490_0 .net *"_s151", 0 0, L_0x9b33320; 1 drivers |
v0x9b2b5b8_0 .net *"_s153", 0 0, L_0x9b34558; 1 drivers |
v0x9b2b548_0 .net *"_s154", 0 0, L_0x9b33130; 1 drivers |
v0x9b2b680_0 .net *"_s156", 0 0, L_0x9b33ea0; 1 drivers |
v0x9b2b608_0 .net *"_s158", 0 0, L_0x9b349a0; 1 drivers |
v0x9b2b750_0 .net *"_s160", 1 0, C4<01>; 1 drivers |
v0x9b2b6d0_0 .net *"_s162", 0 0, L_0x9b34a90; 1 drivers |
v0x9b2b828_0 .net *"_s164", 2 0, C4<011>; 1 drivers |
v0x9b2b7a0_0 .net *"_s166", 2 0, C4<100>; 1 drivers |
v0x9b2b908_0 .net *"_s168", 2 0, L_0x9b34b40; 1 drivers |
v0x9b2b878_0 .net *"_s17", 0 0, L_0x9b32528; 1 drivers |
v0x9b2b9f0_0 .net *"_s170", 2 0, C4<000>; 1 drivers |
v0x9b2b958_0 .net *"_s172", 2 0, L_0x9b34c68; 1 drivers |
v0x9b2bae0_0 .net *"_s176", 3 0, L_0x9b34ea0; 1 drivers |
v0x9b2ba40_0 .net *"_s18", 1 0, C4<01>; 1 drivers |
v0x9b2bbd8_0 .net *"_s20", 0 0, L_0x9b32600; 1 drivers |
v0x9b2bb30_0 .net *"_s22", 2 0, C4<001>; 1 drivers |
v0x9b2bcd8_0 .net *"_s24", 2 0, C4<010>; 1 drivers |
v0x9b2bc28_0 .net *"_s26", 2 0, L_0x9b32750; 1 drivers |
v0x9b2bc78_0 .net *"_s29", 0 0, L_0x9b32868; 1 drivers |
v0x9b2bde8_0 .net *"_s3", 2 0, L_0x9b32208; 1 drivers |
v0x9b2be38_0 .net *"_s31", 0 0, L_0x9b32918; 1 drivers |
v0x9b2bd28_0 .net *"_s33", 0 0, L_0x9b329a0; 1 drivers |
v0x9b2bd88_0 .net *"_s34", 0 0, L_0x9b329f0; 1 drivers |
v0x9b2bf58_0 .net *"_s36", 0 0, L_0x9b32a98; 1 drivers |
v0x9b2bfa8_0 .net *"_s38", 0 0, L_0x9b32ad0; 1 drivers |
v0x9b2be88_0 .net *"_s40", 1 0, C4<01>; 1 drivers |
v0x9b2bee8_0 .net *"_s42", 0 0, L_0x9b32b78; 1 drivers |
v0x9b2c0d8_0 .net *"_s44", 2 0, C4<011>; 1 drivers |
v0x9b2c128_0 .net *"_s46", 2 0, C4<100>; 1 drivers |
v0x9b2bff8_0 .net *"_s48", 2 0, L_0x9b32cb8; 1 drivers |
v0x9b2c058_0 .net *"_s50", 2 0, C4<000>; 1 drivers |
v0x9b2c268_0 .net *"_s52", 2 0, L_0x9b32e10; 1 drivers |
v0x9b2c2b8_0 .net *"_s57", 0 0, L_0x9b33000; 1 drivers |
v0x9b2c178_0 .net *"_s58", 1 0, C4<01>; 1 drivers |
v0x9b2c1d8_0 .net *"_s60", 0 0, L_0x9b33078; 1 drivers |
v0x9b2c408_0 .net *"_s62", 2 0, C4<001>; 1 drivers |
v0x9b2c458_0 .net *"_s64", 2 0, C4<010>; 1 drivers |
v0x9b2c308_0 .net *"_s66", 2 0, L_0x9b331d8; 1 drivers |
v0x9b2c368_0 .net *"_s69", 0 0, L_0x9b332d0; 1 drivers |
v0x9b2c5b8_0 .net *"_s7", 2 0, L_0x9b322c8; 1 drivers |
v0x9b2c608_0 .net *"_s71", 0 0, L_0x9b333d8; 1 drivers |
v0x9b2c4a8_0 .net *"_s73", 0 0, L_0x9b33428; 1 drivers |
v0x9b2c4f8_0 .net *"_s74", 0 0, L_0x9b33388; 1 drivers |
v0x9b2c558_0 .net *"_s76", 0 0, L_0x9b33568; 1 drivers |
v0x9b2c778_0 .net *"_s78", 0 0, L_0x9b33608; 1 drivers |
v0x9b2c658_0 .net *"_s80", 1 0, C4<01>; 1 drivers |
v0x9b2c6b8_0 .net *"_s82", 0 0, L_0x9b336b0; 1 drivers |
v0x9b2c718_0 .net *"_s84", 2 0, C4<011>; 1 drivers |
v0x9b2c8f8_0 .net *"_s86", 2 0, C4<100>; 1 drivers |
v0x9b2c7c8_0 .net *"_s88", 2 0, L_0x9b33788; 1 drivers |
v0x9b2c828_0 .net *"_s90", 2 0, C4<000>; 1 drivers |
v0x9b2c888_0 .net *"_s92", 2 0, L_0x9b338e0; 1 drivers |
v0x9b2ca88_0 .net *"_s97", 0 0, L_0x9b33b38; 1 drivers |
v0x9b2c948_0 .net *"_s98", 1 0, C4<01>; 1 drivers |
v0x9b2c9a8_0 .var "broad_fifo_rd_o", 0 0; |
v0x9b2c9f8_0 .alias "broad_snoop_cpu_id_i", 1 0, v0x9b2d490_0; |
v0x9b2cc28_0 .alias "broad_snoop_id_i", 4 0, v0x9b2d4e0_0; |
v0x9b2cad8_0 .alias "broad_snoop_type_i", 1 0, v0x9b2d530_0; |
v0x9b2cb28_0 .var "broadcast_in_progress", 0 0; |
v0x9b2cb88_0 .alias "cbus_ack_array_i", 3 0, v0x9b2d608_0; |
v0x9b2cdd8_0 .var "cbus_active_broad_array", 3 0; |
v0x9b2cc78_0 .net "cbus_active_en_access_and_not_cbus_ack_array", 3 0, L_0x9b34f10; 1 drivers |
v0x9b2ccd8_0 .var "cbus_active_en_access_array", 3 0; |
v0x9b2cd38_0 .net "cbus_cmd0", 2 0, L_0x9b34d60; 1 drivers |
v0x9b2cf98_0 .net "cbus_cmd1", 2 0, L_0x9b34228; 1 drivers |
v0x9b2ce28_0 .net "cbus_cmd2", 2 0, L_0x9b339d8; 1 drivers |
v0x9b2ce88_0 .net "cbus_cmd3", 2 0, L_0x9b32f08; 1 drivers |
v0x9b2cee8_0 .alias "cbus_cmd_array_o", 11 0, v0x9b2d748_0; |
v0x9b2cf48_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9b2d170_0 .alias "fifo_status_empty_i", 0 0, v0x9b2d7e8_0; |
v0x9b2d1c0_0 .alias "fifo_status_full_i", 0 0, v0x9b2d838_0; |
v0x9b2cfe8_0 .alias "rst", 0 0, v0x9b2e418_0; |
L_0x9b321b8 .part/pv L_0x9b32208, 9, 3, 12; |
L_0x9b32278 .part/pv L_0x9b322c8, 6, 3, 12; |
L_0x9b32338 .part/pv L_0x9b2d920, 3, 3, 12; |
L_0x9b32448 .part/pv L_0x9b324b8, 0, 3, 12; |
L_0x9b32528 .part v0x9b2cdd8_0, 3, 1; |
L_0x9b32600 .cmp/eq 2, L_0x9b357b0, C4<01>; |
L_0x9b32750 .functor MUXZ 3, C4<010>, C4<001>, L_0x9b32600, C4<>; |
L_0x9b32868 .reduce/or v0x9b2cdd8_0; |
L_0x9b32918 .reduce/nor L_0x9b32868; |
L_0x9b329a0 .part v0x9b2ccd8_0, 3, 1; |
L_0x9b32b78 .cmp/eq 2, L_0x9b357b0, C4<01>; |
L_0x9b32cb8 .functor MUXZ 3, C4<100>, C4<011>, L_0x9b32b78, C4<>; |
L_0x9b32e10 .functor MUXZ 3, C4<000>, L_0x9b32cb8, L_0x9b32ad0, C4<>; |
L_0x9b32f08 .functor MUXZ 3, L_0x9b32e10, L_0x9b32750, L_0x9b32528, C4<>; |
L_0x9b33000 .part v0x9b2cdd8_0, 2, 1; |
L_0x9b33078 .cmp/eq 2, L_0x9b357b0, C4<01>; |
L_0x9b331d8 .functor MUXZ 3, C4<010>, C4<001>, L_0x9b33078, C4<>; |
L_0x9b332d0 .reduce/or v0x9b2cdd8_0; |
L_0x9b333d8 .reduce/nor L_0x9b332d0; |
L_0x9b33428 .part v0x9b2ccd8_0, 2, 1; |
L_0x9b336b0 .cmp/eq 2, L_0x9b357b0, C4<01>; |
L_0x9b33788 .functor MUXZ 3, C4<100>, C4<011>, L_0x9b336b0, C4<>; |
L_0x9b338e0 .functor MUXZ 3, C4<000>, L_0x9b33788, L_0x9b33608, C4<>; |
L_0x9b339d8 .functor MUXZ 3, L_0x9b338e0, L_0x9b331d8, L_0x9b33000, C4<>; |
L_0x9b33b38 .part v0x9b2cdd8_0, 1, 1; |
L_0x9b33b88 .cmp/eq 2, L_0x9b357b0, C4<01>; |
L_0x9b33c80 .functor MUXZ 3, C4<010>, C4<001>, L_0x9b33b88, C4<>; |
L_0x9b33cd0 .reduce/or v0x9b2cdd8_0; |
L_0x9b33c10 .reduce/nor L_0x9b33cd0; |
L_0x9b33d98 .part v0x9b2ccd8_0, 1, 1; |
L_0x9b2cd88 .cmp/eq 2, L_0x9b357b0, C4<01>; |
L_0x9b33f80 .functor MUXZ 3, C4<100>, C4<011>, L_0x9b2cd88, C4<>; |
L_0x9b34130 .functor MUXZ 3, C4<000>, L_0x9b33f80, L_0x9b33ed8, C4<>; |
L_0x9b34228 .functor MUXZ 3, L_0x9b34130, L_0x9b33c80, L_0x9b33b38, C4<>; |
L_0x9b34378 .part v0x9b2cdd8_0, 0, 1; |
L_0x9b34010 .cmp/eq 2, L_0x9b357b0, C4<01>; |
L_0x9b342a0 .functor MUXZ 3, C4<010>, C4<001>, L_0x9b34010, C4<>; |
L_0x9b34698 .reduce/or v0x9b2cdd8_0; |
L_0x9b33320 .reduce/nor L_0x9b34698; |
L_0x9b34558 .part v0x9b2ccd8_0, 0, 1; |
L_0x9b34a90 .cmp/eq 2, L_0x9b357b0, C4<01>; |
L_0x9b34b40 .functor MUXZ 3, C4<100>, C4<011>, L_0x9b34a90, C4<>; |
L_0x9b34c68 .functor MUXZ 3, C4<000>, L_0x9b34b40, L_0x9b349a0, C4<>; |
L_0x9b34d60 .functor MUXZ 3, L_0x9b34c68, L_0x9b342a0, L_0x9b34378, C4<>; |
S_0x9b29eb8 .scope module, "broad_fifo" "mesi_isc_basic_fifo" 5 147, 7 49, S_0x9b29d40; |
.timescale -9 -12; |
P_0x9b29f3c .param/l "DATA_WIDTH" 7 63, +C4<0101001>; |
P_0x9b29f50 .param/l "FIFO_SIZE" 7 64, +C4<0100>; |
P_0x9b29f64 .param/l "FIFO_SIZE_LOG2" 7 65, +C4<010>; |
L_0x9af4948 .functor AND 1, L_0x9b35ce0, L_0x9b35328, C4<1>, C4<1>; |
L_0x9b35400 .functor AND 1, L_0x9b353b0, v0x9b2c9a8_0, C4<1>, C4<1>; |
v0x9b29ff8_0 .net *"_s0", 31 0, L_0x9b34fd0; 1 drivers |
v0x9b2a048_0 .net *"_s15", 0 0, L_0x9b35328; 1 drivers |
v0x9b2a098_0 .net *"_s19", 0 0, L_0x9b353b0; 1 drivers |
v0x9b2a0e8_0 .net *"_s3", 29 0, C4<000000000000000000000000000000>; 1 drivers |
v0x9b2a138_0 .net *"_s4", 31 0, C4<00000000000000000000000000000001>; 1 drivers |
v0x9b2a188_0 .net *"_s6", 31 0, L_0x9b345a8; 1 drivers |
v0x9b2a1d8_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9b2a228_0 .net "data_i", 40 0, L_0x9b35570; 1 drivers |
v0x9b2a278_0 .var "data_o", 40 0; |
v0x9b2a2c8_0 .var "dbg_fifo_overflow", 0 0; |
v0x9b2a318_0 .var "dbg_fifo_underflow", 0 0; |
v0x9b2a368 .array "entry", 0 3, 40 0; |
v0x9b2a3b8_0 .net "fifo_depth", 1 0, L_0x9b335a0; 1 drivers |
v0x9b2a418_0 .net "fifo_depth_decrease", 0 0, L_0x9b35400; 1 drivers |
v0x9b2a478_0 .net "fifo_depth_increase", 0 0, L_0x9af4948; 1 drivers |
v0x9b2a4d8_0 .var/i "i", 31 0; |
v0x9b2a580_0 .var "ptr_rd", 1 0; |
v0x9b2a5e0_0 .net "ptr_rd_plus_1", 1 0, L_0x9b351c8; 1 drivers |
v0x9b2a680_0 .var "ptr_wr", 1 0; |
v0x9b2a6d0_0 .alias "rd_i", 0 0, v0x9b2d110_0; |
v0x9b2a630_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9b2a778_0 .var "status_empty", 0 0; |
v0x9b2a720_0 .alias "status_empty_o", 0 0, v0x9b2d7e8_0; |
v0x9b2a838_0 .var "status_full", 0 0; |
v0x9b2a7d8_0 .alias "status_full_o", 0 0, v0x9b2d838_0; |
v0x9b2a900_0 .alias "wr_i", 0 0, v0x9b2dae8_0; |
L_0x9b34fd0 .concat [ 2 30 0 0], v0x9b2a580_0, C4<000000000000000000000000000000>; |
L_0x9b345a8 .arith/sum 32, L_0x9b34fd0, C4<00000000000000000000000000000001>; |
L_0x9b351c8 .part L_0x9b345a8, 0, 2; |
L_0x9b35328 .reduce/nor v0x9b2c9a8_0; |
L_0x9b353b0 .reduce/nor L_0x9b35ce0; |
L_0x9b335a0 .arith/sub 2, v0x9b2a680_0, v0x9b2a580_0; |
S_0x9a826d8 .scope module, "mesi_isc_breq_fifos" "mesi_isc_breq_fifos" 4 174, 8 68, S_0x9aed7c0; |
.timescale -9 -12; |
P_0x9a8275c .param/l "ADDR_WIDTH" 8 87, +C4<0100000>; |
P_0x9a82770 .param/l "BREQ_FIFO_SIZE" 8 90, +C4<010>; |
P_0x9a82784 .param/l "BREQ_FIFO_SIZE_LOG2" 8 91, +C4<01>; |
P_0x9a82798 .param/l "BROAD_ID_WIDTH" 8 89, +C4<0101>; |
P_0x9a827ac .param/l "BROAD_TYPE_WIDTH" 8 88, +C4<010>; |
P_0x9a827c0 .param/l "MBUS_CMD_WIDTH" 8 86, +C4<011>; |
v0x9a126a0_0 .net *"_s100", 1 0, L_0x9b3e3f0; 1 drivers |
v0x9b28a08_0 .net *"_s102", 1 0, L_0x9b3e460; 1 drivers |
v0x9b28a58_0 .net *"_s104", 4 0, L_0x9b3e530; 1 drivers |
v0x9b28aa8_0 .net *"_s107", 31 0, L_0x9b3e7c0; 1 drivers |
v0x9b28af8_0 .net *"_s109", 1 0, L_0x9b3e810; 1 drivers |
v0x9b28b48_0 .net *"_s11", 4 0, L_0x9b3b6d0; 1 drivers |
v0x9b28b98_0 .net *"_s111", 1 0, L_0x9b3eac8; 1 drivers |
v0x9b28be8_0 .net *"_s113", 4 0, L_0x9b3eb50; 1 drivers |
v0x9b28c38_0 .net *"_s14", 31 0, L_0x9b3b990; 1 drivers |
v0x9b28c88_0 .net *"_s16", 1 0, L_0x9b3ba50; 1 drivers |
v0x9b28cd8_0 .net *"_s18", 1 0, L_0x9b3bb10; 1 drivers |
v0x9b28d28_0 .net *"_s20", 4 0, L_0x9b3bbd8; 1 drivers |
v0x9b28d78_0 .net *"_s36", 31 0, L_0x9b3c470; 1 drivers |
v0x9b28dc8_0 .net *"_s38", 1 0, L_0x9b3c3d0; 1 drivers |
v0x9b28e18_0 .net *"_s40", 1 0, L_0x9b3c518; 1 drivers |
v0x9b28e68_0 .net *"_s42", 4 0, L_0x9b3c4c0; 1 drivers |
v0x9b28eb8_0 .net *"_s45", 31 0, L_0x9b3c778; 1 drivers |
v0x9b28f08_0 .net *"_s47", 1 0, L_0x9b3c920; 1 drivers |
v0x9b28fa8_0 .net *"_s49", 1 0, L_0x9b3c870; 1 drivers |
v0x9b28ff8_0 .net *"_s5", 31 0, L_0x9b3b5e0; 1 drivers |
v0x9b28f58_0 .net *"_s51", 4 0, L_0x9b3ca98; 1 drivers |
v0x9b290a0_0 .net *"_s67", 31 0, L_0x9b3cc98; 1 drivers |
v0x9b29048_0 .net *"_s69", 1 0, L_0x9b3d310; 1 drivers |
v0x9b29150_0 .net *"_s7", 1 0, L_0x9b3b630; 1 drivers |
v0x9b290f0_0 .net *"_s71", 1 0, L_0x9b3d278; 1 drivers |
v0x9b29208_0 .net *"_s73", 4 0, L_0x9b3a8d8; 1 drivers |
v0x9b291a0_0 .net *"_s76", 31 0, L_0x9b3d648; 1 drivers |
v0x9b292c8_0 .net *"_s78", 1 0, L_0x9b3d7f0; 1 drivers |
v0x9b29258_0 .net *"_s80", 1 0, L_0x9b3d9a0; 1 drivers |
v0x9b29390_0 .net *"_s82", 4 0, L_0x9b3dae8; 1 drivers |
v0x9b29318_0 .net *"_s9", 1 0, L_0x9b3b680; 1 drivers |
v0x9b29460_0 .net *"_s98", 31 0, L_0x9b3de78; 1 drivers |
RS_0x9b0e0a4 .resolv tri, L_0x9b3a5c0, L_0x9b3a648, L_0x9b39398, L_0x9b3a7d8; |
v0x9b293e0_0 .net8 "breq_cpu_id_array", 7 0, RS_0x9b0e0a4; 4 drivers |
RS_0x9b0e0bc .resolv tri, L_0x9b3a888, L_0x9b3abd0, L_0x9b3ab68, L_0x9b3a988; |
v0x9b29538_0 .net8 "breq_id_array", 19 0, RS_0x9b0e0bc; 4 drivers |
v0x9b294b0_0 .net "breq_type_array", 7 0, v0x9b27d90_0; 1 drivers |
RS_0x9b0e104 .resolv tri, L_0x9b3b850, L_0x9b3c568, L_0x9b3d6d8, L_0x9b3e630; |
v0x9b29618_0 .net8 "broad_addr_array", 127 0, RS_0x9b0e104; 4 drivers |
v0x9b29588_0 .alias "broad_addr_o", 31 0, v0x9b2d9f8_0; |
RS_0x9b0e65c .resolv tri, L_0x9b3b8f0, L_0x9b3c6c0, L_0x9b389c0, L_0x9b3e8b8; |
v0x9b29700_0 .net8 "broad_cpu_id_array", 7 0, RS_0x9b0e65c; 4 drivers |
v0x9b29668_0 .alias "broad_cpu_id_o", 1 0, v0x9b2da48_0; |
v0x9b297f0_0 .alias "broad_fifo_status_full_i", 0 0, v0x9b2da98_0; |
v0x9b29750_0 .alias "broad_fifo_wr_o", 0 0, v0x9b2dae8_0; |
RS_0x9b0e17c .resolv tri, L_0x9b3b940, L_0x9b3c820, L_0x9b3d5f8, L_0x9b3e970; |
v0x9b297a0_0 .net8 "broad_id_array", 19 0, RS_0x9b0e17c; 4 drivers |
v0x9b298f0_0 .alias "broad_id_o", 4 0, v0x9b2dba0_0; |
RS_0x9b0e1ac .resolv tri, L_0x9b3b8a0, L_0x9b3c728, L_0x9b374a8, L_0x9b3e680; |
v0x9b29940_0 .net8 "broad_type_array", 7 0, RS_0x9b0e1ac; 4 drivers |
v0x9b29840_0 .alias "broad_type_o", 1 0, v0x9b2dbf0_0; |
v0x9b29890_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9b29a50_0 .net "fifo_rd_array", 3 0, L_0x9b35bd0; 1 drivers |
RS_0x9b0e20c .resolv tri, L_0x9b3bc90, L_0x9b3c9e0, L_0x9b3dd10, L_0x9b3e9c0; |
v0x9b29aa0_0 .net8 "fifo_status_empty_array", 3 0, RS_0x9b0e20c; 4 drivers |
RS_0x9b0e224 .resolv tri, L_0x9b3bd28, L_0x9b3cc10, L_0x9b364f8, L_0x9b3ea10; |
v0x9b29990_0 .net8 "fifo_status_full_array", 3 0, RS_0x9b0e224; 4 drivers |
v0x9b29a00_0 .net "fifo_wr_array", 3 0, L_0x9b3a470; 1 drivers |
v0x9b29bc0_0 .net "mbus_ack_array_o", 3 0, L_0x9b2d5d0; 1 drivers |
v0x9b29c10_0 .net "mbus_addr_array_i", 127 0, L_0x9b3ef48; 1 drivers |
v0x9b29af0_0 .net "mbus_cmd_array_i", 11 0, L_0x9b3ed58; 1 drivers |
v0x9b29b60_0 .alias "rst", 0 0, v0x9b2e418_0; |
L_0x9b3b4d8 .part L_0x9b3a470, 3, 1; |
L_0x9b3b528 .part L_0x9b35bd0, 3, 1; |
L_0x9b3b5e0 .part L_0x9b3ef48, 96, 32; |
L_0x9b3b630 .part v0x9b27d90_0, 6, 2; |
L_0x9b3b680 .part RS_0x9b0e0a4, 6, 2; |
L_0x9b3b6d0 .part RS_0x9b0e0bc, 15, 5; |
L_0x9b3b720 .concat [ 5 2 2 32], L_0x9b3b6d0, L_0x9b3b680, L_0x9b3b630, L_0x9b3b5e0; |
L_0x9b3b850 .part/pv L_0x9b3b990, 96, 32, 128; |
L_0x9b3b8a0 .part/pv L_0x9b3ba50, 6, 2, 8; |
L_0x9b3b8f0 .part/pv L_0x9b3bb10, 6, 2, 8; |
L_0x9b3b940 .part/pv L_0x9b3bbd8, 15, 5, 20; |
L_0x9b3b990 .part v0x9b248f0_0, 9, 32; |
L_0x9b3ba50 .part v0x9b248f0_0, 7, 2; |
L_0x9b3bb10 .part v0x9b248f0_0, 5, 2; |
L_0x9b3bbd8 .part v0x9b248f0_0, 0, 5; |
L_0x9b3bc90 .part/pv v0x9b24e20_0, 3, 1, 4; |
L_0x9b3bd28 .part/pv v0x9b24ee0_0, 3, 1, 4; |
L_0x9b3c318 .part L_0x9b3a470, 2, 1; |
L_0x9b3c420 .part L_0x9b35bd0, 2, 1; |
L_0x9b3c470 .part L_0x9b3ef48, 64, 32; |
L_0x9b3c3d0 .part v0x9b27d90_0, 4, 2; |
L_0x9b3c518 .part RS_0x9b0e0a4, 4, 2; |
L_0x9b3c4c0 .part RS_0x9b0e0bc, 10, 5; |
L_0x9b3c5c8 .concat [ 5 2 2 32], L_0x9b3c4c0, L_0x9b3c518, L_0x9b3c3d0, L_0x9b3c470; |
L_0x9b3c568 .part/pv L_0x9b3c778, 64, 32, 128; |
L_0x9b3c728 .part/pv L_0x9b3c920, 4, 2, 8; |
L_0x9b3c6c0 .part/pv L_0x9b3c870, 4, 2, 8; |
L_0x9b3c820 .part/pv L_0x9b3ca98, 10, 5, 20; |
L_0x9b3c778 .part v0x9b23d70_0, 9, 32; |
L_0x9b3c920 .part v0x9b23d70_0, 7, 2; |
L_0x9b3c870 .part v0x9b23d70_0, 5, 2; |
L_0x9b3ca98 .part v0x9b23d70_0, 0, 5; |
L_0x9b3c9e0 .part/pv v0x9b242a0_0, 2, 1, 4; |
L_0x9b3cc10 .part/pv v0x9b24360_0, 2, 1, 4; |
L_0x9b3d1d8 .part L_0x9b3a470, 1, 1; |
L_0x9b3d228 .part L_0x9b35bd0, 1, 1; |
L_0x9b3cc98 .part L_0x9b3ef48, 32, 32; |
L_0x9b3d310 .part v0x9b27d90_0, 2, 2; |
L_0x9b3d278 .part RS_0x9b0e0a4, 2, 2; |
L_0x9b3a8d8 .part RS_0x9b0e0bc, 5, 5; |
L_0x9b3ad50 .concat [ 5 2 2 32], L_0x9b3a8d8, L_0x9b3d278, L_0x9b3d310, L_0x9b3cc98; |
L_0x9b3d6d8 .part/pv L_0x9b3d648, 32, 32, 128; |
L_0x9b374a8 .part/pv L_0x9b3d7f0, 2, 2, 8; |
L_0x9b389c0 .part/pv L_0x9b3d9a0, 2, 2, 8; |
L_0x9b3d5f8 .part/pv L_0x9b3dae8, 5, 5, 20; |
L_0x9b3d648 .part v0x99e85a8_0, 9, 32; |
L_0x9b3d7f0 .part v0x99e85a8_0, 7, 2; |
L_0x9b3d9a0 .part v0x99e85a8_0, 5, 2; |
L_0x9b3dae8 .part v0x99e85a8_0, 0, 5; |
L_0x9b3dd10 .part/pv v0x9b237d0_0, 1, 1, 4; |
L_0x9b364f8 .part/pv v0x9b23880_0, 1, 1, 4; |
L_0x9b3e3a0 .part L_0x9b3a470, 0, 1; |
L_0x9b3de28 .part L_0x9b35bd0, 0, 1; |
L_0x9b3de78 .part L_0x9b3ef48, 0, 32; |
L_0x9b3e3f0 .part v0x9b27d90_0, 0, 2; |
L_0x9b3e460 .part RS_0x9b0e0a4, 0, 2; |
L_0x9b3e530 .part RS_0x9b0e0bc, 0, 5; |
L_0x9b3e5a0 .concat [ 5 2 2 32], L_0x9b3e530, L_0x9b3e460, L_0x9b3e3f0, L_0x9b3de78; |
L_0x9b3e630 .part/pv L_0x9b3e7c0, 0, 32, 128; |
L_0x9b3e680 .part/pv L_0x9b3e810, 0, 2, 8; |
L_0x9b3e8b8 .part/pv L_0x9b3eac8, 0, 2, 8; |
L_0x9b3e970 .part/pv L_0x9b3eb50, 0, 5, 20; |
L_0x9b3e7c0 .part v0x9afced8_0, 9, 32; |
L_0x9b3e810 .part v0x9afced8_0, 7, 2; |
L_0x9b3eac8 .part v0x9afced8_0, 5, 2; |
L_0x9b3eb50 .part v0x9afced8_0, 0, 5; |
L_0x9b3e9c0 .part/pv v0x9a34b68_0, 0, 1, 4; |
L_0x9b3ea10 .part/pv v0x9a34c18_0, 0, 1, 4; |
S_0x9b25068 .scope module, "mesi_isc_breq_fifos_cntl" "mesi_isc_breq_fifos_cntl" 8 142, 9 50, S_0x9a826d8; |
.timescale -9 -12; |
P_0x9b24f44 .param/l "ADDR_WIDTH" 9 78, +C4<0100000>; |
P_0x9b24f58 .param/l "BROAD_ID_WIDTH" 9 80, +C4<0101>; |
P_0x9b24f6c .param/l "BROAD_TYPE_WIDTH" 9 79, +C4<010>; |
P_0x9b24f80 .param/l "MBUS_CMD_WIDTH" 9 77, +C4<011>; |
L_0x9b2d5d0 .functor BUFZ 4, v0x9b28370_0, C4<0000>, C4<0000>, C4<0000>; |
L_0x9b35b48 .functor NOT 1, L_0x9b32118, C4<0>, C4<0>, C4<0>; |
L_0x9b35bd0 .functor AND 4, L_0x9b35b80, L_0x9b36a50, C4<1111>, C4<1111>; |
L_0x9b361b8 .functor NOT 4, RS_0x9b0e20c, C4<0000>, C4<0000>, C4<0000>; |
L_0x9b36228 .functor AND 4, L_0x9b361b8, v0x9b28178_0, C4<1111>, C4<1111>; |
L_0x9b36358 .functor NOT 4, RS_0x9b0e20c, C4<0000>, C4<0000>, C4<0000>; |
L_0x9b36390 .functor AND 4, L_0x9b36358, L_0x9b360f8, C4<1111>, C4<1111>; |
L_0x9b364c0 .functor NOT 4, RS_0x9b0e20c, C4<0000>, C4<0000>, C4<0000>; |
L_0x9b361f0 .functor AND 4, L_0x9b364c0, L_0x9b35fd0, C4<1111>, C4<1111>; |
L_0x9b36320 .functor NOT 4, RS_0x9b0e20c, C4<0000>, C4<0000>, C4<0000>; |
L_0x9b36680 .functor AND 4, L_0x9b36320, L_0x9b35e08, C4<1111>, C4<1111>; |
L_0x9b34960 .functor AND 32, L_0x9b35f68, L_0x9b36ca0, C4<11111111111111111111111111111111>, C4<11111111111111111111111111111111>; |
L_0x9b36aa0 .functor AND 32, L_0x9b36e48, L_0x9b36d78, C4<11111111111111111111111111111111>, C4<11111111111111111111111111111111>; |
L_0x9b37370 .functor OR 32, L_0x9b34960, L_0x9b36aa0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b36c10 .functor AND 32, L_0x9b37458, L_0x9b37580, C4<11111111111111111111111111111111>, C4<11111111111111111111111111111111>; |
L_0x9b37510 .functor OR 32, L_0x9b37370, L_0x9b36c10, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b37418 .functor AND 32, L_0x9b37ab0, L_0x9b379b8, C4<11111111111111111111111111111111>, C4<11111111111111111111111111111111>; |
L_0x9b37fe8 .functor OR 32, L_0x9b37510, L_0x9b37418, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; |
L_0x9b38168 .functor AND 2, L_0x9b380e0, L_0x9b37b50, C4<11>, C4<11>; |
L_0x9b385a8 .functor AND 2, L_0x9b38638, L_0x9b36ee8, C4<11>, C4<11>; |
L_0x9b38090 .functor OR 2, L_0x9b38168, L_0x9b385a8, C4<00>, C4<00>; |
L_0x9b387f0 .functor AND 2, L_0x9b38970, L_0x9b38ac8, C4<11>, C4<11>; |
L_0x9b388a8 .functor OR 2, L_0x9b38090, L_0x9b387f0, C4<00>, C4<00>; |
L_0x9b38de0 .functor AND 2, L_0x9b38c90, L_0x9b38b18, C4<11>, C4<11>; |
L_0x9b38ba0 .functor OR 2, L_0x9b388a8, L_0x9b38de0, C4<00>, C4<00>; |
L_0x9b38d80 .functor AND 2, C4<11>, L_0x9b38d30, C4<11>, C4<11>; |
L_0x9b39210 .functor AND 2, C4<10>, L_0x9b38fb8, C4<11>, C4<11>; |
L_0x9b392b8 .functor OR 2, L_0x9b38d80, L_0x9b39210, C4<00>, C4<00>; |
L_0x9b391b8 .functor AND 2, C4<01>, L_0x9b39130, C4<11>, C4<11>; |
L_0x9b39538 .functor OR 2, L_0x9b392b8, L_0x9b391b8, C4<00>, C4<00>; |
L_0x9b394d0 .functor AND 2, C4<00>, L_0x9b39448, C4<11>, C4<11>; |
L_0x9b397a0 .functor OR 2, L_0x9b39538, L_0x9b394d0, C4<00>, C4<00>; |
L_0x9b396d0 .functor AND 5, L_0x9b395e0, L_0x9b39680, C4<11111>, C4<11111>; |
L_0x9b38728 .functor AND 5, L_0x9b39978, L_0x9b386d8, C4<11111>, C4<11111>; |
L_0x9b39ae8 .functor OR 5, L_0x9b396d0, L_0x9b38728, C4<00000>, C4<00000>; |
L_0x9b398d0 .functor AND 5, L_0x9b39e78, L_0x9b39d50, C4<11111>, C4<11111>; |
L_0x9b39dd8 .functor OR 5, L_0x9b39ae8, L_0x9b398d0, C4<00000>, C4<00000>; |
L_0x9b3a0d8 .functor AND 5, L_0x9b3a1b8, L_0x9b3a088, C4<11111>, C4<11111>; |
L_0x9b3a3c8 .functor OR 5, L_0x9b39dd8, L_0x9b3a0d8, C4<00000>, C4<00000>; |
L_0x9b3a470 .functor BUFZ 4, v0x9b28370_0, C4<0000>, C4<0000>, C4<0000>; |
v0x9b251b0_0 .net *"_s101", 1 0, L_0x9b380e0; 1 drivers |
v0x9b25210_0 .net *"_s103", 0 0, L_0x9b381f0; 1 drivers |
v0x9b25270_0 .net *"_s104", 1 0, L_0x9b37b50; 1 drivers |
v0x9b252d0_0 .net *"_s106", 1 0, L_0x9b38168; 1 drivers |
v0x9b25320_0 .net *"_s109", 1 0, L_0x9b38638; 1 drivers |
v0x9b25380_0 .net *"_s11", 0 0, L_0x9b35d30; 1 drivers |
v0x9b253e0_0 .net *"_s111", 0 0, L_0x9b38688; 1 drivers |
v0x9b25440_0 .net *"_s112", 1 0, L_0x9b36ee8; 1 drivers |
v0x9b254c8_0 .net *"_s114", 1 0, L_0x9b385a8; 1 drivers |
v0x9b25528_0 .net *"_s116", 1 0, L_0x9b38090; 1 drivers |
v0x9b25588_0 .net *"_s119", 1 0, L_0x9b38970; 1 drivers |
v0x9b255e8_0 .net *"_s121", 0 0, L_0x9b387a0; 1 drivers |
v0x9b25648_0 .net *"_s122", 1 0, L_0x9b38ac8; 1 drivers |
v0x9b256a8_0 .net *"_s124", 1 0, L_0x9b387f0; 1 drivers |
v0x9b25708_0 .net *"_s126", 1 0, L_0x9b388a8; 1 drivers |
v0x9b25768_0 .net *"_s129", 1 0, L_0x9b38c90; 1 drivers |
v0x9b25810_0 .net *"_s13", 2 0, L_0x9b35d80; 1 drivers |
v0x9b25870_0 .net *"_s131", 0 0, L_0x9b38ce0; 1 drivers |
v0x9b25910_0 .net *"_s132", 1 0, L_0x9b38b18; 1 drivers |
v0x9b25960_0 .net *"_s134", 1 0, L_0x9b38de0; 1 drivers |
v0x9b258c0_0 .net *"_s138", 1 0, C4<11>; 1 drivers |
v0x9b25a08_0 .net *"_s141", 0 0, L_0x9b350d0; 1 drivers |
v0x9b25ab8_0 .net *"_s142", 1 0, L_0x9b38d30; 1 drivers |
v0x9b25b08_0 .net *"_s144", 1 0, L_0x9b38d80; 1 drivers |
v0x9b25a58_0 .net *"_s146", 1 0, C4<10>; 1 drivers |
v0x9b25bc0_0 .net *"_s149", 0 0, L_0x9b38e88; 1 drivers |
v0x9b25b58_0 .net *"_s150", 1 0, L_0x9b38fb8; 1 drivers |
v0x9b25c80_0 .net *"_s152", 1 0, L_0x9b39210; 1 drivers |
v0x9b25c10_0 .net *"_s154", 1 0, L_0x9b392b8; 1 drivers |
v0x9b25d48_0 .net *"_s156", 1 0, C4<01>; 1 drivers |
v0x9b25cd0_0 .net *"_s159", 0 0, L_0x9b390e0; 1 drivers |
v0x9b25e18_0 .net *"_s160", 1 0, L_0x9b39130; 1 drivers |
v0x9b25d98_0 .net *"_s162", 1 0, L_0x9b391b8; 1 drivers |
v0x9b25ef0_0 .net *"_s164", 1 0, L_0x9b39538; 1 drivers |
v0x9b25e68_0 .net *"_s166", 1 0, C4<00>; 1 drivers |
v0x9b25fd0_0 .net *"_s169", 0 0, L_0x9b393f8; 1 drivers |
v0x9b25f40_0 .net *"_s17", 1 0, L_0x9b35ec8; 1 drivers |
v0x9b260b8_0 .net *"_s170", 1 0, L_0x9b39448; 1 drivers |
v0x9b26020_0 .net *"_s172", 1 0, L_0x9b394d0; 1 drivers |
v0x9b261a8_0 .net *"_s177", 4 0, L_0x9b395e0; 1 drivers |
v0x9b26108_0 .net *"_s179", 0 0, L_0x9b39630; 1 drivers |
v0x9b262a0_0 .net *"_s180", 4 0, L_0x9b39680; 1 drivers |
v0x9b261f8_0 .net *"_s182", 4 0, L_0x9b396d0; 1 drivers |
v0x9b263a0_0 .net *"_s185", 4 0, L_0x9b39978; 1 drivers |
v0x9b262f0_0 .net *"_s187", 0 0, L_0x9b39b28; 1 drivers |
v0x9b26340_0 .net *"_s188", 4 0, L_0x9b386d8; 1 drivers |
v0x9b264b0_0 .net *"_s19", 1 0, L_0x9b35f18; 1 drivers |
v0x9b26500_0 .net *"_s190", 4 0, L_0x9b38728; 1 drivers |
v0x9b263f0_0 .net *"_s192", 4 0, L_0x9b39ae8; 1 drivers |
v0x9b26450_0 .net *"_s195", 4 0, L_0x9b39e78; 1 drivers |
v0x9b26620_0 .net *"_s197", 0 0, L_0x9b39d00; 1 drivers |
v0x9b26670_0 .net *"_s198", 4 0, L_0x9b39d50; 1 drivers |
v0x9b26550_0 .net *"_s2", 0 0, L_0x9b35b48; 1 drivers |
v0x9b265b0_0 .net *"_s200", 4 0, L_0x9b398d0; 1 drivers |
v0x9b267a0_0 .net *"_s202", 4 0, L_0x9b39dd8; 1 drivers |
v0x9b267f0_0 .net *"_s205", 4 0, L_0x9b3a1b8; 1 drivers |
v0x9b266c0_0 .net *"_s207", 0 0, L_0x9b3a208; 1 drivers |
v0x9b26720_0 .net *"_s208", 4 0, L_0x9b3a088; 1 drivers |
v0x9b26930_0 .net *"_s210", 4 0, L_0x9b3a0d8; 1 drivers |
v0x9b26980_0 .net/s *"_s226", 1 0, C4<11>; 1 drivers |
v0x9b26840_0 .net *"_s23", 2 0, L_0x9b36058; 1 drivers |
v0x9b268a0_0 .net/s *"_s230", 1 0, C4<10>; 1 drivers |
v0x9b26ad0_0 .net/s *"_s234", 1 0, C4<01>; 1 drivers |
v0x9b26b20_0 .net/s *"_s238", 1 0, C4<00>; 1 drivers |
v0x9b269d0_0 .net *"_s242", 1 0, C4<00>; 1 drivers |
v0x9b26a30_0 .net *"_s244", 4 0, L_0x9b3aa00; 1 drivers |
v0x9b26c80_0 .net *"_s248", 1 0, C4<01>; 1 drivers |
v0x9b26cd0_0 .net *"_s25", 0 0, L_0x9b360a8; 1 drivers |
v0x9b26b70_0 .net *"_s250", 4 0, L_0x9b3aaa8; 1 drivers |
v0x9b26bc0_0 .net *"_s254", 1 0, C4<10>; 1 drivers |
v0x9b26c20_0 .net *"_s256", 4 0, L_0x9b3acd8; 1 drivers |
v0x9b26e40_0 .net *"_s260", 1 0, C4<11>; 1 drivers |
v0x9b26d20_0 .net *"_s262", 4 0, L_0x9b3aef8; 1 drivers |
v0x9b26d80_0 .net *"_s28", 3 0, L_0x9b361b8; 1 drivers |
v0x9b26de0_0 .net *"_s30", 3 0, L_0x9b36228; 1 drivers |
v0x9b26fc0_0 .net *"_s33", 0 0, L_0x9b36298; 1 drivers |
v0x9b26e90_0 .net *"_s34", 3 0, L_0x9b36358; 1 drivers |
v0x9b26ef0_0 .net *"_s36", 3 0, L_0x9b36390; 1 drivers |
v0x9b26f50_0 .net *"_s39", 0 0, L_0x9b36438; 1 drivers |
v0x9b27150_0 .net *"_s4", 3 0, L_0x9b35b80; 1 drivers |
v0x9b27010_0 .net *"_s40", 3 0, L_0x9b364c0; 1 drivers |
v0x9b27070_0 .net *"_s42", 3 0, L_0x9b361f0; 1 drivers |
v0x9b270d0_0 .net *"_s45", 0 0, L_0x9b365f8; 1 drivers |
v0x9b272f0_0 .net *"_s46", 3 0, L_0x9b36320; 1 drivers |
v0x9b271a0_0 .net *"_s48", 3 0, L_0x9b36680; 1 drivers |
v0x9b271f0_0 .net *"_s51", 0 0, L_0x9b36728; 1 drivers |
v0x9b27250_0 .net *"_s52", 3 0, C4<0000>; 1 drivers |
v0x9b274a0_0 .net *"_s54", 3 0, L_0x9b367b0; 1 drivers |
v0x9b27340_0 .net *"_s56", 3 0, L_0x9b368b8; 1 drivers |
v0x9b27390_0 .net *"_s58", 3 0, L_0x9b36978; 1 drivers |
v0x9b273f0_0 .net *"_s63", 31 0, L_0x9b35f68; 1 drivers |
v0x9b27450_0 .net *"_s65", 0 0, L_0x9b369c8; 1 drivers |
v0x9b27668_0 .net *"_s66", 31 0, L_0x9b36ca0; 1 drivers |
v0x9b276b8_0 .net *"_s68", 31 0, L_0x9b34960; 1 drivers |
v0x9b274f0_0 .net *"_s71", 31 0, L_0x9b36e48; 1 drivers |
v0x9b27540_0 .net *"_s73", 0 0, L_0x9b36e98; 1 drivers |
v0x9b275a0_0 .net *"_s74", 31 0, L_0x9b36d78; 1 drivers |
v0x9b27600_0 .net *"_s76", 31 0, L_0x9b36aa0; 1 drivers |
v0x9b27898_0 .net *"_s78", 31 0, L_0x9b37370; 1 drivers |
v0x9b278e8_0 .net *"_s81", 31 0, L_0x9b37458; 1 drivers |
v0x9b27708_0 .net *"_s83", 0 0, L_0x9b36f50; 1 drivers |
v0x9b27768_0 .net *"_s84", 31 0, L_0x9b37580; 1 drivers |
v0x9b277c8_0 .net *"_s86", 31 0, L_0x9b36c10; 1 drivers |
v0x9b27828_0 .net *"_s88", 31 0, L_0x9b37510; 1 drivers |
v0x9b27ae0_0 .net *"_s91", 31 0, L_0x9b37ab0; 1 drivers |
v0x9b27b30_0 .net *"_s93", 0 0, L_0x9b37b00; 1 drivers |
v0x9b27938_0 .net *"_s94", 31 0, L_0x9b379b8; 1 drivers |
v0x9b27998_0 .net *"_s96", 31 0, L_0x9b37418; 1 drivers |
v0x9b279f8_0 .alias "breq_cpu_id_array_o", 7 0, v0x9b293e0_0; |
v0x9b27a58_0 .alias "breq_id_array_o", 19 0, v0x9b29538_0; |
v0x9b27d40_0 .var "breq_id_base", 2 0; |
v0x9b27d90_0 .var "breq_type_array_o", 7 0; |
v0x9b27b80_0 .alias "broad_addr_array_i", 127 0, v0x9b29618_0; |
v0x9b27be0_0 .alias "broad_addr_o", 31 0, v0x9b2d9f8_0; |
v0x9b27c40_0 .alias "broad_cpu_id_o", 1 0, v0x9b2da48_0; |
v0x9b27ca0_0 .alias "broad_fifo_status_full_i", 0 0, v0x9b2da98_0; |
v0x9b27fb8_0 .alias "broad_fifo_wr_o", 0 0, v0x9b2dae8_0; |
v0x9b28008_0 .alias "broad_id_array_i", 19 0, v0x9b297a0_0; |
v0x9b27de0_0 .alias "broad_id_o", 4 0, v0x9b2dba0_0; |
v0x9b27e40_0 .alias "broad_type_array_i", 7 0, v0x9b29940_0; |
v0x9b27ea0_0 .alias "broad_type_o", 1 0, v0x9b2dbf0_0; |
v0x9b27f00_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9b27f50_0 .alias "fifo_rd_array_o", 3 0, v0x9b29a50_0; |
v0x9abb3a0_0 .net "fifo_select_oh", 3 0, L_0x9b36a50; 1 drivers |
v0x9b28058_0 .alias "fifo_status_empty_array_i", 3 0, v0x9b29aa0_0; |
v0x9b280b8_0 .alias "fifo_status_full_array_i", 3 0, v0x9b29990_0; |
v0x9b28118_0 .alias "fifo_wr_array_o", 3 0, v0x9b29a00_0; |
v0x9b28178_0 .var "fifos_priority", 3 0; |
v0x9b281d8_0 .net "fifos_priority_barrel_shiftl_1", 3 0, L_0x9b360f8; 1 drivers |
v0x9b28518_0 .net "fifos_priority_barrel_shiftl_2", 3 0, L_0x9b35fd0; 1 drivers |
v0x9b28310_0 .net "fifos_priority_barrel_shiftl_3", 3 0, L_0x9b35e08; 1 drivers |
v0x9b28370_0 .var "mbus_ack_array", 3 0; |
v0x9b283d0_0 .alias "mbus_ack_array_o", 3 0, v0x9b29bc0_0; |
v0x9b28430_0 .alias "mbus_cmd_array_i", 11 0, v0x9b29af0_0; |
v0x9b28490_0 .net "mbus_cmd_array_i_0", 2 0, L_0x9b3a2f8; 1 drivers |
v0x9b28788_0 .net "mbus_cmd_array_i_1", 2 0, L_0x9b3a2a8; 1 drivers |
v0x9b28568_0 .net "mbus_cmd_array_i_2", 2 0, L_0x9b3a258; 1 drivers |
v0x9b285c8_0 .net "mbus_cmd_array_i_3", 2 0, L_0x9b39f68; 1 drivers |
v0x9b28628_0 .alias "rst", 0 0, v0x9b2e418_0; |
L_0x9b35b80 .concat [ 1 1 1 1], L_0x9b35b48, L_0x9b35b48, L_0x9b35b48, L_0x9b35b48; |
L_0x9b35ce0 .reduce/or L_0x9b35bd0; |
L_0x9b35d30 .part v0x9b28178_0, 0, 1; |
L_0x9b35d80 .part v0x9b28178_0, 1, 3; |
L_0x9b35e08 .concat [ 3 1 0 0], L_0x9b35d80, L_0x9b35d30; |
L_0x9b35ec8 .part v0x9b28178_0, 0, 2; |
L_0x9b35f18 .part v0x9b28178_0, 2, 2; |
L_0x9b35fd0 .concat [ 2 2 0 0], L_0x9b35f18, L_0x9b35ec8; |
L_0x9b36058 .part v0x9b28178_0, 0, 3; |
L_0x9b360a8 .part v0x9b28178_0, 3, 1; |
L_0x9b360f8 .concat [ 1 3 0 0], L_0x9b360a8, L_0x9b36058; |
L_0x9b36298 .reduce/or L_0x9b36228; |
L_0x9b36438 .reduce/or L_0x9b36390; |
L_0x9b365f8 .reduce/or L_0x9b361f0; |
L_0x9b36728 .reduce/or L_0x9b36680; |
L_0x9b367b0 .functor MUXZ 4, C4<0000>, L_0x9b35e08, L_0x9b36728, C4<>; |
L_0x9b368b8 .functor MUXZ 4, L_0x9b367b0, L_0x9b35fd0, L_0x9b365f8, C4<>; |
L_0x9b36978 .functor MUXZ 4, L_0x9b368b8, L_0x9b360f8, L_0x9b36438, C4<>; |
L_0x9b36a50 .functor MUXZ 4, L_0x9b36978, v0x9b28178_0, L_0x9b36298, C4<>; |
L_0x9b35f68 .part RS_0x9b0e104, 96, 32; |
L_0x9b369c8 .part L_0x9b36a50, 3, 1; |
LS_0x9b36ca0_0_0 .concat [ 1 1 1 1], L_0x9b369c8, L_0x9b369c8, L_0x9b369c8, L_0x9b369c8; |
LS_0x9b36ca0_0_4 .concat [ 1 1 1 1], L_0x9b369c8, L_0x9b369c8, L_0x9b369c8, L_0x9b369c8; |
LS_0x9b36ca0_0_8 .concat [ 1 1 1 1], L_0x9b369c8, L_0x9b369c8, L_0x9b369c8, L_0x9b369c8; |
LS_0x9b36ca0_0_12 .concat [ 1 1 1 1], L_0x9b369c8, L_0x9b369c8, L_0x9b369c8, L_0x9b369c8; |
LS_0x9b36ca0_0_16 .concat [ 1 1 1 1], L_0x9b369c8, L_0x9b369c8, L_0x9b369c8, L_0x9b369c8; |
LS_0x9b36ca0_0_20 .concat [ 1 1 1 1], L_0x9b369c8, L_0x9b369c8, L_0x9b369c8, L_0x9b369c8; |
LS_0x9b36ca0_0_24 .concat [ 1 1 1 1], L_0x9b369c8, L_0x9b369c8, L_0x9b369c8, L_0x9b369c8; |
LS_0x9b36ca0_0_28 .concat [ 1 1 1 1], L_0x9b369c8, L_0x9b369c8, L_0x9b369c8, L_0x9b369c8; |
LS_0x9b36ca0_1_0 .concat [ 4 4 4 4], LS_0x9b36ca0_0_0, LS_0x9b36ca0_0_4, LS_0x9b36ca0_0_8, LS_0x9b36ca0_0_12; |
LS_0x9b36ca0_1_4 .concat [ 4 4 4 4], LS_0x9b36ca0_0_16, LS_0x9b36ca0_0_20, LS_0x9b36ca0_0_24, LS_0x9b36ca0_0_28; |
L_0x9b36ca0 .concat [ 16 16 0 0], LS_0x9b36ca0_1_0, LS_0x9b36ca0_1_4; |
L_0x9b36e48 .part RS_0x9b0e104, 64, 32; |
L_0x9b36e98 .part L_0x9b36a50, 2, 1; |
LS_0x9b36d78_0_0 .concat [ 1 1 1 1], L_0x9b36e98, L_0x9b36e98, L_0x9b36e98, L_0x9b36e98; |
LS_0x9b36d78_0_4 .concat [ 1 1 1 1], L_0x9b36e98, L_0x9b36e98, L_0x9b36e98, L_0x9b36e98; |
LS_0x9b36d78_0_8 .concat [ 1 1 1 1], L_0x9b36e98, L_0x9b36e98, L_0x9b36e98, L_0x9b36e98; |
LS_0x9b36d78_0_12 .concat [ 1 1 1 1], L_0x9b36e98, L_0x9b36e98, L_0x9b36e98, L_0x9b36e98; |
LS_0x9b36d78_0_16 .concat [ 1 1 1 1], L_0x9b36e98, L_0x9b36e98, L_0x9b36e98, L_0x9b36e98; |
LS_0x9b36d78_0_20 .concat [ 1 1 1 1], L_0x9b36e98, L_0x9b36e98, L_0x9b36e98, L_0x9b36e98; |
LS_0x9b36d78_0_24 .concat [ 1 1 1 1], L_0x9b36e98, L_0x9b36e98, L_0x9b36e98, L_0x9b36e98; |
LS_0x9b36d78_0_28 .concat [ 1 1 1 1], L_0x9b36e98, L_0x9b36e98, L_0x9b36e98, L_0x9b36e98; |
LS_0x9b36d78_1_0 .concat [ 4 4 4 4], LS_0x9b36d78_0_0, LS_0x9b36d78_0_4, LS_0x9b36d78_0_8, LS_0x9b36d78_0_12; |
LS_0x9b36d78_1_4 .concat [ 4 4 4 4], LS_0x9b36d78_0_16, LS_0x9b36d78_0_20, LS_0x9b36d78_0_24, LS_0x9b36d78_0_28; |
L_0x9b36d78 .concat [ 16 16 0 0], LS_0x9b36d78_1_0, LS_0x9b36d78_1_4; |
L_0x9b37458 .part RS_0x9b0e104, 32, 32; |
L_0x9b36f50 .part L_0x9b36a50, 1, 1; |
LS_0x9b37580_0_0 .concat [ 1 1 1 1], L_0x9b36f50, L_0x9b36f50, L_0x9b36f50, L_0x9b36f50; |
LS_0x9b37580_0_4 .concat [ 1 1 1 1], L_0x9b36f50, L_0x9b36f50, L_0x9b36f50, L_0x9b36f50; |
LS_0x9b37580_0_8 .concat [ 1 1 1 1], L_0x9b36f50, L_0x9b36f50, L_0x9b36f50, L_0x9b36f50; |
LS_0x9b37580_0_12 .concat [ 1 1 1 1], L_0x9b36f50, L_0x9b36f50, L_0x9b36f50, L_0x9b36f50; |
LS_0x9b37580_0_16 .concat [ 1 1 1 1], L_0x9b36f50, L_0x9b36f50, L_0x9b36f50, L_0x9b36f50; |
LS_0x9b37580_0_20 .concat [ 1 1 1 1], L_0x9b36f50, L_0x9b36f50, L_0x9b36f50, L_0x9b36f50; |
LS_0x9b37580_0_24 .concat [ 1 1 1 1], L_0x9b36f50, L_0x9b36f50, L_0x9b36f50, L_0x9b36f50; |
LS_0x9b37580_0_28 .concat [ 1 1 1 1], L_0x9b36f50, L_0x9b36f50, L_0x9b36f50, L_0x9b36f50; |
LS_0x9b37580_1_0 .concat [ 4 4 4 4], LS_0x9b37580_0_0, LS_0x9b37580_0_4, LS_0x9b37580_0_8, LS_0x9b37580_0_12; |
LS_0x9b37580_1_4 .concat [ 4 4 4 4], LS_0x9b37580_0_16, LS_0x9b37580_0_20, LS_0x9b37580_0_24, LS_0x9b37580_0_28; |
L_0x9b37580 .concat [ 16 16 0 0], LS_0x9b37580_1_0, LS_0x9b37580_1_4; |
L_0x9b37ab0 .part RS_0x9b0e104, 0, 32; |
L_0x9b37b00 .part L_0x9b36a50, 0, 1; |
LS_0x9b379b8_0_0 .concat [ 1 1 1 1], L_0x9b37b00, L_0x9b37b00, L_0x9b37b00, L_0x9b37b00; |
LS_0x9b379b8_0_4 .concat [ 1 1 1 1], L_0x9b37b00, L_0x9b37b00, L_0x9b37b00, L_0x9b37b00; |
LS_0x9b379b8_0_8 .concat [ 1 1 1 1], L_0x9b37b00, L_0x9b37b00, L_0x9b37b00, L_0x9b37b00; |
LS_0x9b379b8_0_12 .concat [ 1 1 1 1], L_0x9b37b00, L_0x9b37b00, L_0x9b37b00, L_0x9b37b00; |
LS_0x9b379b8_0_16 .concat [ 1 1 1 1], L_0x9b37b00, L_0x9b37b00, L_0x9b37b00, L_0x9b37b00; |
LS_0x9b379b8_0_20 .concat [ 1 1 1 1], L_0x9b37b00, L_0x9b37b00, L_0x9b37b00, L_0x9b37b00; |
LS_0x9b379b8_0_24 .concat [ 1 1 1 1], L_0x9b37b00, L_0x9b37b00, L_0x9b37b00, L_0x9b37b00; |
LS_0x9b379b8_0_28 .concat [ 1 1 1 1], L_0x9b37b00, L_0x9b37b00, L_0x9b37b00, L_0x9b37b00; |
LS_0x9b379b8_1_0 .concat [ 4 4 4 4], LS_0x9b379b8_0_0, LS_0x9b379b8_0_4, LS_0x9b379b8_0_8, LS_0x9b379b8_0_12; |
LS_0x9b379b8_1_4 .concat [ 4 4 4 4], LS_0x9b379b8_0_16, LS_0x9b379b8_0_20, LS_0x9b379b8_0_24, LS_0x9b379b8_0_28; |
L_0x9b379b8 .concat [ 16 16 0 0], LS_0x9b379b8_1_0, LS_0x9b379b8_1_4; |
L_0x9b380e0 .part RS_0x9b0e1ac, 6, 2; |
L_0x9b381f0 .part L_0x9b36a50, 3, 1; |
L_0x9b37b50 .concat [ 1 1 0 0], L_0x9b381f0, L_0x9b381f0; |
L_0x9b38638 .part RS_0x9b0e1ac, 4, 2; |
L_0x9b38688 .part L_0x9b36a50, 2, 1; |
L_0x9b36ee8 .concat [ 1 1 0 0], L_0x9b38688, L_0x9b38688; |
L_0x9b38970 .part RS_0x9b0e1ac, 2, 2; |
L_0x9b387a0 .part L_0x9b36a50, 1, 1; |
L_0x9b38ac8 .concat [ 1 1 0 0], L_0x9b387a0, L_0x9b387a0; |
L_0x9b38c90 .part RS_0x9b0e1ac, 0, 2; |
L_0x9b38ce0 .part L_0x9b36a50, 0, 1; |
L_0x9b38b18 .concat [ 1 1 0 0], L_0x9b38ce0, L_0x9b38ce0; |
L_0x9b350d0 .part L_0x9b36a50, 3, 1; |
L_0x9b38d30 .concat [ 1 1 0 0], L_0x9b350d0, L_0x9b350d0; |
L_0x9b38e88 .part L_0x9b36a50, 2, 1; |
L_0x9b38fb8 .concat [ 1 1 0 0], L_0x9b38e88, L_0x9b38e88; |
L_0x9b390e0 .part L_0x9b36a50, 1, 1; |
L_0x9b39130 .concat [ 1 1 0 0], L_0x9b390e0, L_0x9b390e0; |
L_0x9b393f8 .part L_0x9b36a50, 0, 1; |
L_0x9b39448 .concat [ 1 1 0 0], L_0x9b393f8, L_0x9b393f8; |
L_0x9b395e0 .part RS_0x9b0e17c, 15, 5; |
L_0x9b39630 .part L_0x9b36a50, 3, 1; |
LS_0x9b39680_0_0 .concat [ 1 1 1 1], L_0x9b39630, L_0x9b39630, L_0x9b39630, L_0x9b39630; |
LS_0x9b39680_0_4 .concat [ 1 0 0 0], L_0x9b39630; |
L_0x9b39680 .concat [ 4 1 0 0], LS_0x9b39680_0_0, LS_0x9b39680_0_4; |
L_0x9b39978 .part RS_0x9b0e17c, 10, 5; |
L_0x9b39b28 .part L_0x9b36a50, 2, 1; |
LS_0x9b386d8_0_0 .concat [ 1 1 1 1], L_0x9b39b28, L_0x9b39b28, L_0x9b39b28, L_0x9b39b28; |
LS_0x9b386d8_0_4 .concat [ 1 0 0 0], L_0x9b39b28; |
L_0x9b386d8 .concat [ 4 1 0 0], LS_0x9b386d8_0_0, LS_0x9b386d8_0_4; |
L_0x9b39e78 .part RS_0x9b0e17c, 5, 5; |
L_0x9b39d00 .part L_0x9b36a50, 1, 1; |
LS_0x9b39d50_0_0 .concat [ 1 1 1 1], L_0x9b39d00, L_0x9b39d00, L_0x9b39d00, L_0x9b39d00; |
LS_0x9b39d50_0_4 .concat [ 1 0 0 0], L_0x9b39d00; |
L_0x9b39d50 .concat [ 4 1 0 0], LS_0x9b39d50_0_0, LS_0x9b39d50_0_4; |
L_0x9b3a1b8 .part RS_0x9b0e17c, 0, 5; |
L_0x9b3a208 .part L_0x9b36a50, 0, 1; |
LS_0x9b3a088_0_0 .concat [ 1 1 1 1], L_0x9b3a208, L_0x9b3a208, L_0x9b3a208, L_0x9b3a208; |
LS_0x9b3a088_0_4 .concat [ 1 0 0 0], L_0x9b3a208; |
L_0x9b3a088 .concat [ 4 1 0 0], LS_0x9b3a088_0_0, LS_0x9b3a088_0_4; |
L_0x9b39f68 .part L_0x9b3ed58, 9, 3; |
L_0x9b3a258 .part L_0x9b3ed58, 6, 3; |
L_0x9b3a2a8 .part L_0x9b3ed58, 3, 3; |
L_0x9b3a2f8 .part L_0x9b3ed58, 0, 3; |
L_0x9b3a5c0 .part/pv C4<11>, 6, 2, 8; |
L_0x9b3a648 .part/pv C4<10>, 4, 2, 8; |
L_0x9b39398 .part/pv C4<01>, 2, 2, 8; |
L_0x9b3a7d8 .part/pv C4<00>, 0, 2, 8; |
L_0x9b3a888 .part/pv L_0x9b3aa00, 15, 5, 20; |
L_0x9b3aa00 .concat [ 2 3 0 0], C4<00>, v0x9b27d40_0; |
L_0x9b3abd0 .part/pv L_0x9b3aaa8, 10, 5, 20; |
L_0x9b3aaa8 .concat [ 2 3 0 0], C4<01>, v0x9b27d40_0; |
L_0x9b3ab68 .part/pv L_0x9b3acd8, 5, 5, 20; |
L_0x9b3acd8 .concat [ 2 3 0 0], C4<10>, v0x9b27d40_0; |
L_0x9b3a988 .part/pv L_0x9b3aef8, 0, 5, 20; |
L_0x9b3aef8 .concat [ 2 3 0 0], C4<11>, v0x9b27d40_0; |
S_0x9b244e8 .scope module, "fifo_3" "mesi_isc_basic_fifo" 8 177, 7 49, S_0x9a826d8; |
.timescale -9 -12; |
P_0x9b243c4 .param/l "DATA_WIDTH" 7 63, +C4<0101001>; |
P_0x9b243d8 .param/l "FIFO_SIZE" 7 64, +C4<010>; |
P_0x9b243ec .param/l "FIFO_SIZE_LOG2" 7 65, +C4<01>; |
L_0x9b3b2b0 .functor AND 1, L_0x9b3b4d8, L_0x9b3b260, C4<1>, C4<1>; |
L_0x9b3b3a8 .functor AND 1, L_0x9b3b320, L_0x9b3b528, C4<1>, C4<1>; |
v0x9b245e8_0 .net *"_s0", 31 0, L_0x9b3b020; 1 drivers |
v0x9b24648_0 .net *"_s15", 0 0, L_0x9b3b260; 1 drivers |
v0x9b246a8_0 .net *"_s19", 0 0, L_0x9b3b320; 1 drivers |
v0x9b24708_0 .net *"_s3", 30 0, C4<0000000000000000000000000000000>; 1 drivers |
v0x9b24758_0 .net *"_s4", 31 0, C4<00000000000000000000000000000001>; 1 drivers |
v0x9b247b8_0 .net *"_s6", 31 0, L_0x9b3ac20; 1 drivers |
v0x9b24818_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9b24868_0 .net "data_i", 40 0, L_0x9b3b720; 1 drivers |
v0x9b248f0_0 .var "data_o", 40 0; |
v0x9b24950_0 .var "dbg_fifo_overflow", 0 0; |
v0x9b249b0_0 .var "dbg_fifo_underflow", 0 0; |
v0x9b24a10 .array "entry", 0 1, 40 0; |
v0x9b24a60_0 .net "fifo_depth", 0 0, L_0x9b3b450; 1 drivers |
v0x9b24ac0_0 .net "fifo_depth_decrease", 0 0, L_0x9b3b3a8; 1 drivers |
v0x9b24b20_0 .net "fifo_depth_increase", 0 0, L_0x9b3b2b0; 1 drivers |
v0x9b24b80_0 .var/i "i", 31 0; |
v0x9b24c28_0 .var "ptr_rd", 0 0; |
v0x9b24c88_0 .net "ptr_rd_plus_1", 0 0, L_0x9b3b168; 1 drivers |
v0x9b24d28_0 .var "ptr_wr", 0 0; |
v0x9b24d78_0 .net "rd_i", 0 0, L_0x9b3b528; 1 drivers |
v0x9b24cd8_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9b24e20_0 .var "status_empty", 0 0; |
v0x9b24dc8_0 .net "status_empty_o", 0 0, v0x9b24e20_0; 1 drivers |
v0x9b24ee0_0 .var "status_full", 0 0; |
v0x9b24e80_0 .net "status_full_o", 0 0, v0x9b24ee0_0; 1 drivers |
v0x9b24fa8_0 .net "wr_i", 0 0, L_0x9b3b4d8; 1 drivers |
L_0x9b3b020 .concat [ 1 31 0 0], v0x9b24c28_0, C4<0000000000000000000000000000000>; |
L_0x9b3ac20 .arith/sum 32, L_0x9b3b020, C4<00000000000000000000000000000001>; |
L_0x9b3b168 .part L_0x9b3ac20, 0, 1; |
L_0x9b3b260 .reduce/nor L_0x9b3b528; |
L_0x9b3b320 .reduce/nor L_0x9b3b4d8; |
L_0x9b3b450 .arith/sub 1, v0x9b24d28_0, v0x9b24c28_0; |
S_0x9b239f8 .scope module, "fifo_2" "mesi_isc_basic_fifo" 8 234, 7 49, S_0x9a826d8; |
.timescale -9 -12; |
P_0x9a57714 .param/l "DATA_WIDTH" 7 63, +C4<0101001>; |
P_0x9a57728 .param/l "FIFO_SIZE" 7 64, +C4<010>; |
P_0x9a5773c .param/l "FIFO_SIZE_LOG2" 7 65, +C4<01>; |
L_0x9b3c0f0 .functor AND 1, L_0x9b3c318, L_0x9b3c0a0, C4<1>, C4<1>; |
L_0x9b3c1e8 .functor AND 1, L_0x9b3c160, L_0x9b3c420, C4<1>, C4<1>; |
v0x9b23a78_0 .net *"_s0", 31 0, L_0x9b3bde8; 1 drivers |
v0x9b23ac8_0 .net *"_s15", 0 0, L_0x9b3c0a0; 1 drivers |
v0x9b23b28_0 .net *"_s19", 0 0, L_0x9b3c160; 1 drivers |
v0x9b23b88_0 .net *"_s3", 30 0, C4<0000000000000000000000000000000>; 1 drivers |
v0x9b23bd8_0 .net *"_s4", 31 0, C4<00000000000000000000000000000001>; 1 drivers |
v0x9b23c38_0 .net *"_s6", 31 0, L_0x9b3b0c0; 1 drivers |
v0x9b23c98_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9b23ce8_0 .net "data_i", 40 0, L_0x9b3c5c8; 1 drivers |
v0x9b23d70_0 .var "data_o", 40 0; |
v0x9b23dd0_0 .var "dbg_fifo_overflow", 0 0; |
v0x9b23e30_0 .var "dbg_fifo_underflow", 0 0; |
v0x9b23e90 .array "entry", 0 1, 40 0; |
v0x9b23ee0_0 .net "fifo_depth", 0 0, L_0x9b3c290; 1 drivers |
v0x9b23f40_0 .net "fifo_depth_decrease", 0 0, L_0x9b3c1e8; 1 drivers |
v0x9b23fa0_0 .net "fifo_depth_increase", 0 0, L_0x9b3c0f0; 1 drivers |
v0x9b24000_0 .var/i "i", 31 0; |
v0x9b240a8_0 .var "ptr_rd", 0 0; |
v0x9b24108_0 .net "ptr_rd_plus_1", 0 0, L_0x9b3bfa8; 1 drivers |
v0x9b241a8_0 .var "ptr_wr", 0 0; |
v0x9b241f8_0 .net "rd_i", 0 0, L_0x9b3c420; 1 drivers |
v0x9b24158_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9b242a0_0 .var "status_empty", 0 0; |
v0x9b24248_0 .net "status_empty_o", 0 0, v0x9b242a0_0; 1 drivers |
v0x9b24360_0 .var "status_full", 0 0; |
v0x9b24300_0 .net "status_full_o", 0 0, v0x9b24360_0; 1 drivers |
v0x9b24428_0 .net "wr_i", 0 0, L_0x9b3c318; 1 drivers |
L_0x9b3bde8 .concat [ 1 31 0 0], v0x9b240a8_0, C4<0000000000000000000000000000000>; |
L_0x9b3b0c0 .arith/sum 32, L_0x9b3bde8, C4<00000000000000000000000000000001>; |
L_0x9b3bfa8 .part L_0x9b3b0c0, 0, 1; |
L_0x9b3c0a0 .reduce/nor L_0x9b3c420; |
L_0x9b3c160 .reduce/nor L_0x9b3c318; |
L_0x9b3c290 .arith/sub 1, v0x9b241a8_0, v0x9b240a8_0; |
S_0x9a3a6b0 .scope module, "fifo_1" "mesi_isc_basic_fifo" 8 291, 7 49, S_0x9a826d8; |
.timescale -9 -12; |
P_0x9afcf9c .param/l "DATA_WIDTH" 7 63, +C4<0101001>; |
P_0x9afcfb0 .param/l "FIFO_SIZE" 7 64, +C4<010>; |
P_0x9afcfc4 .param/l "FIFO_SIZE_LOG2" 7 65, +C4<01>; |
L_0x9b3cfb0 .functor AND 1, L_0x9b3d1d8, L_0x9b3cf60, C4<1>, C4<1>; |
L_0x9b3d0a8 .functor AND 1, L_0x9b3d020, L_0x9b3d228, C4<1>, C4<1>; |
v0x9a0caa0_0 .net *"_s0", 31 0, L_0x9b3cb88; 1 drivers |
v0x9a0cb00_0 .net *"_s15", 0 0, L_0x9b3cf60; 1 drivers |
v0x9a0cb60_0 .net *"_s19", 0 0, L_0x9b3d020; 1 drivers |
v0x9a16270_0 .net *"_s3", 30 0, C4<0000000000000000000000000000000>; 1 drivers |
v0x9a162c0_0 .net *"_s4", 31 0, C4<00000000000000000000000000000001>; 1 drivers |
v0x9a16320_0 .net *"_s6", 31 0, L_0x9b3bec0; 1 drivers |
v0x99e84d0_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x99e8520_0 .net "data_i", 40 0, L_0x9b3ad50; 1 drivers |
v0x99e85a8_0 .var "data_o", 40 0; |
v0x9a45da0_0 .var "dbg_fifo_overflow", 0 0; |
v0x9a45e00_0 .var "dbg_fifo_underflow", 0 0; |
v0x9a45e60 .array "entry", 0 1, 40 0; |
v0x9a575a0_0 .net "fifo_depth", 0 0, L_0x9b3d150; 1 drivers |
v0x9a57600_0 .net "fifo_depth_decrease", 0 0, L_0x9b3d0a8; 1 drivers |
v0x9a57660_0 .net "fifo_depth_increase", 0 0, L_0x9b3cfb0; 1 drivers |
v0x9a576c0_0 .var/i "i", 31 0; |
v0x9b235e8_0 .var "ptr_rd", 0 0; |
v0x9b23638_0 .net "ptr_rd_plus_1", 0 0, L_0x9b3ce68; 1 drivers |
v0x9b236d8_0 .var "ptr_wr", 0 0; |
v0x9b23728_0 .net "rd_i", 0 0, L_0x9b3d228; 1 drivers |
v0x9b23688_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9b237d0_0 .var "status_empty", 0 0; |
v0x9b23778_0 .net "status_empty_o", 0 0, v0x9b237d0_0; 1 drivers |
v0x9b23880_0 .var "status_full", 0 0; |
v0x9b23820_0 .net "status_full_o", 0 0, v0x9b23880_0; 1 drivers |
v0x9b23938_0 .net "wr_i", 0 0, L_0x9b3d1d8; 1 drivers |
L_0x9b3cb88 .concat [ 1 31 0 0], v0x9b235e8_0, C4<0000000000000000000000000000000>; |
L_0x9b3bec0 .arith/sum 32, L_0x9b3cb88, C4<00000000000000000000000000000001>; |
L_0x9b3ce68 .part L_0x9b3bec0, 0, 1; |
L_0x9b3cf60 .reduce/nor L_0x9b3d228; |
L_0x9b3d020 .reduce/nor L_0x9b3d1d8; |
L_0x9b3d150 .arith/sub 1, v0x9b236d8_0, v0x9b235e8_0; |
S_0x9afccd0 .scope module, "fifo_0" "mesi_isc_basic_fifo" 8 348, 7 49, S_0x9a826d8; |
.timescale -9 -12; |
P_0x9afcd54 .param/l "DATA_WIDTH" 7 63, +C4<0101001>; |
P_0x9afcd68 .param/l "FIFO_SIZE" 7 64, +C4<010>; |
P_0x9afcd7c .param/l "FIFO_SIZE_LOG2" 7 65, +C4<01>; |
L_0x9b3e138 .functor AND 1, L_0x9b3e3a0, L_0x9b3e0c8, C4<1>, C4<1>; |
L_0x9b3e270 .functor AND 1, L_0x9b3e1e8, L_0x9b3de28, C4<1>, C4<1>; |
v0x9adc460_0 .net *"_s0", 31 0, L_0x9b3dc48; 1 drivers |
v0x9adc4b0_0 .net *"_s15", 0 0, L_0x9b3e0c8; 1 drivers |
v0x9adc510_0 .net *"_s19", 0 0, L_0x9b3e1e8; 1 drivers |
v0x9acc270_0 .net *"_s3", 30 0, C4<0000000000000000000000000000000>; 1 drivers |
v0x9acc2c0_0 .net *"_s4", 31 0, C4<00000000000000000000000000000001>; 1 drivers |
v0x9acc310_0 .net *"_s6", 31 0, L_0x9b3cd28; 1 drivers |
v0x9abb350_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9abb408_0 .net "data_i", 40 0, L_0x9b3e5a0; 1 drivers |
v0x9afced8_0 .var "data_o", 40 0; |
v0x9afcf38_0 .var "dbg_fifo_overflow", 0 0; |
v0x9aecad8_0 .var "dbg_fifo_underflow", 0 0; |
v0x9aecb38 .array "entry", 0 1, 40 0; |
v0x9aecb88_0 .net "fifo_depth", 0 0, L_0x9b3e318; 1 drivers |
v0x9adc630_0 .net "fifo_depth_decrease", 0 0, L_0x9b3e270; 1 drivers |
v0x9adc690_0 .net "fifo_depth_increase", 0 0, L_0x9b3e138; 1 drivers |
v0x9adc6f0_0 .var/i "i", 31 0; |
v0x99e4f70_0 .var "ptr_rd", 0 0; |
v0x99e4fd0_0 .net "ptr_rd_plus_1", 0 0, L_0x9b3dfd0; 1 drivers |
v0x99e5070_0 .var "ptr_wr", 0 0; |
v0x9a125f8_0 .net "rd_i", 0 0, L_0x9b3de28; 1 drivers |
v0x99e5020_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9a34b68_0 .var "status_empty", 0 0; |
v0x9a12648_0 .net "status_empty_o", 0 0, v0x9a34b68_0; 1 drivers |
v0x9a34c18_0 .var "status_full", 0 0; |
v0x9a34c68_0 .net "status_full_o", 0 0, v0x9a34c18_0; 1 drivers |
v0x9a34bb8_0 .net "wr_i", 0 0, L_0x9b3e3a0; 1 drivers |
L_0x9b3dc48 .concat [ 1 31 0 0], v0x99e4f70_0, C4<0000000000000000000000000000000>; |
L_0x9b3cd28 .arith/sum 32, L_0x9b3dc48, C4<00000000000000000000000000000001>; |
L_0x9b3dfd0 .part L_0x9b3cd28, 0, 1; |
L_0x9b3e0c8 .reduce/nor L_0x9b3de28; |
L_0x9b3e1e8 .reduce/nor L_0x9b3e3a0; |
L_0x9b3e318 .arith/sub 1, v0x99e5070_0, v0x99e4f70_0; |
S_0x9abc5b8 .scope module, "mesi_isc_tb_cpu3" "mesi_isc_tb_cpu" 2 468, 10 49, S_0x9aed928; |
.timescale -9 -12; |
P_0x9a87024 .param/l "ADDR_WIDTH" 10 71, +C4<0100000>; |
P_0x9a87038 .param/l "BREQ_FIFO_SIZE" 10 78, +C4<010>; |
P_0x9a8704c .param/l "BREQ_FIFO_SIZE_LOG2" 10 79, +C4<01>; |
P_0x9a87060 .param/l "BROAD_ID_WIDTH" 10 74, +C4<0101>; |
P_0x9a87074 .param/l "BROAD_REQ_FIFO_SIZE" 10 75, +C4<0100>; |
P_0x9a87088 .param/l "BROAD_REQ_FIFO_SIZE_LOG2" 10 76, +C4<010>; |
P_0x9a8709c .param/l "BROAD_TYPE_WIDTH" 10 73, +C4<010>; |
P_0x9a870b0 .param/l "CBUS_CMD_WIDTH" 10 70, +C4<011>; |
P_0x9a870c4 .param/l "DATA_WIDTH" 10 72, +C4<0100000>; |
P_0x9a870d8 .param/l "MBUS_CMD_WIDTH" 10 77, +C4<011>; |
v0x9acdf80_0 .var "c_addr", 31 0; |
v0x9acdfe0_0 .var "c_state", 3 0; |
v0x9acdaa0 .array "cache", 0 9, 31 0; |
v0x9acdaa0_0 .array/port v0x9acdaa0, 0; |
v0x9acd5f0_0 .net "cache0", 31 0, v0x9acdaa0_0; 1 drivers |
v0x9acdaa0_1 .array/port v0x9acdaa0, 1; |
v0x9add338_0 .net "cache1", 31 0, v0x9acdaa0_1; 1 drivers |
v0x9acdaa0_2 .array/port v0x9acdaa0, 2; |
v0x9add398_0 .net "cache2", 31 0, v0x9acdaa0_2; 1 drivers |
v0x9acdaa0_3 .array/port v0x9acdaa0, 3; |
v0x9add0b8_0 .net "cache3", 31 0, v0x9acdaa0_3; 1 drivers |
v0x9acdaa0_4 .array/port v0x9acdaa0, 4; |
v0x9add118_0 .net "cache4", 31 0, v0x9acdaa0_4; 1 drivers |
v0x9acdaa0_5 .array/port v0x9acdaa0, 5; |
v0x9aded18_0 .net "cache5", 31 0, v0x9acdaa0_5; 1 drivers |
v0x9acdaa0_6 .array/port v0x9acdaa0, 6; |
v0x9adea60_0 .net "cache6", 31 0, v0x9acdaa0_6; 1 drivers |
v0x9acdaa0_7 .array/port v0x9acdaa0, 7; |
v0x9ade7e0_0 .net "cache7", 31 0, v0x9acdaa0_7; 1 drivers |
v0x9acdaa0_8 .array/port v0x9acdaa0, 8; |
v0x9ade840_0 .net "cache8", 31 0, v0x9acdaa0_8; 1 drivers |
v0x9acdaa0_9 .array/port v0x9acdaa0, 9; |
v0x9ade500_0 .net "cache9", 31 0, v0x9acdaa0_9; 1 drivers |
v0x9adce38 .array "cache_state", 0 9, 3 0; |
v0x9adce38_0 .array/port v0x9adce38, 0; |
v0x9aefc38_0 .net "cache_state0", 3 0, v0x9adce38_0; 1 drivers |
v0x9adce38_1 .array/port v0x9adce38, 1; |
v0x9aefc98_0 .net "cache_state1", 3 0, v0x9adce38_1; 1 drivers |
v0x9adce38_2 .array/port v0x9adce38, 2; |
v0x9aef7a0_0 .net "cache_state2", 3 0, v0x9adce38_2; 1 drivers |
v0x9adce38_3 .array/port v0x9adce38, 3; |
v0x9aee7f0_0 .net "cache_state3", 3 0, v0x9adce38_3; 1 drivers |
v0x9adce38_4 .array/port v0x9adce38, 4; |
v0x9aee300_0 .net "cache_state4", 3 0, v0x9adce38_4; 1 drivers |
v0x9adce38_5 .array/port v0x9adce38, 5; |
v0x9aee360_0 .net "cache_state5", 3 0, v0x9adce38_5; 1 drivers |
v0x9adce38_6 .array/port v0x9adce38, 6; |
v0x9aede10_0 .net "cache_state6", 3 0, v0x9adce38_6; 1 drivers |
v0x9adce38_7 .array/port v0x9adce38, 7; |
v0x9aede70_0 .net "cache_state7", 3 0, v0x9adce38_7; 1 drivers |
v0x9adce38_8 .array/port v0x9adce38, 8; |
v0x9a85d50_0 .net "cache_state8", 3 0, v0x9adce38_8; 1 drivers |
v0x9adce38_9 .array/port v0x9adce38, 9; |
v0x9aee840_0 .net "cache_state9", 3 0, v0x9adce38_9; 1 drivers |
v0x9a84e58_0 .var "cbus_ack_o", 0 0; |
v0x9a85cf0_0 .alias "cbus_addr_i", 31 0, v0x9b2ec18_0; |
v0x9a84df0_0 .alias "cbus_cmd_i", 2 0, v0x9b2ee00_0; |
v0x9a91de0_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9a91e30_0 .net "cpu_id_i", 1 0, C4<11>; 1 drivers |
v0x9ab5640_0 .var/i "i", 31 0; |
v0x9abc838_0 .var/i "k", 31 0; |
v0x9aaba38_0 .var "m_addr", 31 0; |
v0x9aaba98_0 .var "m_state", 2 0; |
v0x9ab7f48_0 .var "m_state_c_state_priority", 0 0; |
v0x9ab5690_0 .var/i "m_state_send_rd_br_counter", 31 0; |
v0x9ac3c18_0 .var/i "m_state_send_wr_br_counter", 31 0; |
v0x9ac3c68_0 .net "mbus_ack_i", 0 0, L_0x9b3fb98; 1 drivers |
v0x9ab7f98_0 .var "mbus_addr_o", 31 0; |
v0x9ace888_0 .var "mbus_cmd_o", 2 0; |
v0x9ace8e8_0 .net "mbus_data_i", 31 0, v0x9b2f8f0_0; 1 drivers |
v0x9ae4498_0 .var "mbus_data_o", 31 0; |
v0x9acca70_0 .var "rd_proc_addr", 31 0; |
v0x9accad0_0 .var "rd_proc_wait_for_en", 0 0; |
v0x9accf50_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9accfa0_0 .var "tb_ins_ack_o", 0 0; |
v0x9ace3a8_0 .alias "tb_ins_addr_i", 3 0, v0x9b30740_0; |
v0x9ace408_0 .net "tb_ins_i", 3 0, v0x9b30818_3; 1 drivers |
v0x9aeec18 .array "wr_data", 0 5, 7 0; |
v0x9aeec68_0 .var "wr_proc_addr", 31 0; |
v0x9aef0f8_0 .var "wr_proc_wait_for_en", 0 0; |
S_0x9a842e8 .scope module, "mesi_isc_tb_cpu2" "mesi_isc_tb_cpu" 2 512, 10 49, S_0x9aed928; |
.timescale -9 -12; |
P_0x9ab676c .param/l "ADDR_WIDTH" 10 71, +C4<0100000>; |
P_0x9ab6780 .param/l "BREQ_FIFO_SIZE" 10 78, +C4<010>; |
P_0x9ab6794 .param/l "BREQ_FIFO_SIZE_LOG2" 10 79, +C4<01>; |
P_0x9ab67a8 .param/l "BROAD_ID_WIDTH" 10 74, +C4<0101>; |
P_0x9ab67bc .param/l "BROAD_REQ_FIFO_SIZE" 10 75, +C4<0100>; |
P_0x9ab67d0 .param/l "BROAD_REQ_FIFO_SIZE_LOG2" 10 76, +C4<010>; |
P_0x9ab67e4 .param/l "BROAD_TYPE_WIDTH" 10 73, +C4<010>; |
P_0x9ab67f8 .param/l "CBUS_CMD_WIDTH" 10 70, +C4<011>; |
P_0x9ab680c .param/l "DATA_WIDTH" 10 72, +C4<0100000>; |
P_0x9ab6820 .param/l "MBUS_CMD_WIDTH" 10 77, +C4<011>; |
v0x9a83068_0 .var "c_addr", 31 0; |
v0x9a830b8_0 .var "c_state", 3 0; |
v0x9a82ba0 .array "cache", 0 9, 31 0; |
v0x9a82ba0_0 .array/port v0x9a82ba0, 0; |
v0x9a81d68_0 .net "cache0", 31 0, v0x9a82ba0_0; 1 drivers |
v0x9a82ba0_1 .array/port v0x9a82ba0, 1; |
v0x9a80da0_0 .net "cache1", 31 0, v0x9a82ba0_1; 1 drivers |
v0x9a82ba0_2 .array/port v0x9a82ba0, 2; |
v0x9a80e00_0 .net "cache2", 31 0, v0x9a82ba0_2; 1 drivers |
v0x9a82ba0_3 .array/port v0x9a82ba0, 3; |
v0x9afd0b0_0 .net "cache3", 31 0, v0x9a82ba0_3; 1 drivers |
v0x9a82ba0_4 .array/port v0x9a82ba0, 4; |
v0x9afd110_0 .net "cache4", 31 0, v0x9a82ba0_4; 1 drivers |
v0x9a82ba0_5 .array/port v0x9a82ba0, 5; |
v0x9aecce8_0 .net "cache5", 31 0, v0x9a82ba0_5; 1 drivers |
v0x9a82ba0_6 .array/port v0x9a82ba0, 6; |
v0x9aecd48_0 .net "cache6", 31 0, v0x9a82ba0_6; 1 drivers |
v0x9a82ba0_7 .array/port v0x9a82ba0, 7; |
v0x9adc880_0 .net "cache7", 31 0, v0x9a82ba0_7; 1 drivers |
v0x9a82ba0_8 .array/port v0x9a82ba0, 8; |
v0x9acc460_0 .net "cache8", 31 0, v0x9a82ba0_8; 1 drivers |
v0x9a82ba0_9 .array/port v0x9a82ba0, 9; |
v0x9acc4c0_0 .net "cache9", 31 0, v0x9a82ba0_9; 1 drivers |
v0x9a817f8 .array "cache_state", 0 9, 3 0; |
v0x9a817f8_0 .array/port v0x9a817f8, 0; |
v0x9a815d8_0 .net "cache_state0", 3 0, v0x9a817f8_0; 1 drivers |
v0x9a817f8_1 .array/port v0x9a817f8, 1; |
v0x9abb078_0 .net "cache_state1", 3 0, v0x9a817f8_1; 1 drivers |
v0x9a817f8_2 .array/port v0x9a817f8, 2; |
v0x9a959d0_0 .net "cache_state2", 3 0, v0x9a817f8_2; 1 drivers |
v0x9a817f8_3 .array/port v0x9a817f8, 3; |
v0x9a95a30_0 .net "cache_state3", 3 0, v0x9a817f8_3; 1 drivers |
v0x9a817f8_4 .array/port v0x9a817f8, 4; |
v0x9a87898_0 .net "cache_state4", 3 0, v0x9a817f8_4; 1 drivers |
v0x9a817f8_5 .array/port v0x9a817f8, 5; |
v0x9a906a8_0 .net "cache_state5", 3 0, v0x9a817f8_5; 1 drivers |
v0x9a817f8_6 .array/port v0x9a817f8, 6; |
v0x9abb0c8_0 .net "cache_state6", 3 0, v0x9a817f8_6; 1 drivers |
v0x9a817f8_7 .array/port v0x9a817f8, 7; |
v0x9ab9640_0 .net "cache_state7", 3 0, v0x9a817f8_7; 1 drivers |
v0x9a817f8_8 .array/port v0x9a817f8, 8; |
v0x9a906f8_0 .net "cache_state8", 3 0, v0x9a817f8_8; 1 drivers |
v0x9a817f8_9 .array/port v0x9a817f8, 9; |
v0x9ab4828_0 .net "cache_state9", 3 0, v0x9a817f8_9; 1 drivers |
v0x9ab4888_0 .var "cbus_ack_o", 0 0; |
v0x9ab0848_0 .alias "cbus_addr_i", 31 0, v0x9b2ec18_0; |
v0x9ab0898_0 .alias "cbus_cmd_i", 2 0, v0x9b2edb0_0; |
v0x9ab9690_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9abaf48_0 .net "cpu_id_i", 1 0, C4<10>; 1 drivers |
v0x9aba3a0_0 .var/i "i", 31 0; |
v0x9aba3f0_0 .var/i "k", 31 0; |
v0x9aafa30_0 .var "m_addr", 31 0; |
v0x9a967a0_0 .var "m_state", 2 0; |
v0x9a96800_0 .var "m_state_c_state_priority", 0 0; |
v0x9aaac18_0 .var/i "m_state_send_rd_br_counter", 31 0; |
v0x9a97438_0 .var/i "m_state_send_wr_br_counter", 31 0; |
v0x9a97498_0 .net "mbus_ack_i", 0 0, L_0x9b40688; 1 drivers |
v0x9aa0278_0 .var "mbus_addr_o", 31 0; |
v0x9aa02c8_0 .var "mbus_cmd_o", 2 0; |
v0x9aa2638_0 .alias "mbus_data_i", 31 0, v0x9ace8e8_0; |
v0x9ab17f0_0 .var "mbus_data_o", 31 0; |
v0x9ab1840_0 .var "rd_proc_addr", 31 0; |
v0x9abcab8_0 .var "rd_proc_wait_for_en", 0 0; |
v0x9abe460_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9abe1e0_0 .var "tb_ins_ack_o", 0 0; |
v0x9abe240_0 .alias "tb_ins_addr_i", 3 0, v0x9b306f0_0; |
v0x9abdf60_0 .net "tb_ins_i", 3 0, v0x9b30818_2; 1 drivers |
v0x9abdfc0 .array "wr_data", 0 5, 7 0; |
v0x9abdc38_0 .var "wr_proc_addr", 31 0; |
v0x9abdc98_0 .var "wr_proc_wait_for_en", 0 0; |
S_0x9ab3af8 .scope module, "mesi_isc_tb_cpu1" "mesi_isc_tb_cpu" 2 556, 10 49, S_0x9aed928; |
.timescale -9 -12; |
P_0x9aa7da4 .param/l "ADDR_WIDTH" 10 71, +C4<0100000>; |
P_0x9aa7db8 .param/l "BREQ_FIFO_SIZE" 10 78, +C4<010>; |
P_0x9aa7dcc .param/l "BREQ_FIFO_SIZE_LOG2" 10 79, +C4<01>; |
P_0x9aa7de0 .param/l "BROAD_ID_WIDTH" 10 74, +C4<0101>; |
P_0x9aa7df4 .param/l "BROAD_REQ_FIFO_SIZE" 10 75, +C4<0100>; |
P_0x9aa7e08 .param/l "BROAD_REQ_FIFO_SIZE_LOG2" 10 76, +C4<010>; |
P_0x9aa7e1c .param/l "BROAD_TYPE_WIDTH" 10 73, +C4<010>; |
P_0x9aa7e30 .param/l "CBUS_CMD_WIDTH" 10 70, +C4<011>; |
P_0x9aa7e44 .param/l "DATA_WIDTH" 10 72, +C4<0100000>; |
P_0x9aa7e58 .param/l "MBUS_CMD_WIDTH" 10 77, +C4<011>; |
v0x9ab4110_0 .var "c_addr", 31 0; |
v0x9ab3218_0 .var "c_state", 3 0; |
v0x9ab3278 .array "cache", 0 9, 31 0; |
v0x9ab3278_0 .array/port v0x9ab3278, 0; |
v0x9aaf820_0 .net "cache0", 31 0, v0x9ab3278_0; 1 drivers |
v0x9ab3278_1 .array/port v0x9ab3278, 1; |
v0x9aaf2c8_0 .net "cache1", 31 0, v0x9ab3278_1; 1 drivers |
v0x9ab3278_2 .array/port v0x9ab3278, 2; |
v0x9aaf328_0 .net "cache2", 31 0, v0x9ab3278_2; 1 drivers |
v0x9ab3278_3 .array/port v0x9ab3278, 3; |
v0x9aaed10_0 .net "cache3", 31 0, v0x9ab3278_3; 1 drivers |
v0x9ab3278_4 .array/port v0x9ab3278, 4; |
v0x9aae420_0 .net "cache4", 31 0, v0x9ab3278_4; 1 drivers |
v0x9ab3278_5 .array/port v0x9ab3278, 5; |
v0x9aaa9a8_0 .net "cache5", 31 0, v0x9ab3278_5; 1 drivers |
v0x9ab3278_6 .array/port v0x9ab3278, 6; |
v0x9aaaa08_0 .net "cache6", 31 0, v0x9ab3278_6; 1 drivers |
v0x9ab3278_7 .array/port v0x9ab3278, 7; |
v0x9aaa4b0_0 .net "cache7", 31 0, v0x9ab3278_7; 1 drivers |
v0x9ab3278_8 .array/port v0x9ab3278, 8; |
v0x9aaa510_0 .net "cache8", 31 0, v0x9ab3278_8; 1 drivers |
v0x9ab3278_9 .array/port v0x9ab3278, 9; |
v0x9aa9ee8_0 .net "cache9", 31 0, v0x9ab3278_9; 1 drivers |
v0x9aa9f48 .array "cache_state", 0 9, 3 0; |
v0x9aa9f48_0 .array/port v0x9aa9f48, 0; |
v0x9aa6c68_0 .net "cache_state0", 3 0, v0x9aa9f48_0; 1 drivers |
v0x9aa9f48_1 .array/port v0x9aa9f48, 1; |
v0x9aa6cc8_0 .net "cache_state1", 3 0, v0x9aa9f48_1; 1 drivers |
v0x9aa9f48_2 .array/port v0x9aa9f48, 2; |
v0x9aa5fc0_0 .net "cache_state2", 3 0, v0x9aa9f48_2; 1 drivers |
v0x9aa9f48_3 .array/port v0x9aa9f48, 3; |
v0x9aa4cd0_0 .net "cache_state3", 3 0, v0x9aa9f48_3; 1 drivers |
v0x9aa9f48_4 .array/port v0x9aa9f48, 4; |
v0x9a95760_0 .net "cache_state4", 3 0, v0x9aa9f48_4; 1 drivers |
v0x9aa9f48_5 .array/port v0x9aa9f48, 5; |
v0x9a957b0_0 .net "cache_state5", 3 0, v0x9aa9f48_5; 1 drivers |
v0x9aa9f48_6 .array/port v0x9aa9f48, 6; |
v0x9aa4d20_0 .net "cache_state6", 3 0, v0x9aa9f48_6; 1 drivers |
v0x9aa9f48_7 .array/port v0x9aa9f48, 7; |
v0x9a952d0_0 .net "cache_state7", 3 0, v0x9aa9f48_7; 1 drivers |
v0x9aa9f48_8 .array/port v0x9aa9f48, 8; |
v0x9a94cf8_0 .net "cache_state8", 3 0, v0x9aa9f48_8; 1 drivers |
v0x9aa9f48_9 .array/port v0x9aa9f48, 9; |
v0x9a95278_0 .net "cache_state9", 3 0, v0x9aa9f48_9; 1 drivers |
v0x9a94c98_0 .var "cbus_ack_o", 0 0; |
v0x9b0b198_0 .alias "cbus_addr_i", 31 0, v0x9b2ec18_0; |
v0x9b0b1e8_0 .alias "cbus_cmd_i", 2 0, v0x9b2ed28_0; |
v0x9b02338_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9b02388_0 .net "cpu_id_i", 1 0, C4<01>; 1 drivers |
v0x9a943b0_0 .var/i "i", 31 0; |
v0x9afd868_0 .var/i "k", 31 0; |
v0x9afd8b8_0 .var "m_addr", 31 0; |
v0x9b01018_0 .var "m_state", 2 0; |
v0x99e5858_0 .var "m_state_c_state_priority", 0 0; |
v0x99e58b8_0 .var/i "m_state_send_rd_br_counter", 31 0; |
v0x9ab93d0_0 .var/i "m_state_send_wr_br_counter", 31 0; |
v0x9ab9420_0 .net "mbus_ack_i", 0 0, L_0x9b411d8; 1 drivers |
v0x9a87238_0 .var "mbus_addr_o", 31 0; |
v0x9a852b8_0 .var "mbus_cmd_o", 2 0; |
v0x9a85318_0 .alias "mbus_data_i", 31 0, v0x9ace8e8_0; |
v0x9a85828_0 .var "mbus_data_o", 31 0; |
v0x9a85878_0 .var "rd_proc_addr", 31 0; |
v0x9a848e0_0 .var "rd_proc_wait_for_en", 0 0; |
v0x9a84930_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9a847b0_0 .var "tb_ins_ack_o", 0 0; |
v0x9a84800_0 .alias "tb_ins_addr_i", 3 0, v0x9b306a0_0; |
v0x9a811c0_0 .net "tb_ins_i", 3 0, v0x9b30818_1; 1 drivers |
v0x9a81220 .array "wr_data", 0 5, 7 0; |
v0x9a84418_0 .var "wr_proc_addr", 31 0; |
v0x9a84478_0 .var "wr_proc_wait_for_en", 0 0; |
S_0x9aeed80 .scope module, "mesi_isc_tb_cpu0" "mesi_isc_tb_cpu" 2 600, 10 49, S_0x9aed928; |
.timescale -9 -12; |
P_0x9a8456c .param/l "ADDR_WIDTH" 10 71, +C4<0100000>; |
P_0x9a84580 .param/l "BREQ_FIFO_SIZE" 10 78, +C4<010>; |
P_0x9a84594 .param/l "BREQ_FIFO_SIZE_LOG2" 10 79, +C4<01>; |
P_0x9a845a8 .param/l "BROAD_ID_WIDTH" 10 74, +C4<0101>; |
P_0x9a845bc .param/l "BROAD_REQ_FIFO_SIZE" 10 75, +C4<0100>; |
P_0x9a845d0 .param/l "BROAD_REQ_FIFO_SIZE_LOG2" 10 76, +C4<010>; |
P_0x9a845e4 .param/l "BROAD_TYPE_WIDTH" 10 73, +C4<010>; |
P_0x9a845f8 .param/l "CBUS_CMD_WIDTH" 10 70, +C4<011>; |
P_0x9a8460c .param/l "DATA_WIDTH" 10 72, +C4<0100000>; |
P_0x9a84620 .param/l "MBUS_CMD_WIDTH" 10 77, +C4<011>; |
v0x9ab78f8_0 .var "c_addr", 31 0; |
v0x9aefe80_0 .var "c_state", 3 0; |
v0x9aefd50 .array "cache", 0 9, 31 0; |
v0x9aefd50_0 .array/port v0x9aefd50, 0; |
v0x9aefac0_0 .net "cache0", 31 0, v0x9aefd50_0; 1 drivers |
v0x9aefd50_1 .array/port v0x9aefd50, 1; |
v0x9aef990_0 .net "cache1", 31 0, v0x9aefd50_1; 1 drivers |
v0x9aefd50_2 .array/port v0x9aefd50, 2; |
v0x9aef860_0 .net "cache2", 31 0, v0x9aefd50_2; 1 drivers |
v0x9aefd50_3 .array/port v0x9aefd50, 3; |
v0x9aef5d0_0 .net "cache3", 31 0, v0x9aefd50_3; 1 drivers |
v0x9aefd50_4 .array/port v0x9aefd50, 4; |
v0x9aef4a0_0 .net "cache4", 31 0, v0x9aefd50_4; 1 drivers |
v0x9aefd50_5 .array/port v0x9aefd50, 5; |
v0x9aef370_0 .net "cache5", 31 0, v0x9aefd50_5; 1 drivers |
v0x9aefd50_6 .array/port v0x9aefd50, 6; |
v0x9aeefb8_0 .net "cache6", 31 0, v0x9aefd50_6; 1 drivers |
v0x9aefd50_7 .array/port v0x9aefd50, 7; |
v0x9aeeea0_0 .net "cache7", 31 0, v0x9aefd50_7; 1 drivers |
v0x9aefd50_8 .array/port v0x9aefd50, 8; |
v0x9aeead8_0 .net "cache8", 31 0, v0x9aefd50_8; 1 drivers |
v0x9aefd50_9 .array/port v0x9aefd50, 9; |
v0x9aee918_0 .net "cache9", 31 0, v0x9aefd50_9; 1 drivers |
v0x9aee678 .array "cache_state", 0 9, 3 0; |
v0x9aee678_0 .array/port v0x9aee678, 0; |
v0x9aee548_0 .net "cache_state0", 3 0, v0x9aee678_0; 1 drivers |
v0x9aee678_1 .array/port v0x9aee678, 1; |
v0x9aee418_0 .net "cache_state1", 3 0, v0x9aee678_1; 1 drivers |
v0x9aee678_2 .array/port v0x9aee678, 2; |
v0x9aee188_0 .net "cache_state2", 3 0, v0x9aee678_2; 1 drivers |
v0x9aee678_3 .array/port v0x9aee678, 3; |
v0x9aee058_0 .net "cache_state3", 3 0, v0x9aee678_3; 1 drivers |
v0x9aee678_4 .array/port v0x9aee678, 4; |
v0x9aed1a0_0 .net "cache_state4", 3 0, v0x9aee678_4; 1 drivers |
v0x9aee678_5 .array/port v0x9aee678, 5; |
v0x9aedf28_0 .net "cache_state5", 3 0, v0x9aee678_5; 1 drivers |
v0x9aee678_6 .array/port v0x9aee678, 6; |
v0x9aedf78_0 .net "cache_state6", 3 0, v0x9aee678_6; 1 drivers |
v0x9aee678_7 .array/port v0x9aee678, 7; |
v0x9aee468_0 .net "cache_state7", 3 0, v0x9aee678_7; 1 drivers |
v0x9aee678_8 .array/port v0x9aee678, 8; |
v0x9aedb68_0 .net "cache_state8", 3 0, v0x9aee678_8; 1 drivers |
v0x9aee678_9 .array/port v0x9aee678, 9; |
v0x9aeda38_0 .net "cache_state9", 3 0, v0x9aee678_9; 1 drivers |
v0x9aeda88_0 .var "cbus_ack_o", 0 0; |
v0x9aedc98_0 .alias "cbus_addr_i", 31 0, v0x9b2ec18_0; |
v0x9aecfe0_0 .alias "cbus_cmd_i", 2 0, v0x9b2ec68_0; |
v0x9af0840_0 .alias "clk", 0 0, v0x9b2df50_0; |
v0x9af08a0_0 .net "cpu_id_i", 1 0, C4<00>; 1 drivers |
v0x9aebe50_0 .var/i "i", 31 0; |
v0x9aebea0_0 .var/i "k", 31 0; |
v0x9af48d0_0 .var "m_addr", 31 0; |
v0x9ae0470_0 .var "m_state", 2 0; |
v0x9ad4060_0 .var "m_state_c_state_priority", 0 0; |
v0x9ad40c0_0 .var/i "m_state_send_rd_br_counter", 31 0; |
v0x9acffd0_0 .var/i "m_state_send_wr_br_counter", 31 0; |
v0x9ad0020_0 .net "mbus_ack_i", 0 0, L_0x9b41d08; 1 drivers |
v0x9adc1f0_0 .var "mbus_addr_o", 31 0; |
v0x9abfbf0_0 .var "mbus_cmd_o", 2 0; |
v0x9abfc50_0 .alias "mbus_data_i", 31 0, v0x9ace8e8_0; |
v0x9acb5d0_0 .var "mbus_data_o", 31 0; |
v0x9ab8ec0_0 .var "rd_proc_addr", 31 0; |
v0x9ab8f20_0 .var "rd_proc_wait_for_en", 0 0; |
v0x9ab8908_0 .alias "rst", 0 0, v0x9b2e418_0; |
v0x9ab8958_0 .var "tb_ins_ack_o", 0 0; |
v0x9ab83a8_0 .alias "tb_ins_addr_i", 3 0, v0x9b307c8_0; |
v0x9ab83f8_0 .net "tb_ins_i", 3 0, v0x9b30818_0; 1 drivers |
v0x9ab45b8 .array "wr_data", 0 5, 7 0; |
v0x9ab4608_0 .var "wr_proc_addr", 31 0; |
v0x9ab40c0_0 .var "wr_proc_wait_for_en", 0 0; |
E_0x9afd1d8 .event posedge, v0x9ab8908_0, v0x9af0840_0; |
E_0x9aece10 .event negedge, v0x9af0840_0; |
.scope S_0x9b2a9c0; |
T_2 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b2cfe8_0, 1; |
%jmp/0xz T_2.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2cb28_0, 0, 0; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 0; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2c9a8_0, 0, 0; |
%jmp T_2.1; |
T_2.0 ; |
%load/v 8, v0x9b2cb28_0, 1; |
%inv 8, 1; |
%load/v 9, v0x9b2c9a8_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%jmp/0xz T_2.2, 8; |
%load/v 8, v0x9b2d170_0, 1; |
%inv 8, 1; |
%jmp/0xz T_2.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2cb28_0, 0, 1; |
%load/v 8, v0x9b2c9f8_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_2.6, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_2.7, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_2.8, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_2.9, 6; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 0; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 0; |
%jmp T_2.11; |
T_2.6 ; |
%movi 8, 14, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 8; |
%movi 8, 1, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 8; |
%jmp T_2.11; |
T_2.7 ; |
%movi 8, 13, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 8; |
%movi 8, 2, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 8; |
%jmp T_2.11; |
T_2.8 ; |
%movi 8, 11, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 8; |
%movi 8, 4, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 8; |
%jmp T_2.11; |
T_2.9 ; |
%movi 8, 7, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 8; |
%movi 8, 8, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 8; |
%jmp T_2.11; |
T_2.11 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2c9a8_0, 0, 0; |
%jmp T_2.5; |
T_2.4 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2cb28_0, 0, 0; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 0; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2c9a8_0, 0, 0; |
T_2.5 ; |
%jmp T_2.3; |
T_2.2 ; |
%load/v 8, v0x9b2cdd8_0, 4; |
%or/r 8, 8, 4; |
%jmp/0xz T_2.12, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2cb28_0, 0, 1; |
%load/v 8, v0x9b2cdd8_0, 4; |
%load/v 12, v0x9b2cb88_0, 4; |
%inv 12, 4; |
%and 8, 12, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 8; |
%load/v 8, v0x9b2ccd8_0, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2c9a8_0, 0, 0; |
%jmp T_2.13; |
T_2.12 ; |
%load/v 8, v0x9b2c9a8_0, 1; |
%jmp/0xz T_2.14, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2cb28_0, 0, 0; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2cdd8_0, 0, 0; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b2ccd8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2c9a8_0, 0, 0; |
%jmp T_2.15; |
T_2.14 ; |
%load/v 8, v0x9b2cc78_0, 4; |
%or/r 8, 8, 4; |
%inv 8, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2c9a8_0, 0, 8; |
T_2.15 ; |
T_2.13 ; |
T_2.3 ; |
T_2.1 ; |
%jmp T_2; |
.thread T_2; |
.scope S_0x9b29eb8; |
T_3 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b2a630_0, 1; |
%jmp/0xz T_3.0, 8; |
%set/v v0x9b2a4d8_0, 0, 32; |
T_3.2 ; |
%load/v 8, v0x9b2a4d8_0, 32; |
%cmpi/s 8, 4, 32; |
%jmp/0xz T_3.3, 5; |
%ix/getv/s 3, v0x9b2a4d8_0; |
%jmp/1 t_0, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9b2a368, 0, 0; |
t_0 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b2a4d8_0, 32; |
%set/v v0x9b2a4d8_0, 8, 32; |
%jmp T_3.2; |
T_3.3 ; |
%ix/load 0, 2, 0; |
%assign/v0 v0x9b2a680_0, 0, 0; |
%jmp T_3.1; |
T_3.0 ; |
%load/v 8, v0x9b2a900_0, 1; |
%jmp/0xz T_3.4, 8; |
%load/v 8, v0x9b2a228_0, 41; |
%ix/getv 3, v0x9b2a680_0; |
%jmp/1 t_1, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9b2a368, 0, 8; |
t_1 ; |
%load/v 8, v0x9b2a680_0, 2; |
%mov 10, 0, 30; |
%addi 8, 1, 32; |
%ix/load 0, 2, 0; |
%assign/v0 v0x9b2a680_0, 0, 8; |
T_3.4 ; |
T_3.1 ; |
%jmp T_3; |
.thread T_3; |
.scope S_0x9b29eb8; |
T_4 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b2a630_0, 1; |
%jmp/0xz T_4.0, 8; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b2a278_0, 0, 0; |
%jmp T_4.1; |
T_4.0 ; |
%load/v 8, v0x9b2a778_0, 1; |
%jmp/0xz T_4.2, 8; |
%load/v 8, v0x9b2a228_0, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b2a278_0, 0, 8; |
%jmp T_4.3; |
T_4.2 ; |
%load/v 8, v0x9b2a6d0_0, 1; |
%jmp/0xz T_4.4, 8; |
%ix/getv 3, v0x9b2a5e0_0; |
%load/av 8, v0x9b2a368, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b2a278_0, 0, 8; |
%jmp T_4.5; |
T_4.4 ; |
%ix/getv 3, v0x9b2a580_0; |
%load/av 8, v0x9b2a368, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b2a278_0, 0, 8; |
T_4.5 ; |
T_4.3 ; |
T_4.1 ; |
%jmp T_4; |
.thread T_4; |
.scope S_0x9b29eb8; |
T_5 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b2a630_0, 1; |
%jmp/0xz T_5.0, 8; |
%ix/load 0, 2, 0; |
%assign/v0 v0x9b2a580_0, 0, 0; |
%jmp T_5.1; |
T_5.0 ; |
%load/v 8, v0x9b2a6d0_0, 1; |
%jmp/0xz T_5.2, 8; |
%load/v 8, v0x9b2a580_0, 2; |
%mov 10, 0, 30; |
%addi 8, 1, 32; |
%ix/load 0, 2, 0; |
%assign/v0 v0x9b2a580_0, 0, 8; |
T_5.2 ; |
T_5.1 ; |
%jmp T_5; |
.thread T_5; |
.scope S_0x9b29eb8; |
T_6 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b2a630_0, 1; |
%jmp/0xz T_6.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a778_0, 0, 1; |
%jmp T_6.1; |
T_6.0 ; |
%load/v 8, v0x9b2a3b8_0, 2; |
%mov 10, 0, 1; |
%cmpi/u 8, 1, 3; |
%mov 8, 4, 1; |
%load/v 9, v0x9b2a418_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_6.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a778_0, 0, 1; |
%jmp T_6.3; |
T_6.2 ; |
%load/v 8, v0x9b2a3b8_0, 2; |
%mov 10, 0, 1; |
%cmpi/u 8, 0, 3; |
%mov 8, 4, 1; |
%load/v 9, v0x9b2a778_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9b2a478_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_6.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a778_0, 0, 0; |
T_6.4 ; |
T_6.3 ; |
T_6.1 ; |
%jmp T_6; |
.thread T_6; |
.scope S_0x9b29eb8; |
T_7 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b2a630_0, 1; |
%jmp/0xz T_7.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a838_0, 0, 0; |
%jmp T_7.1; |
T_7.0 ; |
%load/v 8, v0x9b2a3b8_0, 2; |
%mov 10, 0, 4; |
%cmpi/u 8, 3, 6; |
%mov 8, 4, 1; |
%load/v 9, v0x9b2a478_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_7.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a838_0, 0, 1; |
%jmp T_7.3; |
T_7.2 ; |
%load/v 8, v0x9b2a3b8_0, 2; |
%mov 10, 0, 1; |
%cmpi/u 8, 0, 3; |
%mov 8, 4, 1; |
%load/v 9, v0x9b2a838_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9b2a418_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_7.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a838_0, 0, 0; |
T_7.4 ; |
T_7.3 ; |
T_7.1 ; |
%jmp T_7; |
.thread T_7; |
.scope S_0x9b29eb8; |
T_8 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b2a630_0, 1; |
%jmp/0xz T_8.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a2c8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a318_0, 0, 0; |
%jmp T_8.1; |
T_8.0 ; |
%load/v 8, v0x9b2a2c8_0, 1; |
%load/v 9, v0x9b2a838_0, 1; |
%load/v 10, v0x9b2a478_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a2c8_0, 0, 8; |
%load/v 8, v0x9b2a318_0, 1; |
%load/v 9, v0x9b2a778_0, 1; |
%load/v 10, v0x9b2a418_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b2a318_0, 0, 8; |
T_8.1 ; |
%jmp T_8; |
.thread T_8; |
.scope S_0x9b25068; |
T_9 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b28628_0, 1; |
%jmp/0xz T_9.0, 8; |
%movi 8, 1, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b28178_0, 0, 8; |
%jmp T_9.1; |
T_9.0 ; |
%load/v 8, v0x9b27fb8_0, 1; |
%jmp/0xz T_9.2, 8; |
%load/v 8, v0x9b281d8_0, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b28178_0, 0, 8; |
T_9.2 ; |
T_9.1 ; |
%jmp T_9; |
.thread T_9; |
.scope S_0x9b25068; |
T_10 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b28628_0, 1; |
%jmp/0xz T_10.0, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9b28370_0, 0, 0; |
%jmp T_10.1; |
T_10.0 ; |
%ix/load 1, 3, 0; |
%mov 4, 0, 1; |
%jmp/1 T_10.2, 4; |
%load/x1p 8, v0x9b28370_0, 1; |
%jmp T_10.3; |
T_10.2 ; |
%mov 8, 2, 1; |
T_10.3 ; |
; Save base=8 wid=1 in lookaside. |
%inv 8, 1; |
%load/v 9, v0x9b285c8_0, 3; |
%cmpi/u 9, 3, 3; |
%mov 9, 4, 1; |
%load/v 10, v0x9b285c8_0, 3; |
%cmpi/u 10, 4, 3; |
%mov 10, 4, 1; |
%or 9, 10, 1; |
%and 8, 9, 1; |
%ix/load 1, 3, 0; |
%mov 4, 0, 1; |
%jmp/1 T_10.4, 4; |
%load/x1p 11, v0x9b280b8_0, 1; |
%jmp T_10.5; |
T_10.4 ; |
%mov 11, 2, 1; |
T_10.5 ; |
%mov 9, 11, 1; Move signal select into place |
%mov 10, 0, 1; |
%cmpi/u 9, 0, 2; |
%mov 9, 4, 1; |
%and 8, 9, 1; |
%ix/load 0, 1, 0; |
%ix/load 1, 3, 0; |
%assign/v0/x1 v0x9b28370_0, 0, 8; |
%ix/load 1, 2, 0; |
%mov 4, 0, 1; |
%jmp/1 T_10.6, 4; |
%load/x1p 8, v0x9b28370_0, 1; |
%jmp T_10.7; |
T_10.6 ; |
%mov 8, 2, 1; |
T_10.7 ; |
; Save base=8 wid=1 in lookaside. |
%inv 8, 1; |
%load/v 9, v0x9b28568_0, 3; |
%cmpi/u 9, 3, 3; |
%mov 9, 4, 1; |
%load/v 10, v0x9b28568_0, 3; |
%cmpi/u 10, 4, 3; |
%mov 10, 4, 1; |
%or 9, 10, 1; |
%and 8, 9, 1; |
%ix/load 1, 2, 0; |
%mov 4, 0, 1; |
%jmp/1 T_10.8, 4; |
%load/x1p 11, v0x9b280b8_0, 1; |
%jmp T_10.9; |
T_10.8 ; |
%mov 11, 2, 1; |
T_10.9 ; |
%mov 9, 11, 1; Move signal select into place |
%mov 10, 0, 1; |
%cmpi/u 9, 0, 2; |
%mov 9, 4, 1; |
%and 8, 9, 1; |
%ix/load 0, 1, 0; |
%ix/load 1, 2, 0; |
%assign/v0/x1 v0x9b28370_0, 0, 8; |
%ix/load 1, 1, 0; |
%mov 4, 0, 1; |
%jmp/1 T_10.10, 4; |
%load/x1p 8, v0x9b28370_0, 1; |
%jmp T_10.11; |
T_10.10 ; |
%mov 8, 2, 1; |
T_10.11 ; |
; Save base=8 wid=1 in lookaside. |
%inv 8, 1; |
%load/v 9, v0x9b28788_0, 3; |
%cmpi/u 9, 3, 3; |
%mov 9, 4, 1; |
%load/v 10, v0x9b28788_0, 3; |
%cmpi/u 10, 4, 3; |
%mov 10, 4, 1; |
%or 9, 10, 1; |
%and 8, 9, 1; |
%ix/load 1, 1, 0; |
%mov 4, 0, 1; |
%jmp/1 T_10.12, 4; |
%load/x1p 11, v0x9b280b8_0, 1; |
%jmp T_10.13; |
T_10.12 ; |
%mov 11, 2, 1; |
T_10.13 ; |
%mov 9, 11, 1; Move signal select into place |
%mov 10, 0, 1; |
%cmpi/u 9, 0, 2; |
%mov 9, 4, 1; |
%and 8, 9, 1; |
%ix/load 0, 1, 0; |
%ix/load 1, 1, 0; |
%assign/v0/x1 v0x9b28370_0, 0, 8; |
%load/v 8, v0x9b28370_0, 1; Only need 1 of 4 bits |
; Save base=8 wid=1 in lookaside. |
%inv 8, 1; |
%load/v 9, v0x9b28490_0, 3; |
%cmpi/u 9, 3, 3; |
%mov 9, 4, 1; |
%load/v 10, v0x9b28490_0, 3; |
%cmpi/u 10, 4, 3; |
%mov 10, 4, 1; |
%or 9, 10, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9b280b8_0, 1; Select 1 out of 4 bits |
%mov 10, 0, 1; |
%cmpi/u 9, 0, 2; |
%mov 9, 4, 1; |
%and 8, 9, 1; |
%ix/load 0, 1, 0; |
%ix/load 1, 0, 0; |
%assign/v0/x1 v0x9b28370_0, 0, 8; |
T_10.1 ; |
%jmp T_10; |
.thread T_10; |
.scope S_0x9b25068; |
T_11 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b28628_0, 1; |
%jmp/0xz T_11.0, 8; |
%ix/load 0, 8, 0; |
%assign/v0 v0x9b27d90_0, 0, 0; |
%jmp T_11.1; |
T_11.0 ; |
%load/v 8, v0x9b285c8_0, 3; |
%cmpi/u 8, 3, 3; |
%mov 8, 4, 1; |
%jmp/0 T_11.2, 8; |
%movi 9, 1, 2; |
%jmp/1 T_11.4, 8; |
T_11.2 ; End of true expr. |
%load/v 11, v0x9b285c8_0, 3; |
%cmpi/u 11, 4, 3; |
%mov 11, 4, 1; |
%jmp/0 T_11.5, 11; |
%movi 12, 2, 2; |
%jmp/1 T_11.7, 11; |
T_11.5 ; End of true expr. |
%jmp/0 T_11.6, 11; |
; End of false expr. |
%blend 12, 0, 2; Condition unknown. |
%jmp T_11.7; |
T_11.6 ; |
%mov 12, 0, 2; Return false value |
T_11.7 ; |
%jmp/0 T_11.3, 8; |
; End of false expr. |
%blend 9, 12, 2; Condition unknown. |
%jmp T_11.4; |
T_11.3 ; |
%mov 9, 12, 2; Return false value |
T_11.4 ; |
%ix/load 0, 6, 0; |
%set/x0 v0x9b27d90_0, 9, 2; |
%load/v 8, v0x9b28568_0, 3; |
%cmpi/u 8, 3, 3; |
%mov 8, 4, 1; |
%jmp/0 T_11.8, 8; |
%movi 9, 1, 2; |
%jmp/1 T_11.10, 8; |
T_11.8 ; End of true expr. |
%load/v 11, v0x9b28568_0, 3; |
%cmpi/u 11, 4, 3; |
%mov 11, 4, 1; |
%jmp/0 T_11.11, 11; |
%movi 12, 2, 2; |
%jmp/1 T_11.13, 11; |
T_11.11 ; End of true expr. |
%jmp/0 T_11.12, 11; |
; End of false expr. |
%blend 12, 0, 2; Condition unknown. |
%jmp T_11.13; |
T_11.12 ; |
%mov 12, 0, 2; Return false value |
T_11.13 ; |
%jmp/0 T_11.9, 8; |
; End of false expr. |
%blend 9, 12, 2; Condition unknown. |
%jmp T_11.10; |
T_11.9 ; |
%mov 9, 12, 2; Return false value |
T_11.10 ; |
%ix/load 0, 4, 0; |
%set/x0 v0x9b27d90_0, 9, 2; |
%load/v 8, v0x9b28788_0, 3; |
%cmpi/u 8, 3, 3; |
%mov 8, 4, 1; |
%jmp/0 T_11.14, 8; |
%movi 9, 1, 2; |
%jmp/1 T_11.16, 8; |
T_11.14 ; End of true expr. |
%load/v 11, v0x9b28788_0, 3; |
%cmpi/u 11, 4, 3; |
%mov 11, 4, 1; |
%jmp/0 T_11.17, 11; |
%movi 12, 2, 2; |
%jmp/1 T_11.19, 11; |
T_11.17 ; End of true expr. |
%jmp/0 T_11.18, 11; |
; End of false expr. |
%blend 12, 0, 2; Condition unknown. |
%jmp T_11.19; |
T_11.18 ; |
%mov 12, 0, 2; Return false value |
T_11.19 ; |
%jmp/0 T_11.15, 8; |
; End of false expr. |
%blend 9, 12, 2; Condition unknown. |
%jmp T_11.16; |
T_11.15 ; |
%mov 9, 12, 2; Return false value |
T_11.16 ; |
%ix/load 0, 2, 0; |
%set/x0 v0x9b27d90_0, 9, 2; |
%load/v 8, v0x9b28490_0, 3; |
%cmpi/u 8, 3, 3; |
%mov 8, 4, 1; |
%jmp/0 T_11.20, 8; |
%movi 9, 1, 2; |
%jmp/1 T_11.22, 8; |
T_11.20 ; End of true expr. |
%load/v 11, v0x9b28490_0, 3; |
%cmpi/u 11, 4, 3; |
%mov 11, 4, 1; |
%jmp/0 T_11.23, 11; |
%movi 12, 2, 2; |
%jmp/1 T_11.25, 11; |
T_11.23 ; End of true expr. |
%jmp/0 T_11.24, 11; |
; End of false expr. |
%blend 12, 0, 2; Condition unknown. |
%jmp T_11.25; |
T_11.24 ; |
%mov 12, 0, 2; Return false value |
T_11.25 ; |
%jmp/0 T_11.21, 8; |
; End of false expr. |
%blend 9, 12, 2; Condition unknown. |
%jmp T_11.22; |
T_11.21 ; |
%mov 9, 12, 2; Return false value |
T_11.22 ; |
%ix/load 0, 0, 0; |
%set/x0 v0x9b27d90_0, 9, 2; |
T_11.1 ; |
%jmp T_11; |
.thread T_11; |
.scope S_0x9b25068; |
T_12 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b28628_0, 1; |
%jmp/0xz T_12.0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b27d40_0, 0, 0; |
%jmp T_12.1; |
T_12.0 ; |
%load/v 8, v0x9b28118_0, 4; |
%or/r 8, 8, 4; |
%jmp/0xz T_12.2, 8; |
%load/v 8, v0x9b27d40_0, 3; |
%mov 11, 0, 29; |
%addi 8, 1, 32; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b27d40_0, 0, 8; |
T_12.2 ; |
T_12.1 ; |
%jmp T_12; |
.thread T_12; |
.scope S_0x9b244e8; |
T_13 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24cd8_0, 1; |
%jmp/0xz T_13.0, 8; |
%set/v v0x9b24b80_0, 0, 32; |
T_13.2 ; |
%load/v 8, v0x9b24b80_0, 32; |
%cmpi/s 8, 2, 32; |
%jmp/0xz T_13.3, 5; |
%ix/getv/s 3, v0x9b24b80_0; |
%jmp/1 t_2, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9b24a10, 0, 0; |
t_2 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b24b80_0, 32; |
%set/v v0x9b24b80_0, 8, 32; |
%jmp T_13.2; |
T_13.3 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24d28_0, 0, 0; |
%jmp T_13.1; |
T_13.0 ; |
%load/v 8, v0x9b24fa8_0, 1; |
%jmp/0xz T_13.4, 8; |
%load/v 8, v0x9b24868_0, 41; |
%ix/getv 3, v0x9b24d28_0; |
%jmp/1 t_3, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9b24a10, 0, 8; |
t_3 ; |
%load/v 8, v0x9b24d28_0, 1; |
%mov 9, 0, 31; |
%addi 8, 1, 32; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24d28_0, 0, 8; |
T_13.4 ; |
T_13.1 ; |
%jmp T_13; |
.thread T_13; |
.scope S_0x9b244e8; |
T_14 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24cd8_0, 1; |
%jmp/0xz T_14.0, 8; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b248f0_0, 0, 0; |
%jmp T_14.1; |
T_14.0 ; |
%load/v 8, v0x9b24e20_0, 1; |
%jmp/0xz T_14.2, 8; |
%load/v 8, v0x9b24868_0, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b248f0_0, 0, 8; |
%jmp T_14.3; |
T_14.2 ; |
%load/v 8, v0x9b24d78_0, 1; |
%jmp/0xz T_14.4, 8; |
%ix/getv 3, v0x9b24c88_0; |
%load/av 8, v0x9b24a10, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b248f0_0, 0, 8; |
%jmp T_14.5; |
T_14.4 ; |
%ix/getv 3, v0x9b24c28_0; |
%load/av 8, v0x9b24a10, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b248f0_0, 0, 8; |
T_14.5 ; |
T_14.3 ; |
T_14.1 ; |
%jmp T_14; |
.thread T_14; |
.scope S_0x9b244e8; |
T_15 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24cd8_0, 1; |
%jmp/0xz T_15.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24c28_0, 0, 0; |
%jmp T_15.1; |
T_15.0 ; |
%load/v 8, v0x9b24d78_0, 1; |
%jmp/0xz T_15.2, 8; |
%load/v 8, v0x9b24c28_0, 1; |
%mov 9, 0, 31; |
%addi 8, 1, 32; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24c28_0, 0, 8; |
T_15.2 ; |
T_15.1 ; |
%jmp T_15; |
.thread T_15; |
.scope S_0x9b244e8; |
T_16 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24cd8_0, 1; |
%jmp/0xz T_16.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24e20_0, 0, 1; |
%jmp T_16.1; |
T_16.0 ; |
%load/v 8, v0x9b24a60_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%mov 8, 4, 1; |
%load/v 9, v0x9b24ac0_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_16.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24e20_0, 0, 1; |
%jmp T_16.3; |
T_16.2 ; |
%load/v 8, v0x9b24a60_0, 1; |
%mov 9, 0, 1; |
%cmpi/u 8, 0, 2; |
%mov 8, 4, 1; |
%load/v 9, v0x9b24e20_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9b24b20_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_16.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24e20_0, 0, 0; |
T_16.4 ; |
T_16.3 ; |
T_16.1 ; |
%jmp T_16; |
.thread T_16; |
.scope S_0x9b244e8; |
T_17 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24cd8_0, 1; |
%jmp/0xz T_17.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24ee0_0, 0, 0; |
%jmp T_17.1; |
T_17.0 ; |
%load/v 8, v0x9b24a60_0, 1; |
%mov 9, 0, 4; |
%cmpi/u 8, 1, 5; |
%mov 8, 4, 1; |
%load/v 9, v0x9b24b20_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_17.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24ee0_0, 0, 1; |
%jmp T_17.3; |
T_17.2 ; |
%load/v 8, v0x9b24a60_0, 1; |
%mov 9, 0, 1; |
%cmpi/u 8, 0, 2; |
%mov 8, 4, 1; |
%load/v 9, v0x9b24ee0_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9b24ac0_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_17.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24ee0_0, 0, 0; |
T_17.4 ; |
T_17.3 ; |
T_17.1 ; |
%jmp T_17; |
.thread T_17; |
.scope S_0x9b244e8; |
T_18 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24cd8_0, 1; |
%jmp/0xz T_18.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24950_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b249b0_0, 0, 0; |
%jmp T_18.1; |
T_18.0 ; |
%load/v 8, v0x9b24950_0, 1; |
%load/v 9, v0x9b24ee0_0, 1; |
%load/v 10, v0x9b24b20_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24950_0, 0, 8; |
%load/v 8, v0x9b249b0_0, 1; |
%load/v 9, v0x9b24e20_0, 1; |
%load/v 10, v0x9b24ac0_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b249b0_0, 0, 8; |
T_18.1 ; |
%jmp T_18; |
.thread T_18; |
.scope S_0x9b239f8; |
T_19 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24158_0, 1; |
%jmp/0xz T_19.0, 8; |
%set/v v0x9b24000_0, 0, 32; |
T_19.2 ; |
%load/v 8, v0x9b24000_0, 32; |
%cmpi/s 8, 2, 32; |
%jmp/0xz T_19.3, 5; |
%ix/getv/s 3, v0x9b24000_0; |
%jmp/1 t_4, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9b23e90, 0, 0; |
t_4 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b24000_0, 32; |
%set/v v0x9b24000_0, 8, 32; |
%jmp T_19.2; |
T_19.3 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b241a8_0, 0, 0; |
%jmp T_19.1; |
T_19.0 ; |
%load/v 8, v0x9b24428_0, 1; |
%jmp/0xz T_19.4, 8; |
%load/v 8, v0x9b23ce8_0, 41; |
%ix/getv 3, v0x9b241a8_0; |
%jmp/1 t_5, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9b23e90, 0, 8; |
t_5 ; |
%load/v 8, v0x9b241a8_0, 1; |
%mov 9, 0, 31; |
%addi 8, 1, 32; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b241a8_0, 0, 8; |
T_19.4 ; |
T_19.1 ; |
%jmp T_19; |
.thread T_19; |
.scope S_0x9b239f8; |
T_20 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24158_0, 1; |
%jmp/0xz T_20.0, 8; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b23d70_0, 0, 0; |
%jmp T_20.1; |
T_20.0 ; |
%load/v 8, v0x9b242a0_0, 1; |
%jmp/0xz T_20.2, 8; |
%load/v 8, v0x9b23ce8_0, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b23d70_0, 0, 8; |
%jmp T_20.3; |
T_20.2 ; |
%load/v 8, v0x9b241f8_0, 1; |
%jmp/0xz T_20.4, 8; |
%ix/getv 3, v0x9b24108_0; |
%load/av 8, v0x9b23e90, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b23d70_0, 0, 8; |
%jmp T_20.5; |
T_20.4 ; |
%ix/getv 3, v0x9b240a8_0; |
%load/av 8, v0x9b23e90, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9b23d70_0, 0, 8; |
T_20.5 ; |
T_20.3 ; |
T_20.1 ; |
%jmp T_20; |
.thread T_20; |
.scope S_0x9b239f8; |
T_21 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24158_0, 1; |
%jmp/0xz T_21.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b240a8_0, 0, 0; |
%jmp T_21.1; |
T_21.0 ; |
%load/v 8, v0x9b241f8_0, 1; |
%jmp/0xz T_21.2, 8; |
%load/v 8, v0x9b240a8_0, 1; |
%mov 9, 0, 31; |
%addi 8, 1, 32; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b240a8_0, 0, 8; |
T_21.2 ; |
T_21.1 ; |
%jmp T_21; |
.thread T_21; |
.scope S_0x9b239f8; |
T_22 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24158_0, 1; |
%jmp/0xz T_22.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b242a0_0, 0, 1; |
%jmp T_22.1; |
T_22.0 ; |
%load/v 8, v0x9b23ee0_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%mov 8, 4, 1; |
%load/v 9, v0x9b23f40_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_22.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b242a0_0, 0, 1; |
%jmp T_22.3; |
T_22.2 ; |
%load/v 8, v0x9b23ee0_0, 1; |
%mov 9, 0, 1; |
%cmpi/u 8, 0, 2; |
%mov 8, 4, 1; |
%load/v 9, v0x9b242a0_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9b23fa0_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_22.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b242a0_0, 0, 0; |
T_22.4 ; |
T_22.3 ; |
T_22.1 ; |
%jmp T_22; |
.thread T_22; |
.scope S_0x9b239f8; |
T_23 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24158_0, 1; |
%jmp/0xz T_23.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24360_0, 0, 0; |
%jmp T_23.1; |
T_23.0 ; |
%load/v 8, v0x9b23ee0_0, 1; |
%mov 9, 0, 4; |
%cmpi/u 8, 1, 5; |
%mov 8, 4, 1; |
%load/v 9, v0x9b23fa0_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_23.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24360_0, 0, 1; |
%jmp T_23.3; |
T_23.2 ; |
%load/v 8, v0x9b23ee0_0, 1; |
%mov 9, 0, 1; |
%cmpi/u 8, 0, 2; |
%mov 8, 4, 1; |
%load/v 9, v0x9b24360_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9b23f40_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_23.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b24360_0, 0, 0; |
T_23.4 ; |
T_23.3 ; |
T_23.1 ; |
%jmp T_23; |
.thread T_23; |
.scope S_0x9b239f8; |
T_24 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b24158_0, 1; |
%jmp/0xz T_24.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b23dd0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b23e30_0, 0, 0; |
%jmp T_24.1; |
T_24.0 ; |
%load/v 8, v0x9b23dd0_0, 1; |
%load/v 9, v0x9b24360_0, 1; |
%load/v 10, v0x9b23fa0_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b23dd0_0, 0, 8; |
%load/v 8, v0x9b23e30_0, 1; |
%load/v 9, v0x9b242a0_0, 1; |
%load/v 10, v0x9b23f40_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b23e30_0, 0, 8; |
T_24.1 ; |
%jmp T_24; |
.thread T_24; |
.scope S_0x9a3a6b0; |
T_25 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b23688_0, 1; |
%jmp/0xz T_25.0, 8; |
%set/v v0x9a576c0_0, 0, 32; |
T_25.2 ; |
%load/v 8, v0x9a576c0_0, 32; |
%cmpi/s 8, 2, 32; |
%jmp/0xz T_25.3, 5; |
%ix/getv/s 3, v0x9a576c0_0; |
%jmp/1 t_6, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a45e60, 0, 0; |
t_6 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9a576c0_0, 32; |
%set/v v0x9a576c0_0, 8, 32; |
%jmp T_25.2; |
T_25.3 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b236d8_0, 0, 0; |
%jmp T_25.1; |
T_25.0 ; |
%load/v 8, v0x9b23938_0, 1; |
%jmp/0xz T_25.4, 8; |
%load/v 8, v0x99e8520_0, 41; |
%ix/getv 3, v0x9b236d8_0; |
%jmp/1 t_7, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a45e60, 0, 8; |
t_7 ; |
%load/v 8, v0x9b236d8_0, 1; |
%mov 9, 0, 31; |
%addi 8, 1, 32; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b236d8_0, 0, 8; |
T_25.4 ; |
T_25.1 ; |
%jmp T_25; |
.thread T_25; |
.scope S_0x9a3a6b0; |
T_26 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b23688_0, 1; |
%jmp/0xz T_26.0, 8; |
%ix/load 0, 41, 0; |
%assign/v0 v0x99e85a8_0, 0, 0; |
%jmp T_26.1; |
T_26.0 ; |
%load/v 8, v0x9b237d0_0, 1; |
%jmp/0xz T_26.2, 8; |
%load/v 8, v0x99e8520_0, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x99e85a8_0, 0, 8; |
%jmp T_26.3; |
T_26.2 ; |
%load/v 8, v0x9b23728_0, 1; |
%jmp/0xz T_26.4, 8; |
%ix/getv 3, v0x9b23638_0; |
%load/av 8, v0x9a45e60, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x99e85a8_0, 0, 8; |
%jmp T_26.5; |
T_26.4 ; |
%ix/getv 3, v0x9b235e8_0; |
%load/av 8, v0x9a45e60, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x99e85a8_0, 0, 8; |
T_26.5 ; |
T_26.3 ; |
T_26.1 ; |
%jmp T_26; |
.thread T_26; |
.scope S_0x9a3a6b0; |
T_27 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b23688_0, 1; |
%jmp/0xz T_27.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b235e8_0, 0, 0; |
%jmp T_27.1; |
T_27.0 ; |
%load/v 8, v0x9b23728_0, 1; |
%jmp/0xz T_27.2, 8; |
%load/v 8, v0x9b235e8_0, 1; |
%mov 9, 0, 31; |
%addi 8, 1, 32; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b235e8_0, 0, 8; |
T_27.2 ; |
T_27.1 ; |
%jmp T_27; |
.thread T_27; |
.scope S_0x9a3a6b0; |
T_28 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b23688_0, 1; |
%jmp/0xz T_28.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b237d0_0, 0, 1; |
%jmp T_28.1; |
T_28.0 ; |
%load/v 8, v0x9a575a0_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%mov 8, 4, 1; |
%load/v 9, v0x9a57600_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_28.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b237d0_0, 0, 1; |
%jmp T_28.3; |
T_28.2 ; |
%load/v 8, v0x9a575a0_0, 1; |
%mov 9, 0, 1; |
%cmpi/u 8, 0, 2; |
%mov 8, 4, 1; |
%load/v 9, v0x9b237d0_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9a57660_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_28.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b237d0_0, 0, 0; |
T_28.4 ; |
T_28.3 ; |
T_28.1 ; |
%jmp T_28; |
.thread T_28; |
.scope S_0x9a3a6b0; |
T_29 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b23688_0, 1; |
%jmp/0xz T_29.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b23880_0, 0, 0; |
%jmp T_29.1; |
T_29.0 ; |
%load/v 8, v0x9a575a0_0, 1; |
%mov 9, 0, 4; |
%cmpi/u 8, 1, 5; |
%mov 8, 4, 1; |
%load/v 9, v0x9a57660_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_29.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b23880_0, 0, 1; |
%jmp T_29.3; |
T_29.2 ; |
%load/v 8, v0x9a575a0_0, 1; |
%mov 9, 0, 1; |
%cmpi/u 8, 0, 2; |
%mov 8, 4, 1; |
%load/v 9, v0x9b23880_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9a57600_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_29.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9b23880_0, 0, 0; |
T_29.4 ; |
T_29.3 ; |
T_29.1 ; |
%jmp T_29; |
.thread T_29; |
.scope S_0x9a3a6b0; |
T_30 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b23688_0, 1; |
%jmp/0xz T_30.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a45da0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a45e00_0, 0, 0; |
%jmp T_30.1; |
T_30.0 ; |
%load/v 8, v0x9a45da0_0, 1; |
%load/v 9, v0x9b23880_0, 1; |
%load/v 10, v0x9a57660_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a45da0_0, 0, 8; |
%load/v 8, v0x9a45e00_0, 1; |
%load/v 9, v0x9b237d0_0, 1; |
%load/v 10, v0x9a57600_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a45e00_0, 0, 8; |
T_30.1 ; |
%jmp T_30; |
.thread T_30; |
.scope S_0x9afccd0; |
T_31 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x99e5020_0, 1; |
%jmp/0xz T_31.0, 8; |
%set/v v0x9adc6f0_0, 0, 32; |
T_31.2 ; |
%load/v 8, v0x9adc6f0_0, 32; |
%cmpi/s 8, 2, 32; |
%jmp/0xz T_31.3, 5; |
%ix/getv/s 3, v0x9adc6f0_0; |
%jmp/1 t_8, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aecb38, 0, 0; |
t_8 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9adc6f0_0, 32; |
%set/v v0x9adc6f0_0, 8, 32; |
%jmp T_31.2; |
T_31.3 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x99e5070_0, 0, 0; |
%jmp T_31.1; |
T_31.0 ; |
%load/v 8, v0x9a34bb8_0, 1; |
%jmp/0xz T_31.4, 8; |
%load/v 8, v0x9abb408_0, 41; |
%ix/getv 3, v0x99e5070_0; |
%jmp/1 t_9, 4; |
%ix/load 0, 41, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aecb38, 0, 8; |
t_9 ; |
%load/v 8, v0x99e5070_0, 1; |
%mov 9, 0, 31; |
%addi 8, 1, 32; |
%ix/load 0, 1, 0; |
%assign/v0 v0x99e5070_0, 0, 8; |
T_31.4 ; |
T_31.1 ; |
%jmp T_31; |
.thread T_31; |
.scope S_0x9afccd0; |
T_32 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x99e5020_0, 1; |
%jmp/0xz T_32.0, 8; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9afced8_0, 0, 0; |
%jmp T_32.1; |
T_32.0 ; |
%load/v 8, v0x9a34b68_0, 1; |
%jmp/0xz T_32.2, 8; |
%load/v 8, v0x9abb408_0, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9afced8_0, 0, 8; |
%jmp T_32.3; |
T_32.2 ; |
%load/v 8, v0x9a125f8_0, 1; |
%jmp/0xz T_32.4, 8; |
%ix/getv 3, v0x99e4fd0_0; |
%load/av 8, v0x9aecb38, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9afced8_0, 0, 8; |
%jmp T_32.5; |
T_32.4 ; |
%ix/getv 3, v0x99e4f70_0; |
%load/av 8, v0x9aecb38, 41; |
%ix/load 0, 41, 0; |
%assign/v0 v0x9afced8_0, 0, 8; |
T_32.5 ; |
T_32.3 ; |
T_32.1 ; |
%jmp T_32; |
.thread T_32; |
.scope S_0x9afccd0; |
T_33 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x99e5020_0, 1; |
%jmp/0xz T_33.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x99e4f70_0, 0, 0; |
%jmp T_33.1; |
T_33.0 ; |
%load/v 8, v0x9a125f8_0, 1; |
%jmp/0xz T_33.2, 8; |
%load/v 8, v0x99e4f70_0, 1; |
%mov 9, 0, 31; |
%addi 8, 1, 32; |
%ix/load 0, 1, 0; |
%assign/v0 v0x99e4f70_0, 0, 8; |
T_33.2 ; |
T_33.1 ; |
%jmp T_33; |
.thread T_33; |
.scope S_0x9afccd0; |
T_34 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x99e5020_0, 1; |
%jmp/0xz T_34.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a34b68_0, 0, 1; |
%jmp T_34.1; |
T_34.0 ; |
%load/v 8, v0x9aecb88_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%mov 8, 4, 1; |
%load/v 9, v0x9adc630_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_34.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a34b68_0, 0, 1; |
%jmp T_34.3; |
T_34.2 ; |
%load/v 8, v0x9aecb88_0, 1; |
%mov 9, 0, 1; |
%cmpi/u 8, 0, 2; |
%mov 8, 4, 1; |
%load/v 9, v0x9a34b68_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9adc690_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_34.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a34b68_0, 0, 0; |
T_34.4 ; |
T_34.3 ; |
T_34.1 ; |
%jmp T_34; |
.thread T_34; |
.scope S_0x9afccd0; |
T_35 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x99e5020_0, 1; |
%jmp/0xz T_35.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a34c18_0, 0, 0; |
%jmp T_35.1; |
T_35.0 ; |
%load/v 8, v0x9aecb88_0, 1; |
%mov 9, 0, 4; |
%cmpi/u 8, 1, 5; |
%mov 8, 4, 1; |
%load/v 9, v0x9adc690_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_35.2, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a34c18_0, 0, 1; |
%jmp T_35.3; |
T_35.2 ; |
%load/v 8, v0x9aecb88_0, 1; |
%mov 9, 0, 1; |
%cmpi/u 8, 0, 2; |
%mov 8, 4, 1; |
%load/v 9, v0x9a34c18_0, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9adc630_0, 1; |
%and 8, 9, 1; |
%jmp/0xz T_35.4, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a34c18_0, 0, 0; |
T_35.4 ; |
T_35.3 ; |
T_35.1 ; |
%jmp T_35; |
.thread T_35; |
.scope S_0x9afccd0; |
T_36 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x99e5020_0, 1; |
%jmp/0xz T_36.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9afcf38_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aecad8_0, 0, 0; |
%jmp T_36.1; |
T_36.0 ; |
%load/v 8, v0x9afcf38_0, 1; |
%load/v 9, v0x9a34c18_0, 1; |
%load/v 10, v0x9adc690_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9afcf38_0, 0, 8; |
%load/v 8, v0x9aecad8_0, 1; |
%load/v 9, v0x9a34b68_0, 1; |
%load/v 10, v0x9adc630_0, 1; |
%and 9, 10, 1; |
%or 8, 9, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aecad8_0, 0, 8; |
T_36.1 ; |
%jmp T_36; |
.thread T_36; |
.scope S_0x9abc5b8; |
T_37 ; |
%set/v v0x9ab5640_0, 0, 32; |
T_37.0 ; |
%load/v 8, v0x9ab5640_0, 32; |
%cmpi/s 8, 10, 32; |
%jmp/0xz T_37.1, 5; |
%ix/getv/s 3, v0x9ab5640_0; |
%jmp/1 t_10, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9adce38, 0, 4; |
t_10 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9ab5640_0, 32; |
%set/v v0x9ab5640_0, 8, 32; |
%jmp T_37.0; |
T_37.1 ; |
%end; |
.thread T_37; |
.scope S_0x9abc5b8; |
T_38 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9accf50_0, 1; |
%jmp/0xz T_38.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab7f48_0, 0, 0; |
%jmp T_38.1; |
T_38.0 ; |
%load/v 8, v0x9ab7f48_0, 1; |
%inv 8, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab7f48_0, 0, 8; |
T_38.1 ; |
%jmp T_38; |
.thread T_38; |
.scope S_0x9abc5b8; |
T_39 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9accf50_0, 1; |
%jmp/0xz T_39.0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accfa0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aef0f8_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aeec68_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accad0_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9acca70_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ac3c18_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab5690_0, 0, 0; |
%set/v v0x9abc838_0, 0, 32; |
T_39.2 ; |
%load/v 8, v0x9abc838_0, 32; |
%cmpi/s 8, 6, 32; |
%jmp/0xz T_39.3, 5; |
%movi 8, 1, 8; |
%ix/getv/s 3, v0x9abc838_0; |
%jmp/1 t_11, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aeec18, 0, 8; |
t_11 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9abc838_0, 32; |
%set/v v0x9abc838_0, 8, 32; |
%jmp T_39.2; |
T_39.3 ; |
%jmp T_39.1; |
T_39.0 ; |
%load/v 8, v0x9aaba98_0, 3; |
%cmpi/u 8, 0, 3; |
%jmp/1 T_39.4, 6; |
%cmpi/u 8, 1, 3; |
%jmp/1 T_39.5, 6; |
%cmpi/u 8, 2, 3; |
%jmp/1 T_39.6, 6; |
%cmpi/u 8, 3, 3; |
%jmp/1 T_39.7, 6; |
%cmpi/u 8, 4, 3; |
%jmp/1 T_39.8, 6; |
%jmp T_39.9; |
T_39.4 ; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ac3c18_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab5690_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accfa0_0, 0, 0; |
%load/v 8, v0x9acdfe0_0, 4; |
%mov 12, 0, 1; |
%cmpi/u 8, 0, 5; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9ab7f48_0, 1; |
%inv 9, 1; |
%or 8, 9, 1; |
%jmp/0xz T_39.10, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 0; |
%jmp T_39.11; |
T_39.10 ; |
%load/v 8, v0x9ace408_0, 4; |
%cmpi/u 8, 1, 4; |
%mov 8, 4, 1; |
%load/v 9, v0x9ace408_0, 4; |
%cmpi/u 9, 2, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9aef0f8_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9accad0_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%jmp/0xz T_39.12, 8; |
%load/v 8, v0x9ace3a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aaba38_0, 0, 8; |
%load/v 8, v0x9ace3a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab7f98_0, 0, 8; |
%ix/getv 3, v0x9ace3a8_0; |
%load/av 8, v0x9adce38, 4; |
%cmpi/u 8, 9, 4; |
%jmp/1 T_39.14, 6; |
%cmpi/u 8, 5, 4; |
%jmp/1 T_39.15, 6; |
%cmpi/u 8, 3, 4; |
%jmp/1 T_39.16, 6; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_39.17, 6; |
%jmp T_39.18; |
T_39.14 ; |
%load/v 8, v0x9ace408_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_39.19, 4; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%jmp T_39.20; |
T_39.19 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
T_39.20 ; |
%jmp T_39.18; |
T_39.15 ; |
%load/v 8, v0x9ace408_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_39.21, 4; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%jmp T_39.22; |
T_39.21 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
T_39.22 ; |
%jmp T_39.18; |
T_39.16 ; |
%load/v 8, v0x9ace408_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_39.23, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aef0f8_0, 0, 1; |
%load/v 8, v0x9ace3a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aeec68_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 8; |
%jmp T_39.24; |
T_39.23 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
T_39.24 ; |
%jmp T_39.18; |
T_39.17 ; |
%load/v 8, v0x9ace408_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_39.25, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aef0f8_0, 0, 1; |
%load/v 8, v0x9ace3a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aeec68_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 8; |
%jmp T_39.26; |
T_39.25 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accad0_0, 0, 1; |
%load/v 8, v0x9ace3a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9acca70_0, 0, 8; |
%movi 8, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
%movi 11, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 11; |
T_39.26 ; |
%jmp T_39.18; |
T_39.18 ; |
T_39.12 ; |
T_39.11 ; |
%jmp T_39.9; |
T_39.5 ; |
%movi 8, 9, 4; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_12, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9adce38, 0, 8; |
t_12 ; |
%load/v 8, v0x9a91e30_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_39.27, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_39.28, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_39.29, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_39.30, 6; |
%jmp T_39.31; |
T_39.27 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_13, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_13 ; |
%jmp T_39.31; |
T_39.28 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_14, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 8, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_14 ; |
%jmp T_39.31; |
T_39.29 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_15, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 16, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_15 ; |
%jmp T_39.31; |
T_39.30 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_16, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 24, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_16 ; |
%jmp T_39.31; |
T_39.31 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%mov 16, 0, 24; |
%addi 8, 1, 32; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_17, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aeec18, 0, 8; |
t_17 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accfa0_0, 0, 1; |
%jmp T_39.9; |
T_39.6 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accfa0_0, 0, 1; |
%jmp T_39.9; |
T_39.7 ; |
%load/v 8, v0x9aaba38_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab7f98_0, 0, 8; |
%load/v 8, v0x9ac3c18_0, 32; |
%mov 40, 39, 1; |
%addi 8, 1, 33; |
%set/v v0x9ac3c18_0, 8, 32; |
%load/v 8, v0x9ac3c68_0, 1; |
%jmp/0xz T_39.32, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accfa0_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%jmp T_39.33; |
T_39.32 ; |
%movi 8, 31, 32; |
%load/v 40, v0x9ac3c18_0, 32; |
%cmp/s 8, 40, 32; |
%jmp/0xz T_39.34, 5; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accfa0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%jmp T_39.35; |
T_39.34 ; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
T_39.35 ; |
T_39.33 ; |
%jmp T_39.9; |
T_39.8 ; |
%load/v 8, v0x9aaba38_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab7f98_0, 0, 8; |
%load/v 8, v0x9ab5690_0, 32; |
%mov 40, 39, 1; |
%addi 8, 1, 33; |
%set/v v0x9ab5690_0, 8, 32; |
%load/v 8, v0x9ac3c68_0, 1; |
%jmp/0xz T_39.36, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accfa0_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%jmp T_39.37; |
T_39.36 ; |
%movi 8, 31, 32; |
%load/v 40, v0x9ab5690_0, 32; |
%cmp/s 8, 40, 32; |
%jmp/0xz T_39.38, 5; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accfa0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%jmp T_39.39; |
T_39.38 ; |
%movi 8, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aaba98_0, 0, 8; |
T_39.39 ; |
T_39.37 ; |
%jmp T_39.9; |
T_39.9 ; |
T_39.1 ; |
%jmp T_39; |
.thread T_39; |
.scope S_0x9abc5b8; |
T_40 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9accf50_0, 1; |
%jmp/0xz T_40.0, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 0; |
%jmp T_40.1; |
T_40.0 ; |
%load/v 8, v0x9acdfe0_0, 4; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_40.2, 6; |
%cmpi/u 8, 1, 4; |
%jmp/1 T_40.3, 6; |
%cmpi/u 8, 2, 4; |
%jmp/1 T_40.4, 6; |
%cmpi/u 8, 3, 4; |
%jmp/1 T_40.5, 6; |
%cmpi/u 8, 4, 4; |
%jmp/1 T_40.6, 6; |
%cmpi/u 8, 5, 4; |
%jmp/1 T_40.7, 6; |
%cmpi/u 8, 6, 4; |
%jmp/1 T_40.8, 6; |
%cmpi/u 8, 8, 4; |
%jmp/1 T_40.9, 6; |
%jmp T_40.10; |
T_40.2 ; |
%load/v 8, v0x9a85cf0_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9acdf80_0, 0, 8; |
%load/v 8, v0x9aaba98_0, 3; |
%mov 11, 0, 1; |
%cmpi/u 8, 0, 4; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9ab7f48_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9a84e58_0, 1; |
%or 8, 9, 1; |
%jmp/0xz T_40.11, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 0; |
%jmp T_40.12; |
T_40.11 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%load/v 8, v0x9a84df0_0, 3; |
%cmpi/u 8, 0, 3; |
%jmp/1 T_40.13, 6; |
%cmpi/u 8, 1, 3; |
%jmp/1 T_40.14, 6; |
%cmpi/u 8, 2, 3; |
%jmp/1 T_40.15, 6; |
%cmpi/u 8, 3, 3; |
%jmp/1 T_40.16, 6; |
%cmpi/u 8, 4, 3; |
%jmp/1 T_40.17, 6; |
%vpi_call 10 504 "$display", "Error 1. Wrong value - CPU:%d, cbus_cmd_i = %h,time=%d\012", v0x9a91e30_0, v0x9a84df0_0, $time; |
%jmp T_40.19; |
T_40.13 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 0; |
%jmp T_40.19; |
T_40.14 ; |
%movi 8, 1, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 0; |
%jmp T_40.19; |
T_40.15 ; |
%movi 8, 2, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 0; |
%jmp T_40.19; |
T_40.16 ; |
%movi 8, 5, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 0; |
%jmp T_40.19; |
T_40.17 ; |
%movi 8, 6, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 0; |
%jmp T_40.19; |
T_40.19 ; |
T_40.12 ; |
%jmp T_40.10; |
T_40.3 ; |
%ix/getv 3, v0x9acdf80_0; |
%load/av 8, v0x9adce38, 4; |
%cmpi/u 8, 9, 4; |
%jmp/0xz T_40.20, 4; |
%movi 8, 3, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 8; |
%jmp T_40.21; |
T_40.20 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%ix/getv 3, v0x9acdf80_0; |
%jmp/1 t_18, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9adce38, 0, 0; |
t_18 ; |
%ix/getv 3, v0x9acdf80_0; |
%jmp/1 t_19, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9acdaa0, 0, 0; |
t_19 ; |
T_40.21 ; |
%jmp T_40.10; |
T_40.4 ; |
%ix/getv 3, v0x9acdf80_0; |
%load/av 8, v0x9adce38, 4; |
%cmpi/u 8, 9, 4; |
%jmp/0xz T_40.22, 4; |
%movi 8, 3, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 8; |
%jmp T_40.23; |
T_40.22 ; |
%ix/getv 3, v0x9acdf80_0; |
%load/av 8, v0x9adce38, 4; |
%cmpi/u 8, 5, 4; |
%jmp/0xz T_40.24, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9acdf80_0; |
%jmp/1 t_20, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9adce38, 0, 8; |
t_20 ; |
%jmp T_40.25; |
T_40.24 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
T_40.25 ; |
T_40.23 ; |
%jmp T_40.10; |
T_40.5 ; |
%ix/getv 3, v0x9acdf80_0; |
%load/av 8, v0x9adce38, 4; |
%cmpi/u 8, 9, 4; |
%inv 4, 1; |
%jmp/0xz T_40.26, 4; |
%vpi_call 10 550 "$display", "Error 2. cache_state[c_addr] is not M.\012", " CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time:%d", v0x9a91e30_0, v0x9acdf80_0, &A<v0x9adce38, v0x9acdf80_0 >, $time; |
%wait E_0x9aece10; |
%vpi_call 10 556 "$finish"; |
%jmp T_40.27; |
T_40.26 ; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 8; |
%load/v 8, v0x9acdf80_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab7f98_0, 0, 8; |
%ix/getv 3, v0x9acdf80_0; |
%load/av 8, v0x9acdaa0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ae4498_0, 0, 8; |
%load/v 8, v0x9ac3c68_0, 1; |
%jmp/0xz T_40.28, 8; |
%ix/getv 3, v0x9acdf80_0; |
%jmp/1 t_21, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9adce38, 0, 0; |
t_21 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
T_40.28 ; |
T_40.27 ; |
%jmp T_40.10; |
T_40.6 ; |
%ix/getv 3, v0x9acdf80_0; |
%load/av 8, v0x9adce38, 4; |
%cmpi/u 8, 3, 4; |
%mov 8, 4, 1; |
%ix/getv 3, v0x9acdf80_0; |
%load/av 9, v0x9adce38, 4; |
%cmpi/u 9, 5, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%inv 8, 1; |
%jmp/0xz T_40.30, 8; |
%vpi_call 10 586 "$display", "Error 3. cache_state[c_addr] is not S or E.\012"; |
%vpi_call 10 587 "$display", " CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time=%d", v0x9a91e30_0, v0x9acdf80_0, &A<v0x9adce38, v0x9acdf80_0 >, $time; |
%wait E_0x9aece10; |
%vpi_call 10 592 "$finish"; |
%jmp T_40.31; |
T_40.30 ; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 8; |
%load/v 8, v0x9acdf80_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab7f98_0, 0, 8; |
%ix/getv 3, v0x9acdf80_0; |
%load/av 8, v0x9acdaa0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ae4498_0, 0, 8; |
%load/v 8, v0x9ac3c68_0, 1; |
%jmp/0xz T_40.32, 8; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9acdf80_0; |
%jmp/1 t_22, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9adce38, 0, 8; |
t_22 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 1; |
T_40.32 ; |
T_40.31 ; |
%jmp T_40.10; |
T_40.7 ; |
%load/v 8, v0x9aef0f8_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9aeec68_0, 32; |
%load/v 41, v0x9acdf80_0, 32; |
%cmp/u 9, 41, 32; |
%inv 4, 1; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_40.34, 8; |
%vpi_call 10 621 "$display", "Error 4. Write to cache without early broadcast.\012", " CPU:%d,wr_proc_wait_for_en=%h,wr_proc_addr=%h,c_addr=%h, time:%d", v0x9a91e30_0, v0x9aef0f8_0, v0x9aeec68_0, v0x9acdf80_0, $time; |
%wait E_0x9aece10; |
%vpi_call 10 628 "$finish"; |
T_40.34 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 8; |
%load/v 8, v0x9acdf80_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab7f98_0, 0, 8; |
%load/v 8, v0x9ac3c68_0, 1; |
%jmp/0xz T_40.36, 8; |
%load/v 8, v0x9ace8e8_0, 32; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_23, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_23 ; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_24, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9adce38, 0, 8; |
t_24 ; |
%movi 8, 8, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
T_40.36 ; |
%jmp T_40.10; |
T_40.8 ; |
%load/v 8, v0x9accad0_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9acca70_0, 32; |
%load/v 41, v0x9acdf80_0, 32; |
%cmp/u 9, 41, 32; |
%inv 4, 1; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_40.38, 8; |
%vpi_call 10 655 "$display", "Error 5. Read to cache without early broadcast.\012", " CPU:%d,rd_proc_wait_for_en=%h,rd_proc_addr=%h,c_addr=%h,time:%d\012", v0x9a91e30_0, v0x9accad0_0, v0x9acca70_0, v0x9acdf80_0, $time; |
%wait E_0x9aece10; |
%vpi_call 10 662 "$finish"; |
T_40.38 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 8; |
%load/v 8, v0x9acdf80_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab7f98_0, 0, 8; |
%load/v 8, v0x9ac3c68_0, 1; |
%jmp/0xz T_40.40, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%load/v 8, v0x9ace8e8_0, 32; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_25, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_25 ; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_26, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9adce38, 0, 8; |
t_26 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9accad0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
T_40.40 ; |
%jmp T_40.10; |
T_40.9 ; |
%load/v 8, v0x9a91e30_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_40.42, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_40.43, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_40.44, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_40.45, 6; |
%jmp T_40.46; |
T_40.42 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_27, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_27 ; |
%jmp T_40.46; |
T_40.43 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_28, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 8, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_28 ; |
%jmp T_40.46; |
T_40.44 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_29, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 16, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_29 ; |
%jmp T_40.46; |
T_40.45 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_30, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 24, 0; part off |
%assign/av v0x9acdaa0, 0, 8; |
t_30 ; |
%jmp T_40.46; |
T_40.46 ; |
%ix/getv 3, v0x9aaba38_0; |
%load/av 8, v0x9aeec18, 8; |
%mov 16, 0, 24; |
%addi 8, 1, 32; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_31, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aeec18, 0, 8; |
t_31 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9acdfe0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ace888_0, 0, 0; |
%movi 8, 9, 4; |
%ix/getv 3, v0x9aaba38_0; |
%jmp/1 t_32, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9adce38, 0, 8; |
t_32 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84e58_0, 0, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aef0f8_0, 0, 0; |
%jmp T_40.10; |
T_40.10 ; |
T_40.1 ; |
%jmp T_40; |
.thread T_40; |
.scope S_0x9a842e8; |
T_41 ; |
%set/v v0x9aba3a0_0, 0, 32; |
T_41.0 ; |
%load/v 8, v0x9aba3a0_0, 32; |
%cmpi/s 8, 10, 32; |
%jmp/0xz T_41.1, 5; |
%ix/getv/s 3, v0x9aba3a0_0; |
%jmp/1 t_33, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9a817f8, 0, 4; |
t_33 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9aba3a0_0, 32; |
%set/v v0x9aba3a0_0, 8, 32; |
%jmp T_41.0; |
T_41.1 ; |
%end; |
.thread T_41; |
.scope S_0x9a842e8; |
T_42 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9abe460_0, 1; |
%jmp/0xz T_42.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a96800_0, 0, 0; |
%jmp T_42.1; |
T_42.0 ; |
%load/v 8, v0x9a96800_0, 1; |
%inv 8, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a96800_0, 0, 8; |
T_42.1 ; |
%jmp T_42; |
.thread T_42; |
.scope S_0x9a842e8; |
T_43 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9abe460_0, 1; |
%jmp/0xz T_43.0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abe1e0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abdc98_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9abdc38_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abcab8_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab1840_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a97438_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aaac18_0, 0, 0; |
%set/v v0x9aba3f0_0, 0, 32; |
T_43.2 ; |
%load/v 8, v0x9aba3f0_0, 32; |
%cmpi/s 8, 6, 32; |
%jmp/0xz T_43.3, 5; |
%movi 8, 1, 8; |
%ix/getv/s 3, v0x9aba3f0_0; |
%jmp/1 t_34, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9abdfc0, 0, 8; |
t_34 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9aba3f0_0, 32; |
%set/v v0x9aba3f0_0, 8, 32; |
%jmp T_43.2; |
T_43.3 ; |
%jmp T_43.1; |
T_43.0 ; |
%load/v 8, v0x9a967a0_0, 3; |
%cmpi/u 8, 0, 3; |
%jmp/1 T_43.4, 6; |
%cmpi/u 8, 1, 3; |
%jmp/1 T_43.5, 6; |
%cmpi/u 8, 2, 3; |
%jmp/1 T_43.6, 6; |
%cmpi/u 8, 3, 3; |
%jmp/1 T_43.7, 6; |
%cmpi/u 8, 4, 3; |
%jmp/1 T_43.8, 6; |
%jmp T_43.9; |
T_43.4 ; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a97438_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aaac18_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abe1e0_0, 0, 0; |
%load/v 8, v0x9a830b8_0, 4; |
%mov 12, 0, 1; |
%cmpi/u 8, 0, 5; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9a96800_0, 1; |
%inv 9, 1; |
%or 8, 9, 1; |
%jmp/0xz T_43.10, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 0; |
%jmp T_43.11; |
T_43.10 ; |
%load/v 8, v0x9abdf60_0, 4; |
%cmpi/u 8, 1, 4; |
%mov 8, 4, 1; |
%load/v 9, v0x9abdf60_0, 4; |
%cmpi/u 9, 2, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9abdc98_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9abcab8_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%jmp/0xz T_43.12, 8; |
%load/v 8, v0x9abe240_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aafa30_0, 0, 8; |
%load/v 8, v0x9abe240_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aa0278_0, 0, 8; |
%ix/getv 3, v0x9abe240_0; |
%load/av 8, v0x9a817f8, 4; |
%cmpi/u 8, 9, 4; |
%jmp/1 T_43.14, 6; |
%cmpi/u 8, 5, 4; |
%jmp/1 T_43.15, 6; |
%cmpi/u 8, 3, 4; |
%jmp/1 T_43.16, 6; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_43.17, 6; |
%jmp T_43.18; |
T_43.14 ; |
%load/v 8, v0x9abdf60_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_43.19, 4; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%jmp T_43.20; |
T_43.19 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
T_43.20 ; |
%jmp T_43.18; |
T_43.15 ; |
%load/v 8, v0x9abdf60_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_43.21, 4; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%jmp T_43.22; |
T_43.21 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
T_43.22 ; |
%jmp T_43.18; |
T_43.16 ; |
%load/v 8, v0x9abdf60_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_43.23, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abdc98_0, 0, 1; |
%load/v 8, v0x9abe240_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9abdc38_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 8; |
%jmp T_43.24; |
T_43.23 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
T_43.24 ; |
%jmp T_43.18; |
T_43.17 ; |
%load/v 8, v0x9abdf60_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_43.25, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abdc98_0, 0, 1; |
%load/v 8, v0x9abe240_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9abdc38_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 8; |
%jmp T_43.26; |
T_43.25 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abcab8_0, 0, 1; |
%load/v 8, v0x9abe240_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab1840_0, 0, 8; |
%movi 8, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
%movi 11, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 11; |
T_43.26 ; |
%jmp T_43.18; |
T_43.18 ; |
T_43.12 ; |
T_43.11 ; |
%jmp T_43.9; |
T_43.5 ; |
%movi 8, 9, 4; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_35, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a817f8, 0, 8; |
t_35 ; |
%load/v 8, v0x9abaf48_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_43.27, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_43.28, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_43.29, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_43.30, 6; |
%jmp T_43.31; |
T_43.27 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_36, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_36 ; |
%jmp T_43.31; |
T_43.28 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_37, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 8, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_37 ; |
%jmp T_43.31; |
T_43.29 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_38, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 16, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_38 ; |
%jmp T_43.31; |
T_43.30 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_39, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 24, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_39 ; |
%jmp T_43.31; |
T_43.31 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%mov 16, 0, 24; |
%addi 8, 1, 32; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_40, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9abdfc0, 0, 8; |
t_40 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abe1e0_0, 0, 1; |
%jmp T_43.9; |
T_43.6 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abe1e0_0, 0, 1; |
%jmp T_43.9; |
T_43.7 ; |
%load/v 8, v0x9aafa30_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aa0278_0, 0, 8; |
%load/v 8, v0x9a97438_0, 32; |
%mov 40, 39, 1; |
%addi 8, 1, 33; |
%set/v v0x9a97438_0, 8, 32; |
%load/v 8, v0x9a97498_0, 1; |
%jmp/0xz T_43.32, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abe1e0_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%jmp T_43.33; |
T_43.32 ; |
%movi 8, 31, 32; |
%load/v 40, v0x9a97438_0, 32; |
%cmp/s 8, 40, 32; |
%jmp/0xz T_43.34, 5; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abe1e0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%jmp T_43.35; |
T_43.34 ; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
T_43.35 ; |
T_43.33 ; |
%jmp T_43.9; |
T_43.8 ; |
%load/v 8, v0x9aafa30_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aa0278_0, 0, 8; |
%load/v 8, v0x9aaac18_0, 32; |
%mov 40, 39, 1; |
%addi 8, 1, 33; |
%set/v v0x9aaac18_0, 8, 32; |
%load/v 8, v0x9a97498_0, 1; |
%jmp/0xz T_43.36, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abe1e0_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%jmp T_43.37; |
T_43.36 ; |
%movi 8, 31, 32; |
%load/v 40, v0x9aaac18_0, 32; |
%cmp/s 8, 40, 32; |
%jmp/0xz T_43.38, 5; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abe1e0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%jmp T_43.39; |
T_43.38 ; |
%movi 8, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a967a0_0, 0, 8; |
T_43.39 ; |
T_43.37 ; |
%jmp T_43.9; |
T_43.9 ; |
T_43.1 ; |
%jmp T_43; |
.thread T_43; |
.scope S_0x9a842e8; |
T_44 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9abe460_0, 1; |
%jmp/0xz T_44.0, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 0; |
%jmp T_44.1; |
T_44.0 ; |
%load/v 8, v0x9a830b8_0, 4; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_44.2, 6; |
%cmpi/u 8, 1, 4; |
%jmp/1 T_44.3, 6; |
%cmpi/u 8, 2, 4; |
%jmp/1 T_44.4, 6; |
%cmpi/u 8, 3, 4; |
%jmp/1 T_44.5, 6; |
%cmpi/u 8, 4, 4; |
%jmp/1 T_44.6, 6; |
%cmpi/u 8, 5, 4; |
%jmp/1 T_44.7, 6; |
%cmpi/u 8, 6, 4; |
%jmp/1 T_44.8, 6; |
%cmpi/u 8, 8, 4; |
%jmp/1 T_44.9, 6; |
%jmp T_44.10; |
T_44.2 ; |
%load/v 8, v0x9ab0848_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a83068_0, 0, 8; |
%load/v 8, v0x9a967a0_0, 3; |
%mov 11, 0, 1; |
%cmpi/u 8, 0, 4; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9a96800_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9ab4888_0, 1; |
%or 8, 9, 1; |
%jmp/0xz T_44.11, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 0; |
%jmp T_44.12; |
T_44.11 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%load/v 8, v0x9ab0898_0, 3; |
%cmpi/u 8, 0, 3; |
%jmp/1 T_44.13, 6; |
%cmpi/u 8, 1, 3; |
%jmp/1 T_44.14, 6; |
%cmpi/u 8, 2, 3; |
%jmp/1 T_44.15, 6; |
%cmpi/u 8, 3, 3; |
%jmp/1 T_44.16, 6; |
%cmpi/u 8, 4, 3; |
%jmp/1 T_44.17, 6; |
%vpi_call 10 504 "$display", "Error 1. Wrong value - CPU:%d, cbus_cmd_i = %h,time=%d\012", v0x9abaf48_0, v0x9ab0898_0, $time; |
%jmp T_44.19; |
T_44.13 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 0; |
%jmp T_44.19; |
T_44.14 ; |
%movi 8, 1, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 0; |
%jmp T_44.19; |
T_44.15 ; |
%movi 8, 2, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 0; |
%jmp T_44.19; |
T_44.16 ; |
%movi 8, 5, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 0; |
%jmp T_44.19; |
T_44.17 ; |
%movi 8, 6, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 0; |
%jmp T_44.19; |
T_44.19 ; |
T_44.12 ; |
%jmp T_44.10; |
T_44.3 ; |
%ix/getv 3, v0x9a83068_0; |
%load/av 8, v0x9a817f8, 4; |
%cmpi/u 8, 9, 4; |
%jmp/0xz T_44.20, 4; |
%movi 8, 3, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 8; |
%jmp T_44.21; |
T_44.20 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%ix/getv 3, v0x9a83068_0; |
%jmp/1 t_41, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a817f8, 0, 0; |
t_41 ; |
%ix/getv 3, v0x9a83068_0; |
%jmp/1 t_42, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a82ba0, 0, 0; |
t_42 ; |
T_44.21 ; |
%jmp T_44.10; |
T_44.4 ; |
%ix/getv 3, v0x9a83068_0; |
%load/av 8, v0x9a817f8, 4; |
%cmpi/u 8, 9, 4; |
%jmp/0xz T_44.22, 4; |
%movi 8, 3, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 8; |
%jmp T_44.23; |
T_44.22 ; |
%ix/getv 3, v0x9a83068_0; |
%load/av 8, v0x9a817f8, 4; |
%cmpi/u 8, 5, 4; |
%jmp/0xz T_44.24, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9a83068_0; |
%jmp/1 t_43, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a817f8, 0, 8; |
t_43 ; |
%jmp T_44.25; |
T_44.24 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
T_44.25 ; |
T_44.23 ; |
%jmp T_44.10; |
T_44.5 ; |
%ix/getv 3, v0x9a83068_0; |
%load/av 8, v0x9a817f8, 4; |
%cmpi/u 8, 9, 4; |
%inv 4, 1; |
%jmp/0xz T_44.26, 4; |
%vpi_call 10 550 "$display", "Error 2. cache_state[c_addr] is not M.\012", " CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time:%d", v0x9abaf48_0, v0x9a83068_0, &A<v0x9a817f8, v0x9a83068_0 >, $time; |
%wait E_0x9aece10; |
%vpi_call 10 556 "$finish"; |
%jmp T_44.27; |
T_44.26 ; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 8; |
%load/v 8, v0x9a83068_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aa0278_0, 0, 8; |
%ix/getv 3, v0x9a83068_0; |
%load/av 8, v0x9a82ba0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab17f0_0, 0, 8; |
%load/v 8, v0x9a97498_0, 1; |
%jmp/0xz T_44.28, 8; |
%ix/getv 3, v0x9a83068_0; |
%jmp/1 t_44, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a817f8, 0, 0; |
t_44 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
T_44.28 ; |
T_44.27 ; |
%jmp T_44.10; |
T_44.6 ; |
%ix/getv 3, v0x9a83068_0; |
%load/av 8, v0x9a817f8, 4; |
%cmpi/u 8, 3, 4; |
%mov 8, 4, 1; |
%ix/getv 3, v0x9a83068_0; |
%load/av 9, v0x9a817f8, 4; |
%cmpi/u 9, 5, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%inv 8, 1; |
%jmp/0xz T_44.30, 8; |
%vpi_call 10 586 "$display", "Error 3. cache_state[c_addr] is not S or E.\012"; |
%vpi_call 10 587 "$display", " CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time=%d", v0x9abaf48_0, v0x9a83068_0, &A<v0x9a817f8, v0x9a83068_0 >, $time; |
%wait E_0x9aece10; |
%vpi_call 10 592 "$finish"; |
%jmp T_44.31; |
T_44.30 ; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 8; |
%load/v 8, v0x9a83068_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aa0278_0, 0, 8; |
%ix/getv 3, v0x9a83068_0; |
%load/av 8, v0x9a82ba0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab17f0_0, 0, 8; |
%load/v 8, v0x9a97498_0, 1; |
%jmp/0xz T_44.32, 8; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9a83068_0; |
%jmp/1 t_45, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a817f8, 0, 8; |
t_45 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 1; |
T_44.32 ; |
T_44.31 ; |
%jmp T_44.10; |
T_44.7 ; |
%load/v 8, v0x9abdc98_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9abdc38_0, 32; |
%load/v 41, v0x9a83068_0, 32; |
%cmp/u 9, 41, 32; |
%inv 4, 1; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_44.34, 8; |
%vpi_call 10 621 "$display", "Error 4. Write to cache without early broadcast.\012", " CPU:%d,wr_proc_wait_for_en=%h,wr_proc_addr=%h,c_addr=%h, time:%d", v0x9abaf48_0, v0x9abdc98_0, v0x9abdc38_0, v0x9a83068_0, $time; |
%wait E_0x9aece10; |
%vpi_call 10 628 "$finish"; |
T_44.34 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 8; |
%load/v 8, v0x9a83068_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aa0278_0, 0, 8; |
%load/v 8, v0x9a97498_0, 1; |
%jmp/0xz T_44.36, 8; |
%load/v 8, v0x9aa2638_0, 32; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_46, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_46 ; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_47, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a817f8, 0, 8; |
t_47 ; |
%movi 8, 8, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
T_44.36 ; |
%jmp T_44.10; |
T_44.8 ; |
%load/v 8, v0x9abcab8_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9ab1840_0, 32; |
%load/v 41, v0x9a83068_0, 32; |
%cmp/u 9, 41, 32; |
%inv 4, 1; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_44.38, 8; |
%vpi_call 10 655 "$display", "Error 5. Read to cache without early broadcast.\012", " CPU:%d,rd_proc_wait_for_en=%h,rd_proc_addr=%h,c_addr=%h,time:%d\012", v0x9abaf48_0, v0x9abcab8_0, v0x9ab1840_0, v0x9a83068_0, $time; |
%wait E_0x9aece10; |
%vpi_call 10 662 "$finish"; |
T_44.38 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 8; |
%load/v 8, v0x9a83068_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9aa0278_0, 0, 8; |
%load/v 8, v0x9a97498_0, 1; |
%jmp/0xz T_44.40, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%load/v 8, v0x9aa2638_0, 32; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_48, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_48 ; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_49, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a817f8, 0, 8; |
t_49 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abcab8_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
T_44.40 ; |
%jmp T_44.10; |
T_44.9 ; |
%load/v 8, v0x9abaf48_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_44.42, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_44.43, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_44.44, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_44.45, 6; |
%jmp T_44.46; |
T_44.42 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_50, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_50 ; |
%jmp T_44.46; |
T_44.43 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_51, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 8, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_51 ; |
%jmp T_44.46; |
T_44.44 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_52, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 16, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_52 ; |
%jmp T_44.46; |
T_44.45 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_53, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 24, 0; part off |
%assign/av v0x9a82ba0, 0, 8; |
t_53 ; |
%jmp T_44.46; |
T_44.46 ; |
%ix/getv 3, v0x9aafa30_0; |
%load/av 8, v0x9abdfc0, 8; |
%mov 16, 0, 24; |
%addi 8, 1, 32; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_54, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9abdfc0, 0, 8; |
t_54 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9a830b8_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9aa02c8_0, 0, 0; |
%movi 8, 9, 4; |
%ix/getv 3, v0x9aafa30_0; |
%jmp/1 t_55, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a817f8, 0, 8; |
t_55 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab4888_0, 0, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9abdc98_0, 0, 0; |
%jmp T_44.10; |
T_44.10 ; |
T_44.1 ; |
%jmp T_44; |
.thread T_44; |
.scope S_0x9ab3af8; |
T_45 ; |
%set/v v0x9a943b0_0, 0, 32; |
T_45.0 ; |
%load/v 8, v0x9a943b0_0, 32; |
%cmpi/s 8, 10, 32; |
%jmp/0xz T_45.1, 5; |
%ix/getv/s 3, v0x9a943b0_0; |
%jmp/1 t_56, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9aa9f48, 0, 4; |
t_56 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9a943b0_0, 32; |
%set/v v0x9a943b0_0, 8, 32; |
%jmp T_45.0; |
T_45.1 ; |
%end; |
.thread T_45; |
.scope S_0x9ab3af8; |
T_46 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9a84930_0, 1; |
%jmp/0xz T_46.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x99e5858_0, 0, 0; |
%jmp T_46.1; |
T_46.0 ; |
%load/v 8, v0x99e5858_0, 1; |
%inv 8, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x99e5858_0, 0, 8; |
T_46.1 ; |
%jmp T_46; |
.thread T_46; |
.scope S_0x9ab3af8; |
T_47 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9a84930_0, 1; |
%jmp/0xz T_47.0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a847b0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84478_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a84418_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a848e0_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a85878_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab93d0_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x99e58b8_0, 0, 0; |
%set/v v0x9afd868_0, 0, 32; |
T_47.2 ; |
%load/v 8, v0x9afd868_0, 32; |
%cmpi/s 8, 6, 32; |
%jmp/0xz T_47.3, 5; |
%movi 8, 1, 8; |
%ix/getv/s 3, v0x9afd868_0; |
%jmp/1 t_57, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a81220, 0, 8; |
t_57 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9afd868_0, 32; |
%set/v v0x9afd868_0, 8, 32; |
%jmp T_47.2; |
T_47.3 ; |
%jmp T_47.1; |
T_47.0 ; |
%load/v 8, v0x9b01018_0, 3; |
%cmpi/u 8, 0, 3; |
%jmp/1 T_47.4, 6; |
%cmpi/u 8, 1, 3; |
%jmp/1 T_47.5, 6; |
%cmpi/u 8, 2, 3; |
%jmp/1 T_47.6, 6; |
%cmpi/u 8, 3, 3; |
%jmp/1 T_47.7, 6; |
%cmpi/u 8, 4, 3; |
%jmp/1 T_47.8, 6; |
%jmp T_47.9; |
T_47.4 ; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab93d0_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x99e58b8_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a847b0_0, 0, 0; |
%load/v 8, v0x9ab3218_0, 4; |
%mov 12, 0, 1; |
%cmpi/u 8, 0, 5; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x99e5858_0, 1; |
%inv 9, 1; |
%or 8, 9, 1; |
%jmp/0xz T_47.10, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 0; |
%jmp T_47.11; |
T_47.10 ; |
%load/v 8, v0x9a811c0_0, 4; |
%cmpi/u 8, 1, 4; |
%mov 8, 4, 1; |
%load/v 9, v0x9a811c0_0, 4; |
%cmpi/u 9, 2, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9a84478_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9a848e0_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%jmp/0xz T_47.12, 8; |
%load/v 8, v0x9a84800_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9afd8b8_0, 0, 8; |
%load/v 8, v0x9a84800_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a87238_0, 0, 8; |
%ix/getv 3, v0x9a84800_0; |
%load/av 8, v0x9aa9f48, 4; |
%cmpi/u 8, 9, 4; |
%jmp/1 T_47.14, 6; |
%cmpi/u 8, 5, 4; |
%jmp/1 T_47.15, 6; |
%cmpi/u 8, 3, 4; |
%jmp/1 T_47.16, 6; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_47.17, 6; |
%jmp T_47.18; |
T_47.14 ; |
%load/v 8, v0x9a811c0_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_47.19, 4; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%jmp T_47.20; |
T_47.19 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
T_47.20 ; |
%jmp T_47.18; |
T_47.15 ; |
%load/v 8, v0x9a811c0_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_47.21, 4; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%jmp T_47.22; |
T_47.21 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
T_47.22 ; |
%jmp T_47.18; |
T_47.16 ; |
%load/v 8, v0x9a811c0_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_47.23, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84478_0, 0, 1; |
%load/v 8, v0x9a84800_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a84418_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 8; |
%jmp T_47.24; |
T_47.23 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
T_47.24 ; |
%jmp T_47.18; |
T_47.17 ; |
%load/v 8, v0x9a811c0_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_47.25, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84478_0, 0, 1; |
%load/v 8, v0x9a84800_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a84418_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 8; |
%jmp T_47.26; |
T_47.25 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a848e0_0, 0, 1; |
%load/v 8, v0x9a84800_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a85878_0, 0, 8; |
%movi 8, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
%movi 11, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 11; |
T_47.26 ; |
%jmp T_47.18; |
T_47.18 ; |
T_47.12 ; |
T_47.11 ; |
%jmp T_47.9; |
T_47.5 ; |
%movi 8, 9, 4; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_58, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aa9f48, 0, 8; |
t_58 ; |
%load/v 8, v0x9b02388_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_47.27, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_47.28, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_47.29, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_47.30, 6; |
%jmp T_47.31; |
T_47.27 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_59, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_59 ; |
%jmp T_47.31; |
T_47.28 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_60, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 8, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_60 ; |
%jmp T_47.31; |
T_47.29 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_61, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 16, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_61 ; |
%jmp T_47.31; |
T_47.30 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_62, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 24, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_62 ; |
%jmp T_47.31; |
T_47.31 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%mov 16, 0, 24; |
%addi 8, 1, 32; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_63, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a81220, 0, 8; |
t_63 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a847b0_0, 0, 1; |
%jmp T_47.9; |
T_47.6 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a847b0_0, 0, 1; |
%jmp T_47.9; |
T_47.7 ; |
%load/v 8, v0x9afd8b8_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a87238_0, 0, 8; |
%load/v 8, v0x9ab93d0_0, 32; |
%mov 40, 39, 1; |
%addi 8, 1, 33; |
%set/v v0x9ab93d0_0, 8, 32; |
%load/v 8, v0x9ab9420_0, 1; |
%jmp/0xz T_47.32, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a847b0_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%jmp T_47.33; |
T_47.32 ; |
%movi 8, 31, 32; |
%load/v 40, v0x9ab93d0_0, 32; |
%cmp/s 8, 40, 32; |
%jmp/0xz T_47.34, 5; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a847b0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%jmp T_47.35; |
T_47.34 ; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
T_47.35 ; |
T_47.33 ; |
%jmp T_47.9; |
T_47.8 ; |
%load/v 8, v0x9afd8b8_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a87238_0, 0, 8; |
%load/v 8, v0x99e58b8_0, 32; |
%mov 40, 39, 1; |
%addi 8, 1, 33; |
%set/v v0x99e58b8_0, 8, 32; |
%load/v 8, v0x9ab9420_0, 1; |
%jmp/0xz T_47.36, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a847b0_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%jmp T_47.37; |
T_47.36 ; |
%movi 8, 31, 32; |
%load/v 40, v0x99e58b8_0, 32; |
%cmp/s 8, 40, 32; |
%jmp/0xz T_47.38, 5; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a847b0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%jmp T_47.39; |
T_47.38 ; |
%movi 8, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9b01018_0, 0, 8; |
T_47.39 ; |
T_47.37 ; |
%jmp T_47.9; |
T_47.9 ; |
T_47.1 ; |
%jmp T_47; |
.thread T_47; |
.scope S_0x9ab3af8; |
T_48 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9a84930_0, 1; |
%jmp/0xz T_48.0, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 0; |
%jmp T_48.1; |
T_48.0 ; |
%load/v 8, v0x9ab3218_0, 4; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_48.2, 6; |
%cmpi/u 8, 1, 4; |
%jmp/1 T_48.3, 6; |
%cmpi/u 8, 2, 4; |
%jmp/1 T_48.4, 6; |
%cmpi/u 8, 3, 4; |
%jmp/1 T_48.5, 6; |
%cmpi/u 8, 4, 4; |
%jmp/1 T_48.6, 6; |
%cmpi/u 8, 5, 4; |
%jmp/1 T_48.7, 6; |
%cmpi/u 8, 6, 4; |
%jmp/1 T_48.8, 6; |
%cmpi/u 8, 8, 4; |
%jmp/1 T_48.9, 6; |
%jmp T_48.10; |
T_48.2 ; |
%load/v 8, v0x9b0b198_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab4110_0, 0, 8; |
%load/v 8, v0x9b01018_0, 3; |
%mov 11, 0, 1; |
%cmpi/u 8, 0, 4; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x99e5858_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9a94c98_0, 1; |
%or 8, 9, 1; |
%jmp/0xz T_48.11, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 0; |
%jmp T_48.12; |
T_48.11 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%load/v 8, v0x9b0b1e8_0, 3; |
%cmpi/u 8, 0, 3; |
%jmp/1 T_48.13, 6; |
%cmpi/u 8, 1, 3; |
%jmp/1 T_48.14, 6; |
%cmpi/u 8, 2, 3; |
%jmp/1 T_48.15, 6; |
%cmpi/u 8, 3, 3; |
%jmp/1 T_48.16, 6; |
%cmpi/u 8, 4, 3; |
%jmp/1 T_48.17, 6; |
%vpi_call 10 504 "$display", "Error 1. Wrong value - CPU:%d, cbus_cmd_i = %h,time=%d\012", v0x9b02388_0, v0x9b0b1e8_0, $time; |
%jmp T_48.19; |
T_48.13 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 0; |
%jmp T_48.19; |
T_48.14 ; |
%movi 8, 1, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 0; |
%jmp T_48.19; |
T_48.15 ; |
%movi 8, 2, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 0; |
%jmp T_48.19; |
T_48.16 ; |
%movi 8, 5, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 0; |
%jmp T_48.19; |
T_48.17 ; |
%movi 8, 6, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 0; |
%jmp T_48.19; |
T_48.19 ; |
T_48.12 ; |
%jmp T_48.10; |
T_48.3 ; |
%ix/getv 3, v0x9ab4110_0; |
%load/av 8, v0x9aa9f48, 4; |
%cmpi/u 8, 9, 4; |
%jmp/0xz T_48.20, 4; |
%movi 8, 3, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 8; |
%jmp T_48.21; |
T_48.20 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%ix/getv 3, v0x9ab4110_0; |
%jmp/1 t_64, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aa9f48, 0, 0; |
t_64 ; |
%ix/getv 3, v0x9ab4110_0; |
%jmp/1 t_65, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9ab3278, 0, 0; |
t_65 ; |
T_48.21 ; |
%jmp T_48.10; |
T_48.4 ; |
%ix/getv 3, v0x9ab4110_0; |
%load/av 8, v0x9aa9f48, 4; |
%cmpi/u 8, 9, 4; |
%jmp/0xz T_48.22, 4; |
%movi 8, 3, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 8; |
%jmp T_48.23; |
T_48.22 ; |
%ix/getv 3, v0x9ab4110_0; |
%load/av 8, v0x9aa9f48, 4; |
%cmpi/u 8, 5, 4; |
%jmp/0xz T_48.24, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9ab4110_0; |
%jmp/1 t_66, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aa9f48, 0, 8; |
t_66 ; |
%jmp T_48.25; |
T_48.24 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
T_48.25 ; |
T_48.23 ; |
%jmp T_48.10; |
T_48.5 ; |
%ix/getv 3, v0x9ab4110_0; |
%load/av 8, v0x9aa9f48, 4; |
%cmpi/u 8, 9, 4; |
%inv 4, 1; |
%jmp/0xz T_48.26, 4; |
%vpi_call 10 550 "$display", "Error 2. cache_state[c_addr] is not M.\012", " CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time:%d", v0x9b02388_0, v0x9ab4110_0, &A<v0x9aa9f48, v0x9ab4110_0 >, $time; |
%wait E_0x9aece10; |
%vpi_call 10 556 "$finish"; |
%jmp T_48.27; |
T_48.26 ; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 8; |
%load/v 8, v0x9ab4110_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a87238_0, 0, 8; |
%ix/getv 3, v0x9ab4110_0; |
%load/av 8, v0x9ab3278, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a85828_0, 0, 8; |
%load/v 8, v0x9ab9420_0, 1; |
%jmp/0xz T_48.28, 8; |
%ix/getv 3, v0x9ab4110_0; |
%jmp/1 t_67, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aa9f48, 0, 0; |
t_67 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
T_48.28 ; |
T_48.27 ; |
%jmp T_48.10; |
T_48.6 ; |
%ix/getv 3, v0x9ab4110_0; |
%load/av 8, v0x9aa9f48, 4; |
%cmpi/u 8, 3, 4; |
%mov 8, 4, 1; |
%ix/getv 3, v0x9ab4110_0; |
%load/av 9, v0x9aa9f48, 4; |
%cmpi/u 9, 5, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%inv 8, 1; |
%jmp/0xz T_48.30, 8; |
%vpi_call 10 586 "$display", "Error 3. cache_state[c_addr] is not S or E.\012"; |
%vpi_call 10 587 "$display", " CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time=%d", v0x9b02388_0, v0x9ab4110_0, &A<v0x9aa9f48, v0x9ab4110_0 >, $time; |
%wait E_0x9aece10; |
%vpi_call 10 592 "$finish"; |
%jmp T_48.31; |
T_48.30 ; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 8; |
%load/v 8, v0x9ab4110_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a87238_0, 0, 8; |
%ix/getv 3, v0x9ab4110_0; |
%load/av 8, v0x9ab3278, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a85828_0, 0, 8; |
%load/v 8, v0x9ab9420_0, 1; |
%jmp/0xz T_48.32, 8; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9ab4110_0; |
%jmp/1 t_68, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aa9f48, 0, 8; |
t_68 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 1; |
T_48.32 ; |
T_48.31 ; |
%jmp T_48.10; |
T_48.7 ; |
%load/v 8, v0x9a84478_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9a84418_0, 32; |
%load/v 41, v0x9ab4110_0, 32; |
%cmp/u 9, 41, 32; |
%inv 4, 1; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_48.34, 8; |
%vpi_call 10 621 "$display", "Error 4. Write to cache without early broadcast.\012", " CPU:%d,wr_proc_wait_for_en=%h,wr_proc_addr=%h,c_addr=%h, time:%d", v0x9b02388_0, v0x9a84478_0, v0x9a84418_0, v0x9ab4110_0, $time; |
%wait E_0x9aece10; |
%vpi_call 10 628 "$finish"; |
T_48.34 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 8; |
%load/v 8, v0x9ab4110_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a87238_0, 0, 8; |
%load/v 8, v0x9ab9420_0, 1; |
%jmp/0xz T_48.36, 8; |
%load/v 8, v0x9a85318_0, 32; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_69, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_69 ; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_70, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aa9f48, 0, 8; |
t_70 ; |
%movi 8, 8, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
T_48.36 ; |
%jmp T_48.10; |
T_48.8 ; |
%load/v 8, v0x9a848e0_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9a85878_0, 32; |
%load/v 41, v0x9ab4110_0, 32; |
%cmp/u 9, 41, 32; |
%inv 4, 1; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_48.38, 8; |
%vpi_call 10 655 "$display", "Error 5. Read to cache without early broadcast.\012", " CPU:%d,rd_proc_wait_for_en=%h,rd_proc_addr=%h,c_addr=%h,time:%d\012", v0x9b02388_0, v0x9a848e0_0, v0x9a85878_0, v0x9ab4110_0, $time; |
%wait E_0x9aece10; |
%vpi_call 10 662 "$finish"; |
T_48.38 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 8; |
%load/v 8, v0x9ab4110_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9a87238_0, 0, 8; |
%load/v 8, v0x9ab9420_0, 1; |
%jmp/0xz T_48.40, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%load/v 8, v0x9a85318_0, 32; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_71, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_71 ; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_72, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aa9f48, 0, 8; |
t_72 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a848e0_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
T_48.40 ; |
%jmp T_48.10; |
T_48.9 ; |
%load/v 8, v0x9b02388_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_48.42, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_48.43, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_48.44, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_48.45, 6; |
%jmp T_48.46; |
T_48.42 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_73, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_73 ; |
%jmp T_48.46; |
T_48.43 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_74, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 8, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_74 ; |
%jmp T_48.46; |
T_48.44 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_75, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 16, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_75 ; |
%jmp T_48.46; |
T_48.45 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_76, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 24, 0; part off |
%assign/av v0x9ab3278, 0, 8; |
t_76 ; |
%jmp T_48.46; |
T_48.46 ; |
%ix/getv 3, v0x9afd8b8_0; |
%load/av 8, v0x9a81220, 8; |
%mov 16, 0, 24; |
%addi 8, 1, 32; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_77, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9a81220, 0, 8; |
t_77 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9ab3218_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9a852b8_0, 0, 0; |
%movi 8, 9, 4; |
%ix/getv 3, v0x9afd8b8_0; |
%jmp/1 t_78, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aa9f48, 0, 8; |
t_78 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a94c98_0, 0, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9a84478_0, 0, 0; |
%jmp T_48.10; |
T_48.10 ; |
T_48.1 ; |
%jmp T_48; |
.thread T_48; |
.scope S_0x9aeed80; |
T_49 ; |
%set/v v0x9aebe50_0, 0, 32; |
T_49.0 ; |
%load/v 8, v0x9aebe50_0, 32; |
%cmpi/s 8, 10, 32; |
%jmp/0xz T_49.1, 5; |
%ix/getv/s 3, v0x9aebe50_0; |
%jmp/1 t_79, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9aee678, 0, 4; |
t_79 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9aebe50_0, 32; |
%set/v v0x9aebe50_0, 8, 32; |
%jmp T_49.0; |
T_49.1 ; |
%end; |
.thread T_49; |
.scope S_0x9aeed80; |
T_50 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9ab8908_0, 1; |
%jmp/0xz T_50.0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ad4060_0, 0, 0; |
%jmp T_50.1; |
T_50.0 ; |
%load/v 8, v0x9ad4060_0, 1; |
%inv 8, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ad4060_0, 0, 8; |
T_50.1 ; |
%jmp T_50; |
.thread T_50; |
.scope S_0x9aeed80; |
T_51 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9ab8908_0, 1; |
%jmp/0xz T_51.0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8958_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab40c0_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab4608_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8f20_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab8ec0_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9acffd0_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ad40c0_0, 0, 0; |
%set/v v0x9aebea0_0, 0, 32; |
T_51.2 ; |
%load/v 8, v0x9aebea0_0, 32; |
%cmpi/s 8, 6, 32; |
%jmp/0xz T_51.3, 5; |
%movi 8, 1, 8; |
%ix/getv/s 3, v0x9aebea0_0; |
%jmp/1 t_80, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9ab45b8, 0, 8; |
t_80 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9aebea0_0, 32; |
%set/v v0x9aebea0_0, 8, 32; |
%jmp T_51.2; |
T_51.3 ; |
%jmp T_51.1; |
T_51.0 ; |
%load/v 8, v0x9ae0470_0, 3; |
%cmpi/u 8, 0, 3; |
%jmp/1 T_51.4, 6; |
%cmpi/u 8, 1, 3; |
%jmp/1 T_51.5, 6; |
%cmpi/u 8, 2, 3; |
%jmp/1 T_51.6, 6; |
%cmpi/u 8, 3, 3; |
%jmp/1 T_51.7, 6; |
%cmpi/u 8, 4, 3; |
%jmp/1 T_51.8, 6; |
%jmp T_51.9; |
T_51.4 ; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9acffd0_0, 0, 0; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ad40c0_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8958_0, 0, 0; |
%load/v 8, v0x9aefe80_0, 4; |
%mov 12, 0, 1; |
%cmpi/u 8, 0, 5; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9ad4060_0, 1; |
%inv 9, 1; |
%or 8, 9, 1; |
%jmp/0xz T_51.10, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 0; |
%jmp T_51.11; |
T_51.10 ; |
%load/v 8, v0x9ab83f8_0, 4; |
%cmpi/u 8, 1, 4; |
%mov 8, 4, 1; |
%load/v 9, v0x9ab83f8_0, 4; |
%cmpi/u 9, 2, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9ab40c0_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%load/v 9, v0x9ab8f20_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%jmp/0xz T_51.12, 8; |
%load/v 8, v0x9ab83a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9af48d0_0, 0, 8; |
%load/v 8, v0x9ab83a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9adc1f0_0, 0, 8; |
%ix/getv 3, v0x9ab83a8_0; |
%load/av 8, v0x9aee678, 4; |
%cmpi/u 8, 9, 4; |
%jmp/1 T_51.14, 6; |
%cmpi/u 8, 5, 4; |
%jmp/1 T_51.15, 6; |
%cmpi/u 8, 3, 4; |
%jmp/1 T_51.16, 6; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_51.17, 6; |
%jmp T_51.18; |
T_51.14 ; |
%load/v 8, v0x9ab83f8_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_51.19, 4; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%jmp T_51.20; |
T_51.19 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
T_51.20 ; |
%jmp T_51.18; |
T_51.15 ; |
%load/v 8, v0x9ab83f8_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_51.21, 4; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%jmp T_51.22; |
T_51.21 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
T_51.22 ; |
%jmp T_51.18; |
T_51.16 ; |
%load/v 8, v0x9ab83f8_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_51.23, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab40c0_0, 0, 1; |
%load/v 8, v0x9ab83a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab4608_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 8; |
%jmp T_51.24; |
T_51.23 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
T_51.24 ; |
%jmp T_51.18; |
T_51.17 ; |
%load/v 8, v0x9ab83f8_0, 4; |
%cmpi/u 8, 1, 4; |
%jmp/0xz T_51.25, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab40c0_0, 0, 1; |
%load/v 8, v0x9ab83a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab4608_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 8; |
%jmp T_51.26; |
T_51.25 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8f20_0, 0, 1; |
%load/v 8, v0x9ab83a8_0, 4; |
%mov 12, 0, 28; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab8ec0_0, 0, 8; |
%movi 8, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
%movi 11, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 11; |
T_51.26 ; |
%jmp T_51.18; |
T_51.18 ; |
T_51.12 ; |
T_51.11 ; |
%jmp T_51.9; |
T_51.5 ; |
%movi 8, 9, 4; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_81, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aee678, 0, 8; |
t_81 ; |
%load/v 8, v0x9af08a0_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_51.27, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_51.28, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_51.29, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_51.30, 6; |
%jmp T_51.31; |
T_51.27 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_82, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_82 ; |
%jmp T_51.31; |
T_51.28 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_83, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 8, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_83 ; |
%jmp T_51.31; |
T_51.29 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_84, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 16, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_84 ; |
%jmp T_51.31; |
T_51.30 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_85, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 24, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_85 ; |
%jmp T_51.31; |
T_51.31 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%mov 16, 0, 24; |
%addi 8, 1, 32; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_86, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9ab45b8, 0, 8; |
t_86 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8958_0, 0, 1; |
%jmp T_51.9; |
T_51.6 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8958_0, 0, 1; |
%jmp T_51.9; |
T_51.7 ; |
%load/v 8, v0x9af48d0_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9adc1f0_0, 0, 8; |
%load/v 8, v0x9acffd0_0, 32; |
%mov 40, 39, 1; |
%addi 8, 1, 33; |
%set/v v0x9acffd0_0, 8, 32; |
%load/v 8, v0x9ad0020_0, 1; |
%jmp/0xz T_51.32, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8958_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%jmp T_51.33; |
T_51.32 ; |
%movi 8, 31, 32; |
%load/v 40, v0x9acffd0_0, 32; |
%cmp/s 8, 40, 32; |
%jmp/0xz T_51.34, 5; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8958_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%jmp T_51.35; |
T_51.34 ; |
%movi 8, 3, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
T_51.35 ; |
T_51.33 ; |
%jmp T_51.9; |
T_51.8 ; |
%load/v 8, v0x9af48d0_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9adc1f0_0, 0, 8; |
%load/v 8, v0x9ad40c0_0, 32; |
%mov 40, 39, 1; |
%addi 8, 1, 33; |
%set/v v0x9ad40c0_0, 8, 32; |
%load/v 8, v0x9ad0020_0, 1; |
%jmp/0xz T_51.36, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8958_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%jmp T_51.37; |
T_51.36 ; |
%movi 8, 31, 32; |
%load/v 40, v0x9ad40c0_0, 32; |
%cmp/s 8, 40, 32; |
%jmp/0xz T_51.38, 5; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8958_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%jmp T_51.39; |
T_51.38 ; |
%movi 8, 4, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9ae0470_0, 0, 8; |
T_51.39 ; |
T_51.37 ; |
%jmp T_51.9; |
T_51.9 ; |
T_51.1 ; |
%jmp T_51; |
.thread T_51; |
.scope S_0x9aeed80; |
T_52 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9ab8908_0, 1; |
%jmp/0xz T_52.0, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 0; |
%jmp T_52.1; |
T_52.0 ; |
%load/v 8, v0x9aefe80_0, 4; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_52.2, 6; |
%cmpi/u 8, 1, 4; |
%jmp/1 T_52.3, 6; |
%cmpi/u 8, 2, 4; |
%jmp/1 T_52.4, 6; |
%cmpi/u 8, 3, 4; |
%jmp/1 T_52.5, 6; |
%cmpi/u 8, 4, 4; |
%jmp/1 T_52.6, 6; |
%cmpi/u 8, 5, 4; |
%jmp/1 T_52.7, 6; |
%cmpi/u 8, 6, 4; |
%jmp/1 T_52.8, 6; |
%cmpi/u 8, 8, 4; |
%jmp/1 T_52.9, 6; |
%jmp T_52.10; |
T_52.2 ; |
%load/v 8, v0x9aedc98_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9ab78f8_0, 0, 8; |
%load/v 8, v0x9ae0470_0, 3; |
%mov 11, 0, 1; |
%cmpi/u 8, 0, 4; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9ad4060_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9aeda88_0, 1; |
%or 8, 9, 1; |
%jmp/0xz T_52.11, 8; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 0; |
%jmp T_52.12; |
T_52.11 ; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%load/v 8, v0x9aecfe0_0, 3; |
%cmpi/u 8, 0, 3; |
%jmp/1 T_52.13, 6; |
%cmpi/u 8, 1, 3; |
%jmp/1 T_52.14, 6; |
%cmpi/u 8, 2, 3; |
%jmp/1 T_52.15, 6; |
%cmpi/u 8, 3, 3; |
%jmp/1 T_52.16, 6; |
%cmpi/u 8, 4, 3; |
%jmp/1 T_52.17, 6; |
%vpi_call 10 504 "$display", "Error 1. Wrong value - CPU:%d, cbus_cmd_i = %h,time=%d\012", v0x9af08a0_0, v0x9aecfe0_0, $time; |
%jmp T_52.19; |
T_52.13 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 0; |
%jmp T_52.19; |
T_52.14 ; |
%movi 8, 1, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 0; |
%jmp T_52.19; |
T_52.15 ; |
%movi 8, 2, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 0; |
%jmp T_52.19; |
T_52.16 ; |
%movi 8, 5, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 0; |
%jmp T_52.19; |
T_52.17 ; |
%movi 8, 6, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 8; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 0; |
%jmp T_52.19; |
T_52.19 ; |
T_52.12 ; |
%jmp T_52.10; |
T_52.3 ; |
%ix/getv 3, v0x9ab78f8_0; |
%load/av 8, v0x9aee678, 4; |
%cmpi/u 8, 9, 4; |
%jmp/0xz T_52.20, 4; |
%movi 8, 3, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 8; |
%jmp T_52.21; |
T_52.20 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%ix/getv 3, v0x9ab78f8_0; |
%jmp/1 t_87, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aee678, 0, 0; |
t_87 ; |
%ix/getv 3, v0x9ab78f8_0; |
%jmp/1 t_88, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aefd50, 0, 0; |
t_88 ; |
T_52.21 ; |
%jmp T_52.10; |
T_52.4 ; |
%ix/getv 3, v0x9ab78f8_0; |
%load/av 8, v0x9aee678, 4; |
%cmpi/u 8, 9, 4; |
%jmp/0xz T_52.22, 4; |
%movi 8, 3, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 8; |
%jmp T_52.23; |
T_52.22 ; |
%ix/getv 3, v0x9ab78f8_0; |
%load/av 8, v0x9aee678, 4; |
%cmpi/u 8, 5, 4; |
%jmp/0xz T_52.24, 4; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9ab78f8_0; |
%jmp/1 t_89, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aee678, 0, 8; |
t_89 ; |
%jmp T_52.25; |
T_52.24 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 1; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
T_52.25 ; |
T_52.23 ; |
%jmp T_52.10; |
T_52.5 ; |
%ix/getv 3, v0x9ab78f8_0; |
%load/av 8, v0x9aee678, 4; |
%cmpi/u 8, 9, 4; |
%inv 4, 1; |
%jmp/0xz T_52.26, 4; |
%vpi_call 10 550 "$display", "Error 2. cache_state[c_addr] is not M.\012", " CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time:%d", v0x9af08a0_0, v0x9ab78f8_0, &A<v0x9aee678, v0x9ab78f8_0 >, $time; |
%wait E_0x9aece10; |
%vpi_call 10 556 "$finish"; |
%jmp T_52.27; |
T_52.26 ; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 8; |
%load/v 8, v0x9ab78f8_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9adc1f0_0, 0, 8; |
%ix/getv 3, v0x9ab78f8_0; |
%load/av 8, v0x9aefd50, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9acb5d0_0, 0, 8; |
%load/v 8, v0x9ad0020_0, 1; |
%jmp/0xz T_52.28, 8; |
%ix/getv 3, v0x9ab78f8_0; |
%jmp/1 t_90, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aee678, 0, 0; |
t_90 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 1; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
T_52.28 ; |
T_52.27 ; |
%jmp T_52.10; |
T_52.6 ; |
%ix/getv 3, v0x9ab78f8_0; |
%load/av 8, v0x9aee678, 4; |
%cmpi/u 8, 3, 4; |
%mov 8, 4, 1; |
%ix/getv 3, v0x9ab78f8_0; |
%load/av 9, v0x9aee678, 4; |
%cmpi/u 9, 5, 4; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%inv 8, 1; |
%jmp/0xz T_52.30, 8; |
%vpi_call 10 586 "$display", "Error 3. cache_state[c_addr] is not S or E.\012"; |
%vpi_call 10 587 "$display", " CPU:%d,c_addr=%h,cache_state[c_addr]=%h,time=%d", v0x9af08a0_0, v0x9ab78f8_0, &A<v0x9aee678, v0x9ab78f8_0 >, $time; |
%wait E_0x9aece10; |
%vpi_call 10 592 "$finish"; |
%jmp T_52.31; |
T_52.30 ; |
%movi 8, 1, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 8; |
%load/v 8, v0x9ab78f8_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9adc1f0_0, 0, 8; |
%ix/getv 3, v0x9ab78f8_0; |
%load/av 8, v0x9aefd50, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9acb5d0_0, 0, 8; |
%load/v 8, v0x9ad0020_0, 1; |
%jmp/0xz T_52.32, 8; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9ab78f8_0; |
%jmp/1 t_91, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aee678, 0, 8; |
t_91 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 1; |
T_52.32 ; |
T_52.31 ; |
%jmp T_52.10; |
T_52.7 ; |
%load/v 8, v0x9ab40c0_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9ab4608_0, 32; |
%load/v 41, v0x9ab78f8_0, 32; |
%cmp/u 9, 41, 32; |
%inv 4, 1; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_52.34, 8; |
%vpi_call 10 621 "$display", "Error 4. Write to cache without early broadcast.\012", " CPU:%d,wr_proc_wait_for_en=%h,wr_proc_addr=%h,c_addr=%h, time:%d", v0x9af08a0_0, v0x9ab40c0_0, v0x9ab4608_0, v0x9ab78f8_0, $time; |
%wait E_0x9aece10; |
%vpi_call 10 628 "$finish"; |
T_52.34 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 8; |
%load/v 8, v0x9ab78f8_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9adc1f0_0, 0, 8; |
%load/v 8, v0x9ad0020_0, 1; |
%jmp/0xz T_52.36, 8; |
%load/v 8, v0x9abfc50_0, 32; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_92, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_92 ; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_93, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aee678, 0, 8; |
t_93 ; |
%movi 8, 8, 4; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
T_52.36 ; |
%jmp T_52.10; |
T_52.8 ; |
%load/v 8, v0x9ab8f20_0, 1; |
%mov 9, 0, 2; |
%cmpi/u 8, 1, 3; |
%inv 4, 1; |
%mov 8, 4, 1; |
%load/v 9, v0x9ab8ec0_0, 32; |
%load/v 41, v0x9ab78f8_0, 32; |
%cmp/u 9, 41, 32; |
%inv 4, 1; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%jmp/0xz T_52.38, 8; |
%vpi_call 10 655 "$display", "Error 5. Read to cache without early broadcast.\012", " CPU:%d,rd_proc_wait_for_en=%h,rd_proc_addr=%h,c_addr=%h,time:%d\012", v0x9af08a0_0, v0x9ab8f20_0, v0x9ab8ec0_0, v0x9ab78f8_0, $time; |
%wait E_0x9aece10; |
%vpi_call 10 662 "$finish"; |
T_52.38 ; |
%movi 8, 2, 3; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 8; |
%load/v 8, v0x9ab78f8_0, 32; |
%ix/load 0, 32, 0; |
%assign/v0 v0x9adc1f0_0, 0, 8; |
%load/v 8, v0x9ad0020_0, 1; |
%jmp/0xz T_52.40, 8; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%load/v 8, v0x9abfc50_0, 32; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_94, 4; |
%ix/load 0, 32, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_94 ; |
%movi 8, 3, 4; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_95, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aee678, 0, 8; |
t_95 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab8f20_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
T_52.40 ; |
%jmp T_52.10; |
T_52.9 ; |
%load/v 8, v0x9af08a0_0, 2; |
%cmpi/u 8, 0, 2; |
%jmp/1 T_52.42, 6; |
%cmpi/u 8, 1, 2; |
%jmp/1 T_52.43, 6; |
%cmpi/u 8, 2, 2; |
%jmp/1 T_52.44, 6; |
%cmpi/u 8, 3, 2; |
%jmp/1 T_52.45, 6; |
%jmp T_52.46; |
T_52.42 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_96, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_96 ; |
%jmp T_52.46; |
T_52.43 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_97, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 8, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_97 ; |
%jmp T_52.46; |
T_52.44 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_98, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 16, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_98 ; |
%jmp T_52.46; |
T_52.45 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_99, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 24, 0; part off |
%assign/av v0x9aefd50, 0, 8; |
t_99 ; |
%jmp T_52.46; |
T_52.46 ; |
%ix/getv 3, v0x9af48d0_0; |
%load/av 8, v0x9ab45b8, 8; |
%mov 16, 0, 24; |
%addi 8, 1, 32; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_100, 4; |
%ix/load 0, 8, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9ab45b8, 0, 8; |
t_100 ; |
%ix/load 0, 4, 0; |
%assign/v0 v0x9aefe80_0, 0, 0; |
%ix/load 0, 3, 0; |
%assign/v0 v0x9abfbf0_0, 0, 0; |
%movi 8, 9, 4; |
%ix/getv 3, v0x9af48d0_0; |
%jmp/1 t_101, 4; |
%ix/load 0, 4, 0; word width |
%ix/load 1, 0, 0; part off |
%assign/av v0x9aee678, 0, 8; |
t_101 ; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9aeda88_0, 0, 1; |
%ix/load 0, 1, 0; |
%assign/v0 v0x9ab40c0_0, 0, 0; |
%jmp T_52.10; |
T_52.10 ; |
T_52.1 ; |
%jmp T_52; |
.thread T_52; |
.scope S_0x9aed928; |
T_53 ; |
%wait E_0x9afd1d8; |
%set/v v0x9b2f108_0, 0, 32; |
T_53.0 ; |
%load/v 8, v0x9b2f108_0, 32; |
%cmpi/s 8, 4, 32; |
%jmp/0xz T_53.1, 5; |
%ix/getv/s 1, v0x9b2f108_0; |
%jmp/1 T_53.2, 4; |
%load/x1p 8, v0x9b2f168_0, 1; |
%jmp T_53.3; |
T_53.2 ; |
%mov 8, 2, 1; |
T_53.3 ; |
; Save base=8 wid=1 in lookaside. |
%jmp/0xz T_53.4, 8; |
%ix/getv/s 3, v0x9b2f108_0; |
%load/av 8, v0x9b2f4e8, 32; |
%set/v v0x9b2e790_0, 8, 32; |
%fork TD_mesi_isc_tb.sanity_check_cache_status, S_0x9b2e710; |
%join; |
T_53.4 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b2f108_0, 32; |
%set/v v0x9b2f108_0, 8, 32; |
%jmp T_53.0; |
T_53.1 ; |
%jmp T_53; |
.thread T_53; |
.scope S_0x9aed928; |
T_54 ; |
%wait E_0x99e4598; |
%load/v 8, v0x9b24950_0, 1; |
%load/v 9, v0x9b249b0_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9b23dd0_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9b23e30_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9a45da0_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9a45e00_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9afcf38_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9aecad8_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9b2a2c8_0, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9b2a318_0, 1; |
%or 8, 9, 1; |
%jmp/0xz T_54.0, 8; |
%vpi_call 3 182 "$display", "ERROR 8. Fifo overflow or underflow\012"; |
%vpi_call 3 183 "$display", "mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_3.dbg_fifo_underflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_2.dbg_fifo_underflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_1.dbg_fifo_underflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_breq_fifos.fifo_0.dbg_fifo_underflow = %h, mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow = %h, mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow = %h", v0x9b24950_0, v0x9b249b0_0, v0x9b23dd0_0, v0x9b23e30_0, v0x9a45da0_0, v0x9a45e00_0, v0x9afcf38_0, v0x9aecad8_0, v0x9b2a2c8_0, v0x9b2a318_0; |
%vpi_call 3 193 "$finish"; |
T_54.0 ; |
%jmp T_54; |
.thread T_54, $push; |
.scope S_0x9aed928; |
T_55 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b30080_0, 1; |
%jmp/0xz T_55.0, 8; |
%ix/load 1, 0, 0; |
%ix/load 3, 3, 0; |
%set/av v0x9b30818, 0, 4; |
%ix/load 1, 0, 0; |
%ix/load 3, 2, 0; |
%set/av v0x9b30818, 0, 4; |
%ix/load 1, 0, 0; |
%ix/load 3, 1, 0; |
%set/av v0x9b30818, 0, 4; |
%ix/load 1, 0, 0; |
%ix/load 3, 0, 0; |
%set/av v0x9b30818, 0, 4; |
%ix/load 1, 0, 0; |
%ix/load 3, 3, 0; |
%set/av v0x9b30950, 0, 4; |
%ix/load 1, 0, 0; |
%ix/load 3, 2, 0; |
%set/av v0x9b30950, 0, 4; |
%ix/load 1, 0, 0; |
%ix/load 3, 1, 0; |
%set/av v0x9b30950, 0, 4; |
%ix/load 1, 0, 0; |
%ix/load 3, 0, 0; |
%set/av v0x9b30950, 0, 4; |
%ix/load 1, 0, 0; |
%ix/load 3, 3, 0; |
%set/av v0x9b30868, 0, 8; |
%ix/load 1, 0, 0; |
%ix/load 3, 2, 0; |
%set/av v0x9b30868, 0, 8; |
%ix/load 1, 0, 0; |
%ix/load 3, 1, 0; |
%set/av v0x9b30868, 0, 8; |
%ix/load 1, 0, 0; |
%ix/load 3, 0, 0; |
%set/av v0x9b30868, 0, 8; |
%jmp T_55.1; |
T_55.0 ; |
%set/v v0x9b2f1b8_0, 0, 32; |
T_55.2 ; |
%load/v 8, v0x9b2f1b8_0, 32; |
%cmpi/s 8, 9, 32; |
%jmp/0xz T_55.3, 5; |
%vpi_func 2 206 "$random", 8, 32, v0x9b300d0_0; |
%ix/getv/s 3, v0x9b2f1b8_0; |
%jmp/1 t_102, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b303f0, 8, 32; |
t_102 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b2f1b8_0, 32; |
%set/v v0x9b2f1b8_0, 8, 32; |
%jmp T_55.2; |
T_55.3 ; |
%ix/load 3, 0, 0; |
%mov 4, 0, 1; |
%load/av 8, v0x9b303f0, 32; |
%movi 40, 4, 32; |
%mod 8, 40, 32; |
%set/v v0x9b30390_0, 8, 2; |
%set/v v0x9b2f0b0_0, 0, 32; |
T_55.4 ; |
%load/v 8, v0x9b2f0b0_0, 32; |
%cmpi/s 8, 4, 32; |
%jmp/0xz T_55.5, 5; |
%load/v 8, v0x9b30390_0, 2; |
%mov 10, 0, 31; |
%load/v 41, v0x9b2f0b0_0, 32; |
%mov 73, 0, 1; |
%add 8, 41, 33; |
%movi 41, 4, 33; |
%mod 8, 41, 33; |
%set/v v0x9b2f010_0, 8, 32; |
%ix/getv/s 3, v0x9b2f010_0; |
%load/av 8, v0x9b30868, 8; |
%mov 16, 0, 1; |
%cmp/u 0, 8, 9; |
%jmp/0xz T_55.6, 5; |
%ix/getv/s 3, v0x9b2f010_0; |
%jmp/1 t_103, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b30818, 0, 4; |
t_103 ; |
%ix/getv/s 3, v0x9b2f010_0; |
%load/av 8, v0x9b30868, 8; |
%mov 16, 0, 24; |
%subi 8, 1, 32; |
%ix/getv/s 3, v0x9b2f010_0; |
%jmp/1 t_104, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b30868, 8, 8; |
t_104 ; |
%jmp T_55.7; |
T_55.6 ; |
%ix/getv/s 1, v0x9b2f010_0; |
%jmp/1 T_55.8, 4; |
%load/x1p 8, v0x9b305f8_0, 1; |
%jmp T_55.9; |
T_55.8 ; |
%mov 8, 2, 1; |
T_55.9 ; |
; Save base=8 wid=1 in lookaside. |
%jmp/0xz T_55.10, 8; |
%ix/getv/s 3, v0x9b2f010_0; |
%jmp/1 t_105, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b30818, 0, 4; |
t_105 ; |
%jmp T_55.11; |
T_55.10 ; |
%ix/getv/s 3, v0x9b2f010_0; |
%load/av 8, v0x9b30818, 4; |
%cmpi/u 8, 0, 4; |
%jmp/0xz T_55.12, 4; |
%ix/load 0, 1, 0; |
%load/vp0/s 40, v0x9b2f0b0_0, 32; |
%ix/get/s 3, 40, 32; |
%load/av 8, v0x9b303f0, 32; |
%movi 40, 20, 32; |
%mod 8, 40, 32; |
%set/v v0x9b304e8_0, 8, 2; |
%movi 8, 1, 3; |
%load/v 11, v0x9b304e8_0, 2; |
%mov 13, 0, 1; |
%cmp/u 8, 11, 3; |
%jmp/0xz T_55.14, 5; |
%movi 8, 2, 2; |
%set/v v0x9b304e8_0, 8, 2; |
T_55.14 ; |
%ix/load 0, 5, 0; |
%load/vp0/s 41, v0x9b2f0b0_0, 32; |
%ix/get/s 3, 41, 32; |
%load/av 8, v0x9b303f0, 32; |
%mov 40, 0, 1; |
%movi 41, 5, 33; |
%mod 8, 41, 33; |
%addi 8, 1, 33; |
%set/v v0x9b30248_0, 8, 8; |
%ix/load 3, 9, 0; |
%mov 4, 0, 1; |
%load/av 8, v0x9b303f0, 32; |
%mov 40, 0, 1; |
%movi 41, 10, 33; |
%mod 8, 41, 33; |
%addi 8, 1, 33; |
%set/v v0x9b30498_0, 8, 8; |
%load/v 8, v0x9b304e8_0, 2; |
%mov 10, 0, 1; |
%cmpi/u 8, 0, 3; |
%jmp/0xz T_55.16, 4; |
%load/v 8, v0x9b30498_0, 8; |
%ix/getv/s 3, v0x9b2f010_0; |
%jmp/1 t_106, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b30868, 8, 8; |
t_106 ; |
%jmp T_55.17; |
T_55.16 ; |
%load/v 8, v0x9b304e8_0, 2; |
%mov 10, 0, 2; |
%ix/getv/s 3, v0x9b2f010_0; |
%jmp/1 t_107, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b30818, 8, 4; |
t_107 ; |
%load/v 8, v0x9b30248_0, 8; |
%ix/getv/s 3, v0x9b2f010_0; |
%jmp/1 t_108, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b30950, 8, 4; |
t_108 ; |
T_55.17 ; |
T_55.12 ; |
T_55.11 ; |
T_55.7 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b2f0b0_0, 32; |
%set/v v0x9b2f0b0_0, 8, 32; |
%jmp T_55.4; |
T_55.5 ; |
T_55.1 ; |
%jmp T_55; |
.thread T_55; |
.scope S_0x9aed928; |
T_56 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b30080_0, 1; |
%jmp/0xz T_56.0, 8; |
%set/v v0x9b30158_0, 0, 32; |
T_56.2 ; |
%load/v 8, v0x9b30158_0, 32; |
%cmpi/s 8, 4, 32; |
%jmp/0xz T_56.3, 5; |
%ix/getv/s 3, v0x9b30158_0; |
%jmp/1 t_109, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b302f0, 0, 32; |
t_109 ; |
%ix/getv/s 3, v0x9b30158_0; |
%jmp/1 t_110, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b30340, 0, 32; |
t_110 ; |
%ix/getv/s 3, v0x9b30158_0; |
%jmp/1 t_111, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b301f8, 0, 32; |
t_111 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b30158_0, 32; |
%set/v v0x9b30158_0, 8, 32; |
%jmp T_56.2; |
T_56.3 ; |
%jmp T_56.1; |
T_56.0 ; |
%set/v v0x9b301a8_0, 0, 32; |
T_56.4 ; |
%load/v 8, v0x9b301a8_0, 32; |
%cmpi/s 8, 4, 32; |
%jmp/0xz T_56.5, 5; |
%ix/getv/s 1, v0x9b301a8_0; |
%jmp/1 T_56.6, 4; |
%load/x1p 8, v0x9b305f8_0, 1; |
%jmp T_56.7; |
T_56.6 ; |
%mov 8, 2, 1; |
T_56.7 ; |
; Save base=8 wid=1 in lookaside. |
%jmp/0xz T_56.8, 8; |
%ix/getv/s 3, v0x9b301a8_0; |
%load/av 8, v0x9b30818, 4; |
%cmpi/u 8, 0, 4; |
%jmp/1 T_56.10, 6; |
%cmpi/u 8, 1, 4; |
%jmp/1 T_56.11, 6; |
%cmpi/u 8, 2, 4; |
%jmp/1 T_56.12, 6; |
%jmp T_56.13; |
T_56.10 ; |
%ix/getv/s 3, v0x9b301a8_0; |
%load/av 8, v0x9b302f0, 32; |
%mov 40, 0, 1; |
%addi 8, 1, 33; |
%ix/getv/s 3, v0x9b301a8_0; |
%jmp/1 t_112, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b302f0, 8, 32; |
t_112 ; |
%jmp T_56.13; |
T_56.11 ; |
%ix/getv/s 3, v0x9b301a8_0; |
%load/av 8, v0x9b301f8, 32; |
%mov 40, 0, 1; |
%addi 8, 1, 33; |
%ix/getv/s 3, v0x9b301a8_0; |
%jmp/1 t_113, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b301f8, 8, 32; |
t_113 ; |
%jmp T_56.13; |
T_56.12 ; |
%ix/getv/s 3, v0x9b301a8_0; |
%load/av 8, v0x9b30340, 32; |
%mov 40, 0, 1; |
%addi 8, 1, 33; |
%ix/getv/s 3, v0x9b301a8_0; |
%jmp/1 t_114, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b30340, 8, 32; |
t_114 ; |
%jmp T_56.13; |
T_56.13 ; |
T_56.8 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b301a8_0, 32; |
%set/v v0x9b301a8_0, 8, 32; |
%jmp T_56.4; |
T_56.5 ; |
T_56.1 ; |
%jmp T_56; |
.thread T_56; |
.scope S_0x9aed928; |
T_57 ; |
%delay 50000, 0; |
%load/v 8, v0x9b2ee88_0, 1; |
%inv 8, 1; |
%set/v v0x9b2ee88_0, 8, 1; |
%jmp T_57; |
.thread T_57; |
.scope S_0x9aed928; |
T_58 ; |
%set/v v0x9b2efc0_0, 0, 32; |
T_58.0 ; |
%load/v 8, v0x9b2efc0_0, 32; |
%cmpi/s 8, 10, 32; |
%jmp/0xz T_58.1, 5; |
%ix/getv/s 3, v0x9b2efc0_0; |
%jmp/1 t_115, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b2fb88, 0, 32; |
t_115 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b2efc0_0, 32; |
%set/v v0x9b2efc0_0, 8, 32; |
%jmp T_58.0; |
T_58.1 ; |
%set/v v0x9b2ee88_0, 1, 1; |
%set/v v0x9b30080_0, 1, 1; |
%movi 8, 10, 5; |
T_58.2 %cmp/s 0, 8, 5; |
%jmp/0xz T_58.3, 5; |
%add 8, 1, 5; |
%wait E_0x9aece10; |
%jmp T_58.2; |
T_58.3 ; |
%set/v v0x9b30080_0, 0, 1; |
%movi 8, 20000, 16; |
T_58.4 %cmp/s 0, 8, 16; |
%jmp/0xz T_58.5, 5; |
%add 8, 1, 16; |
%wait E_0x9aece10; |
%jmp T_58.4; |
T_58.5 ; |
%vpi_call 2 293 "$display", "Watchdog finish\012"; |
%vpi_call 2 294 "$display", "Statistic\012"; |
%vpi_call 2 295 "$display", "CPU 3. WR:%d RD:%d NOP:%d \012", &A<v0x9b301f8, 3>, &A<v0x9b30340, 3>, &A<v0x9b302f0, 3>; |
%vpi_call 2 298 "$display", "CPU 2. WR:%d RD:%d NOP:%d\012", &A<v0x9b301f8, 2>, &A<v0x9b30340, 2>, &A<v0x9b302f0, 2>; |
%vpi_call 2 301 "$display", "CPU 1. WR:%d RD:%d NOP:%d\012", &A<v0x9b301f8, 1>, &A<v0x9b30340, 1>, &A<v0x9b302f0, 1>; |
%vpi_call 2 304 "$display", "CPU 0. WR: %d RD:%d NOP:%d\012", &A<v0x9b301f8, 0>, &A<v0x9b30340, 0>, &A<v0x9b302f0, 0>; |
%ix/load 3, 3, 0; |
%mov 4, 0, 1; |
%load/av 8, v0x9b301f8, 32; |
%ix/load 3, 3, 0; |
%mov 4, 0, 1; |
%load/av 40, v0x9b30340, 32; |
%add 8, 40, 32; |
%ix/load 3, 2, 0; |
%mov 4, 0, 1; |
%load/av 40, v0x9b301f8, 32; |
%add 8, 40, 32; |
%ix/load 3, 2, 0; |
%mov 4, 0, 1; |
%load/av 40, v0x9b30340, 32; |
%add 8, 40, 32; |
%ix/load 3, 1, 0; |
%mov 4, 0, 1; |
%load/av 40, v0x9b301f8, 32; |
%add 8, 40, 32; |
%ix/load 3, 1, 0; |
%mov 4, 0, 1; |
%load/av 40, v0x9b30340, 32; |
%add 8, 40, 32; |
%ix/load 3, 0, 0; |
%mov 4, 0, 1; |
%load/av 40, v0x9b301f8, 32; |
%add 8, 40, 32; |
%ix/load 3, 0, 0; |
%mov 4, 0, 1; |
%load/av 40, v0x9b30340, 32; |
%add 8, 40, 32; |
%vpi_call 2 307 "$display", "Total rd and wr accesses: %d\012", T<8,32,u>; |
%vpi_call 2 315 "$finish"; |
%end; |
.thread T_58; |
.scope S_0x9aed928; |
T_59 ; |
%vpi_call 2 323 "$dumpfile", "./dump.vcd"; |
%vpi_call 2 324 "$dumpvars", 1'sb0, S_0x9aed928; |
%end; |
.thread T_59; |
.scope S_0x9aed928; |
T_60 ; |
%wait E_0x9afd1d8; |
%load/v 8, v0x9b30080_0, 1; |
%jmp/0xz T_60.0, 8; |
%set/v v0x9b2ef20_0, 0, 2; |
%set/v v0x9b2ef70_0, 0, 4; |
%jmp T_60.1; |
T_60.0 ; |
%set/v v0x9b2f280_0, 0, 4; |
%set/v v0x9b2ff58_0, 0, 1; |
%set/v v0x9b2f060_0, 0, 32; |
T_60.2 ; |
%load/v 8, v0x9b2f060_0, 32; |
%cmpi/s 8, 4, 32; |
%jmp/0xz T_60.3, 5; |
%load/v 11, v0x9b2ef20_0, 2; |
%movi 13, 0, 30; |
%load/v 43, v0x9b2f060_0, 32; |
%add 11, 43, 32; |
%ix/get 3, 11, 32; |
%load/av 8, v0x9b2f6d0, 3; |
%cmpi/u 8, 1, 3; |
%mov 8, 4, 1; |
%load/v 12, v0x9b2ef20_0, 2; |
%movi 14, 0, 30; |
%load/v 44, v0x9b2f060_0, 32; |
%add 12, 44, 32; |
%ix/get 3, 12, 32; |
%load/av 9, v0x9b2f6d0, 3; |
%cmpi/u 9, 2, 3; |
%mov 9, 4, 1; |
%or 8, 9, 1; |
%load/v 9, v0x9b2ff58_0, 1; |
%inv 9, 1; |
%and 8, 9, 1; |
%jmp/0xz T_60.4, 8; |
%set/v v0x9b2ff58_0, 1, 1; |
%load/v 8, v0x9b2ef20_0, 2; |
%mov 10, 0, 30; |
%load/v 40, v0x9b2f060_0, 32; |
%add 8, 40, 32; |
%set/v v0x9b2ef70_0, 8, 4; |
%load/v 8, v0x9b2ef20_0, 2; |
%movi 10, 0, 30; |
%load/v 40, v0x9b2f060_0, 32; |
%add 8, 40, 32; |
%ix/get 0, 8, 32; |
%jmp/1 t_116, 4; |
%set/x0 v0x9b2f280_0, 1, 1; |
t_116 ; |
%load/v 11, v0x9b2ef20_0, 2; |
%movi 13, 0, 30; |
%load/v 43, v0x9b2f060_0, 32; |
%add 11, 43, 32; |
%ix/get 3, 11, 32; |
%load/av 8, v0x9b2f6d0, 3; |
%cmpi/u 8, 1, 3; |
%jmp/0xz T_60.6, 4; |
%load/v 8, v0x9b2ef70_0, 4; |
%set/v v0x9b2e5d0_0, 8, 4; |
%load/v 40, v0x9b2ef20_0, 2; |
%movi 42, 0, 30; |
%load/v 72, v0x9b2f060_0, 32; |
%add 40, 72, 32; |
%ix/get 3, 40, 32; |
%load/av 8, v0x9b2f4e8, 32; |
%set/v v0x9b2e670_0, 8, 32; |
%load/v 40, v0x9b2ef20_0, 2; |
%movi 42, 0, 30; |
%load/v 72, v0x9b2f060_0, 32; |
%add 40, 72, 32; |
%ix/get 3, 40, 32; |
%load/av 8, v0x9b2fc38, 32; |
%set/v v0x9b2e6c0_0, 8, 32; |
%fork TD_mesi_isc_tb.sanity_check_rule1_rule2, S_0x9b2e550; |
%join; |
%load/v 40, v0x9b2ef20_0, 2; |
%movi 42, 0, 30; |
%load/v 72, v0x9b2f060_0, 32; |
%add 40, 72, 32; |
%ix/get 3, 40, 32; |
%load/av 8, v0x9b2fc38, 32; |
%load/v 72, v0x9b2ef20_0, 2; |
%movi 74, 0, 30; |
%load/v 104, v0x9b2f060_0, 32; |
%add 72, 104, 32; |
%ix/get 3, 72, 32; |
%load/av 40, v0x9b2f4e8, 32; |
%ix/get 3, 40, 32; |
%jmp/1 t_117, 4; |
%ix/load 1, 0, 0; |
%set/av v0x9b2fb88, 8, 32; |
t_117 ; |
%jmp T_60.7; |
T_60.6 ; |
%load/v 72, v0x9b2ef20_0, 2; |
%movi 74, 0, 30; |
%load/v 104, v0x9b2f060_0, 32; |
%add 72, 104, 32; |
%ix/get 3, 72, 32; |
%load/av 40, v0x9b2f4e8, 32; |
%ix/get 3, 40, 32; |
%load/av 8, v0x9b2fb88, 32; |
%set/v v0x9b2f8f0_0, 8, 32; |
T_60.7 ; |
T_60.4 ; |
%ix/load 0, 1, 0; |
%load/vp0/s 8, v0x9b2f060_0, 32; |
%set/v v0x9b2f060_0, 8, 32; |
%jmp T_60.2; |
T_60.3 ; |
T_60.1 ; |
%jmp T_60; |
.thread T_60; |
# The file index is used to find the file name in the following table. |
:file_names 11; |
"N/A"; |
"<interactive>"; |
"../src/tb/mesi_isc_tb.v"; |
"../src/tb/mesi_isc_tb_sanity_check.v"; |
"../src/rtl/mesi_isc.v"; |
"../src/rtl/mesi_isc_broad.v"; |
"../src/rtl/mesi_isc_broad_cntl.v"; |
"../src/rtl/mesi_isc_basic_fifo.v"; |
"../src/rtl/mesi_isc_breq_fifos.v"; |
"../src/rtl/mesi_isc_breq_fifos_cntl.v"; |
"../src/tb/mesi_isc_tb_cpu.v"; |
sim/mesi_isc.out
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim/a.out
===================================================================
--- sim/a.out (nonexistent)
+++ sim/a.out (revision 3)
@@ -0,0 +1,627 @@
+#! /usr/bin/vvp
+:ivl_version "0.9.3 " "(v0_9_3)";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x90c59c0 .scope module, "mesi_isc_tb_cpu" "mesi_isc_tb_cpu" 2 48;
+ .timescale -9 -12;
+P_0x90d529c .param/l "ADDR_WIDTH" 2 70, +C4<0100000>;
+P_0x90d52b0 .param/l "BREQ_FIFO_SIZE" 2 77, +C4<010>;
+P_0x90d52c4 .param/l "BREQ_FIFO_SIZE_LOG2" 2 78, +C4<01>;
+P_0x90d52d8 .param/l "BROAD_ID_WIDTH" 2 73, +C4<0101>;
+P_0x90d52ec .param/l "BROAD_REQ_FIFO_SIZE" 2 74, +C4<0100>;
+P_0x90d5300 .param/l "BROAD_REQ_FIFO_SIZE_LOG2" 2 75, +C4<010>;
+P_0x90d5314 .param/l "BROAD_TYPE_WIDTH" 2 72, +C4<010>;
+P_0x90d5328 .param/l "CBUS_CMD_WIDTH" 2 69, +C4<011>;
+P_0x90d533c .param/l "CPU_ID" 2 68, +C4<0>;
+P_0x90d5350 .param/l "DATA_WIDTH" 2 71, +C4<0100000>;
+P_0x90d5364 .param/l "MBUS_CMD_WIDTH" 2 76, +C4<010>;
+v0x90d5d78_0 .var "c_addr", 31 0;
+v0x90fee40_0 .var "c_state", 3 0;
+v0x90feea0_0 .var "cbus_ack_o", 0 0;
+v0x90fef00_0 .net "cbus_addr_i", 31 0, C4; 0 drivers
+v0x90fef60_0 .net "cbus_cmd_i", 2 0, C4; 0 drivers
+v0x90fefc0_0 .net "clk", 0 0, C4; 0 drivers
+v0x90ff040_0 .var/i "i", 31 0;
+v0x90ff0a0_0 .var "m_addr", 31 0;
+v0x90ff128_0 .var "m_state", 3 0;
+v0x90ff188_0 .var "m_state_c_state_priority", 0 0;
+v0x90ff218_0 .net "mbus_ack_i", 0 0, C4; 0 drivers
+v0x90ff278_0 .var "mbus_addr_o", 31 0;
+v0x90ff310_0 .var "mbus_cmd_o", 1 0;
+v0x90ff370_0 .net "mbus_data_i", 31 0, C4; 0 drivers
+v0x90ff410_0 .var "mbus_data_o", 31 0;
+v0x90ff470 .array "mem", 0 9, 31 0;
+v0x90ff508 .array "mem_state", 0 9, 2 0;
+v0x90ff558_0 .var "rd_proc_addr", 31 0;
+v0x90ff5f8_0 .var "rd_proc_wait_for_en", 0 0;
+v0x90ff648_0 .net "rst", 0 0, C4; 0 drivers
+v0x90ff5a8_0 .var "tb_ins_ack_o", 0 0;
+v0x90ff6f0_0 .net "tb_ins_addr_i", 31 0, C4; 0 drivers
+v0x90ff7a0_0 .net "tb_ins_i", 31 0, C4; 0 drivers
+v0x90ff7f0_0 .var "wr_data", 31 0;
+v0x90ff740_0 .var "wr_proc_addr", 31 0;
+v0x90ff8a8_0 .var "wr_proc_wait_for_en", 0 0;
+E_0x90cb4d8 .event posedge, v0x90ff648_0, v0x90fefc0_0;
+ .scope S_0x90c59c0;
+T_0 ;
+ %set/v v0x90ff040_0, 0, 32;
+T_0.0 ;
+ %load/v 8, v0x90ff040_0, 32;
+ %cmpi/s 8, 10, 32;
+ %jmp/0xz T_0.1, 5;
+ %ix/getv/s 3, v0x90ff040_0;
+ %jmp/1 t_0, 4;
+ %ix/load 1, 0, 0;
+ %set/av v0x90ff470, 0, 32;
+t_0 ;
+ %ix/getv/s 3, v0x90ff040_0;
+ %jmp/1 t_1, 4;
+ %ix/load 1, 0, 0;
+ %set/av v0x90ff508, 0, 3;
+t_1 ;
+ %ix/load 0, 1, 0;
+ %load/vp0/s 8, v0x90ff040_0, 32;
+ %set/v v0x90ff040_0, 8, 32;
+ %jmp T_0.0;
+T_0.1 ;
+ %end;
+ .thread T_0;
+ .scope S_0x90c59c0;
+T_1 ;
+ %wait E_0x90cb4d8;
+ %load/v 8, v0x90ff648_0, 1;
+ %jmp/0xz T_1.0, 8;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff188_0, 0, 0;
+ %jmp T_1.1;
+T_1.0 ;
+ %load/v 8, v0x90ff188_0, 1;
+ %mov 9, 0, 1;
+ %inv 8, 2;
+ %cmpi/u 8, 0, 2;
+ %or 5, 4, 1;
+ %mov 8, 5, 1;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff188_0, 0, 8;
+T_1.1 ;
+ %jmp T_1;
+ .thread T_1;
+ .scope S_0x90c59c0;
+T_2 ;
+ %wait E_0x90cb4d8;
+ %load/v 8, v0x90ff648_0, 1;
+ %jmp/0xz T_2.0, 8;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5a8_0, 0, 0;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff7f0_0, 0, 0;
+ %ix/load 0, 2, 0;
+ %assign/v0 v0x90ff310_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff8a8_0, 0, 0;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff740_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5f8_0, 0, 0;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff558_0, 0, 0;
+ %jmp T_2.1;
+T_2.0 ;
+ %load/v 8, v0x90ff128_0, 4;
+ %cmpi/u 8, 0, 4;
+ %jmp/1 T_2.2, 6;
+ %cmpi/u 8, 1, 4;
+ %jmp/1 T_2.3, 6;
+ %cmpi/u 8, 2, 4;
+ %jmp/1 T_2.4, 6;
+ %cmpi/u 8, 3, 4;
+ %jmp/1 T_2.5, 6;
+ %cmpi/u 8, 4, 4;
+ %jmp/1 T_2.6, 6;
+ %jmp T_2.7;
+T_2.2 ;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5a8_0, 0, 0;
+ %load/v 8, v0x90fee40_0, 4;
+ %mov 12, 0, 1;
+ %cmpi/u 8, 0, 5;
+ %inv 4, 1;
+ %mov 8, 4, 1;
+ %load/v 9, v0x90ff188_0, 1;
+ %inv 9, 1;
+ %or 8, 9, 1;
+ %jmp/0xz T_2.8, 8;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 0;
+ %jmp T_2.9;
+T_2.8 ;
+ %load/v 8, v0x90ff7a0_0, 32;
+ %cmpi/u 8, 1, 32;
+ %mov 8, 4, 1;
+ %load/v 9, v0x90ff7a0_0, 32;
+ %cmpi/u 9, 2, 32;
+ %mov 9, 4, 1;
+ %or 8, 9, 1;
+ %jmp/0xz T_2.10, 8;
+ %load/v 8, v0x90ff6f0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff0a0_0, 0, 8;
+ %ix/getv 3, v0x90ff6f0_0;
+ %load/av 8, v0x90ff508, 3;
+ %cmpi/u 8, 0, 3;
+ %jmp/1 T_2.12, 6;
+ %cmpi/u 8, 1, 3;
+ %jmp/1 T_2.13, 6;
+ %cmpi/u 8, 2, 3;
+ %jmp/1 T_2.14, 6;
+ %cmpi/u 8, 3, 3;
+ %jmp/1 T_2.15, 6;
+ %jmp T_2.16;
+T_2.12 ;
+ %load/v 8, v0x90ff7a0_0, 32;
+ %cmpi/u 8, 1, 32;
+ %mov 8, 4, 1;
+ %jmp/0 T_2.17, 8;
+ %movi 9, 1, 4;
+ %jmp/1 T_2.19, 8;
+T_2.17 ; End of true expr.
+ %movi 13, 2, 4;
+ %jmp/0 T_2.18, 8;
+ ; End of false expr.
+ %blend 9, 13, 4; Condition unknown.
+ %jmp T_2.19;
+T_2.18 ;
+ %mov 9, 13, 4; Return false value
+T_2.19 ;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 9;
+ %jmp T_2.16;
+T_2.13 ;
+ %load/v 8, v0x90ff7a0_0, 32;
+ %cmpi/u 8, 1, 32;
+ %mov 8, 4, 1;
+ %jmp/0 T_2.20, 8;
+ %movi 9, 1, 4;
+ %jmp/1 T_2.22, 8;
+T_2.20 ; End of true expr.
+ %movi 13, 2, 4;
+ %jmp/0 T_2.21, 8;
+ ; End of false expr.
+ %blend 9, 13, 4; Condition unknown.
+ %jmp T_2.22;
+T_2.21 ;
+ %mov 9, 13, 4; Return false value
+T_2.22 ;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 9;
+ %jmp T_2.16;
+T_2.14 ;
+ %load/v 8, v0x90ff7a0_0, 32;
+ %cmpi/u 8, 1, 32;
+ %jmp/0xz T_2.23, 4;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff8a8_0, 0, 1;
+ %load/v 8, v0x90ff6f0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff740_0, 0, 8;
+ %movi 8, 3, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 8;
+ %jmp T_2.24;
+T_2.23 ;
+ %movi 8, 2, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 8;
+T_2.24 ;
+ %jmp T_2.16;
+T_2.15 ;
+ %load/v 8, v0x90ff7a0_0, 32;
+ %cmpi/u 8, 1, 32;
+ %jmp/0xz T_2.25, 4;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff8a8_0, 0, 1;
+ %load/v 8, v0x90ff6f0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff740_0, 0, 8;
+ %movi 8, 3, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 8;
+ %jmp T_2.26;
+T_2.25 ;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5f8_0, 0, 1;
+ %load/v 8, v0x90ff6f0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff558_0, 0, 8;
+ %movi 8, 4, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 8;
+T_2.26 ;
+ %jmp T_2.16;
+T_2.16 ;
+T_2.10 ;
+T_2.9 ;
+ %jmp T_2.7;
+T_2.3 ;
+ %ix/getv 3, v0x90ff0a0_0;
+ %jmp/1 t_2, 4;
+ %ix/load 0, 3, 0; word width
+ %ix/load 1, 0, 0; part off
+ %assign/av v0x90ff508, 0, 0;
+t_2 ;
+ %load/v 8, v0x90ff7f0_0, 32;
+ %ix/getv 3, v0x90ff0a0_0;
+ %jmp/1 t_3, 4;
+ %ix/load 1, 0, 0;
+ %set/av v0x90ff470, 8, 8;
+t_3 ;
+ %load/v 8, v0x90ff7f0_0, 32;
+ %mov 40, 0, 1;
+ %addi 8, 1, 33;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff7f0_0, 0, 8;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5a8_0, 0, 1;
+ %jmp T_2.7;
+T_2.4 ;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5a8_0, 0, 1;
+ %jmp T_2.7;
+T_2.5 ;
+ %movi 8, 1, 2;
+ %ix/load 0, 2, 0;
+ %assign/v0 v0x90ff310_0, 0, 8;
+ %load/v 8, v0x90ff0a0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff278_0, 0, 8;
+ %load/v 8, v0x90ff218_0, 1;
+ %jmp/0xz T_2.27, 8;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5a8_0, 0, 1;
+ %jmp T_2.28;
+T_2.27 ;
+ %movi 8, 3, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 8;
+T_2.28 ;
+ %jmp T_2.7;
+T_2.6 ;
+ %movi 8, 2, 2;
+ %ix/load 0, 2, 0;
+ %assign/v0 v0x90ff310_0, 0, 8;
+ %load/v 8, v0x90ff0a0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff278_0, 0, 8;
+ %load/v 8, v0x90ff218_0, 1;
+ %jmp/0xz T_2.29, 8;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5a8_0, 0, 1;
+ %jmp T_2.30;
+T_2.29 ;
+ %movi 8, 3, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90ff128_0, 0, 8;
+T_2.30 ;
+ %jmp T_2.7;
+T_2.7 ;
+T_2.1 ;
+ %jmp T_2;
+ .thread T_2;
+ .scope S_0x90c59c0;
+T_3 ;
+ %wait E_0x90cb4d8;
+ %load/v 8, v0x90ff648_0, 1;
+ %jmp/0xz T_3.0, 8;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90feea0_0, 0, 0;
+ %jmp T_3.1;
+T_3.0 ;
+ %load/v 8, v0x90fee40_0, 4;
+ %cmpi/u 8, 0, 4;
+ %jmp/1 T_3.2, 6;
+ %cmpi/u 8, 1, 4;
+ %jmp/1 T_3.3, 6;
+ %cmpi/u 8, 2, 4;
+ %jmp/1 T_3.4, 6;
+ %cmpi/u 8, 3, 4;
+ %jmp/1 T_3.5, 6;
+ %cmpi/u 8, 4, 4;
+ %jmp/1 T_3.6, 6;
+ %cmpi/u 8, 5, 4;
+ %jmp/1 T_3.7, 6;
+ %cmpi/u 8, 6, 4;
+ %jmp/1 T_3.8, 6;
+ %cmpi/u 8, 7, 4;
+ %jmp/1 T_3.9, 6;
+ %jmp T_3.10;
+T_3.2 ;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90feea0_0, 0, 0;
+ %load/v 8, v0x90fef00_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90d5d78_0, 0, 8;
+ %load/v 8, v0x90ff128_0, 4;
+ %mov 12, 0, 1;
+ %cmpi/u 8, 0, 5;
+ %inv 4, 1;
+ %mov 8, 4, 1;
+ %load/v 9, v0x90ff188_0, 1;
+ %or 8, 9, 1;
+ %jmp/0xz T_3.11, 8;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 0;
+ %jmp T_3.12;
+T_3.11 ;
+ %load/v 8, v0x90fef60_0, 3;
+ %cmpi/u 8, 0, 3;
+ %jmp/1 T_3.13, 6;
+ %cmpi/u 8, 1, 3;
+ %jmp/1 T_3.14, 6;
+ %cmpi/u 8, 2, 3;
+ %jmp/1 T_3.15, 6;
+ %cmpi/u 8, 3, 3;
+ %jmp/1 T_3.16, 6;
+ %cmpi/u 8, 4, 3;
+ %jmp/1 T_3.17, 6;
+ %vpi_call 2 371 "$display", "Error 1. cbus_cmd_i = %h\012", v0x90fef60_0;
+ %jmp T_3.19;
+T_3.13 ;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 0;
+ %jmp T_3.19;
+T_3.14 ;
+ %movi 8, 1, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 8;
+ %jmp T_3.19;
+T_3.15 ;
+ %movi 8, 2, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 8;
+ %jmp T_3.19;
+T_3.16 ;
+ %movi 8, 7, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 8;
+ %jmp T_3.19;
+T_3.17 ;
+ %movi 8, 6, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 8;
+ %jmp T_3.19;
+T_3.19 ;
+T_3.12 ;
+ %jmp T_3.10;
+T_3.3 ;
+ %ix/getv 3, v0x90fef00_0;
+ %load/av 8, v0x90ff508, 3;
+ %mov 11, 0, 1;
+ %cmpi/u 8, 0, 4;
+ %jmp/0xz T_3.20, 4;
+ %movi 8, 3, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 8;
+ %jmp T_3.21;
+T_3.20 ;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90feea0_0, 0, 1;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 0;
+T_3.21 ;
+ %jmp T_3.10;
+T_3.4 ;
+ %ix/getv 3, v0x90fef00_0;
+ %load/av 8, v0x90ff508, 3;
+ %mov 11, 0, 1;
+ %cmpi/u 8, 0, 4;
+ %jmp/0xz T_3.22, 4;
+ %movi 8, 4, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 8;
+ %jmp T_3.23;
+T_3.22 ;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90feea0_0, 0, 1;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 0;
+T_3.23 ;
+ %jmp T_3.10;
+T_3.5 ;
+ %ix/getv 3, v0x90d5d78_0;
+ %load/av 8, v0x90ff508, 3;
+ %mov 11, 0, 1;
+ %cmpi/u 8, 0, 4;
+ %inv 4, 1;
+ %jmp/0xz T_3.24, 4;
+ %vpi_call 2 396 "$DISPLAY", "Error 2. mem_state[cbus_addr_i] is not M.\012", "c_addr=%h,mem_state[cbus_addr_i]=%h", v0x90d5d78_0, &A;
+ %jmp T_3.25;
+T_3.24 ;
+ %movi 8, 1, 2;
+ %ix/load 0, 2, 0;
+ %assign/v0 v0x90ff310_0, 0, 8;
+ %load/v 8, v0x90ff0a0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff278_0, 0, 8;
+ %ix/getv 3, v0x90d5d78_0;
+ %load/av 8, v0x90ff470, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff410_0, 0, 8;
+ %load/v 8, v0x90ff218_0, 1;
+ %jmp/0xz T_3.26, 8;
+ %movi 8, 3, 3;
+ %ix/getv 3, v0x90d5d78_0;
+ %jmp/1 t_4, 4;
+ %ix/load 0, 3, 0; word width
+ %ix/load 1, 0, 0; part off
+ %assign/av v0x90ff508, 0, 8;
+t_4 ;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90feea0_0, 0, 1;
+T_3.26 ;
+T_3.25 ;
+ %jmp T_3.10;
+T_3.6 ;
+ %ix/getv 3, v0x90d5d78_0;
+ %load/av 8, v0x90ff508, 3;
+ %mov 11, 0, 1;
+ %cmpi/u 8, 2, 4;
+ %mov 8, 4, 1;
+ %ix/getv 3, v0x90d5d78_0;
+ %load/av 9, v0x90ff508, 3;
+ %mov 12, 0, 1;
+ %cmpi/u 9, 1, 4;
+ %mov 9, 4, 1;
+ %or 8, 9, 1;
+ %inv 8, 1;
+ %jmp/0xz T_3.28, 8;
+ %vpi_call 2 419 "$DISPLAY", "Error 3. mem_state[cbus_addr_i] is not S or E.\012";
+ %vpi_call 2 420 "$DISPLAY", "c_addr=%h,mem_state[cbus_addr_i]=%h", v0x90d5d78_0, &A;
+ %jmp T_3.29;
+T_3.28 ;
+ %movi 8, 1, 2;
+ %ix/load 0, 2, 0;
+ %assign/v0 v0x90ff310_0, 0, 8;
+ %load/v 8, v0x90ff0a0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff278_0, 0, 8;
+ %ix/getv 3, v0x90d5d78_0;
+ %load/av 8, v0x90ff470, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff410_0, 0, 8;
+ %load/v 8, v0x90ff218_0, 1;
+ %jmp/0xz T_3.30, 8;
+ %movi 8, 2, 3;
+ %ix/getv 3, v0x90d5d78_0;
+ %jmp/1 t_5, 4;
+ %ix/load 0, 3, 0; word width
+ %ix/load 1, 0, 0; part off
+ %assign/av v0x90ff508, 0, 8;
+t_5 ;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90feea0_0, 0, 1;
+T_3.30 ;
+T_3.29 ;
+ %jmp T_3.10;
+T_3.7 ;
+ %load/v 8, v0x90ff8a8_0, 1;
+ %mov 9, 0, 2;
+ %cmpi/u 8, 1, 3;
+ %inv 4, 1;
+ %mov 8, 4, 1;
+ %load/v 9, v0x90ff740_0, 32;
+ %load/v 41, v0x90d5d78_0, 32;
+ %cmp/u 9, 41, 32;
+ %inv 4, 1;
+ %mov 9, 4, 1;
+ %or 8, 9, 1;
+ %jmp/0xz T_3.32, 8;
+ %vpi_call 2 441 "$DISPLAY", "Error 4. Write to cache witout early broadcast.\012", "wr_proc_wait_for_en=%h,wr_proc_addr=%h,c_addr=%h", v0x90ff8a8_0, v0x90ff740_0, v0x90d5d78_0;
+ %jmp T_3.33;
+T_3.32 ;
+ %movi 8, 1, 2;
+ %ix/load 0, 2, 0;
+ %assign/v0 v0x90ff310_0, 0, 8;
+ %load/v 8, v0x90ff0a0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff278_0, 0, 8;
+ %load/v 8, v0x90ff218_0, 1;
+ %jmp/0xz T_3.34, 8;
+ %load/v 8, v0x90ff370_0, 32;
+ %ix/getv 3, v0x90ff0a0_0;
+ %jmp/1 t_6, 4;
+ %ix/load 0, 32, 0; word width
+ %ix/load 1, 0, 0; part off
+ %assign/av v0x90ff470, 0, 8;
+t_6 ;
+ %movi 8, 7, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 8;
+T_3.34 ;
+T_3.33 ;
+ %jmp T_3.10;
+T_3.8 ;
+ %load/v 8, v0x90ff5f8_0, 1;
+ %mov 9, 0, 2;
+ %cmpi/u 8, 1, 3;
+ %inv 4, 1;
+ %mov 8, 4, 1;
+ %load/v 9, v0x90ff558_0, 32;
+ %load/v 41, v0x90d5d78_0, 32;
+ %cmp/u 9, 41, 32;
+ %inv 4, 1;
+ %mov 9, 4, 1;
+ %or 8, 9, 1;
+ %jmp/0xz T_3.36, 8;
+ %vpi_call 2 462 "$DISPLAY", "Error 5. Read to cache witout early broadcast.\012", "rd_proc_wait_for_en=%h,rd_proc_addr=%h,c_addr=%h", v0x90ff5f8_0, v0x90ff558_0, v0x90d5d78_0;
+ %jmp T_3.37;
+T_3.36 ;
+ %movi 8, 1, 2;
+ %ix/load 0, 2, 0;
+ %assign/v0 v0x90ff310_0, 0, 8;
+ %load/v 8, v0x90ff0a0_0, 32;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff278_0, 0, 8;
+ %load/v 8, v0x90ff218_0, 1;
+ %jmp/0xz T_3.38, 8;
+ %load/v 8, v0x90ff370_0, 32;
+ %ix/getv 3, v0x90ff0a0_0;
+ %jmp/1 t_7, 4;
+ %ix/load 0, 32, 0; word width
+ %ix/load 1, 0, 0; part off
+ %assign/av v0x90ff470, 0, 8;
+t_7 ;
+ %movi 8, 7, 4;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 8;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5f8_0, 0, 0;
+T_3.38 ;
+T_3.37 ;
+ %jmp T_3.10;
+T_3.9 ;
+ %load/v 8, v0x90ff7f0_0, 32;
+ %ix/getv 3, v0x90ff0a0_0;
+ %jmp/1 t_8, 4;
+ %ix/load 0, 8, 0; word width
+ %ix/load 1, 0, 0; part off
+ %assign/av v0x90ff470, 0, 8;
+t_8 ;
+ %load/v 8, v0x90ff7f0_0, 32;
+ %mov 40, 0, 1;
+ %addi 8, 1, 33;
+ %ix/load 0, 32, 0;
+ %assign/v0 v0x90ff7f0_0, 0, 8;
+ %ix/load 0, 4, 0;
+ %assign/v0 v0x90fee40_0, 0, 0;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90feea0_0, 0, 1;
+ %ix/load 0, 1, 0;
+ %assign/v0 v0x90ff5f8_0, 0, 1;
+ %jmp T_3.10;
+T_3.10 ;
+T_3.1 ;
+ %jmp T_3;
+ .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+ "N/A";
+ "";
+ "../src/tb/mesi_isc_tb_cpu.v";
sim/a.out
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim/run_wave
===================================================================
--- sim/run_wave (nonexistent)
+++ sim/run_wave (revision 3)
@@ -0,0 +1,38 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+gtkwave dump.vcd -a dump.sav &
sim/run_wave
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim/filters/m_state.filter
===================================================================
--- sim/filters/m_state.filter (nonexistent)
+++ sim/filters/m_state.filter (revision 3)
@@ -0,0 +1,45 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+000 IDLE
+001 WR_CACHE
+010 RD_CACHE
+011 SEND_WR_BR
+100 SEND_RD_BR
+101 -
+110 -
+111 -
\ No newline at end of file
Index: sim/filters/wr_rd.filter
===================================================================
--- sim/filters/wr_rd.filter (nonexistent)
+++ sim/filters/wr_rd.filter (revision 3)
@@ -0,0 +1,42 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+00 -
+01 rd
+10 wr
+11 rdwr
+
Index: sim/filters/tb_ins.filter
===================================================================
--- sim/filters/tb_ins.filter (nonexistent)
+++ sim/filters/tb_ins.filter (revision 3)
@@ -0,0 +1,53 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+0000 NOP
+0001 WR
+0010 RD
+0011 -
+0100 -
+0101 -
+0110 -
+0111 -
+1000 -
+1001 -
+1010 -
+1011 -
+1100 -
+1101 -
+1110 -
+1111 -
\ No newline at end of file
Index: sim/filters/cbus_cmd.filter
===================================================================
--- sim/filters/cbus_cmd.filter (nonexistent)
+++ sim/filters/cbus_cmd.filter (revision 3)
@@ -0,0 +1,45 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+000 -
+001 wr_sn
+010 rd_sn
+011 en_wr
+100 en_rd
+101 ERR
+110 ERR
+111 ERR
Index: sim/filters/mesi_states.filter
===================================================================
--- sim/filters/mesi_states.filter (nonexistent)
+++ sim/filters/mesi_states.filter (revision 3)
@@ -0,0 +1,42 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+1001 M
+0101 E
+0011 S
+0000 I
+
Index: sim/filters/full_empty.filter
===================================================================
--- sim/filters/full_empty.filter (nonexistent)
+++ sim/filters/full_empty.filter (revision 3)
@@ -0,0 +1,42 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+00 non
+01 empty
+10 full
+11 f-e
+
Index: sim/filters/c_state.filter
===================================================================
--- sim/filters/c_state.filter (nonexistent)
+++ sim/filters/c_state.filter (revision 3)
@@ -0,0 +1,53 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+0000 IDLE
+0001 WR_SN
+0010 RD_SN
+0011 EV_IN
+0100 EV
+0101 RD_L_WR
+0110 RD_L_RD
+0111 RD_C
+1000 WR_C
+1001 -
+1010 -
+1011 -
+1100 -
+1101 -
+1110 -
+1111 -
Index: sim/filters/rd.filter
===================================================================
--- sim/filters/rd.filter (nonexistent)
+++ sim/filters/rd.filter (revision 3)
@@ -0,0 +1,40 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+1 rd
+0 _
+
Index: sim/filters/rst.filter
===================================================================
--- sim/filters/rst.filter (nonexistent)
+++ sim/filters/rst.filter (revision 3)
@@ -0,0 +1,40 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+1 RST
+0 0
+
Index: sim/filters/mbus_cmd.filter
===================================================================
--- sim/filters/mbus_cmd.filter (nonexistent)
+++ sim/filters/mbus_cmd.filter (revision 3)
@@ -0,0 +1,45 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+000 NOP
+001 WR
+010 RD
+011 WR_BR
+100 RD_BR
+101 -
+110 -
+111 -
Index: sim/sim.log
===================================================================
--- sim/sim.log (nonexistent)
+++ sim/sim.log (revision 3)
@@ -0,0 +1,15 @@
+VCD info: dumpfile ./dump.vcd opened for output.
+Watchdog finish
+
+Statistic
+
+CPU 3. WR: 155 RD: 186 NOP: 389
+
+CPU 2. WR: 141 RD: 202 NOP: 390
+
+CPU 1. WR: 136 RD: 207 NOP: 343
+
+CPU 0. WR: 145 RD: 196 NOP: 362
+
+Total rd and wr accesses: 1368
+
Index: sim/sim.cmd
===================================================================
--- sim/sim.cmd (nonexistent)
+++ sim/sim.cmd (revision 3)
@@ -0,0 +1 @@
+../src/tb/mesi_isc_tb.v
Index: sim/README.txt
===================================================================
--- sim/README.txt (nonexistent)
+++ sim/README.txt (revision 3)
@@ -0,0 +1,48 @@
+//////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MESI_ISC Project ////
+//// ////
+//// Author(s): ////
+//// - Yair Amitay yair.amitay@yahoo.com ////
+//// www.linkedin.com/in/yairamitay ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+MESI_ISC Project
+=================
+
+Directoy: sim
+=================
+
+A synthesis environment of the project.
+
+./run_sim - To run simulation.
+./run_wave - To run waveform.
+sim.log - Simulation results.
Index: sim/.gtkwaverc
===================================================================
Index: sim/run_sim
===================================================================
--- sim/run_sim (nonexistent)
+++ sim/run_sim (revision 3)
@@ -0,0 +1,49 @@
+#//////////////////////////////////////////////////////////////////
+#//// ////
+#//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+#//// ////
+#//// This source file may be used and distributed without ////
+#//// restriction provided that this copyright statement is not ////
+#//// removed from the file and that any derivative work contains ////
+#//// the original copyright notice and the associated disclaimer. ////
+#//// ////
+#//// This source file is free software; you can redistribute it ////
+#//// and/or modify it under the terms of the GNU Lesser General ////
+#//// Public License as published by the Free Software Foundation; ////
+#//// either version 2.1 of the License, or (at your option) any ////
+#//// later version. ////
+#//// ////
+#//// This source is distributed in the hope that it will be ////
+#//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#//// PURPOSE. See the GNU Lesser General Public License for more ////
+#//// details. ////
+#//// ////
+#//// You should have received a copy of the GNU Lesser General ////
+#//// Public License along with this source; if not, download it ////
+#//// from http://www.opencores.org/lgpl.shtml ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+#//////////////////////////////////////////////////////////////////////
+#//// ////
+#//// MESI_ISC Project ////
+#//// ////
+#//// Author(s): ////
+#//// - Yair Amitay yair.amitay@yahoo.com ////
+#//// www.linkedin.com/in/yairamitay ////
+#//// ////
+#//////////////////////////////////////////////////////////////////////
+
+\rm mesi_isc.out
+iverilog -o mesi_isc.out \
+ -I ../src/rtl \
+ -I ../src/tb \
+ -y ../src/rtl \
+ -y ../src/tb \
+ -c sim.cmd \
+ -v \
+ > iverilog.log
+grep error iverilog.log
+vvp -l sim.log \
+ mesi_isc.out
sim/run_sim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim/dump.sav
===================================================================
--- sim/dump.sav (nonexistent)
+++ sim/dump.sav (revision 3)
@@ -0,0 +1,511 @@
+[timestart] 9443000000
+[size] 1366 719
+[pos] -1 -1
+*-27.579500 10363547000 97000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] mesi_isc_tb.
+[treeopen] mesi_isc_tb.mesi_isc.mesi_isc_broad.
+@2028
+^1 /home/yair/Work/Projects/mesi_isc/sim/filters/rst.filter
+mesi_isc_tb.rst
+@28
+mesi_isc_tb.clk
+@800200
+-tb
+@c00200
+-tb_inst
+@2028
+^2 /home/yair/Work/Projects/mesi_isc/sim/filters/tb_ins.filter
+mesi_isc_tb.tb_ins3[3:0]
+@2024
+^2 /home/yair/Work/Projects/mesi_isc/sim/filters/tb_ins.filter
+mesi_isc_tb.tb_ins_addr3[3:0]
+@28
+(0)mesi_isc_tb.tb_ins_ack[3:0]
+@2028
+^2 /home/yair/Work/Projects/mesi_isc/sim/filters/tb_ins.filter
+mesi_isc_tb.tb_ins2[3:0]
+@2024
+^2 /home/yair/Work/Projects/mesi_isc/sim/filters/tb_ins.filter
+mesi_isc_tb.tb_ins_addr2[3:0]
+@28
+(1)mesi_isc_tb.tb_ins_ack[3:0]
+@2028
+^2 /home/yair/Work/Projects/mesi_isc/sim/filters/tb_ins.filter
+mesi_isc_tb.tb_ins1[3:0]
+@2024
+^2 /home/yair/Work/Projects/mesi_isc/sim/filters/tb_ins.filter
+mesi_isc_tb.tb_ins_addr1[3:0]
+@28
+(2)mesi_isc_tb.tb_ins_ack[3:0]
+@2028
+^2 /home/yair/Work/Projects/mesi_isc/sim/filters/tb_ins.filter
+mesi_isc_tb.tb_ins0[3:0]
+@2024
+^2 /home/yair/Work/Projects/mesi_isc/sim/filters/tb_ins.filter
+mesi_isc_tb.tb_ins_addr0[3:0]
+@28
+(3)mesi_isc_tb.tb_ins_ack[3:0]
+@1401200
+-tb_inst
+@c00200
+-tb_other
+@22
+mesi_isc_tb.cur_stimulus_cpu[31:0]
+mesi_isc_tb.tb_ins_nop_period0[7:0]
+mesi_isc_tb.tb_ins_nop_period1[7:0]
+mesi_isc_tb.tb_ins_nop_period2[7:0]
+mesi_isc_tb.tb_ins_nop_period3[7:0]
+@24
+mesi_isc_tb.cpu_priority[1:0]
+@28
+mesi_isc_tb.mbus_ack_memory[3:0]
+mesi_isc_tb.mbus_ack_mesi_isc[3:0]
+mesi_isc_tb.mbus_ack[3:0]
+@1401200
+-tb_other
+@1000200
+-tb
+@800200
+-mbus
+@22
+mesi_isc_tb.mbus_data_rd[31:0]
+@2028
+^3 /home/yair/Work/Projects/mesi_isc/sim/filters/mbus_cmd.filter
+mesi_isc_tb.mbus_cmd3[2:0]
+@22
+mesi_isc_tb.mesi_isc.mbus_addr3_i[31:0]
+mesi_isc_tb.mbus_data_wr3[31:0]
+@28
+(0)mesi_isc_tb.mbus_ack[3:0]
+@2028
+^3 /home/yair/Work/Projects/mesi_isc/sim/filters/mbus_cmd.filter
+mesi_isc_tb.mbus_cmd2[2:0]
+@22
+mesi_isc_tb.mesi_isc.mbus_addr2_i[31:0]
+mesi_isc_tb.mbus_data_wr2[31:0]
+@28
+(1)mesi_isc_tb.mbus_ack[3:0]
+@2028
+^3 /home/yair/Work/Projects/mesi_isc/sim/filters/mbus_cmd.filter
+mesi_isc_tb.mbus_cmd1[2:0]
+@22
+mesi_isc_tb.mesi_isc.mbus_addr1_i[31:0]
+mesi_isc_tb.mbus_data_wr1[31:0]
+@28
+(2)mesi_isc_tb.mbus_ack[3:0]
+@2028
+^3 /home/yair/Work/Projects/mesi_isc/sim/filters/mbus_cmd.filter
+mesi_isc_tb.mbus_cmd0[2:0]
+@c00022
+mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+@28
+(0)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(1)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(2)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(3)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(4)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(5)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(6)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(7)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(8)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(9)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(10)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(11)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(12)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(13)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(14)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(15)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(16)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(17)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(18)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(19)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(20)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(21)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(22)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(23)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(24)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(25)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(26)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(27)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(28)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(29)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(30)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+(31)mesi_isc_tb.mesi_isc.mbus_addr0_i[31:0]
+@1401200
+-group_end
+@22
+mesi_isc_tb.mbus_data_wr0[31:0]
+@28
+(3)mesi_isc_tb.mbus_ack[3:0]
+@1000200
+-mbus
+@800200
+-cbus
+@22
+mesi_isc_tb.mesi_isc.cbus_addr_o[31:0]
+@2028
+^4 /home/yair/Work/Projects/mesi_isc/sim/filters/cbus_cmd.filter
+mesi_isc_tb.mesi_isc.cbus_cmd3_o[2:0]
+@28
+mesi_isc_tb.mesi_isc.cbus_ack3_i
+@2028
+^4 /home/yair/Work/Projects/mesi_isc/sim/filters/cbus_cmd.filter
+mesi_isc_tb.mesi_isc.cbus_cmd2_o[2:0]
+@28
+mesi_isc_tb.mesi_isc.cbus_ack2_i
+@2028
+^4 /home/yair/Work/Projects/mesi_isc/sim/filters/cbus_cmd.filter
+mesi_isc_tb.mesi_isc.cbus_cmd1_o[2:0]
+@28
+mesi_isc_tb.mesi_isc.cbus_ack1_i
+@2008
+^4 /home/yair/Work/Projects/mesi_isc/sim/filters/cbus_cmd.filter
+mesi_isc_tb.mesi_isc.cbus_cmd0_o[2:0]
+@28
+mesi_isc_tb.mesi_isc.cbus_ack0_i
+@1000200
+-cbus
+@c00200
+-broad_cntl
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.broadcast_in_progress
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.cbus_active_broad_array[3:0]
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.cbus_active_en_access_array[3:0]
+@24
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.broad_snoop_cpu_id_i[1:0]
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.cbus_ack_array_i[3:0]
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.cbus_active_en_access_array[3:0]
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.broad_fifo_rd_o
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.fifo_status_empty_i
+@22
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.fifo_rd_array_o[3:0]
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.broad_addr_o[31:0]
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.cbus_active_en_access_array[3:0]
+mesi_isc_tb.mesi_isc.mesi_isc_broad.mesi_isc_broad_cntl.cbus_ack_array_i[3:0]
+@1401200
+-broad_cntl
+@c00200
+-tb_cpu3
+@2028
+^5 /home/yair/Work/Projects/mesi_isc/sim/filters/c_state.filter
+mesi_isc_tb.mesi_isc_tb_cpu3.c_state[3:0]
+^6 /home/yair/Work/Projects/mesi_isc/sim/filters/m_state.filter
+mesi_isc_tb.mesi_isc_tb_cpu3.m_state[2:0]
+@28
+mesi_isc_tb.mesi_isc_tb_cpu3.mbus_ack_i
+mesi_isc_tb.mesi_isc_tb_cpu3.mbus_cmd_o[2:0]
+mesi_isc_tb.mesi_isc_tb_cpu3.mbus_ack_i
+@22
+mesi_isc_tb.mesi_isc_tb_cpu3.tb_ins_i[3:0]
+@28
+mesi_isc_tb.mesi_isc_tb_cpu3.cbus_cmd_i[2:0]
+@22
+mesi_isc_tb.mesi_isc_tb_cpu3.c_addr[31:0]
+@28
+mesi_isc_tb.mesi_isc_tb_cpu3.wr_proc_wait_for_en
+@22
+mesi_isc_tb.mesi_isc_tb_cpu3.wr_proc_addr[31:0]
+@28
+mesi_isc_tb.mesi_isc_tb_cpu3.rd_proc_wait_for_en
+@22
+mesi_isc_tb.mesi_isc_tb_cpu3.rd_proc_addr[31:0]
+@1401200
+-tb_cpu3
+@c00200
+-tb_cpu2
+@2028
+^5 /home/yair/Work/Projects/mesi_isc/sim/filters/c_state.filter
+mesi_isc_tb.mesi_isc_tb_cpu2.c_state[3:0]
+^6 /home/yair/Work/Projects/mesi_isc/sim/filters/m_state.filter
+mesi_isc_tb.mesi_isc_tb_cpu2.m_state[2:0]
+@1401200
+-tb_cpu2
+@800200
+-tb_cpu1
+@2028
+^5 /home/yair/Work/Projects/mesi_isc/sim/filters/c_state.filter
+mesi_isc_tb.mesi_isc_tb_cpu1.c_state[3:0]
+^6 /home/yair/Work/Projects/mesi_isc/sim/filters/m_state.filter
+mesi_isc_tb.mesi_isc_tb_cpu1.m_state[2:0]
+@28
+mesi_isc_tb.mesi_isc_tb_cpu1.rd_proc_wait_for_en
+@1000200
+-tb_cpu1
+@c00200
+-tb_cpu0
+@2028
+^5 /home/yair/Work/Projects/mesi_isc/sim/filters/c_state.filter
+mesi_isc_tb.mesi_isc_tb_cpu0.c_state[3:0]
+^6 /home/yair/Work/Projects/mesi_isc/sim/filters/m_state.filter
+mesi_isc_tb.mesi_isc_tb_cpu0.m_state[2:0]
+@28
+mesi_isc_tb.mesi_isc_tb_cpu0.rd_proc_wait_for_en
+@22
+mesi_isc_tb.mesi_isc_tb_cpu0.rd_proc_addr[31:0]
+@28
+mesi_isc_tb.mesi_isc_tb_cpu0.wr_proc_wait_for_en
+@22
+mesi_isc_tb.mesi_isc_tb_cpu0.wr_proc_addr[31:0]
+@1401200
+-tb_cpu0
+@28
+mesi_isc_tb.clk
+@c00200
+-broad_fifo
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.rd_i
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.wr_i
+@24
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.fifo_depth[1:0]
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.ptr_rd[1:0]
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.ptr_wr[1:0]
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.fifo_depth_decrease
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.fifo_depth_increase
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.status_empty
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.status_full
+@22
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_i[40:0]
+@c00022
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+@28
+(0)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(1)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(2)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(3)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(4)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(5)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(6)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(7)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(8)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(9)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(10)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(11)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(12)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(13)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(14)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(15)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(16)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(17)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(18)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(19)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(20)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(21)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(22)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(23)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(24)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(25)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(26)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(27)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(28)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(29)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(30)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(31)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(32)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(33)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(34)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(35)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(36)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(37)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(38)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(39)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+(40)mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.data_o[40:0]
+@1401200
+-group_end
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_overflow
+mesi_isc_tb.mesi_isc.mesi_isc_broad.broad_fifo.dbg_fifo_underflow
+@1401200
+-broad_fifo
+@c00200
+-breq_cntl
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.clk
+@22
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.fifo_rd_array_o[3:0]
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.fifo_wr_array_o[3:0]
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.mbus_ack_array[3:0]
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.fifo_select_oh[3:0]
+@22
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.broad_cpu_id_o[1:0]
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.broad_fifo_wr_o
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.mesi_isc_breq_fifos_cntl.broad_fifo_status_full_i
+@1401200
+-breq_cntl
+@c00200
+-breq_fifos
+@22
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_3.data_i[40:0]
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_3.fifo_depth
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_3.status_full
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_3.status_empty
+@22
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_2.data_i[40:0]
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_2.fifo_depth
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_2.status_full
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_2.status_empty
+@22
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_1.data_i[40:0]
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_1.fifo_depth
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_1.status_full
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_1.status_empty
+@22
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_0.data_i[40:0]
+@28
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_0.fifo_depth
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_0.status_full
+mesi_isc_tb.mesi_isc.mesi_isc_breq_fifos.fifo_0.status_empty
+@1401200
+-breq_fifos
+@800200
+-mem1
+@22
+mesi_isc_tb.mem1[31:0]
+@2028
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu3.cache_state1[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu2.cache_state1[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu1.cache_state1[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu0.cache_state1[3:0]
+@1000200
+-mem1
+@800200
+-mem2
+@22
+mesi_isc_tb.mem2[31:0]
+@2028
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu3.cache_state2[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu2.cache_state2[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu1.cache_state2[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu0.cache_state2[3:0]
+@c00200
+-mem2_more
+@22
+mesi_isc_tb.mesi_isc_tb_cpu3.cache2[31:0]
+mesi_isc_tb.mesi_isc_tb_cpu2.cache2[31:0]
+mesi_isc_tb.mesi_isc_tb_cpu1.cache2[31:0]
+mesi_isc_tb.mesi_isc_tb_cpu0.cache2[31:0]
+@800022
+mesi_isc_tb.mem2[31:0]
+@c00022
+#{mem2_3} (0)mesi_isc_tb.mem2[31:0] (1)mesi_isc_tb.mem2[31:0] (2)mesi_isc_tb.mem2[31:0] (3)mesi_isc_tb.mem2[31:0] (4)mesi_isc_tb.mem2[31:0] (5)mesi_isc_tb.mem2[31:0] (6)mesi_isc_tb.mem2[31:0] (7)mesi_isc_tb.mem2[31:0]
+@28
+(0)mesi_isc_tb.mem2[31:0]
+(1)mesi_isc_tb.mem2[31:0]
+(2)mesi_isc_tb.mem2[31:0]
+(3)mesi_isc_tb.mem2[31:0]
+(4)mesi_isc_tb.mem2[31:0]
+(5)mesi_isc_tb.mem2[31:0]
+(6)mesi_isc_tb.mem2[31:0]
+(7)mesi_isc_tb.mem2[31:0]
+@1401200
+-group_end
+@c00022
+#{mem2_2} (8)mesi_isc_tb.mem2[31:0] (9)mesi_isc_tb.mem2[31:0] (10)mesi_isc_tb.mem2[31:0] (11)mesi_isc_tb.mem2[31:0] (12)mesi_isc_tb.mem2[31:0] (13)mesi_isc_tb.mem2[31:0] (14)mesi_isc_tb.mem2[31:0] (15)mesi_isc_tb.mem2[31:0]
+@28
+(8)mesi_isc_tb.mem2[31:0]
+(9)mesi_isc_tb.mem2[31:0]
+(10)mesi_isc_tb.mem2[31:0]
+(11)mesi_isc_tb.mem2[31:0]
+(12)mesi_isc_tb.mem2[31:0]
+(13)mesi_isc_tb.mem2[31:0]
+(14)mesi_isc_tb.mem2[31:0]
+(15)mesi_isc_tb.mem2[31:0]
+@1401200
+-group_end
+@c00022
+#{mem2_1} (16)mesi_isc_tb.mem2[31:0] (17)mesi_isc_tb.mem2[31:0] (18)mesi_isc_tb.mem2[31:0] (19)mesi_isc_tb.mem2[31:0] (20)mesi_isc_tb.mem2[31:0] (21)mesi_isc_tb.mem2[31:0] (22)mesi_isc_tb.mem2[31:0] (23)mesi_isc_tb.mem2[31:0]
+@28
+(16)mesi_isc_tb.mem2[31:0]
+(17)mesi_isc_tb.mem2[31:0]
+(18)mesi_isc_tb.mem2[31:0]
+(19)mesi_isc_tb.mem2[31:0]
+(20)mesi_isc_tb.mem2[31:0]
+(21)mesi_isc_tb.mem2[31:0]
+(22)mesi_isc_tb.mem2[31:0]
+(23)mesi_isc_tb.mem2[31:0]
+@1401200
+-group_end
+@c00022
+#{mem2_0} (24)mesi_isc_tb.mem2[31:0] (25)mesi_isc_tb.mem2[31:0] (26)mesi_isc_tb.mem2[31:0] (27)mesi_isc_tb.mem2[31:0] (28)mesi_isc_tb.mem2[31:0] (29)mesi_isc_tb.mem2[31:0] (30)mesi_isc_tb.mem2[31:0] (31)mesi_isc_tb.mem2[31:0]
+@28
+(24)mesi_isc_tb.mem2[31:0]
+(25)mesi_isc_tb.mem2[31:0]
+(26)mesi_isc_tb.mem2[31:0]
+(27)mesi_isc_tb.mem2[31:0]
+(28)mesi_isc_tb.mem2[31:0]
+(29)mesi_isc_tb.mem2[31:0]
+(30)mesi_isc_tb.mem2[31:0]
+(31)mesi_isc_tb.mem2[31:0]
+@1401200
+-group_end
+@1001200
+-group_end
+@1401200
+-mem2_more
+@1000200
+-group_end
+@800201
+-mem3
+@23
+mesi_isc_tb.mem3[31:0]
+@2029
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu3.cache_state3[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu2.cache_state3[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu1.cache_state3[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu0.cache_state3[3:0]
+@1000201
+-mem3
+@800200
+-mem4
+@22
+mesi_isc_tb.mem4[31:0]
+@2028
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu3.cache_state4[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu2.cache_state4[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu1.cache_state4[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu0.cache_state4[3:0]
+@1000200
+-mem4
+@800200
+-mem5
+@22
+mesi_isc_tb.mem5[31:0]
+@2028
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu3.cache_state5[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu2.cache_state5[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu1.cache_state5[3:0]
+^7 /home/yair/Work/Projects/mesi_isc/sim/filters/mesi_states.filter
+mesi_isc_tb.mesi_isc_tb_cpu0.cache_state5[3:0]
+@1000200
+-mem5
+@c00200
+-wr_data
+@1401200
+-wr_data
+[pattern_trace] 1
+[pattern_trace] 0