URL
https://opencores.org/ocsvn/mini_aes/mini_aes/trunk
Subversion Repositories mini_aes
Compare Revisions
- This comparison shows the changes necessary to convert path
/mini_aes/trunk
- from Rev 15 to Rev 16
- ↔ Reverse comparison
Rev 15 → Rev 16
/bench/modelsim_bench.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Top module to connect all component in test bench. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/bench/input.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Input stimuli file for test bench. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |
/bench/output.vhdl
13,11 → 13,8
------------------------------------------------------------------------------- |
-- Description : Output file to analize and record output of test bench. |
------------------------------------------------------------------------------- |
-- Copyright (C) 2005 Arif E. Nugroho |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- Copyright (C) 2005 Arif Endro Nugroho |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
-- |
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION |
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT |