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/clock_gate.vhd
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-------------------------------------------------------------------------- |
-- -- |
-- -- |
-- miniMIPS Superscalar Processor : Clock gating stage -- |
-- based on miniMIPS Processor -- |
-- -- |
-- -- |
-- Author : Miguel Cafruni -- |
-- miguel_cafruni@hotmail.com -- |
-- December 2018 -- |
-------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
|
library work; |
use work.pack_mips.all; |
|
entity clock_gate is |
port ( |
clock_in1 : in bus1; |
clock_in2 : in bus1; |
clock_out1 : out bus1; |
clock_out2 : out bus1; |
gate1 : in bus1; |
gate2 : in bus1 |
); |
end clock_gate; |
|
architecture rtl of clock_gate is |
|
begin |
-- chaveamento dos clocks |
clock_out1 <= clock_in1;-- when gate1 = '0' else '1'; |
clock_out2 <= clock_in2;-- when gate2 = '0' else '1'; |
|
end rtl; |