URL
https://opencores.org/ocsvn/miniuart2/miniuart2/trunk
Subversion Repositories miniuart2
Compare Revisions
- This comparison shows the changes necessary to convert path
/miniuart2/trunk/sim/Foundation sim
- from Rev 23 to Rev 26
- ↔ Reverse comparison
Rev 23 → Rev 26
/testrx.pdf
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testrx.pdf
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Index: testtx.pdf
===================================================================
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Index: testtx.pdf
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--- testtx.pdf (nonexistent)
+++ testtx.pdf (revision 26)
testtx.pdf
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Index: TESTRxLimit.CMD
===================================================================
--- TESTRxLimit.CMD (nonexistent)
+++ TESTRxLimit.CMD (revision 26)
@@ -0,0 +1,37 @@
+| Script file for testing the minimal an maximal Baudrate excursion around the
+| nominal Baudrate of 125kHz (in term of %)
+
+| Initial settings
+delete_waveforms
+restart
+stepsize 50nS
+
+| Watched Signals and Vectors
+watch WB_CLK_I | Wishbone clock
+watch WB_RST_I
+
+vector RxData RxData7 RxData6 RxData5 RxData4 RxData3 RxData2 RxData1 RxData0
+watch RxD_PAD_I | RS232 Rx Line
+watch IntRx_O | Emit Buffer is empty
+watch BR_Clk_I
+watch EnabRx
+
+| Stimulators Assignment
+clock WB_CLK_I 1 0 | BR_CLK_I=10MHz
+wfm WB_RST_I @1nS=L 100nS=H 100nS=L
+assign WB_STB_I 0
+assign WB_WE_I 0
+
+wfm BR_Clk_I @0nS=L (0.946uS=H 1uS=L)*8000 | BR_Clk_I=500kHz
+| BRDIVISOR=1. Baudrate=500000/1/4=125kHz (Bit period=8uS)
+| Below is a generation of 50 same frames, coding 40h.
+wfm RxD_PAD_I @0nS=H +
+ 102.7uS=H (8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=H 8uS=L 8uS=H)*150 8uS=H
+
+| Perform Simulation
+sim 10mS
+
+| Results:
+| max BR_Clk_I: 2.118uS
+| min BR_Clk_I: 1.946uS
+
TESTRxLimit.CMD
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+*
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Index: TESTTx.CMD
===================================================================
--- TESTTx.CMD (nonexistent)
+++ TESTTx.CMD (revision 26)
@@ -0,0 +1,47 @@
+| Script file for testing the UART in echo mode (Txd and must be RxD tied)
+| 2 writes followed by 2 read
+
+| Initial settings
+delete_waveforms
+restart
+stepsize 50nS
+
+| Watched Signals and Vectors
+|
+| Define your signal and vector watch list here
+watch WB_CLK_I
+watch WB_RST_I
+watch WB_WE_I
+watch WB_STB_I
+watch WB_ACK_O
+vector WB_ADR WB_ADR_I[1:0]
+vector WB_DI WB_DAT_I[7:0]
+vector WB_DO WB_DAT_O[7:0]
+watch TxD_PAD_O | RS232 Tx Line
+watch IntTx_O | Byte present in buffer
+watch IntRx_O | Emit Buffer is empty
+watch BR_Clk_I
+watch EnabTx EnabRx
+
+| Stimulators Assignment
+| 1/Write Byte
+| 2/Write another byte
+clock WB_CLK_I 1 0
+wfm WB_RST_I @1nS=L 100nS=H 100nS=L
+wfm WB_STB_I @1nS=L +
+ @100.001uS=H 100nS=L +
+ @250.001uS=H 100nS=L
+wfm WB_WE_I @1nS=L +
+ @100.001uS=H +
+ @250.001uS=H
+wfm WB_ADR @1nS=L +
+ @100.001uS=0\H 100nS=Z +
+ @250.001uS=0\H 100nS=Z
+wfm WB_DI @1nS=\0H +
+ @100.001uS=81\H 101nS=Z +
+ @250.001uS=55\H 101nS=Z
+wfm BR_Clk_I @610nS=L (500nS=H 500nS=L)*1500
+
+| Perform Simulation
+sim 1500uS
+
TESTTx.CMD
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+*
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Index: TESTUART.CMD
===================================================================
--- TESTUART.CMD (nonexistent)
+++ TESTUART.CMD (revision 26)
@@ -0,0 +1,56 @@
+| Script file for testing the UART in echo mode (Txd and must be RxD tied)
+| 2 writes followed by 2 read
+
+| Initial settings
+delete_waveforms
+restart
+stepsize 50nS
+
+| Watched Signals and Vectors
+|
+| Define your signal and vector watch list here
+watch WB_CLK_I
+watch WB_RST_I
+watch WB_WE_I
+watch WB_STB_I
+watch WB_ACK_O
+vector WB_ADR ADR_I[1:0]
+vector WB_DI DAT_I[7:0]
+vector WB_DO DAT_O[7:0]
+watch RxD TEcho| RS232 Rx Line
+watch TxD | RS232 Tx Line
+watch IntTx | Byte present in buffer
+watch IntRx | Emit Buffer is empty
+watch BRClk
+watch EnabTx EnabRx
+
+| Stimulators Assignment
+| 1/Write Byte
+| 2/Write another byte
+| 3/Read Byte
+| 4/Read Byte
+clock WB_CLK_I 1 0
+wfm WB_RST_I @1nS=L 100nS=H 100nS=L
+wfm WB_STB_I @1nS=L +
+ @100.001uS=H 100nS=L +
+ @200.001uS=H 100nS=L +
+ @250.001uS=H 100nS=L +
+ @355.501uS=H 100nS=L
+wfm WB_WE_I @1nS=L +
+ @100.001uS=H +
+ @200.001uS=L +
+ @250.001uS=H +
+ @355.501uS=L
+wfm WB_ADR @1nS=L +
+ @100.001uS=0\H 100nS=Z +
+ @200.001uS=0\H 100nS=Z +
+ @250.001uS=0\H 100nS=Z +
+ @355.501uS=0\H 100nS=Z
+wfm WB_DI @1nS=\0H +
+ @100.001uS=81\H 101nS=Z +
+ @250.001uS=55\H 101nS=Z
+wfm BRClk @0nS=L (500nS=H 500nS=L)*500
+
+| Perform Simulation
+sim 400uS
+
TESTUART.CMD
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+*
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Index: TESTRx.CMD
===================================================================
--- TESTRx.CMD (nonexistent)
+++ TESTRx.CMD (revision 26)
@@ -0,0 +1,54 @@
+| Script file for testing the receiver
+| for multi frames
+
+| Initial settings
+delete_waveforms
+restart
+stepsize 50nS
+
+| Watched Signals and Vectors
+watch WB_CLK_I | Wishbone clock
+watch WB_RST_I
+watch WB_WE_I
+watch WB_STB_I
+watch WB_ACK_O
+vector ADR WB_ADR_I[1:0]
+vector DI WB_DAT_I[7:0]
+vector DO WB_DAT_O[7:0]
+watch RxD_PAD_I | RS232 Rx Line
+watch IntRx_O | Emit Buffer is empty
+watch BR_Clk_I
+watch EnabRx
+
+| Stimulators Assignment
+| 1/Read SReg
+| 2/Read Byte Rx
+| 3/Read SReg
+| 4/Read Byte Rx
+clock WB_CLK_I 1 0 | BR_CLK_I=10MHz
+wfm WB_RST_I @1nS=L 100nS=H 100nS=L
+wfm WB_STB_I @1nS=L +
+ @190.001uS=H 100nS=L +
+ @200.001uS=H 100nS=L +
+ @210.001uS=H 100nS=L +
+ @355.501uS=H 100nS=L
+wfm WB_WE_I @1nS=L +
+ @190.001uS=L +
+ @200.001uS=L +
+ @210.001uS=L +
+ @355.501uS=L
+wfm ADR @1nS=L +
+ @190.001uS=1\H 100nS=Z +
+ @200.001uS=0\H 100nS=Z +
+ @210.001uS=1\H 100nS=Z +
+ @355.501uS=0\H 100nS=Z
+
+wfm BR_Clk_I @0nS=L (1uS=H 1uS=L)*8000 | BR_Clk_I=500kHz
+| BRDIVISOR=1. Baudrate=500000/1/4=125kHz (Bit period=8uS)
+| Below is a generation of 50 same frames, coding 40h.
+wfm RxD_PAD_I @0nS=H +
+ 102.7uS=H (8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=H 8uS=L 8uS=H)*50 8uS=H
+
+| Perform Simulation
+sim 4000uS
+
TESTRx.CMD
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