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Rev 23 → Rev 26

/test.vhd
0,0 → 1,130
-------------------------------------------------------------------------------
-- Title : UART Testbench
-- Project : UART
-------------------------------------------------------------------------------
-- File : test.vhd
-- Author : Philippe CARTON
-- (philippe.carton2@libertysurf.fr)
-- Organization:
-- Created : 8/1/2003
-- Last update : 9/1/2003
-- Platform : Windows
-- Simulators : ModelSim 5.5b
-- Dependency : IEEE std_logic_1164, simu_lib
-------------------------------------------------------------------------------
-- Description :
-- test entity UART
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library simu_lib;
use simu_lib.HORLOGE;
use simu_lib.GEN_WAVE_BUS;
 
library work;
use work.all;
-------------------------------------------------------------------------------
entity TEST_MINIUART is
generic( CHEMIN : string := "test_bench3/");
end TEST_MINIUART;
-------------------------------------------------------------------------------
-- behavioural architecture type
-------------------------------------------------------------------------------
architecture ARCH_TEST_BENCH OF TEST_MINIUART is
 
-------------------------------------------------------------------------------
-- internal signals connection declaration
-------------------------------------------------------------------------------
signal ZERO : std_logic;
signal UN : std_logic;
 
signal PATT : std_logic_vector(13 downto 0);
signal VISU : std_logic_vector(11 downto 0);
 
signal CLK : std_logic; -- system clock
signal BRCLK : std_logic; -- Baudrate clock
 
-------------------------------------------------------------------------------
component HORLOGE
generic ( NOM_FICHIER_HORLOGE : string := "HORLOGE.IN" );
port ( CLOCK : out std_logic );
end component;
 
-------------------------------------------------------------------------------
component GEN_WAVE_BUS
generic ( nb_bits : integer := 4; -- bus width
NOM_FICHIER_WAVE : string := "GEN_WAVE.IN" );
port ( SIGNAL_OUT : out std_logic_vector((nb_bits-1) downto 0) );
end component;
 
-------------------------------------------------------------------------------
component UART
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130); -- Baud rate divisor
port(
-- Wishbone signals
WB_CLK_I : in std_logic; -- clock
WB_RST_I : in std_logic; -- Reset input
WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
WB_WE_I : in std_logic; -- Write Enable
WB_STB_I : in std_logic; -- Strobe
WB_ACK_O : out std_logic; -- Acknowledge
-- process signals
IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
TxD_PAD_O: out std_logic; -- Tx RS232 Line
RxD_PAD_I: in std_logic -- Rx RS232 Line
);
end component;
 
-------------------------------------------------------------------------------
-- begin body entity
-------------------------------------------------------------------------------
begin
UN <= '1';
ZERO <= '0';
 
-------------------------------------------------------------------------------
GERE_BUS : GEN_WAVE_BUS
generic map ( nb_bits => PATT'length,
NOM_FICHIER_WAVE => CHEMIN & "patt.in")
port map ( SIGNAL_OUT => PATT );
-------------------------------------------------------------------------------
HORLOGE_CLK : HORLOGE
generic map ( NOM_FICHIER_HORLOGE => CHEMIN & "clk.in")
port map ( CLOCK => CLK );
-------------------------------------------------------------------------------
HORLOGE_BRCLK : HORLOGE
generic map ( NOM_FICHIER_HORLOGE => CHEMIN & "brclk.in")
port map ( CLOCK => BRCLK );
-------------------------------------------------------------------------------
DUT : UART
generic map (BRDIVISOR => 1)
port map(
WB_CLK_I => CLK,
WB_RST_I => PATT(0),
WB_ADR_I => PATT(2 downto 1),
WB_DAT_I => PATT(10 downto 3),
WB_DAT_O => VISU(7 downto 0),
WB_WE_I => PATT(11),
WB_STB_I => PATT(12),
WB_ACK_O => VISU(8),
IntTx_O => VISU(9),
IntRx_O => VISU(10),
BR_Clk_I => BRCLK,
TxD_PAD_O => VISU(11),
RxD_PAD_I => PATT(13)
);
-------------------------------------------------------------------------------
 
end ARCH_TEST_BENCH;
 
/brclk.in
0,0 → 1,19
-----------------------------
-- file brclk.in
-----------------------------
--
-- build a baudrate at 230415bpS
-- format :
-- p -> period
-- d -> delay / start. simu. > 0
-- r -> cyclic ratio in %
-- or
-- h high state time
-- c -> cycle number (~pattern number)
----------------------
p 4.34 us
d 100 ns
r 50
c 500000
--
-- enf of file
/wave.do
0,0 → 1,26
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {WishBone signals}
add wave -noupdate -format Logic -label wb_rst_i -radix binary /test_miniuart/dut/wb_rst_i
add wave -noupdate -format Logic -label wb_clk_i -radix binary /test_miniuart/dut/wb_clk_i
add wave -noupdate -format Logic -label wb_stb_i -radix binary /test_miniuart/dut/wb_stb_i
add wave -noupdate -format Logic -label wb_ack_o -radix binary /test_miniuart/dut/wb_ack_o
add wave -noupdate -format Logic -label wb_we_i -radix binary /test_miniuart/dut/wb_we_i
add wave -noupdate -format Literal -label wb_adr_i -radix hexadecimal /test_miniuart/dut/wb_adr_i
add wave -noupdate -format Literal -label wb_dat_i -radix hexadecimal /test_miniuart/dut/wb_dat_i
add wave -noupdate -format Literal -label wb_dat_o -radix hexadecimal /test_miniuart/dut/wb_dat_o
add wave -noupdate -divider {UART signals}
add wave -noupdate -format Logic -label br_clk_i -radix binary /test_miniuart/dut/br_clk_i
add wave -noupdate -format Logic -label rxd_pad_i -radix binary /test_miniuart/dut/rxd_pad_i
add wave -noupdate -format Logic -label intrx_o -radix binary /test_miniuart/dut/intrx_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {141951 ns}
WaveRestoreZoom {0 ns} {245610 ns}
configure wave -namecolwidth 110
configure wave -valuecolwidth 40
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
/info.txt
0,0 → 1,12
This testbench will simulate a BitStream on the RxD pad. The RxUnit unserialise it and
store it in the receive register.
 
at 17.2uS, the RxD line is driven low. This is the start bit.
from 34.4uS to 139.2uS follows the others bits from 0 to 7.
at 139.2uS the RxD line is driven high. This is the stop bit.
at 173.6uS the intrx_o signal goes high. This indicates that a byte has been received by
the Rx unit.
at 190uS the status reg is read (adr 01). It contains the value 0x03. This indicates that
a char is available in the receive register (bit1 = 1).
at 200uS the receive buffer is read. It contains the value 0x32.
The baudrate is 57600bps.
/test.bak
0,0 → 1,143
--------------------------------------------------------
-- Title : UART Testbench
-- Project : UART
-------------------------------------------------------
-------------------------------------------------------
-- VHDL description (RTL level)
--
-------------------------------------------------------
-- Designed by : ISIS_MPP
-- file : Interface.vhd
-------------------------------------------------------
-- Version : A
-- Author : P.CARTON
-- date : 24 Octobre 2002
-- Description :
-------------------------------------------------------
-- Evolutions :
-- date Author Version Description
--
-------------------------------------------------------
--=====================================================
--=====================================================
--------------------------------------------------------
-- Auteur : N.PERRENOT
-- 30/09/02
-- Version A
--------------------------------------------------------
-- fichier 'test.vhd'
--------------------------------------------------------
-- Fonction :
-- test entity UART
--------------------------------------------------------
--------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
library simu_lib;
use simu_lib.HORLOGE;
use simu_lib.GEN_WAVE_BUS;
 
library work;
use work.all;
 
--------------------------------------------------------
entity TEST_MINIUART is
generic( CHEMIN : string := "test_bench3/");
end TEST_MINIUART;
----------------------------------------------------------------------
-- architecture de type comportementale
----------------------------------------------------------------------
architecture ARCH_TEST_BENCH OF TEST_MINIUART is
 
------------------------------------------
-- declaration des signaux internes de connection
------------------------------------------
signal ZERO : std_logic;
signal UN : std_logic;
 
signal PATT : std_logic_vector(13 downto 0);
signal VISU : std_logic_vector(11 downto 0);
 
signal CLK : std_logic; -- Horloge systeme
signal BRCLK : std_logic; -- Horloge Baudrate
 
------------------------------------------
component HORLOGE
generic ( NOM_FICHIER_HORLOGE : string := "HORLOGE.IN" );
port ( CLOCK : out std_logic );
end component;
 
------------------------------------------
component GEN_WAVE_BUS
generic ( nb_bits : integer := 4; -- largeur bus
NOM_FICHIER_WAVE : string := "GEN_WAVE.IN" );
port ( SIGNAL_OUT : out std_logic_vector((nb_bits-1) downto 0) );
end component;
 
------------------------------------------
component UART
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130); -- Baud rate divisor
port(
-- Wishbone signals
WB_CLK_I : in std_logic; -- clock
WB_RST_I : in std_logic; -- Reset input
WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
WB_WE_I : in std_logic; -- Write Enable
WB_STB_I : in std_logic; -- Strobe
WB_ACK_O : out std_logic; -- Acknowledge
-- process signals
IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
TxD_PAD_O: out std_logic; -- Tx RS232 Line
RxD_PAD_I: in std_logic -- Rx RS232 Line
);
end component;
 
-----------------------------------------
-- debut du corps de l'entite
------------------------------------------
begin
UN <= '1';
ZERO <= '0';
 
--------------------------------------
GERE_BUS : GEN_WAVE_BUS
generic map ( nb_bits => PATT'length,
NOM_FICHIER_WAVE => CHEMIN & "patt.in")
port map ( SIGNAL_OUT => PATT );
------------------------------------------
HORLOGE_CLK : HORLOGE
generic map ( NOM_FICHIER_HORLOGE => CHEMIN & "clk.in")
port map ( CLOCK => CLK );
------------------------------------------
HORLOGE_BRCLK : HORLOGE
generic map ( NOM_FICHIER_HORLOGE => CHEMIN & "brclk.in")
port map ( CLOCK => BRCLK );
------------------------------------------
DUT : UART
generic map (BRDIVISOR => 1)
port map(
WB_CLK_I => CLK,
WB_RST_I => PATT(0),
WB_ADR_I => PATT(2 downto 1),
WB_DAT_I => PATT(10 downto 3),
WB_DAT_O => VISU(7 downto 0),
WB_WE_I => PATT(11),
WB_STB_I => PATT(12),
WB_ACK_O => VISU(8),
IntTx_O => VISU(9),
IntRx_O => VISU(10),
BR_Clk_I => BRCLK,
TxD_PAD_O => VISU(11),
RxD_PAD_I => PATT(13)
);
 
--------------------------------------------
 
end ARCH_TEST_BENCH;
 
/patt.in
0,0 → 1,39
-----------------------------
-- file patt.IN
-----------------------------
-- clk 100 ns
--
-- time run 220 us
------------------------------------------
------------------------------------------
-- WB_RST_I => PATT(0),
-- WB_ADR_I => PATT(2 downto 1),
-- WB_DAT_I => PATT(10 downto 3),
-- WB_DAT_O => VISU(7 downto 0),
-- WB_WE_I => PATT(11),
-- WB_STB_I => PATT(12),
-- WB_ACK_O => VISU(8),
--
-- IntTx_O => VISU(9),
-- IntRx_O => VISU(10),
--
-- TxD_PAD_O => VISU(11),
-- RxD_PAD_I => PATT(13)
--
A 0 ns b_1_00_00000000_00_1 --rst async
R 17.36 us b_0_00_00000000_00_0 --start bit
R 17.36 us b_0_00_00000000_00_0 --bit 0 |
R 17.36 us b_1_00_00000000_00_0 --bit 1 |
R 17.36 us b_0_00_00000000_00_0 --bit 2 |
R 17.36 us b_0_00_00000000_00_0 --bit 3 } byte 0x32
R 17.36 us b_1_00_00000000_00_0 --bit 4 |
R 17.36 us b_1_00_00000000_00_0 --bit 5 |
R 17.36 us b_0_00_00000000_00_0 --bit 6 |
R 17.36 us b_0_00_00000000_00_0 --bit 7 |
R 17.36 us b_1_00_00000000_00_0 --stop bit
A 190 us b_1_10_00000000_01_0 --read status register
R 100 ns b_1_00_00000000_00_0 --release strobe
A 200 us b_1_10_00000000_00_0 --read Rx register
R 100 ns b_1_00_00000000_00_0 --release strobe
--
-- end file
/clk.in
0,0 → 1,19
-----------------------------
-- file clk.in
-----------------------------
--
-- build a clock signal at 10MHz
-- format :
-- p -> period
-- d -> delay / start. simu. > 0
-- r -> cyclic ratio in %
-- or
-- h high state time
-- c -> cycle number (~pattern number)
----------------------
p 100 ns
d 1 ns
r 50
c 50000000
--
-- end of file

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