URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc/branches/verilator/prj/src
- from Rev 133 to Rev 139
- ↔ Reverse comparison
Rev 133 → Rev 139
/minsoc_bench.prj
0,0 → 1,8
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog) |
PROJECT_SRC=(minsoc_bench_defines.v |
minsoc_bench.v |
minsoc_memory_model.v |
dbg_comm_vpi.v |
fpga_memory_primitives.v |
timescale.v) |
|
/ethmac.prj
0,0 → 1,27
PROJECT_DIR=rtl/verilog/ethmac/rtl/verilog |
PROJECT_SRC=(eth_cop.v |
eth_registers.v |
eth_rxethmac.v |
eth_miim.v |
ethmac.v |
eth_rxaddrcheck.v |
eth_outputcontrol.v |
eth_rxstatem.v |
eth_txethmac.v |
eth_wishbone.v |
eth_maccontrol.v |
eth_txstatem.v |
ethmac_defines.v |
eth_spram_256x32.v |
eth_shiftreg.v |
eth_clockgen.v |
eth_crc.v |
eth_rxcounters.v |
eth_macstatus.v |
eth_random.v |
eth_register.v |
eth_fifo.v |
eth_receivecontrol.v |
eth_transmitcontrol.v |
eth_txcounters.v |
xilinx_dist_ram_16x32.v) |
/blackboxes/or1200_top.v
0,0 → 1,145
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`include "or1200_defines.v" |
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module or1200_top( |
// System |
clk_i, rst_i, pic_ints_i, clmode_i, |
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// Instruction WISHBONE INTERFACE |
iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i, |
iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o, |
`ifdef OR1200_WB_CAB |
iwb_cab_o, |
`endif |
`ifdef OR1200_WB_B3 |
iwb_cti_o, iwb_bte_o, |
`endif |
// Data WISHBONE INTERFACE |
dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i, |
dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o, |
`ifdef OR1200_WB_CAB |
dwb_cab_o, |
`endif |
`ifdef OR1200_WB_B3 |
dwb_cti_o, dwb_bte_o, |
`endif |
|
// External Debug Interface |
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, |
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o, |
|
`ifdef OR1200_BIST |
// RAM BIST |
mbist_si_i, mbist_so_o, mbist_ctrl_i, |
`endif |
// Power Management |
pm_cpustall_i, |
pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, |
pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o |
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); |
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parameter dw = `OR1200_OPERAND_WIDTH; |
parameter aw = `OR1200_OPERAND_WIDTH; |
parameter ppic_ints = `OR1200_PIC_INTS; |
|
// |
// I/O |
// |
|
// |
// System |
// |
input clk_i; |
input rst_i; |
input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 |
input [ppic_ints-1:0] pic_ints_i; |
|
// |
// Instruction WISHBONE interface |
// |
input iwb_clk_i; // clock input |
input iwb_rst_i; // reset input |
input iwb_ack_i; // normal termination |
input iwb_err_i; // termination w/ error |
input iwb_rty_i; // termination w/ retry |
input [dw-1:0] iwb_dat_i; // input data bus |
output iwb_cyc_o; // cycle valid output |
output [aw-1:0] iwb_adr_o; // address bus outputs |
output iwb_stb_o; // strobe output |
output iwb_we_o; // indicates write transfer |
output [3:0] iwb_sel_o; // byte select outputs |
output [dw-1:0] iwb_dat_o; // output data bus |
`ifdef OR1200_WB_CAB |
output iwb_cab_o; // indicates consecutive address burst |
`endif |
`ifdef OR1200_WB_B3 |
output [2:0] iwb_cti_o; // cycle type identifier |
output [1:0] iwb_bte_o; // burst type extension |
`endif |
|
// |
// Data WISHBONE interface |
// |
input dwb_clk_i; // clock input |
input dwb_rst_i; // reset input |
input dwb_ack_i; // normal termination |
input dwb_err_i; // termination w/ error |
input dwb_rty_i; // termination w/ retry |
input [dw-1:0] dwb_dat_i; // input data bus |
output dwb_cyc_o; // cycle valid output |
output [aw-1:0] dwb_adr_o; // address bus outputs |
output dwb_stb_o; // strobe output |
output dwb_we_o; // indicates write transfer |
output [3:0] dwb_sel_o; // byte select outputs |
output [dw-1:0] dwb_dat_o; // output data bus |
`ifdef OR1200_WB_CAB |
output dwb_cab_o; // indicates consecutive address burst |
`endif |
`ifdef OR1200_WB_B3 |
output [2:0] dwb_cti_o; // cycle type identifier |
output [1:0] dwb_bte_o; // burst type extension |
`endif |
|
// |
// External Debug Interface |
// |
input dbg_stall_i; // External Stall Input |
input dbg_ewt_i; // External Watchpoint Trigger Input |
output [3:0] dbg_lss_o; // External Load/Store Unit Status |
output [1:0] dbg_is_o; // External Insn Fetch Status |
output [10:0] dbg_wp_o; // Watchpoints Outputs |
output dbg_bp_o; // Breakpoint Output |
input dbg_stb_i; // External Address/Data Strobe |
input dbg_we_i; // External Write Enable |
input [aw-1:0] dbg_adr_i; // External Address Input |
input [dw-1:0] dbg_dat_i; // External Data Input |
output [dw-1:0] dbg_dat_o; // External Data Output |
output dbg_ack_o; // External Data Acknowledge (not WB compatible) |
|
`ifdef OR1200_BIST |
// |
// RAM BIST |
// |
input mbist_si_i; |
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; |
output mbist_so_o; |
`endif |
|
// |
// Power Management |
// |
input pm_cpustall_i; |
output [3:0] pm_clksd_o; |
output pm_dc_gate_o; |
output pm_ic_gate_o; |
output pm_dmmu_gate_o; |
output pm_immu_gate_o; |
output pm_tt_gate_o; |
output pm_cpu_gate_o; |
output pm_wakeup_o; |
output pm_lvolt_o; |
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endmodule |
/blackboxes/ethmac.v
0,0 → 1,113
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`include "ethmac_defines.v" |
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module ethmac |
( |
// WISHBONE common |
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, |
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// WISHBONE slave |
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, |
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// WISHBONE master |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o, |
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, |
m_wb_stb_o, m_wb_ack_i, m_wb_err_i, |
|
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o, m_wb_bte_o, |
`endif |
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//TX |
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, |
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//RX |
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, |
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// MIIM |
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, |
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int_o |
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// Bist |
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
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); |
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parameter Tp = 1; |
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// WISHBONE common |
input wb_clk_i; // WISHBONE clock |
input wb_rst_i; // WISHBONE reset |
input [31:0] wb_dat_i; // WISHBONE data input |
output [31:0] wb_dat_o; // WISHBONE data output |
output wb_err_o; // WISHBONE error output |
|
// WISHBONE slave |
input [11:2] wb_adr_i; // WISHBONE address input |
input [3:0] wb_sel_i; // WISHBONE byte select input |
input wb_we_i; // WISHBONE write enable input |
input wb_cyc_i; // WISHBONE cycle input |
input wb_stb_i; // WISHBONE strobe input |
output wb_ack_o; // WISHBONE acknowledge output |
|
// WISHBONE master |
output [31:0] m_wb_adr_o; |
output [3:0] m_wb_sel_o; |
output m_wb_we_o; |
input [31:0] m_wb_dat_i; |
output [31:0] m_wb_dat_o; |
output m_wb_cyc_o; |
output m_wb_stb_o; |
input m_wb_ack_i; |
input m_wb_err_i; |
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wire [29:0] m_wb_adr_tmp; |
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`ifdef ETH_WISHBONE_B3 |
output [2:0] m_wb_cti_o; // Cycle Type Identifier |
output [1:0] m_wb_bte_o; // Burst Type Extension |
`endif |
|
// Tx |
input mtx_clk_pad_i; // Transmit clock (from PHY) |
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) |
output mtxen_pad_o; // Transmit enable (to PHY) |
output mtxerr_pad_o; // Transmit error (to PHY) |
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// Rx |
input mrx_clk_pad_i; // Receive clock (from PHY) |
input [3:0] mrxd_pad_i; // Receive nibble (from PHY) |
input mrxdv_pad_i; // Receive data valid (from PHY) |
input mrxerr_pad_i; // Receive data error (from PHY) |
|
// Common Tx and Rx |
input mcoll_pad_i; // Collision (from PHY) |
input mcrs_pad_i; // Carrier sense (from PHY) |
|
// MII Management interface |
input md_pad_i; // MII data input (from I/O cell) |
output mdc_pad_o; // MII Management data clock (to PHY) |
output md_pad_o; // MII data output (to I/O cell) |
output md_padoe_o; // MII data output enable (to I/O cell) |
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output int_o; // Interrupt output |
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// Bist |
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
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endmodule |
/blackboxes/uart_top.v
0,0 → 1,58
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`include "uart_defines.v" |
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module uart_top ( |
wb_clk_i, |
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// Wishbone signals |
wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, |
int_o, // interrupt request |
|
// UART signals |
// serial input/output |
stx_pad_o, srx_pad_i, |
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// modem signals |
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i |
`ifdef UART_HAS_BAUDRATE_OUTPUT |
, baud_o |
`endif |
); |
|
parameter uart_data_width = `UART_DATA_WIDTH; |
parameter uart_addr_width = `UART_ADDR_WIDTH; |
|
input wb_clk_i; |
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// WISHBONE interface |
input wb_rst_i; |
input [uart_addr_width-1:0] wb_adr_i; |
input [uart_data_width-1:0] wb_dat_i; |
output [uart_data_width-1:0] wb_dat_o; |
input wb_we_i; |
input wb_stb_i; |
input wb_cyc_i; |
input [3:0] wb_sel_i; |
output wb_ack_o; |
output int_o; |
|
// UART signals |
input srx_pad_i; |
output stx_pad_o; |
output rts_pad_o; |
input cts_pad_i; |
output dtr_pad_o; |
input dsr_pad_i; |
input ri_pad_i; |
input dcd_pad_i; |
|
// optional baudrate output |
`ifdef UART_HAS_BAUDRATE_OUTPUT |
output baud_o; |
`endif |
|
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endmodule |
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/blackboxes/adbg_top.v
0,0 → 1,180
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`include "adbg_defines.v" |
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module adbg_top( |
// JTAG signals |
tck_i, |
tdi_i, |
tdo_o, |
rst_i, |
|
|
// TAP states |
shift_dr_i, |
pause_dr_i, |
update_dr_i, |
capture_dr_i, |
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// Instructions |
debug_select_i |
|
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`ifdef DBG_WISHBONE_SUPPORTED |
// WISHBONE common signals |
, |
wb_clk_i, |
wb_rst_i, |
|
// WISHBONE master interface |
wb_adr_o, |
wb_dat_o, |
wb_dat_i, |
wb_cyc_o, |
wb_stb_o, |
wb_sel_o, |
wb_we_o, |
wb_ack_i, |
wb_cab_o, |
wb_err_i, |
wb_cti_o, |
wb_bte_o |
`endif |
|
`ifdef DBG_CPU0_SUPPORTED |
// CPU signals |
, |
cpu0_clk_i, |
cpu0_addr_o, |
cpu0_data_i, |
cpu0_data_o, |
cpu0_bp_i, |
cpu0_stall_o, |
cpu0_stb_o, |
cpu0_we_o, |
cpu0_ack_i, |
cpu0_rst_o |
`endif |
|
`ifdef DBG_CPU1_SUPPORTED |
// CPU signals |
, |
cpu1_clk_i, |
cpu1_addr_o, |
cpu1_data_i, |
cpu1_data_o, |
cpu1_bp_i, |
cpu1_stall_o, |
cpu1_stb_o, |
cpu1_we_o, |
cpu1_ack_i, |
cpu1_rst_o |
`endif |
|
`ifdef DBG_JSP_SUPPORTED |
, |
`ifndef DBG_WISHBONE_SUPPORTED |
wb_clk_i, |
wb_rst_i, |
`endif |
|
// WISHBONE target interface |
wb_jsp_adr_i, |
wb_jsp_dat_o, |
wb_jsp_dat_i, |
wb_jsp_cyc_i, |
wb_jsp_stb_i, |
wb_jsp_sel_i, |
wb_jsp_we_i, |
wb_jsp_ack_o, |
wb_jsp_cab_i, |
wb_jsp_err_o, |
wb_jsp_cti_i, |
wb_jsp_bte_i, |
int_o |
`endif |
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); |
|
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// JTAG signals |
input tck_i; |
input tdi_i; |
output tdo_o; |
input rst_i; |
|
// TAP states |
input shift_dr_i; |
input pause_dr_i; |
input update_dr_i; |
input capture_dr_i; |
|
// Module select from TAP |
input debug_select_i; |
|
`ifdef DBG_WISHBONE_SUPPORTED |
input wb_clk_i; |
input wb_rst_i; |
output [31:0] wb_adr_o; |
output [31:0] wb_dat_o; |
input [31:0] wb_dat_i; |
output wb_cyc_o; |
output wb_stb_o; |
output [3:0] wb_sel_o; |
output wb_we_o; |
input wb_ack_i; |
output wb_cab_o; |
input wb_err_i; |
output [2:0] wb_cti_o; |
output [1:0] wb_bte_o; |
`endif |
|
`ifdef DBG_CPU0_SUPPORTED |
// CPU signals |
input cpu0_clk_i; |
output [31:0] cpu0_addr_o; |
input [31:0] cpu0_data_i; |
output [31:0] cpu0_data_o; |
input cpu0_bp_i; |
output cpu0_stall_o; |
output cpu0_stb_o; |
output cpu0_we_o; |
input cpu0_ack_i; |
output cpu0_rst_o; |
`endif |
|
`ifdef DBG_CPU1_SUPPORTED |
input cpu1_clk_i; |
output [31:0] cpu1_addr_o; |
input [31:0] cpu1_data_i; |
output [31:0] cpu1_data_o; |
input cpu1_bp_i; |
output cpu1_stall_o; |
output cpu1_stb_o; |
output cpu1_we_o; |
input cpu1_ack_i; |
output cpu1_rst_o; |
`endif |
|
`ifdef DBG_JSP_SUPPORTED |
`ifndef DBG_WISHBONE_SUPPORTED |
input wb_clk_i; |
input wb_rst_i; |
`endif |
input [31:0] wb_jsp_adr_i; |
output [31:0] wb_jsp_dat_o; |
input [31:0] wb_jsp_dat_i; |
input wb_jsp_cyc_i; |
input wb_jsp_stb_i; |
input [3:0] wb_jsp_sel_i; |
input wb_jsp_we_i; |
output wb_jsp_ack_o; |
input wb_jsp_cab_i; |
output wb_jsp_err_o; |
input [2:0] wb_jsp_cti_i; |
input [1:0] wb_jsp_bte_i; |
output int_o; |
`endif |
|
|
endmodule |
/or1200_top.prj
0,0 → 1,60
PROJECT_DIR=rtl/verilog/or1200/rtl/verilog |
PROJECT_SRC=(or1200_spram_512x20.v |
or1200_spram_64x24.v |
or1200_du.v |
or1200_spram_2048x32_bw.v |
or1200_rf.v |
or1200_alu.v |
or1200_dmmu_top.v |
or1200_lsu.v |
or1200_spram_1024x32.v |
or1200_dc_top.v |
or1200_cpu.v |
or1200_gmultp2_32x32.v |
or1200_immu_top.v |
or1200_dpram_256x32.v |
or1200_tt.v |
or1200_iwb_biu.v |
or1200_rfram_generic.v |
or1200_dc_tag.v |
or1200_spram_2048x8.v |
or1200_immu_tlb.v |
or1200_ic_tag.v |
or1200_spram_64x14.v |
or1200_spram_32x24.v |
or1200_dpram_32x32.v |
or1200_xcv_ram32x8d.v |
or1200_spram_1024x8.v |
or1200_mem2reg.v |
or1200_pm.v |
or1200_spram_256x21.v |
or1200_operandmuxes.v |
or1200_pic.v |
or1200_cfgr.v |
or1200_if.v |
or1200_qmem_top.v |
or1200_genpc.v |
or1200_defines.v |
or1200_wbmux.v |
or1200_ic_ram.v |
or1200_dmmu_tlb.v |
or1200_sb_fifo.v |
or1200_sprs.v |
or1200_tpram_32x32.v |
or1200_ctrl.v |
or1200_sb.v |
or1200_mult_mac.v |
or1200_ic_fsm.v |
or1200_amultp2_32x32.v |
or1200_reg2mem.v |
or1200_spram_2048x32.v |
or1200_except.v |
or1200_top.v |
or1200_ic_top.v |
or1200_dc_ram.v |
or1200_spram_1024x32_bw.v |
or1200_freeze.v |
or1200_spram_128x32.v |
or1200_dc_fsm.v |
or1200_wb_biu.v |
or1200_spram_64x22.v) |
/altera_virtual_jtag.prj
0,0 → 1,2
PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/ |
PROJECT_SRC=altera_virtual_jtag.vhd |
/minsoc_top.prj
0,0 → 1,17
PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog) |
PROJECT_SRC=(minsoc_defines.v |
timescale.v |
minsoc_top.v |
minsoc_tc_top.v |
minsoc_onchip_ram.v |
minsoc_onchip_ram_top.v |
minsoc_clock_manager.v |
altera_pll.v |
xilinx_dcm.v |
minsoc_xilinx_internal_jtag.v |
spi_top.v |
spi_defines.v |
spi_shift.v |
spi_clgen.v |
OR1K_startup_generic.v) |
|
/jtag_top.prj
0,0 → 1,3
PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog |
PROJECT_SRC=(tap_top.v |
tap_defines.v) |
/uart_top.prj
0,0 → 1,12
PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog |
PROJECT_SRC=(uart_top.v |
uart_sync_flops.v |
uart_transmitter.v |
uart_debug_if.v |
uart_wb.v |
uart_receiver.v |
uart_tfifo.v |
uart_regs.v |
uart_rfifo.v |
uart_defines.v |
raminfr.v) |
/adbg_top.prj
0,0 → 1,11
PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog |
PROJECT_SRC=(adbg_wb_biu.v |
adbg_wb_module.v |
adbg_or1k_module.v |
adbg_wb_defines.v |
adbg_defines.v |
adbg_crc32.v |
adbg_or1k_biu.v |
adbg_or1k_defines.v |
adbg_or1k_status_reg.v |
adbg_top.v) |