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/minsoc/trunk/bench/verilog/vpi
- from Rev 4 to Rev 71
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Rev 4 → Rev 71
/dbg_comm_vpi.v
74,6 → 74,7
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`include "timescale.v" |
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`define JP_PORT "4567" |
`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits. |