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  • This comparison shows the changes necessary to convert path 
    /mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks
    from Rev 2 to Rev 12
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Rev 2 → Rev 12

/PLL_100MHz_to_33MHz_66MHz.v
0,0 → 1,90
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.1
// \ \ Application : xaw2verilog
// / / Filename : PLL_100MHz_to_33MHz_66MHz.v
// /___/ /\ Timestamp : 11/18/2012 13:35:59
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st C:\root\Work\Gauss\delclk\ipcore_dir\.\PLL_100MHz_to_33MHz_66MHz.xaw C:\root\Work\Gauss\delclk\ipcore_dir\.\PLL_100MHz_to_33MHz_66MHz
//Design Name: PLL_100MHz_to_33MHz_66MHz
//Device: xc5vlx110t-1ff1136
//
// Module PLL_100MHz_to_33MHz_66MHz
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.186 ns
// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT1 = 0.162 ns
`timescale 1ns / 1ps
 
module PLL_100MHz_to_33MHz_66MHz(CLKIN1_IN,
RST_IN,
CLKOUT0_OUT,
CLKOUT1_OUT,
LOCKED_OUT);
 
input CLKIN1_IN;
input RST_IN;
output CLKOUT0_OUT;
output CLKOUT1_OUT;
output LOCKED_OUT;
wire CLKFBOUT_CLKFBIN;
wire CLKIN1_IBUFG;
wire CLKOUT0_BUF;
wire CLKOUT1_BUF;
wire GND_BIT;
wire [4:0] GND_BUS_5;
wire [15:0] GND_BUS_16;
wire VCC_BIT;
assign GND_BIT = 0;
assign GND_BUS_5 = 5'b00000;
assign GND_BUS_16 = 16'b0000000000000000;
assign VCC_BIT = 1;
IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN),
.O(CLKIN1_IBUFG));
BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF),
.O(CLKOUT0_OUT));
BUFG CLKOUT1_BUFG_INST (.I(CLKOUT1_BUF),
.O(CLKOUT1_OUT));
PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(10.000),
.CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(12), .CLKOUT1_DIVIDE(6),
.CLKOUT0_PHASE(0.000), .CLKOUT1_PHASE(0.000),
.CLKOUT0_DUTY_CYCLE(0.500), .CLKOUT1_DUTY_CYCLE(0.500),
.COMPENSATION("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE(1),
.CLKFBOUT_MULT(4), .CLKFBOUT_PHASE(0.0), .REF_JITTER(0.005000) )
PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN),
.CLKINSEL(VCC_BIT),
.CLKIN1(CLKIN1_IBUFG),
.CLKIN2(GND_BIT),
.DADDR(GND_BUS_5[4:0]),
.DCLK(GND_BIT),
.DEN(GND_BIT),
.DI(GND_BUS_16[15:0]),
.DWE(GND_BIT),
.REL(GND_BIT),
.RST(RST_IN),
.CLKFBDCM(),
.CLKFBOUT(CLKFBOUT_CLKFBIN),
.CLKOUTDCM0(),
.CLKOUTDCM1(),
.CLKOUTDCM2(),
.CLKOUTDCM3(),
.CLKOUTDCM4(),
.CLKOUTDCM5(),
.CLKOUT0(CLKOUT0_BUF),
.CLKOUT1(CLKOUT1_BUF),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.DO(),
.DRDY(),
.LOCKED(LOCKED_OUT));
endmodule
PLL_100MHz_to_33MHz_66MHz.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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