OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mips789/branches/avendor/synplify_prj/mips_core
    from Rev 10 to Rev 51
    ↔ Reverse comparison
  •

Rev 10 → Rev 51

/syntmp/mips_core_cons_ui.tcl
0,0 → 1,5
source "C:/Program Files/Synplicity/fpga_81/lib/altera/quartus_cons.tcl"
syn_create_and_open_prj mips_core
source $::quartus(binpath)/prj_asd_import.tcl
syn_create_and_open_csf mips_core
syn_handle_cons mips_core
/syntmp/mips_core.plg
0,0 → 1,16
@P: Part : EP1C6QC240-6
@P: Worst Slack : -1.920
@P: mips_core|clk - Estimated Frequency : 78.1 MHz
@P: mips_core|clk - Requested Frequency : 91.9 MHz
@P: mips_core|clk - Estimated Period : 12.802
@P: mips_core|clk - Requested Period : 10.881
@P: mips_core|clk - Slack : -1.920
@P: System - Estimated Frequency : 837.8 MHz
@P: System - Requested Frequency : 985.6 MHz
@P: System - Estimated Period : 1.194
@P: System - Requested Period : 1.015
@P: System - Slack : -0.179
@P: mips_core Part : ep1c6qc240-6
@P: mips_core I/O ATOMs : 300
@P: mips_core Total LUTs: : 2992 of 5980 (50%)
@P: mips_core Logic resources : 3054 ATOMs of 5980 (51%)
/syntmp/fsm_tmp_cons_ui.tcl
0,0 → 1,5
source "C:/Program Files/Synplicity/fpga_81/lib/altera/quartus_cons.tcl"
syn_create_and_open_prj mips_core
source $::quartus(binpath)/prj_asd_import.tcl
syn_create_and_open_csf mips_core
syn_handle_cons mips_core
/syntmp/mips_core.msg --- syntmp/mips_core_flink.htm (nonexistent) +++ syntmp/mips_core_flink.htm (revision 51) @@ -0,0 +1,9 @@ + + +
+ + +Log File Links:
+Session Log
+
mips_core
+
mips_core\par_1
/syntmp/mips_core_toc.htm
0,0 → 1,22
<table border="0" cellpadding="0" cellspacing="2">
<tr>
<td nowrap width="500" class="content" valign="top">
<body bgcolor="rgb(245,245,255)">
<font size=2 face="arial">
<dl>
<font size=3><a><b>mips_core (mips_core)</a></b><br><br></font>
<b><dt><a href="mips_core_srr.htm#compilerReport18" target="srrFrame">Compiler Report</a></dt></b><br>
<b><dt><a href="mips_core_srr.htm#mapperReport19" target="srrFrame">Mapper Report</a></dt></b><br>
<b><dt><a href="mips_core_srr.htm#timingReport20" target="srrFrame">Timing Report</a></dt></b><br>
<dt><a href="mips_core_srr.htm#performanceSummary21" target="srrFrame">Performance Summary</a></dt><br>
<dt><a href="mips_core_srr.htm#clockRelationships22" target="srrFrame">Clock Relationships</a></dt><br>
<dt><a href="mips_core_srr.htm#interfaceInfo23" target="srrFrame">Interface Information</a></dt><br>
<dt><a href="mips_core_srr.htm#clockReport24" target="srrFrame">Detailed Report for Clock: mips_core|clk</a></dt><br>
<dd><a href="mips_core_srr.htm#startingSlack25" target="srrFrame">Starting Points with Worst Slack</a></dd><br>
<dd><a href="mips_core_srr.htm#endingSlack26" target="srrFrame">Ending Points with Worst Slack</a></dd><br>
<dd><a href="mips_core_srr.htm#worstPaths27" target="srrFrame">Worst Path Information</a></dd><br>
<dt><a href="mips_core_srr.htm#clockReport28" target="srrFrame">Detailed Report for Clock: System</a></dt><br>
<dd><a href="mips_core_srr.htm#startingSlack29" target="srrFrame">Starting Points with Worst Slack</a></dd><br>
<dd><a href="mips_core_srr.htm#endingSlack30" target="srrFrame">Ending Points with Worst Slack</a></dd><br>
<dd><a href="mips_core_srr.htm#worstPaths31" target="srrFrame">Worst Path Information</a></dd><br>
<b><dt><a href="mips_core_srr.htm#areaReport32" target="srrFrame">Resource Utilization</a></dt></b><br>
/syntmp/mips_core_srr.htm
0,0 → 1,10032
<html>
<body><samp><pre>
<!@TC:1190195874>
#Program: Synplify Pro 8.1
#OS: Windows_NT
 
<a name=compilerReport18>$ Start of Compile
#Wed Sep 19 17:53:25 2007
 
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
 
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"
@I::"F:\a\rtl\verilog\ctl_fsm.v"
@I:"F:\a\rtl\verilog\ctl_fsm.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:43:58:56:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190195874> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:57:58:66:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190195874> | Read full_case directive
<font color=#A52A2A>@W:<a href="@W:CG286:@XP_HELP">CG286</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CG286:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190195874> | Case statement has both a full_case directive and a default clause. The full_case directive is ignored.</font>
@I::"F:\a\rtl\verilog\decode_pipe.v"
@I:"F:\a\rtl\verilog\decode_pipe.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:31:34:31:47:@N::@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:34:45:34:58:@N::@XP_MSG">decode_pipe.v(34)</a><!@TM:1190195874> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:533:47:533:60:@N::@XP_MSG">decode_pipe.v(533)</a><!@TM:1190195874> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:835:49:835:62:@N::@XP_MSG">decode_pipe.v(835)</a><!@TM:1190195874> | Read parallel_case directive
@I::"F:\a\rtl\verilog\dvc.v"
@I:"F:\a\rtl\verilog\dvc.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\EXEC_stage.v"
@I:"F:\a\rtl\verilog\EXEC_stage.v":"F:\a\rtl\verilog\include.h"
@I:"F:\a\rtl\verilog\EXEC_stage.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:694:80:694:93:@N::@XP_MSG">exec_stage.v(694)</a><!@TM:1190195874> | Read parallel_case directive
@I::"F:\a\rtl\verilog\fifo.v"
@I:"F:\a\rtl\verilog\fifo.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\forward.v"
@I:"F:\a\rtl\verilog\forward.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mem_module.v"
@I:"F:\a\rtl\verilog\mem_module.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_core.v"
@I:"F:\a\rtl\verilog\mips_core.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_dvc.v"
@I:"F:\a\rtl\verilog\mips_dvc.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_sys.v"
@I:"F:\a\rtl\verilog\mips_sys.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_uart.v"
@I:"F:\a\rtl\verilog\mips_uart.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\ram_module.v"
@I:"F:\a\rtl\verilog\ram_module.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\RF_components.v"
@I:"F:\a\rtl\verilog\RF_components.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\RF_stage.v"
@I:"F:\a\rtl\verilog\RF_stage.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\sim_ram.v"
@I::"F:\a\rtl\verilog\tools.v"
@I:"F:\a\rtl\verilog\tools.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\fifo512_cyclone.v"
@N: : <a href="f:\a\rtl\verilog\fifo512_cyclone.v:39:12:39:25:@N::@XP_MSG">fifo512_cyclone.v(39)</a><!@TM:1190195874> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\fifo512_cyclone.v:41:12:41:24:@N::@XP_MSG">fifo512_cyclone.v(41)</a><!@TM:1190195874> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\fifo512_cyclone.v:74:16:74:29:@N::@XP_MSG">fifo512_cyclone.v(74)</a><!@TM:1190195874> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\fifo512_cyclone.v:81:16:81:28:@N::@XP_MSG">fifo512_cyclone.v(81)</a><!@TM:1190195874> | Read directive translate_on
Verilog syntax check successful!
 
Compiler output is up to date. No re-compile necessary
 
Selecting top level module mips_core
@N: : <a href="f:\a\rtl\verilog\mem_module.v:78:7:78:26:@N::@XP_MSG">mem_module.v(78)</a><!@TM:1190195874> | Synthesizing module infile_dmem_ctl_reg
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <30> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <29> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <28> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <27> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <26> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <25> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <24> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <23> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <22> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <21> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <20> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <19> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <18> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <17> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <16> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <15> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <14> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <13> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <12> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <11> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <10> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <9> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <8> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <7> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <6> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <5> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <4> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <3> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190195874> | Input port bit <2> of dmem_addr_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\mem_module.v:96:7:96:19:@N::@XP_MSG">mem_module.v(96)</a><!@TM:1190195874> | Synthesizing module mem_addr_ctl
 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\mem_module.v:102:4:102:8:@W:CL118:@XP_MSG">mem_module.v(102)</a><!@TM:1190195874> | Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <31> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <30> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <29> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <28> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <27> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <26> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <25> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <24> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <23> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <22> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <21> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <20> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <19> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <18> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <17> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <16> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <15> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <14> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <13> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <12> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <11> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <10> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <9> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <8> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <7> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <6> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <5> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <4> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <3> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190195874> | Input port bit <2> of addr_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\mem_module.v:199:7:199:18:@N::@XP_MSG">mem_module.v(199)</a><!@TM:1190195874> | Synthesizing module mem_din_ctl
 
@N: : <a href="f:\a\rtl\verilog\mem_module.v:130:7:130:19:@N::@XP_MSG">mem_module.v(130)</a><!@TM:1190195874> | Synthesizing module mem_dout_ctl
 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\mem_module.v:161:4:161:8:@W:CL118:@XP_MSG">mem_module.v(161)</a><!@TM:1190195874> | Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt</font>
@N: : <a href="f:\a\rtl\verilog\mem_module.v:4:7:4:17:@N::@XP_MSG">mem_module.v(4)</a><!@TM:1190195874> | Synthesizing module mem_module
 
@N: : <a href="f:\a\rtl\verilog\tools.v:3:7:3:14:@N::@XP_MSG">tools.v(3)</a><!@TM:1190195874> | Synthesizing module cal_cpi
 
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:2:7:2:14:@N::@XP_MSG">ctl_fsm.v(2)</a><!@TM:1190195874> | Synthesizing module ctl_FSM
 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190195874> | Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL113:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190195874> | Feedback mux created for signal iack.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190195874> | Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190195874> | Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:224:4:224:10:@N:CL201:@XP_MSG">ctl_fsm.v(224)</a><!@TM:1190195874> | Trying to extract state machine for register CurrState_Sreg0
Extracted state machine for register CurrState_Sreg0
State machine has 9 reachable states with original encodings of:
0000
0001
0010
0011
0100
0101
0110
0111
1000
@N: : <a href="f:\a\rtl\verilog\rf_components.v:50:7:50:13:@N::@XP_MSG">rf_components.v(50)</a><!@TM:1190195874> | Synthesizing module pc_gen
 
@N: : <a href="f:\a\rtl\verilog\rf_components.v:30:7:30:14:@N::@XP_MSG">rf_components.v(30)</a><!@TM:1190195874> | Synthesizing module compare
 
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="f:\a\rtl\verilog\rf_components.v:36:14:36:17:@W:CG133:@XP_MSG">rf_components.v(36)</a><!@TM:1190195874> | No assignment to sum</font>
@N: : <a href="f:\a\rtl\verilog\rf_components.v:2:7:2:10:@N::@XP_MSG">rf_components.v(2)</a><!@TM:1190195874> | Synthesizing module ext
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190195874> | Input port bit <31> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190195874> | Input port bit <30> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190195874> | Input port bit <29> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190195874> | Input port bit <28> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190195874> | Input port bit <27> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190195874> | Input port bit <26> of ins_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\tools.v:104:7:104:22:@N::@XP_MSG">tools.v(104)</a><!@TM:1190195874> | Synthesizing module r32_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:104:167:104:172:@N:CG179:@XP_MSG">tools.v(104)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:30:7:30:11:@N::@XP_MSG">tools.v(30)</a><!@TM:1190195874> | Synthesizing module jack
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <31> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <30> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <29> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <28> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <27> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <26> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <10> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <9> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <8> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <7> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <6> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <5> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <4> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <3> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <2> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <1> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190195874> | Input port bit <0> of ins_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\tools.v:64:7:64:13:@N::@XP_MSG">tools.v(64)</a><!@TM:1190195874> | Synthesizing module rd_sel
 
@N: : <a href="f:\a\rtl\verilog\rf_components.v:90:7:90:16:@N::@XP_MSG">rf_components.v(90)</a><!@TM:1190195874> | Synthesizing module reg_array
 
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="f:\a\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1190195874> | Found RAM reg_bank, depth=32, width=32
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="f:\a\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1190195874> | Found RAM reg_bank, depth=32, width=32
@N: : <a href="f:\a\rtl\verilog\forward.v:25:7:25:14:@N::@XP_MSG">forward.v(25)</a><!@TM:1190195874> | Synthesizing module fwd_mux
 
@N: : <a href="f:\a\rtl\verilog\rf_stage.v:3:7:3:15:@N::@XP_MSG">rf_stage.v(3)</a><!@TM:1190195874> | Synthesizing module rf_stage
 
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\rf_stage.v:91:24:91:30:@W:CS149:@XP_MSG">rf_stage.v(91)</a><!@TM:1190195874> | Port width mismatch for port ins_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\rf_stage.v:90:24:90:30:@W:CS149:@XP_MSG">rf_stage.v(90)</a><!@TM:1190195874> | Port width mismatch for port clk_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="f:\a\rtl\verilog\rf_stage.v:87:12:87:19:@W:CL168:@XP_MSG">rf_stage.v(87)</a><!@TM:1190195874> | Pruning instance CAL_CPI - not in use ...</font>
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:521:7:521:16:@N::@XP_MSG">exec_stage.v(521)</a><!@TM:1190195874> | Synthesizing module muldiv_ff
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190195874> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2 </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190195874> | Pruning Register START_SECTION.over[32:0] </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190195874> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190195874> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqz </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190195874> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64 </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190195874> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2 </font>
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:233:7:233:10:@N::@XP_MSG">exec_stage.v(233)</a><!@TM:1190195874> | Synthesizing module alu
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:238:16:238:17:@W::@XP_MSG">exec_stage.v(238)</a><!@TM:1190195874> | No assignment to wire c</font>
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:266:4:266:15:@N::@XP_MSG">exec_stage.v(266)</a><!@TM:1190195874> | Synthesizing module shifter_tak
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <31> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <30> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <29> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <28> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <27> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <26> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <25> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <24> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <23> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <22> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <21> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <20> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <19> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <18> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <17> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <16> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <15> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <14> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <13> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <12> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <11> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <10> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <9> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <8> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <7> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <6> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190195874> | Input port bit <5> of shift_amount[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:138:7:138:14:@N::@XP_MSG">exec_stage.v(138)</a><!@TM:1190195874> | Synthesizing module big_alu
 
@N: : <a href="f:\a\rtl\verilog\tools.v:22:7:22:12:@N::@XP_MSG">tools.v(22)</a><!@TM:1190195874> | Synthesizing module add32
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:188:7:188:15:@N::@XP_MSG">exec_stage.v(188)</a><!@TM:1190195874> | Synthesizing module alu_muxa
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:212:7:212:15:@N::@XP_MSG">exec_stage.v(212)</a><!@TM:1190195874> | Synthesizing module alu_muxb
 
@N: : <a href="f:\a\rtl\verilog\tools.v:150:7:150:14:@N::@XP_MSG">tools.v(150)</a><!@TM:1190195874> | Synthesizing module r32_reg
 
@N: : <a href="f:\a\rtl\verilog\tools.v:173:7:173:18:@N::@XP_MSG">tools.v(173)</a><!@TM:1190195874> | Synthesizing module r32_reg_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:173:132:173:137:@N:CG179:@XP_MSG">tools.v(173)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:3:7:3:17:@N::@XP_MSG">exec_stage.v(3)</a><!@TM:1190195874> | Synthesizing module exec_stage
 
@N: : <a href="f:\a\rtl\verilog\tools.v:54:7:54:11:@N::@XP_MSG">tools.v(54)</a><!@TM:1190195874> | Synthesizing module or32
 
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:2:7:2:14:@N::@XP_MSG">decode_pipe.v(2)</a><!@TM:1190195874> | Synthesizing module decoder
 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <15> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <14> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <13> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <12> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <11> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <10> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <9> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <8> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <7> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190195874> | Input port bit <6> of ins_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\tools.v:90:7:90:27:@N::@XP_MSG">tools.v(90)</a><!@TM:1190195874> | Synthesizing module muxb_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:90:202:90:212:@N:CG179:@XP_MSG">tools.v(90)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:94:7:94:29:@N::@XP_MSG">tools.v(94)</a><!@TM:1190195874> | Synthesizing module wb_mux_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:94:216:94:228:@N:CG179:@XP_MSG">tools.v(94)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:95:7:95:24:@N::@XP_MSG">tools.v(95)</a><!@TM:1190195874> | Synthesizing module wb_we_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:95:181:95:188:@N:CG179:@XP_MSG">tools.v(95)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:141:7:141:16:@N::@XP_MSG">tools.v(141)</a><!@TM:1190195874> | Synthesizing module wb_we_reg
 
@N: : <a href="f:\a\rtl\verilog\tools.v:117:7:117:25:@N::@XP_MSG">tools.v(117)</a><!@TM:1190195874> | Synthesizing module wb_mux_ctl_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:113:7:113:23:@N::@XP_MSG">tools.v(113)</a><!@TM:1190195874> | Synthesizing module muxb_ctl_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:116:7:116:23:@N::@XP_MSG">tools.v(116)</a><!@TM:1190195874> | Synthesizing module dmem_ctl_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:114:7:114:23:@N::@XP_MSG">tools.v(114)</a><!@TM:1190195874> | Synthesizing module alu_func_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:112:7:112:23:@N::@XP_MSG">tools.v(112)</a><!@TM:1190195874> | Synthesizing module muxa_ctl_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:140:7:140:21:@N::@XP_MSG">tools.v(140)</a><!@TM:1190195874> | Synthesizing module wb_mux_ctl_reg
 
@N: : <a href="f:\a\rtl\verilog\tools.v:118:7:118:20:@N::@XP_MSG">tools.v(118)</a><!@TM:1190195874> | Synthesizing module wb_we_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:86:7:86:26:@N::@XP_MSG">tools.v(86)</a><!@TM:1190195874> | Synthesizing module cmp_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:86:195:86:204:@N:CG179:@XP_MSG">tools.v(86)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:115:7:115:21:@N::@XP_MSG">tools.v(115)</a><!@TM:1190195874> | Synthesizing module alu_we_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:91:7:91:27:@N::@XP_MSG">tools.v(91)</a><!@TM:1190195874> | Synthesizing module alu_func_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:91:202:91:212:@N:CG179:@XP_MSG">tools.v(91)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:93:7:93:27:@N::@XP_MSG">tools.v(93)</a><!@TM:1190195874> | Synthesizing module dmem_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:93:202:93:212:@N:CG179:@XP_MSG">tools.v(93)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:84:7:84:26:@N::@XP_MSG">tools.v(84)</a><!@TM:1190195874> | Synthesizing module ext_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:84:195:84:204:@N:CG179:@XP_MSG">tools.v(84)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:85:7:85:25:@N::@XP_MSG">tools.v(85)</a><!@TM:1190195874> | Synthesizing module rd_sel_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:85:188:85:196:@N:CG179:@XP_MSG">tools.v(85)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:92:7:92:25:@N::@XP_MSG">tools.v(92)</a><!@TM:1190195874> | Synthesizing module alu_we_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:92:188:92:196:@N:CG179:@XP_MSG">tools.v(92)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:89:7:89:27:@N::@XP_MSG">tools.v(89)</a><!@TM:1190195874> | Synthesizing module muxa_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:89:202:89:212:@N:CG179:@XP_MSG">tools.v(89)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:87:7:87:29:@N::@XP_MSG">tools.v(87)</a><!@TM:1190195874> | Synthesizing module pc_gen_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:87:216:87:228:@N:CG179:@XP_MSG">tools.v(87)</a><!@TM:1190195874> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:139:7:139:19:@N::@XP_MSG">tools.v(139)</a><!@TM:1190195874> | Synthesizing module dmem_ctl_reg
 
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:1090:7:1090:20:@N::@XP_MSG">decode_pipe.v(1090)</a><!@TM:1190195874> | Synthesizing module pipelinedregs
 
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:1419:7:1419:18:@N::@XP_MSG">decode_pipe.v(1419)</a><!@TM:1190195874> | Synthesizing module decode_pipe
 
@N: : <a href="f:\a\rtl\verilog\forward.v:12:7:12:19:@N::@XP_MSG">forward.v(12)</a><!@TM:1190195874> | Synthesizing module forward_node
 
@N: : <a href="f:\a\rtl\verilog\forward.v:4:7:4:16:@N::@XP_MSG">forward.v(4)</a><!@TM:1190195874> | Synthesizing module fw_latch5
 
@N: : <a href="f:\a\rtl\verilog\forward.v:41:7:41:14:@N::@XP_MSG">forward.v(41)</a><!@TM:1190195874> | Synthesizing module forward
 
@N: : <a href="f:\a\rtl\verilog\tools.v:149:7:149:13:@N::@XP_MSG">tools.v(149)</a><!@TM:1190195874> | Synthesizing module r5_reg
 
@N: : <a href="f:\a\rtl\verilog\tools.v:43:7:43:13:@N::@XP_MSG">tools.v(43)</a><!@TM:1190195874> | Synthesizing module wb_mux
 
@N: : <a href="f:\a\rtl\verilog\mips_core.v:3:7:3:16:@N::@XP_MSG">mips_core.v(3)</a><!@TM:1190195874> | Synthesizing module mips_core
 
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Sep 19 17:53:27 2007
 
###########################################################[
Version 8.1
<a name=mapperReport19>Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May 6 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
 
 
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_din_ctl(mem_din_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_addr_ctl(mem_addr_ctl)
Automatic dissolve at startup in view:work.mem_module(verilog) of dmem_ctl_post(infile_dmem_ctl_reg)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rs_fwd_rs(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of rf_fwd_rt(fwd_mux)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack2(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of jack1(jack)
Automatic dissolve at startup in view:work.rf_stage(verilog) of ins_reg(r32_reg_clr_cls)
Automatic dissolve at startup in view:work.rf_stage(verilog) of i_pc_gen(pc_gen)
Automatic dissolve at startup in view:work.exec_stage(verilog) of spc(r32_reg_cls)
Automatic dissolve at startup in view:work.exec_stage(verilog) of pc_nxt(r32_reg)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxb(alu_muxb)
Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxa(alu_muxa)
Automatic dissolve at startup in view:work.exec_stage(verilog) of dmem_fw_mux(fwd_mux)
Automatic dissolve at startup in view:work.exec_stage(verilog) of add4(add32)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U9(dmem_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U8(pc_gen_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U7(muxa_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U6(alu_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U5(rd_sel_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U4(ext_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U3(dmem_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U26(alu_func_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U24(alu_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U22(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U21(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U20(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U2(cmp_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U19(wb_we_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U18(wb_mux_ctl_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U17(muxa_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U16(alu_func_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U15(dmem_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U14(muxb_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U13(wb_mux_ctl_reg_clr)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U12(wb_we_reg)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U11(wb_we_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U10(wb_mux_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U1(muxb_ctl_reg_clr_cls)
Automatic dissolve at startup in view:work.decode_pipe(verilog) of pipereg(pipelinedregs)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rnt(fw_latch5)
Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rns(fw_latch5)
Automatic dissolve at startup in view:work.mips_core(verilog) of wb_mux(wb_mux)
Automatic dissolve at startup in view:work.mips_core(verilog) of rt_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rs_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass2(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass1(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass0(r5_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of pc(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of ext_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_dout_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_reg(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_or(or32)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass1(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass0(r32_reg)
Automatic dissolve at startup in view:work.mips_core(verilog) of iexec_stage(exec_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of iRF_stage(rf_stage)
Automatic dissolve at startup in view:work.mips_core(verilog) of MEM_CTL(mem_module)
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_1[0]</font>
4) instance work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_1[1]</font>
5) instance work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_1[2]</font>
6) instance work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_1[0]</font>
7) instance work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_1[1]</font>
8) instance work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_1[0]</font>
9) instance work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_1[1]</font>
10) instance work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_1[2]</font>
11) instance work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_1[0]</font>
12) instance work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_1[1]</font>
13) instance work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_1[2]</font>
14) instance work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_1[0]</font>
15) instance work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_1[1]</font>
16) instance work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_1[0]</font>
17) instance work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_1[1]</font>
18) instance work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_1[0]</font>
19) instance work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_1[1]</font>
20) instance work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_1[2]</font>
21) instance work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_1[3]</font>
22) instance work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_1[4]</font>
23) instance work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_1[0]</font>
24) instance work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_1[1]</font>
25) instance work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_1[2]</font>
26) instance work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_1[3]</font>
27) instance work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_we[0]</font>
28) instance work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_mux[0]</font>
29) instance work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_we[0]</font>
30) instance work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
@N:<a href="@N:MT204:@XP_HELP">MT204</a> : <!@TM:1190195874> | Autoconstrain Mode is ON
RTL optimization done.
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net fsm_dly_1[0]</font>
1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net fsm_dly_1[1]</font>
2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net fsm_dly_1[2]</font>
3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)
input nets to instance:
net "fsm_dly_2[1]" in work.decoder(verilog)
net "fsm_dly_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_mux_1[0]</font>
4) instance work.decoder(verilog)-wb_mux_1[0], output net "wb_mux_1[0]" in work.decoder(verilog)
input nets to instance:
net "un1_alu_we_3_sqmuxa_4" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "wb_mux[0]" in work.decoder(verilog)
net "un1_wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_we_1[0]</font>
5) instance work.decoder(verilog)-wb_we_1[0], output net "wb_we_1[0]" in work.decoder(verilog)
input nets to instance:
net "un1_alu_we_3_sqmuxa_3" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "wb_we[0]" in work.decoder(verilog)
net "un1_wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2[0]</font>
6) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2[1]</font>
7) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2[2]</font>
8) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2[3]</font>
9) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2[4]</font>
10) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_func_1[0]" in work.decoder(verilog)
net "alu_func_1[1]" in work.decoder(verilog)
net "alu_func_1[2]" in work.decoder(verilog)
net "alu_func_1[3]" in work.decoder(verilog)
net "alu_func_1[4]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_we_1[0]</font>
11) instance work.decoder(verilog)-alu_we_1[0], output net "alu_we_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "alu_we[0]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2[0]</font>
12) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2[1]</font>
13) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2[2]</font>
14) instance work.decoder(verilog)-ext_ctl_2[2:0], output net "ext_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "ext_ctl_1[0]" in work.decoder(verilog)
net "ext_ctl_1[1]" in work.decoder(verilog)
net "ext_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_2[0]</font>
15) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_2[1]</font>
16) instance work.decoder(verilog)-muxa_ctl_2[1:0], output net "muxa_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxa_ctl_1[0]" in work.decoder(verilog)
net "muxa_ctl_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_2[0]</font>
17) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_2[1]</font>
18) instance work.decoder(verilog)-muxb_ctl_2[1:0], output net "muxb_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "muxb_ctl_1[0]" in work.decoder(verilog)
net "muxb_ctl_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2[0]</font>
19) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2[1]</font>
20) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2[2]</font>
21) instance work.decoder(verilog)-pc_gen_ctl_2[2:0], output net "pc_gen_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "pc_gen_ctl_1[0]" in work.decoder(verilog)
net "pc_gen_ctl_1[1]" in work.decoder(verilog)
net "pc_gen_ctl_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_2[0]</font>
22) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_2[1]</font>
23) instance work.decoder(verilog)-rd_sel_2[1:0], output net "rd_sel_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "rd_sel_1[0]" in work.decoder(verilog)
net "rd_sel_1[1]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2[0]</font>
24) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we294_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2[1]</font>
25) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we294_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2[2]</font>
26) instance work.decoder(verilog)-cmp_ctl_2[2:0], output net "cmp_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we294_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "cmp_ctl_1[0]" in work.decoder(verilog)
net "cmp_ctl_1[1]" in work.decoder(verilog)
net "cmp_ctl_1[2]" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2[0]</font>
27) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[0]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we307_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2[1]</font>
28) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[1]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we307_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2[2]</font>
29) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[2]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we307_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2[3]</font>
30) instance work.decoder(verilog)-dmem_ctl_2[3:0], output net "dmem_ctl_2[3]" in work.decoder(verilog)
input nets to instance:
net "un1_wb_we307_2" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)
net "dmem_ctl_1[0]" in work.decoder(verilog)
net "dmem_ctl_1[1]" in work.decoder(verilog)
net "dmem_ctl_1[2]" in work.decoder(verilog)
net "dmem_ctl_1[3]" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
End of loops
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="f:\a\rtl\verilog\mem_module.v:88:4:88:10:@W:BN132:@XP_MSG">mem_module.v(88)</a><!@TM:1190195874> | Removing sequential instance MEM_CTL.dmem_ctl_post.byte_addr_o[0], because it is equivalent to instance alu_pass0.r32_o[0]</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="f:\a\rtl\verilog\mem_module.v:88:4:88:10:@W:BN132:@XP_MSG">mem_module.v(88)</a><!@TM:1190195874> | Removing sequential instance MEM_CTL.dmem_ctl_post.byte_addr_o[1], because it is equivalent to instance alu_pass0.r32_o[1]</font>
Encoding state machine work.ctl_FSM(verilog)-CurrState_Sreg0[8:0]
original code -> new code
0000 -> 000000000
0001 -> 000000011
0010 -> 000000101
0011 -> 000001001
0100 -> 000010001
0101 -> 000100001
0110 -> 001000001
0111 -> 010000001
1000 -> 100000001
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@N::@XP_MSG">exec_stage.v(572)</a><!@TM:1190195874> | Found counter in view:work.muldiv_ff(verilog) inst count[5:0]
Warning: Found 30 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
29) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
30) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[2:0] work.decoder(verilog)-fsm_dly_2[2:0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_0_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_1_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_3_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_4_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_5_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_6_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_7_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_8_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_9_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_10_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_11_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_12_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_13_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_14_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_15_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_16_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_17_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_18_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_19_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_20_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_21_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_22_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_23_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_24_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_25_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_26_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_27_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_func_28_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_2_sqmuxa" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_3_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "alu_we_4_sqmuxa" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we292" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we293" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "wb_we294" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we295" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we296" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we297" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we298" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we299" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we300" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we301" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we302" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we303" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we304" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we305" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_0_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "alu_we_1_sqmuxa_1" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "VCC" in work.decoder(verilog)
net "alu_we_2_sqmuxa_1" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "fsm_dly_1[1]" in work.decoder(verilog)
net "fsm_dly_1[2]" in work.decoder(verilog)
net "wb_we307" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we308" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we309" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we310" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we311" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "wb_we312" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
net "GND" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_22" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_21" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance fsm_dly_2[0] work.decoder(verilog)-fsm_dly_2[0], output net "fsm_dly_2[0]" in work.decoder(verilog)
input nets to instance:
net "N_172" in work.decoder(verilog)
net "fsm_dly_1[0]" in work.decoder(verilog)
net "N_415" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance ext_ctl_1[0] work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance ext_ctl_1[1] work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance ext_ctl_1[2] work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "ext_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance rd_sel_1[0] work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance rd_sel_1[1] work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)
input nets to instance:
net "rd_sel_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance cmp_ctl_1[0] work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance cmp_ctl_1[1] work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance cmp_ctl_1[2] work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "cmp_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance pc_gen_ctl_1[0] work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance pc_gen_ctl_1[1] work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance pc_gen_ctl_1[2] work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "pc_gen_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance muxa_ctl_1[0] work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance muxa_ctl_1[1] work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxa_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance muxb_ctl_1[0] work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance muxb_ctl_1[1] work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "muxb_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance alu_func_1[0] work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance alu_func_1[1] work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance alu_func_1[2] work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance alu_func_1[3] work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance alu_func_1[4] work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)
input nets to instance:
net "alu_func_2[4]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance dmem_ctl_1[0] work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_23" in work.decoder(verilog)
net "un1_ins_i_20" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance dmem_ctl_1[1] work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[1]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_438" in work.decoder(verilog)
net "wb_we315" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance dmem_ctl_1[2] work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[2]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "un1_ins_i_24" in work.decoder(verilog)
net "un1_ins_i_15" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance dmem_ctl_1[3] work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)
input nets to instance:
net "dmem_ctl_2[3]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance alu_we[0] work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)
input nets to instance:
net "alu_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance wb_mux[0] work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)
input nets to instance:
net "wb_mux_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance wb_we[0] work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)
input nets to instance:
net "wb_we_1[0]" in work.decoder(verilog)
net "un1_wb_we312" in work.decoder(verilog)
net "N_436" in work.decoder(verilog)
End of loops
Automatic dissolve during optimization of view:work.mips_core(verilog) of iRF_stage.reg_bank(reg_array)
Auto Dissolve of decoder_pipe (inst of view:work.decode_pipe(verilog))
Auto Dissolve of iRF_stage.i_cmp (inst of view:work.compare(verilog))
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance decoder_pipe.idecoder.fsm_dly_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.fsm_dly_1[0], output net "BUS197[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance decoder_pipe.idecoder.ext_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[0], output net "decoder_pipe.BUS2072[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1346" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance decoder_pipe.idecoder.ext_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[1], output net "decoder_pipe.BUS2072[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1347" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance decoder_pipe.idecoder.ext_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[2], output net "decoder_pipe.BUS2072[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance decoder_pipe.idecoder.rd_sel_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[0], output net "decoder_pipe.BUS2110[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance decoder_pipe.idecoder.rd_sel_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[1], output net "decoder_pipe.BUS2110[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[0], output net "decoder_pipe.BUS2056[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[1], output net "decoder_pipe.BUS2056[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[2], output net "decoder_pipe.BUS2056[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "decoder_pipe.BUS2102[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1349" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "decoder_pipe.BUS2102[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "decoder_pipe.BUS2102[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1232_i" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[0], output net "decoder_pipe.BUS2086[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[1], output net "decoder_pipe.BUS2086[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[0], output net "decoder_pipe.BUS2094[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[1], output net "decoder_pipe.BUS2094[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance decoder_pipe.idecoder.alu_func_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[0], output net "decoder_pipe.BUS2040[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance decoder_pipe.idecoder.alu_func_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[1], output net "decoder_pipe.BUS2040[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance decoder_pipe.idecoder.alu_func_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[2], output net "decoder_pipe.BUS2040[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1345" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance decoder_pipe.idecoder.alu_func_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[3], output net "decoder_pipe.BUS2040[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance decoder_pipe.idecoder.alu_func_1[4] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[4], output net "decoder_pipe.BUS2040[4]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[0], output net "decoder_pipe.BUS2064[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[1], output net "decoder_pipe.BUS2064[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[2], output net "decoder_pipe.BUS2064[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_24" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_15" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[3], output net "decoder_pipe.BUS2064[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance decoder_pipe.idecoder.alu_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_we[0], output net "decoder_pipe.BUS2048[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance decoder_pipe.idecoder.wb_mux[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_mux[0], output net "decoder_pipe.BUS2118[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance decoder_pipe.idecoder.wb_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_we[0], output net "decoder_pipe.BUS2126[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
End of loops
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190195874> | Removing sequential instance iRF_stage.ins_reg.r32_o[31] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190195874> | Removing sequential instance iRF_stage.ins_reg.r32_o[30] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190195874> | Removing sequential instance iRF_stage.ins_reg.r32_o[29] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190195874> | Removing sequential instance iRF_stage.ins_reg.r32_o[28] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190195874> | Removing sequential instance iRF_stage.ins_reg.r32_o[27] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
<font color=#A52A2A>@W:<a href="@W:BN116:@XP_HELP">BN116</a> : <a href="f:\a\rtl\verilog\tools.v:104:111:104:117:@W:BN116:@XP_MSG">tools.v(104)</a><!@TM:1190195874> | Removing sequential instance iRF_stage.ins_reg.r32_o[26] of view:PrimLib.dff(prim) because there are no references to its outputs </font>
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance decoder_pipe.idecoder.fsm_dly_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.fsm_dly_1[0], output net "BUS197[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance decoder_pipe.idecoder.ext_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[0], output net "decoder_pipe.BUS2072[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1346" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance decoder_pipe.idecoder.ext_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[1], output net "decoder_pipe.BUS2072[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1347" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance decoder_pipe.idecoder.ext_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[2], output net "decoder_pipe.BUS2072[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance decoder_pipe.idecoder.rd_sel_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[0], output net "decoder_pipe.BUS2110[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance decoder_pipe.idecoder.rd_sel_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[1], output net "decoder_pipe.BUS2110[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[0], output net "decoder_pipe.BUS2056[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[1], output net "decoder_pipe.BUS2056[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[2], output net "decoder_pipe.BUS2056[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "decoder_pipe.BUS2102[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1349" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "decoder_pipe.BUS2102[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "decoder_pipe.BUS2102[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1232_i" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[0], output net "decoder_pipe.BUS2086[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[1], output net "decoder_pipe.BUS2086[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[0], output net "decoder_pipe.BUS2094[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[1], output net "decoder_pipe.BUS2094[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance decoder_pipe.idecoder.alu_func_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[0], output net "decoder_pipe.BUS2040[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance decoder_pipe.idecoder.alu_func_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[1], output net "decoder_pipe.BUS2040[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance decoder_pipe.idecoder.alu_func_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[2], output net "decoder_pipe.BUS2040[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1345" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance decoder_pipe.idecoder.alu_func_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[3], output net "decoder_pipe.BUS2040[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance decoder_pipe.idecoder.alu_func_1[4] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[4], output net "decoder_pipe.BUS2040[4]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[0], output net "decoder_pipe.BUS2064[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[1], output net "decoder_pipe.BUS2064[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[2], output net "decoder_pipe.BUS2064[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_15" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[3], output net "decoder_pipe.BUS2064[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance decoder_pipe.idecoder.alu_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_we[0], output net "decoder_pipe.BUS2048[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance decoder_pipe.idecoder.wb_mux[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_mux[0], output net "decoder_pipe.BUS2118[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance decoder_pipe.idecoder.wb_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_we[0], output net "decoder_pipe.BUS2126[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance decoder_pipe.idecoder.fsm_dly_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.fsm_dly_1[0], output net "BUS197[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance decoder_pipe.idecoder.ext_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[0], output net "decoder_pipe.BUS2072[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1346" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance decoder_pipe.idecoder.ext_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[1], output net "decoder_pipe.BUS2072[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1347" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance decoder_pipe.idecoder.ext_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[2], output net "decoder_pipe.BUS2072[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance decoder_pipe.idecoder.rd_sel_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[0], output net "decoder_pipe.BUS2110[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance decoder_pipe.idecoder.rd_sel_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[1], output net "decoder_pipe.BUS2110[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[0], output net "decoder_pipe.BUS2056[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[1], output net "decoder_pipe.BUS2056[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[2], output net "decoder_pipe.BUS2056[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "decoder_pipe.BUS2102[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1349" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "decoder_pipe.BUS2102[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "decoder_pipe.BUS2102[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1232_i" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[0], output net "decoder_pipe.BUS2086[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[1], output net "decoder_pipe.BUS2086[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[0], output net "decoder_pipe.BUS2094[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[1], output net "decoder_pipe.BUS2094[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance decoder_pipe.idecoder.alu_func_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[0], output net "decoder_pipe.BUS2040[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance decoder_pipe.idecoder.alu_func_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[1], output net "decoder_pipe.BUS2040[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance decoder_pipe.idecoder.alu_func_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[2], output net "decoder_pipe.BUS2040[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1345" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance decoder_pipe.idecoder.alu_func_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[3], output net "decoder_pipe.BUS2040[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance decoder_pipe.idecoder.alu_func_1[4] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[4], output net "decoder_pipe.BUS2040[4]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[0], output net "decoder_pipe.BUS2064[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[1], output net "decoder_pipe.BUS2064[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[2], output net "decoder_pipe.BUS2064[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_15" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[3], output net "decoder_pipe.BUS2064[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance decoder_pipe.idecoder.alu_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_we[0], output net "decoder_pipe.BUS2048[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance decoder_pipe.idecoder.wb_mux[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_mux[0], output net "decoder_pipe.BUS2118[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance decoder_pipe.idecoder.wb_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_we[0], output net "decoder_pipe.BUS2126[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance decoder_pipe.idecoder.fsm_dly_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.fsm_dly_1[0], output net "BUS197[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance decoder_pipe.idecoder.ext_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[0], output net "decoder_pipe.BUS2072[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1346" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance decoder_pipe.idecoder.ext_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[1], output net "decoder_pipe.BUS2072[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1347" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance decoder_pipe.idecoder.ext_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[2], output net "decoder_pipe.BUS2072[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance decoder_pipe.idecoder.rd_sel_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[0], output net "decoder_pipe.BUS2110[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance decoder_pipe.idecoder.rd_sel_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[1], output net "decoder_pipe.BUS2110[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[0], output net "decoder_pipe.BUS2056[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[1], output net "decoder_pipe.BUS2056[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[2], output net "decoder_pipe.BUS2056[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "decoder_pipe.BUS2102[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1349" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "decoder_pipe.BUS2102[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "decoder_pipe.BUS2102[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1232_i" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[0], output net "decoder_pipe.BUS2086[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[1], output net "decoder_pipe.BUS2086[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[0], output net "decoder_pipe.BUS2094[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[1], output net "decoder_pipe.BUS2094[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance decoder_pipe.idecoder.alu_func_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[0], output net "decoder_pipe.BUS2040[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance decoder_pipe.idecoder.alu_func_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[1], output net "decoder_pipe.BUS2040[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance decoder_pipe.idecoder.alu_func_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[2], output net "decoder_pipe.BUS2040[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1345" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance decoder_pipe.idecoder.alu_func_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[3], output net "decoder_pipe.BUS2040[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance decoder_pipe.idecoder.alu_func_1[4] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[4], output net "decoder_pipe.BUS2040[4]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[0], output net "decoder_pipe.BUS2064[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[1], output net "decoder_pipe.BUS2064[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[2], output net "decoder_pipe.BUS2064[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_15" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[3], output net "decoder_pipe.BUS2064[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance decoder_pipe.idecoder.alu_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_we[0], output net "decoder_pipe.BUS2048[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance decoder_pipe.idecoder.wb_mux[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_mux[0], output net "decoder_pipe.BUS2118[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance decoder_pipe.idecoder.wb_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_we[0], output net "decoder_pipe.BUS2126[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
1) instance decoder_pipe.idecoder.fsm_dly_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.fsm_dly_1[0], output net "BUS197[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
2) instance decoder_pipe.idecoder.ext_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[0], output net "decoder_pipe.BUS2072[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1346" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
3) instance decoder_pipe.idecoder.ext_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[1], output net "decoder_pipe.BUS2072[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1347" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
4) instance decoder_pipe.idecoder.ext_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[2], output net "decoder_pipe.BUS2072[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
5) instance decoder_pipe.idecoder.rd_sel_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[0], output net "decoder_pipe.BUS2110[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
6) instance decoder_pipe.idecoder.rd_sel_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[1], output net "decoder_pipe.BUS2110[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
7) instance decoder_pipe.idecoder.cmp_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[0], output net "decoder_pipe.BUS2056[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
8) instance decoder_pipe.idecoder.cmp_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[1], output net "decoder_pipe.BUS2056[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
9) instance decoder_pipe.idecoder.cmp_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[2], output net "decoder_pipe.BUS2056[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
10) instance decoder_pipe.idecoder.pc_gen_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "decoder_pipe.BUS2102[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1349" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
11) instance decoder_pipe.idecoder.pc_gen_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "decoder_pipe.BUS2102[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
12) instance decoder_pipe.idecoder.pc_gen_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "decoder_pipe.BUS2102[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1232_i" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
13) instance decoder_pipe.idecoder.muxa_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[0], output net "decoder_pipe.BUS2086[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
14) instance decoder_pipe.idecoder.muxa_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[1], output net "decoder_pipe.BUS2086[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
15) instance decoder_pipe.idecoder.muxb_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[0], output net "decoder_pipe.BUS2094[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
16) instance decoder_pipe.idecoder.muxb_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[1], output net "decoder_pipe.BUS2094[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
17) instance decoder_pipe.idecoder.alu_func_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[0], output net "decoder_pipe.BUS2040[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
18) instance decoder_pipe.idecoder.alu_func_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[1], output net "decoder_pipe.BUS2040[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
19) instance decoder_pipe.idecoder.alu_func_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[2], output net "decoder_pipe.BUS2040[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1345" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
20) instance decoder_pipe.idecoder.alu_func_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[3], output net "decoder_pipe.BUS2040[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
21) instance decoder_pipe.idecoder.alu_func_1[4] work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[4], output net "decoder_pipe.BUS2040[4]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
22) instance decoder_pipe.idecoder.dmem_ctl_1[0] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[0], output net "decoder_pipe.BUS2064[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
23) instance decoder_pipe.idecoder.dmem_ctl_1[1] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[1], output net "decoder_pipe.BUS2064[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
24) instance decoder_pipe.idecoder.dmem_ctl_1[2] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[2], output net "decoder_pipe.BUS2064[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_15" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
25) instance decoder_pipe.idecoder.dmem_ctl_1[3] work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[3], output net "decoder_pipe.BUS2064[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
26) instance decoder_pipe.idecoder.alu_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.alu_we[0], output net "decoder_pipe.BUS2048[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
27) instance decoder_pipe.idecoder.wb_mux[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_mux[0], output net "decoder_pipe.BUS2118[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN134:@XP_HELP">BN134</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN134:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping</font>
28) instance decoder_pipe.idecoder.wb_we[0] work.mips_core(verilog)-decoder_pipe.idecoder.wb_we[0], output net "decoder_pipe.BUS2126[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
End of loops
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net BUS197[0]</font>
1) instance work.mips_core(verilog)-decoder_pipe.idecoder.fsm_dly_1[0], output net "BUS197[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2072[0]</font>
2) instance work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[0], output net "decoder_pipe.BUS2072[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1346" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2072[1]</font>
3) instance work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[1], output net "decoder_pipe.BUS2072[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1347" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2072[2]</font>
4) instance work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_1[2], output net "decoder_pipe.BUS2072[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.ext_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2110[0]</font>
5) instance work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[0], output net "decoder_pipe.BUS2110[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2110[1]</font>
6) instance work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_1[1], output net "decoder_pipe.BUS2110[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.rd_sel_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2056[0]</font>
7) instance work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[0], output net "decoder_pipe.BUS2056[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2056[1]</font>
8) instance work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[1], output net "decoder_pipe.BUS2056[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2056[2]</font>
9) instance work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_1[2], output net "decoder_pipe.BUS2056[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.cmp_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2102[0]</font>
10) instance work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[0], output net "decoder_pipe.BUS2102[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1349" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2102[1]</font>
11) instance work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[1], output net "decoder_pipe.BUS2102[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.pc_gen_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2102[2]</font>
12) instance work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_1[2], output net "decoder_pipe.BUS2102[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1232_i_0" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2086[0]</font>
13) instance work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[0], output net "decoder_pipe.BUS2086[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2086[1]</font>
14) instance work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_1[1], output net "decoder_pipe.BUS2086[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxa_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2094[0]</font>
15) instance work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[0], output net "decoder_pipe.BUS2094[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2094[1]</font>
16) instance work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_1[1], output net "decoder_pipe.BUS2094[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.muxb_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2040[0]</font>
17) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[0], output net "decoder_pipe.BUS2040[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2040[1]</font>
18) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[1], output net "decoder_pipe.BUS2040[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2040[2]</font>
19) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[2], output net "decoder_pipe.BUS2040[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.N_1345" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2040[3]</font>
20) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[3], output net "decoder_pipe.BUS2040[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2040[4]</font>
21) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_1[4], output net "decoder_pipe.BUS2040[4]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2064[0]</font>
22) instance work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[0], output net "decoder_pipe.BUS2064[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_23" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_20" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2064[1]</font>
23) instance work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[1], output net "decoder_pipe.BUS2064[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_438" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we315" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2064[2]</font>
24) instance work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[2], output net "decoder_pipe.BUS2064[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_18_m" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_ins_i_15" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2064[3]</font>
25) instance work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_1[3], output net "decoder_pipe.BUS2064[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.dmem_ctl_2[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2048[0]</font>
26) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_we[0], output net "decoder_pipe.BUS2048[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2118[0]</font>
27) instance work.mips_core(verilog)-decoder_pipe.idecoder.wb_mux[0], output net "decoder_pipe.BUS2118[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_mux_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.BUS2126[0]</font>
28) instance work.mips_core(verilog)-decoder_pipe.idecoder.wb_we[0], output net "decoder_pipe.BUS2126[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.wb_we_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.un1_wb_we312" in work.mips_core(verilog)
net "decoder_pipe.idecoder.N_436" in work.mips_core(verilog)
End of loops
@N:<a href="@N:MF197:@XP_HELP">MF197</a> : <!@TM:1190195874> | Retiming summary : 6 registers retimed to 0
 
##### BEGIN RETIMING REPORT #####
 
Retiming summary : 6 registers retimed to 0
 
Original and Pipelined registers replaced by retiming :
iRF_stage.ins_reg.r32_o[26]
iRF_stage.ins_reg.r32_o[27]
iRF_stage.ins_reg.r32_o[28]
iRF_stage.ins_reg.r32_o[29]
iRF_stage.ins_reg.r32_o[30]
iRF_stage.ins_reg.r32_o[31]
 
New registers created by retiming :
None
 
 
##### END RETIMING REPORT #####
 
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.fsm_dly_2_0_0_x[0]</font>
1) instance work.mips_core(verilog)-decoder_pipe.idecoder.fsm_dly_2_0_0_x[0], output net "decoder_pipe.idecoder.fsm_dly_2_0_0_x[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2_0_0_0[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.ext_ctl_2_0_0_o3[2]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.wb_mux_1_0_0[0]</font>
2) instance work.mips_core(verilog)-decoder_pipe.idecoder.wb_mux_1_0_0[0], output net "decoder_pipe.idecoder.wb_mux_1_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.BUS2118[0]" in work.mips_core(verilog)
net "zz_ins_i_c[29]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_mux_1_0_0_a2_0[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_mux_1_0_0_a2_x[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.wb_we_1_0_0[0]</font>
3) instance work.mips_core(verilog)-decoder_pipe.idecoder.wb_we_1_0_0[0], output net "decoder_pipe.idecoder.wb_we_1_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.BUS2126[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_we_1_0_0_a[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.alu_func_2_0_0[0]</font>
4) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_2_0_0[0], output net "decoder_pipe.idecoder.alu_func_2_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a3_0[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a3_0_0_0_x[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_3[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.alu_func_2_0_0[1]</font>
5) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_2_0_0[1], output net "decoder_pipe.idecoder.alu_func_2_0_0[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2_0_0_a[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.fsm_dly_2_0_0_a2_x[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_o2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_3[1]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.alu_func_2_0_0[3]</font>
6) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_2_0_0[3], output net "decoder_pipe.idecoder.alu_func_2_0_0[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a3_1[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a3_0_0_x[3]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.alu_func_2_0_0[4]</font>
7) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_2_0_0[4], output net "decoder_pipe.idecoder.alu_func_2_0_0[4]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_2[4]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.alu_we_1_0_0[0]</font>
8) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_we_1_0_0[0], output net "decoder_pipe.idecoder.alu_we_1_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_we_1_0_0_a3_0_0[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_we_1_0_0_0[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_we_1_0_0_a[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.ext_ctl_2_0_0[2]</font>
9) instance work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_2_0_0[2], output net "decoder_pipe.idecoder.ext_ctl_2_0_0[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.ext_ctl_2_0_0_a3_1_x[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.ext_ctl_2_0_0_a2_0_x[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.ext_ctl_2_0_0_o3[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.ext_ctl_2_0_0_a[2]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.muxa_ctl_2_0_0[0]</font>
10) instance work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_2_0_0[0], output net "decoder_pipe.idecoder.muxa_ctl_2_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_o2_x[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.ext_ctl_2_0_0_a2_2[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.muxa_ctl_2_0_0_a[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.muxa_ctl_2_0_0_x[1]</font>
11) instance work.mips_core(verilog)-decoder_pipe.idecoder.muxa_ctl_2_0_0_x[1], output net "decoder_pipe.idecoder.muxa_ctl_2_0_0_x[1]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.muxa_ctl_2_0_0_2[1]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.muxb_ctl_2_0_0[0]</font>
12) instance work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_2_0_0[0], output net "decoder_pipe.idecoder.muxb_ctl_2_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "zz_ins_i_c[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.muxb_ctl_2_0_0_1[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.muxa_ctl_2_0_0_o2_0[1]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.muxb_ctl_2_0_0[1]</font>
13) instance work.mips_core(verilog)-decoder_pipe.idecoder.muxb_ctl_2_0_0[1], output net "decoder_pipe.idecoder.muxb_ctl_2_0_0[1]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_mux_1_0_0_a2_0[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_2_x[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.muxb_ctl_2_0_0_a[1]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1]</font>
14) instance work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1], output net "decoder_pipe.idecoder.pc_gen_ctl_2_0_0[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.pc_gen_ctl_2_0_0_a2_x[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_3_x[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.pc_gen_ctl_2_0_0_a[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_2[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.rd_sel_2_0_0[0]</font>
15) instance work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_2_0_0[0], output net "decoder_pipe.idecoder.rd_sel_2_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2_0_0_a2_x[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_o2[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.rd_sel_2_0_0_0[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.rd_sel_2_0_0_a3[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.rd_sel_2_0_0[1]</font>
16) instance work.mips_core(verilog)-decoder_pipe.idecoder.rd_sel_2_0_0[1], output net "decoder_pipe.idecoder.rd_sel_2_0_0[1]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_core(verilog)
net "zz_ins_i_c[31]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_mux_1_0_0_a2_0[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.rd_sel_2_0_0_a[1]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.cmp_ctl_2_0_0[0]</font>
17) instance work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_2_0_0[0], output net "decoder_pipe.idecoder.cmp_ctl_2_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_1[0]" in work.mips_core(verilog)
net "decoder_pipe.BUS2056[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.cmp_ctl_2_0_0_1[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.cmp_ctl_2_0_0[1]</font>
18) instance work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_2_0_0[1], output net "decoder_pipe.idecoder.cmp_ctl_2_0_0[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.BUS2056[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_0_x[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.cmp_ctl_2_0_0_a[1]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.cmp_ctl_2_0_0[2]</font>
19) instance work.mips_core(verilog)-decoder_pipe.idecoder.cmp_ctl_2_0_0[2], output net "decoder_pipe.idecoder.cmp_ctl_2_0_0[2]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[27]" in work.mips_core(verilog)
net "zz_ins_i_c[26]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.cmp_ctl_2_0_0_a2_x[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.cmp_ctl_2_0_0_a[2]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.dmem_ctl_2_0_0[0]</font>
20) instance work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_2_0_0[0], output net "decoder_pipe.idecoder.dmem_ctl_2_0_0[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "decoder_pipe.BUS2064[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a3_1_x[4]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.dmem_ctl_2_0_0[1]</font>
21) instance work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_2_0_0[1], output net "decoder_pipe.idecoder.dmem_ctl_2_0_0[1]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "decoder_pipe.BUS2064[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.dmem_ctl_2_0_0_1[1]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.dmem_ctl_2_0_0[2]</font>
22) instance work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_2_0_0[2], output net "decoder_pipe.idecoder.dmem_ctl_2_0_0[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.BUS2064[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.wb_mux_1_0_0_a2_x[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.dmem_ctl_2_0_0_a[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.dmem_ctl_2_0_0_a3_1[2]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.dmem_ctl_2_0_0[3]</font>
23) instance work.mips_core(verilog)-decoder_pipe.idecoder.dmem_ctl_2_0_0[3], output net "decoder_pipe.idecoder.dmem_ctl_2_0_0[3]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.BUS2064[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[1]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.fsm_dly_2_0_0_o2_x[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.dmem_ctl_2_0_0_a[3]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2]</font>
24) instance work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2], output net "decoder_pipe.idecoder.pc_gen_ctl_2_i_0[2]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.BUS2102[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.fsm_dly_2_0_0_a3_0[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.pc_gen_ctl_2_i_0_a[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.pc_gen_ctl_2_i_0_5[2]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.alu_func_2_i_m3_0[2]</font>
25) instance work.mips_core(verilog)-decoder_pipe.idecoder.alu_func_2_i_m3_0[2], output net "decoder_pipe.idecoder.alu_func_2_i_m3_0[2]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[28]" in work.mips_core(verilog)
net "zz_ins_i_c[27]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0[4]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_i_m3_0_a[2]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0]</font>
26) instance work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0], output net "decoder_pipe.idecoder.ext_ctl_2_i_m3_0[0]" in work.mips_core(verilog)
input nets to instance:
net "decoder_pipe.idecoder.fsm_dly_2_0_0_a3_0[2]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_o3[3]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.ext_ctl_2_i_m3_0_2[0]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1]</font>
27) instance work.mips_core(verilog)-decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1], output net "decoder_pipe.idecoder.ext_ctl_2_i_m3_0[1]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[29]" in work.mips_core(verilog)
net "zz_ins_i_c[28]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.alu_func_2_0_0_a2_0_x[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.ext_ctl_2_i_m3_0_a[1]" in work.mips_core(verilog)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0]</font>
28) instance work.mips_core(verilog)-decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0], output net "decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0[0]" in work.mips_core(verilog)
input nets to instance:
net "zz_ins_i_c[28]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_o2_0_x[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_3[0]" in work.mips_core(verilog)
net "decoder_pipe.idecoder.pc_gen_ctl_2_i_m3_0_a[0]" in work.mips_core(verilog)
End of loops
 
Writing Analyst data base F:\a\syn\mips_core\mips_core.srm
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net BUS197_0</font>
1) instance work.decoder(netlist)-fsm_dly_1[0], output net "BUS197_0" in work.decoder(netlist)
input nets to instance:
net "G_1707" in work.decoder(netlist)
net "un1_wb_we312_x" in work.decoder(netlist)
net "un1_ins_i_22_1" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_2_0_0_x_0</font>
2) instance work.decoder(netlist)-muxa_ctl_2_0_0_x[1], output net "muxa_ctl_2_0_0_x_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "muxa_ctl_2_0_0_2[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0</font>
3) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2102_2" in work.decoder(netlist)
net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0</font>
4) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1</font>
5) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_0</font>
6) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_0" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0_0_0_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_3[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_1</font>
7) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o2[1]" in work.decoder(netlist)
net "alu_func_2_0_0_3[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_4</font>
8) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[4]" in work.decoder(netlist)
net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_3</font>
9) instance work.decoder(netlist)-alu_func_2_0_0[3], output net "alu_func_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_2[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0_0_x[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0</font>
10) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_28" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_o2_0_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_3[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_we_1_0_0_0</font>
11) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_3" in work.decoder(netlist)
net "alu_we_1_0_0_a3_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_1</font>
12) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2056_1" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_2</font>
13) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_27" in work.decoder(netlist)
net "zz_ins_i_c_26" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_0</font>
14) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
net "BUS2056_0" in work.decoder(netlist)
net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_i_m3_0_0</font>
15) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_28" in work.decoder(netlist)
net "zz_ins_i_c_27" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[4]" in work.decoder(netlist)
net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_0_0_0</font>
16) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "ext_ctl_2_0_0_a3_1_x[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_0_x[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_1</font>
17) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_1" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_0</font>
18) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_0" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1_x[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_2</font>
19) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "BUS2064_2" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a3_1[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_3</font>
20) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "BUS2064_3" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_2_0_0_0</font>
21) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "zz_ins_i_c_4" in work.decoder(netlist)
net "muxb_ctl_2_0_0_1[0]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_2_0_0_1</font>
22) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2_x[3]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0</font>
23) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "pc_gen_ctl_2_0_0_a2_x[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_0_0_a[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_2_0_0_0</font>
24) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o2[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_0[0]" in work.decoder(netlist)
net "rd_sel_2_0_0_a3[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_2_0_0_1</font>
25) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_31" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_2_0_0_0</font>
26) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_2[2]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_we_1_0_0_0</font>
27) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2126_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_mux_1_0_0_0</font>
28) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2118_0" in work.decoder(netlist)
net "zz_ins_i_c_29" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
End of loops
Writing Verilog Netlist and constraint files
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net BUS197_0</font>
1) instance work.decoder(netlist)-fsm_dly_1[0], output net "BUS197_0" in work.decoder(netlist)
input nets to instance:
net "G_1707" in work.decoder(netlist)
net "un1_wb_we312_x" in work.decoder(netlist)
net "un1_ins_i_22_1" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_2_0_0_x_0</font>
2) instance work.decoder(netlist)-muxa_ctl_2_0_0_x[1], output net "muxa_ctl_2_0_0_x_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "muxa_ctl_2_0_0_2[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0</font>
3) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2102_2" in work.decoder(netlist)
net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0</font>
4) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1</font>
5) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_0</font>
6) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_0" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0_0_0_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_3[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_1</font>
7) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o2[1]" in work.decoder(netlist)
net "alu_func_2_0_0_3[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_4</font>
8) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[4]" in work.decoder(netlist)
net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_3</font>
9) instance work.decoder(netlist)-alu_func_2_0_0[3], output net "alu_func_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_2[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0_0_x[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0</font>
10) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_28" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_o2_0_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_3[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_we_1_0_0_0</font>
11) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_3" in work.decoder(netlist)
net "alu_we_1_0_0_a3_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_1</font>
12) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2056_1" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_2</font>
13) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_27" in work.decoder(netlist)
net "zz_ins_i_c_26" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_0</font>
14) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
net "BUS2056_0" in work.decoder(netlist)
net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_i_m3_0_0</font>
15) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_28" in work.decoder(netlist)
net "zz_ins_i_c_27" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[4]" in work.decoder(netlist)
net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_0_0_0</font>
16) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "ext_ctl_2_0_0_a3_1_x[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_0_x[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_1</font>
17) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_1" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_0</font>
18) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_0" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1_x[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_2</font>
19) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "BUS2064_2" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a3_1[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_3</font>
20) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "BUS2064_3" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_2_0_0_0</font>
21) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "zz_ins_i_c_4" in work.decoder(netlist)
net "muxb_ctl_2_0_0_1[0]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_2_0_0_1</font>
22) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2_x[3]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0</font>
23) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "pc_gen_ctl_2_0_0_a2_x[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_0_0_a[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_2_0_0_0</font>
24) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o2[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_0[0]" in work.decoder(netlist)
net "rd_sel_2_0_0_a3[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_2_0_0_1</font>
25) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_31" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_2_0_0_0</font>
26) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_2[2]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_we_1_0_0_0</font>
27) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2126_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_mux_1_0_0_0</font>
28) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2118_0" in work.decoder(netlist)
net "zz_ins_i_c_29" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
End of loops
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to F:\a\syn\mips_core\mips_core.xrf
Warning: Found 28 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net BUS197_0</font>
1) instance work.decoder(netlist)-fsm_dly_1[0], output net "BUS197_0" in work.decoder(netlist)
input nets to instance:
net "G_1707" in work.decoder(netlist)
net "un1_wb_we312_x" in work.decoder(netlist)
net "un1_ins_i_22_1" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_2_0_0_x_0</font>
2) instance work.decoder(netlist)-muxa_ctl_2_0_0_x[1], output net "muxa_ctl_2_0_0_x_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "muxa_ctl_2_0_0_2[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_i_0_0</font>
3) instance work.decoder(netlist)-pc_gen_ctl_2_i_0[2], output net "pc_gen_ctl_2_i_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2102_2" in work.decoder(netlist)
net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_a[2]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_0_5[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_0</font>
4) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[0], output net "ext_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "fsm_dly_2_0_0_a3_0[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o3[3]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_2[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_i_m3_0_1</font>
5) instance work.decoder(netlist)-ext_ctl_2_i_m3_0[1], output net "ext_ctl_2_i_m3_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_28" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "ext_ctl_2_i_m3_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_0</font>
6) instance work.decoder(netlist)-alu_func_2_0_0[0], output net "alu_func_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_0" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0_0_0_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_3[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_1</font>
7) instance work.decoder(netlist)-alu_func_2_0_0[1], output net "alu_func_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o2[1]" in work.decoder(netlist)
net "alu_func_2_0_0_3[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_4</font>
8) instance work.decoder(netlist)-alu_func_2_0_0[4], output net "alu_func_2_0_0_4" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[4]" in work.decoder(netlist)
net "alu_func_2_0_0_a[4]" in work.decoder(netlist)
net "alu_func_2_0_0_2[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_0_0_3</font>
9) instance work.decoder(netlist)-alu_func_2_0_0[3], output net "alu_func_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_2[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a[3]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_0_0_x[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_i_m3_0_0</font>
10) instance work.decoder(netlist)-pc_gen_ctl_2_i_m3_0[0], output net "pc_gen_ctl_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_28" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_o2_0_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_3[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_i_m3_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_we_1_0_0_0</font>
11) instance work.decoder(netlist)-alu_we_1_0_0[0], output net "alu_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_3" in work.decoder(netlist)
net "alu_we_1_0_0_a3_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_0[0]" in work.decoder(netlist)
net "alu_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_1</font>
12) instance work.decoder(netlist)-cmp_ctl_2_0_0[1], output net "cmp_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "BUS2056_1" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_0_x[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_2</font>
13) instance work.decoder(netlist)-cmp_ctl_2_0_0[2], output net "cmp_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_27" in work.decoder(netlist)
net "zz_ins_i_c_26" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_x[0]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net cmp_ctl_2_0_0_0</font>
14) instance work.decoder(netlist)-cmp_ctl_2_0_0[0], output net "cmp_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "cmp_ctl_2_0_0_a2_1[0]" in work.decoder(netlist)
net "BUS2056_0" in work.decoder(netlist)
net "cmp_ctl_2_0_0_1[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net alu_func_2_i_m3_0_0</font>
15) instance work.decoder(netlist)-alu_func_2_i_m3_0[2], output net "alu_func_2_i_m3_0_0" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_28" in work.decoder(netlist)
net "zz_ins_i_c_27" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[4]" in work.decoder(netlist)
net "alu_func_2_i_m3_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net ext_ctl_2_0_0_0</font>
16) instance work.decoder(netlist)-ext_ctl_2_0_0[2], output net "ext_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "ext_ctl_2_0_0_a3_1_x[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_0_x[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_o3[2]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_1</font>
17) instance work.decoder(netlist)-dmem_ctl_2_0_0[1], output net "dmem_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_1" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_1[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_0</font>
18) instance work.decoder(netlist)-dmem_ctl_2_0_0[0], output net "dmem_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "BUS2064_0" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_a3_1_x[4]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_2</font>
19) instance work.decoder(netlist)-dmem_ctl_2_0_0[2], output net "dmem_ctl_2_0_0_2" in work.decoder(netlist)
input nets to instance:
net "BUS2064_2" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a3_1[2]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net dmem_ctl_2_0_0_3</font>
20) instance work.decoder(netlist)-dmem_ctl_2_0_0[3], output net "dmem_ctl_2_0_0_3" in work.decoder(netlist)
input nets to instance:
net "BUS2064_3" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "dmem_ctl_2_0_0_a[3]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_2_0_0_0</font>
21) instance work.decoder(netlist)-muxb_ctl_2_0_0[0], output net "muxb_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "zz_ins_i_c_4" in work.decoder(netlist)
net "muxb_ctl_2_0_0_1[0]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_o2_0[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxb_ctl_2_0_0_1</font>
22) instance work.decoder(netlist)-muxb_ctl_2_0_0[1], output net "muxb_ctl_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2_x[3]" in work.decoder(netlist)
net "muxb_ctl_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net pc_gen_ctl_2_0_0_0</font>
23) instance work.decoder(netlist)-pc_gen_ctl_2_0_0[1], output net "pc_gen_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "pc_gen_ctl_2_0_0_a2_x[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_3_x[0]" in work.decoder(netlist)
net "pc_gen_ctl_2_0_0_a[1]" in work.decoder(netlist)
net "alu_func_2_0_0_a2_2[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_2_0_0_0</font>
24) instance work.decoder(netlist)-rd_sel_2_0_0[0], output net "rd_sel_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "fsm_dly_2_0_0_a2_x[2]" in work.decoder(netlist)
net "alu_func_2_0_0_o2[1]" in work.decoder(netlist)
net "rd_sel_2_0_0_0[0]" in work.decoder(netlist)
net "rd_sel_2_0_0_a3[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net rd_sel_2_0_0_1</font>
25) instance work.decoder(netlist)-rd_sel_2_0_0[1], output net "rd_sel_2_0_0_1" in work.decoder(netlist)
input nets to instance:
net "zz_ins_i_c_29" in work.decoder(netlist)
net "zz_ins_i_c_31" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "rd_sel_2_0_0_a[1]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net muxa_ctl_2_0_0_0</font>
26) instance work.decoder(netlist)-muxa_ctl_2_0_0[0], output net "muxa_ctl_2_0_0_0" in work.decoder(netlist)
input nets to instance:
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "alu_func_2_0_0_o2_x[3]" in work.decoder(netlist)
net "ext_ctl_2_0_0_a2_2[2]" in work.decoder(netlist)
net "muxa_ctl_2_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_we_1_0_0_0</font>
27) instance work.decoder(netlist)-wb_we_1_0_0[0], output net "wb_we_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2126_0" in work.decoder(netlist)
net "alu_func_2_0_0_a2_0[1]" in work.decoder(netlist)
net "fsm_dly_2_0_0_o2_x[2]" in work.decoder(netlist)
net "wb_we_1_0_0_a[0]" in work.decoder(netlist)
<font color=#A52A2A>@W:<a href="@W:BN137:@XP_HELP">BN137</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:BN137:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190195874> | Found combinational loop during mapping at net wb_mux_1_0_0_0</font>
28) instance work.decoder(netlist)-wb_mux_1_0_0[0], output net "wb_mux_1_0_0_0" in work.decoder(netlist)
input nets to instance:
net "BUS2118_0" in work.decoder(netlist)
net "zz_ins_i_c_29" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_0[0]" in work.decoder(netlist)
net "wb_mux_1_0_0_a2_x[0]" in work.decoder(netlist)
End of loops
Found clock mips_core|clk with period 10.88ns
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:161:4:161:8:@W::@XP_MSG">mem_module.v(161)</a><!@TM:1190195874> | Net un1_byte_addr_2_combout appears to be a clock source which was not identified. Assuming default frequency. </font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190195874> | Net un1_NextState_Sreg0_6 appears to be a clock source which was not identified. Assuming default frequency. </font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:1:1:961:16:@W::@XP_MSG">decode_pipe.v(1)</a><!@TM:1190195874> | Net un1_wb_we312_x appears to be a clock source which was not identified. Assuming default frequency. </font>
 
 
<a name=timingReport20>##### START OF TIMING REPORT #####[
# Timing Report written on Wed Sep 19 17:57:51 2007
#
 
 
Top view: mips_core
Requested Frequency: 91.9 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1190195874> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
 
@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:1190195874> | Clock constraints cover only FF-to-FF paths associated with the clock..
 
 
 
<a name=performanceSummary21>Performance Summary
*******************
 
 
Worst slack in design: -1.920
 
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------
mips_core|clk 91.9 MHz 78.1 MHz 10.881 12.802 -1.920 inferred Autoconstr_clkgroup_0
System 985.6 MHz 837.8 MHz 1.015 1.194 -0.179 system default_clkgroup
========================================================================================================================
 
 
 
 
 
<a name=clockRelationships22>Clock Relationships
*******************
 
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------------------
mips_core|clk mips_core|clk | 10.881 -1.920 | No paths - | No paths - | No paths -
=====================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
 
<a name=interfaceInfo23>Interface Information
*********************
 
No IO constraint found
 
 
 
====================================
<a name=clockReport24>Detailed Report for Clock: mips_core|clk
====================================
 
 
 
<a name=startingSlack25>Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------
rnd_pass1.r5_o[3] mips_core|clk cyclone_lcell_ff regout r5_o_3 0.173 -1.920
rnd_pass1.r5_o[2] mips_core|clk cyclone_lcell_ff regout r5_o_2 0.173 -1.898
rnd_pass1.r5_o[0] mips_core|clk cyclone_lcell_ff regout r5_o_0 0.173 -1.783
rnd_pass1.r5_o[4] mips_core|clk cyclone_lcell_ff regout r5_o_4 0.173 -1.783
iRF_stage.ins_reg.r32_o[24] mips_core|clk cyclone_lcell_ff regout r32_o_24 0.173 -1.722
rnd_pass1.r5_o[1] mips_core|clk cyclone_lcell_ff regout r5_o_1 0.173 -1.646
iRF_stage.ins_reg.r32_o[22] mips_core|clk cyclone_lcell_ff regout r32_o_22 0.173 -1.607
iRF_stage.ins_reg.r32_o[23] mips_core|clk cyclone_lcell_ff regout r32_o_23 0.173 -1.492
iRF_stage.ins_reg.r32_o[25] mips_core|clk cyclone_lcell_ff regout r32_o_25 0.173 -1.470
iRF_stage.ins_reg.r32_o[21] mips_core|clk cyclone_lcell_ff regout r32_o_21 0.173 -1.377
=================================================================================================================
 
 
<a name=endingSlack26>Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------
pc.r32_o[31] mips_core|clk cyclone_lcell_ff datad un1_pc_add31 10.852 -1.920
pc.r32_o[30] mips_core|clk cyclone_lcell_ff datad un1_pc_add30 10.852 -1.893
pc.r32_o[29] mips_core|clk cyclone_lcell_ff datad un1_pc_add29 10.852 -1.866
pc.r32_o[28] mips_core|clk cyclone_lcell_ff datad un1_pc_add28 10.852 -1.839
pc.r32_o[27] mips_core|clk cyclone_lcell_ff datad un1_pc_add27 10.852 -1.812
pc.r32_o[26] mips_core|clk cyclone_lcell_ff datad un1_pc_add26 10.852 -1.785
pc.r32_o[25] mips_core|clk cyclone_lcell_ff datad un1_pc_add25 10.852 -1.758
pc.r32_o[24] mips_core|clk cyclone_lcell_ff datad un1_pc_add24 10.852 -1.731
pc.r32_o[23] mips_core|clk cyclone_lcell_ff datad un1_pc_add23 10.852 -1.704
pc.r32_o[22] mips_core|clk cyclone_lcell_ff datad un1_pc_add22 10.852 -1.677
======================================================================================================
 
 
 
<a name=worstPaths27>Worst Path Information
<a href="F:\a\syn\mips_core\mips_core.srr:fp:469563:486327:@XP_NAMES">View Worst Path in Analyst</a>
***********************
 
 
Path information for path number 1:
Requested Period: 10.881
- Setup time: 0.029
= Required time: 10.852
 
- Propagation time: 12.773
= Slack (critical) : -1.920
 
Number of logic level(s): 43
Starting point: rnd_pass1.r5_o[3] / regout
Ending point: pc.r32_o[31] / datad
The start point is clocked by mips_core|clk [rising] on pin clk
The end point is clocked by mips_core|clk [rising] on pin clk
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
rnd_pass1.r5_o[3] cyclone_lcell_ff regout Out 0.173 0.173 -
r5_o_3 Net - - 0.635 - 6
iforward.fw_alu_rs.un14_mux_fw_0 cyclone_lcell datac In - 0.808 -
iforward.fw_alu_rs.un14_mux_fw_0 cyclone_lcell combout Out 0.225 1.033 -
un14_mux_fw_0 Net - - 0.455 - 4
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell datac In - 1.488 -
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell combout Out 0.225 1.713 -
mux_fw_1_a Net - - 0.245 - 1
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell datad In - 1.958 -
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell combout Out 0.088 2.046 -
mux_fw_1 Net - - 1.253 - 34
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell datad In - 3.300 -
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell combout Out 0.088 3.388 -
un32_mux_fw Net - - 0.274 - 2
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell datad In - 3.662 -
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell combout Out 0.088 3.750 -
N_30_i_0_s2 Net - - 1.218 - 32
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell datac In - 4.968 -
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell combout Out 0.225 5.193 -
dout_iv_a_2 Net - - 0.274 - 2
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell datad In - 5.467 -
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell combout Out 0.088 5.555 -
iRF_stage.rs_fwd_rs.dout_iv[4] Net - - 0.364 - 3
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell dataa In - 5.920 -
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell combout Out 0.454 6.374 -
res_2_NE_6 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell dataa In - 6.619 -
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell combout Out 0.454 7.073 -
res_2_NE_10_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE cyclone_lcell dataa In - 7.318 -
iRF_stage.i_cmp.res_2_NE cyclone_lcell combout Out 0.454 7.772 -
res_2_NE Net - - 0.274 - 2
iRF_stage.i_cmp.res_3_0 cyclone_lcell datad In - 8.047 -
iRF_stage.i_cmp.res_3_0 cyclone_lcell combout Out 0.088 8.135 -
res_3_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_7_0 cyclone_lcell datac In - 8.380 -
iRF_stage.i_cmp.res_7_0 cyclone_lcell combout Out 0.225 8.605 -
res_7_0 Net - - 1.166 - 29
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell datad In - 9.770 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell combout Out 0.088 9.858 -
un1_pc_prectl_1_0_a4[0] Net - - 0.455 - 4
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[3] cyclone_lcell datad In - 10.313 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[3] cyclone_lcell combout Out 0.088 10.401 -
un1_pc_prectl_1_0_a2_0_a2[3] Net - - 0.245 - 1
iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell datab In - 10.646 -
iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell cout Out 0.645 11.291 -
un1_pc_carry_3 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cin In - 11.291 -
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cout Out 0.027 11.318 -
un1_pc_carry_4 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cin In - 11.318 -
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cout Out 0.027 11.345 -
un1_pc_carry_5 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cin In - 11.345 -
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cout Out 0.027 11.372 -
un1_pc_carry_6 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cin In - 11.372 -
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cout Out 0.027 11.399 -
un1_pc_carry_7 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cin In - 11.399 -
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cout Out 0.027 11.426 -
un1_pc_carry_8 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cin In - 11.426 -
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cout Out 0.027 11.453 -
un1_pc_carry_9 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cin In - 11.453 -
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cout Out 0.027 11.480 -
un1_pc_carry_10 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cin In - 11.480 -
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cout Out 0.027 11.507 -
un1_pc_carry_11 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cin In - 11.507 -
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cout Out 0.027 11.534 -
un1_pc_carry_12 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cin In - 11.534 -
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cout Out 0.027 11.561 -
un1_pc_carry_13 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cin In - 11.561 -
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cout Out 0.027 11.588 -
un1_pc_carry_14 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cin In - 11.588 -
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cout Out 0.027 11.615 -
un1_pc_carry_15 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cin In - 11.615 -
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cout Out 0.027 11.642 -
un1_pc_carry_16 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cin In - 11.642 -
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cout Out 0.027 11.669 -
un1_pc_carry_17 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cin In - 11.669 -
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cout Out 0.027 11.696 -
un1_pc_carry_18 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cin In - 11.696 -
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cout Out 0.027 11.723 -
un1_pc_carry_19 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cin In - 11.723 -
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cout Out 0.027 11.750 -
un1_pc_carry_20 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cin In - 11.750 -
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cout Out 0.027 11.777 -
un1_pc_carry_21 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cin In - 11.777 -
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cout Out 0.027 11.804 -
un1_pc_carry_22 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cin In - 11.804 -
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cout Out 0.027 11.831 -
un1_pc_carry_23 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cin In - 11.831 -
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cout Out 0.027 11.858 -
un1_pc_carry_24 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cin In - 11.858 -
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cout Out 0.027 11.885 -
un1_pc_carry_25 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cin In - 11.885 -
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cout Out 0.027 11.912 -
un1_pc_carry_26 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cin In - 11.912 -
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cout Out 0.027 11.939 -
un1_pc_carry_27 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cin In - 11.939 -
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cout Out 0.027 11.966 -
un1_pc_carry_28 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cin In - 11.966 -
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cout Out 0.027 11.993 -
un1_pc_carry_29 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cin In - 11.993 -
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cout Out 0.027 12.020 -
un1_pc_carry_30 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell cin In - 12.020 -
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell combout Out 0.478 12.498 -
un1_pc_add31 Net - - 0.274 - 2
pc.r32_o[31] cyclone_lcell_ff datad In - 12.773 -
=============================================================================================================================
Total path delay (propagation time + setup) of 12.802 is 4.932(38.5%) logic and 7.870(61.5%) route.
 
 
Path information for path number 2:
Requested Period: 10.881
- Setup time: 0.029
= Required time: 10.852
 
- Propagation time: 12.773
= Slack (critical) : -1.920
 
Number of logic level(s): 43
Starting point: rnd_pass1.r5_o[3] / regout
Ending point: pc.r32_o[31] / datad
The start point is clocked by mips_core|clk [rising] on pin clk
The end point is clocked by mips_core|clk [rising] on pin clk
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
rnd_pass1.r5_o[3] cyclone_lcell_ff regout Out 0.173 0.173 -
r5_o_3 Net - - 0.635 - 6
iforward.fw_alu_rs.un14_mux_fw_0 cyclone_lcell datac In - 0.808 -
iforward.fw_alu_rs.un14_mux_fw_0 cyclone_lcell combout Out 0.225 1.033 -
un14_mux_fw_0 Net - - 0.455 - 4
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell datac In - 1.488 -
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell combout Out 0.225 1.713 -
mux_fw_1_a Net - - 0.245 - 1
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell datad In - 1.958 -
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell combout Out 0.088 2.046 -
mux_fw_1 Net - - 1.253 - 34
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell datad In - 3.300 -
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell combout Out 0.088 3.388 -
un32_mux_fw Net - - 0.274 - 2
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell datad In - 3.662 -
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell combout Out 0.088 3.750 -
N_30_i_0_s2 Net - - 1.218 - 32
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell datac In - 4.968 -
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell combout Out 0.225 5.193 -
dout_iv_a_2 Net - - 0.274 - 2
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell datad In - 5.467 -
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell combout Out 0.088 5.555 -
iRF_stage.rs_fwd_rs.dout_iv[4] Net - - 0.364 - 3
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell dataa In - 5.920 -
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell combout Out 0.454 6.374 -
res_2_NE_6 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell dataa In - 6.619 -
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell combout Out 0.454 7.073 -
res_2_NE_10_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE cyclone_lcell dataa In - 7.318 -
iRF_stage.i_cmp.res_2_NE cyclone_lcell combout Out 0.454 7.772 -
res_2_NE Net - - 0.274 - 2
iRF_stage.i_cmp.res_6_0 cyclone_lcell datac In - 8.047 -
iRF_stage.i_cmp.res_6_0 cyclone_lcell combout Out 0.225 8.272 -
res_6_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_7_0 cyclone_lcell datad In - 8.517 -
iRF_stage.i_cmp.res_7_0 cyclone_lcell combout Out 0.088 8.605 -
res_7_0 Net - - 1.166 - 29
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell datad In - 9.770 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell combout Out 0.088 9.858 -
un1_pc_prectl_1_0_a4[0] Net - - 0.455 - 4
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[3] cyclone_lcell datad In - 10.313 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[3] cyclone_lcell combout Out 0.088 10.401 -
un1_pc_prectl_1_0_a2_0_a2[3] Net - - 0.245 - 1
iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell datab In - 10.646 -
iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell cout Out 0.645 11.291 -
un1_pc_carry_3 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cin In - 11.291 -
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cout Out 0.027 11.318 -
un1_pc_carry_4 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cin In - 11.318 -
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cout Out 0.027 11.345 -
un1_pc_carry_5 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cin In - 11.345 -
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cout Out 0.027 11.372 -
un1_pc_carry_6 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cin In - 11.372 -
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cout Out 0.027 11.399 -
un1_pc_carry_7 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cin In - 11.399 -
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cout Out 0.027 11.426 -
un1_pc_carry_8 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cin In - 11.426 -
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cout Out 0.027 11.453 -
un1_pc_carry_9 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cin In - 11.453 -
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cout Out 0.027 11.480 -
un1_pc_carry_10 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cin In - 11.480 -
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cout Out 0.027 11.507 -
un1_pc_carry_11 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cin In - 11.507 -
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cout Out 0.027 11.534 -
un1_pc_carry_12 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cin In - 11.534 -
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cout Out 0.027 11.561 -
un1_pc_carry_13 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cin In - 11.561 -
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cout Out 0.027 11.588 -
un1_pc_carry_14 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cin In - 11.588 -
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cout Out 0.027 11.615 -
un1_pc_carry_15 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cin In - 11.615 -
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cout Out 0.027 11.642 -
un1_pc_carry_16 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cin In - 11.642 -
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cout Out 0.027 11.669 -
un1_pc_carry_17 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cin In - 11.669 -
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cout Out 0.027 11.696 -
un1_pc_carry_18 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cin In - 11.696 -
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cout Out 0.027 11.723 -
un1_pc_carry_19 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cin In - 11.723 -
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cout Out 0.027 11.750 -
un1_pc_carry_20 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cin In - 11.750 -
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cout Out 0.027 11.777 -
un1_pc_carry_21 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cin In - 11.777 -
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cout Out 0.027 11.804 -
un1_pc_carry_22 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cin In - 11.804 -
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cout Out 0.027 11.831 -
un1_pc_carry_23 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cin In - 11.831 -
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cout Out 0.027 11.858 -
un1_pc_carry_24 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cin In - 11.858 -
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cout Out 0.027 11.885 -
un1_pc_carry_25 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cin In - 11.885 -
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cout Out 0.027 11.912 -
un1_pc_carry_26 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cin In - 11.912 -
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cout Out 0.027 11.939 -
un1_pc_carry_27 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cin In - 11.939 -
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cout Out 0.027 11.966 -
un1_pc_carry_28 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cin In - 11.966 -
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cout Out 0.027 11.993 -
un1_pc_carry_29 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cin In - 11.993 -
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cout Out 0.027 12.020 -
un1_pc_carry_30 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell cin In - 12.020 -
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell combout Out 0.478 12.498 -
un1_pc_add31 Net - - 0.274 - 2
pc.r32_o[31] cyclone_lcell_ff datad In - 12.773 -
=============================================================================================================================
Total path delay (propagation time + setup) of 12.802 is 4.932(38.5%) logic and 7.870(61.5%) route.
 
 
Path information for path number 3:
Requested Period: 10.881
- Setup time: 0.029
= Required time: 10.852
 
- Propagation time: 12.751
= Slack (non-critical) : -1.898
 
Number of logic level(s): 43
Starting point: rnd_pass1.r5_o[2] / regout
Ending point: pc.r32_o[31] / datad
The start point is clocked by mips_core|clk [rising] on pin clk
The end point is clocked by mips_core|clk [rising] on pin clk
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
rnd_pass1.r5_o[2] cyclone_lcell_ff regout Out 0.173 0.173 -
r5_o_2 Net - - 0.635 - 6
iforward.fw_alu_rs.un14_mux_fw_2 cyclone_lcell datab In - 0.808 -
iforward.fw_alu_rs.un14_mux_fw_2 cyclone_lcell combout Out 0.340 1.148 -
un14_mux_fw_2 Net - - 0.455 - 4
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell datad In - 1.603 -
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell combout Out 0.088 1.691 -
mux_fw_1_a Net - - 0.245 - 1
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell datad In - 1.936 -
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell combout Out 0.088 2.024 -
mux_fw_1 Net - - 1.253 - 34
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell datad In - 3.278 -
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell combout Out 0.088 3.366 -
un32_mux_fw Net - - 0.274 - 2
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell datad In - 3.640 -
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell combout Out 0.088 3.728 -
N_30_i_0_s2 Net - - 1.218 - 32
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell datac In - 4.946 -
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell combout Out 0.225 5.171 -
dout_iv_a_2 Net - - 0.274 - 2
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell datad In - 5.445 -
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell combout Out 0.088 5.533 -
iRF_stage.rs_fwd_rs.dout_iv[4] Net - - 0.364 - 3
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell dataa In - 5.898 -
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell combout Out 0.454 6.352 -
res_2_NE_6 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell dataa In - 6.597 -
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell combout Out 0.454 7.051 -
res_2_NE_10_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE cyclone_lcell dataa In - 7.296 -
iRF_stage.i_cmp.res_2_NE cyclone_lcell combout Out 0.454 7.750 -
res_2_NE Net - - 0.274 - 2
iRF_stage.i_cmp.res_3_0 cyclone_lcell datad In - 8.025 -
iRF_stage.i_cmp.res_3_0 cyclone_lcell combout Out 0.088 8.113 -
res_3_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_7_0 cyclone_lcell datac In - 8.358 -
iRF_stage.i_cmp.res_7_0 cyclone_lcell combout Out 0.225 8.583 -
res_7_0 Net - - 1.166 - 29
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell datad In - 9.748 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell combout Out 0.088 9.836 -
un1_pc_prectl_1_0_a4[0] Net - - 0.455 - 4
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[3] cyclone_lcell datad In - 10.291 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[3] cyclone_lcell combout Out 0.088 10.379 -
un1_pc_prectl_1_0_a2_0_a2[3] Net - - 0.245 - 1
iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell datab In - 10.624 -
iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell cout Out 0.645 11.269 -
un1_pc_carry_3 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cin In - 11.269 -
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cout Out 0.027 11.296 -
un1_pc_carry_4 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cin In - 11.296 -
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cout Out 0.027 11.323 -
un1_pc_carry_5 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cin In - 11.323 -
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cout Out 0.027 11.350 -
un1_pc_carry_6 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cin In - 11.350 -
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cout Out 0.027 11.377 -
un1_pc_carry_7 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cin In - 11.377 -
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cout Out 0.027 11.404 -
un1_pc_carry_8 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cin In - 11.404 -
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cout Out 0.027 11.431 -
un1_pc_carry_9 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cin In - 11.431 -
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cout Out 0.027 11.458 -
un1_pc_carry_10 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cin In - 11.458 -
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cout Out 0.027 11.485 -
un1_pc_carry_11 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cin In - 11.485 -
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cout Out 0.027 11.512 -
un1_pc_carry_12 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cin In - 11.512 -
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cout Out 0.027 11.539 -
un1_pc_carry_13 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cin In - 11.539 -
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cout Out 0.027 11.566 -
un1_pc_carry_14 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cin In - 11.566 -
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cout Out 0.027 11.593 -
un1_pc_carry_15 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cin In - 11.593 -
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cout Out 0.027 11.620 -
un1_pc_carry_16 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cin In - 11.620 -
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cout Out 0.027 11.647 -
un1_pc_carry_17 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cin In - 11.647 -
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cout Out 0.027 11.674 -
un1_pc_carry_18 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cin In - 11.674 -
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cout Out 0.027 11.701 -
un1_pc_carry_19 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cin In - 11.701 -
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cout Out 0.027 11.728 -
un1_pc_carry_20 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cin In - 11.728 -
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cout Out 0.027 11.755 -
un1_pc_carry_21 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cin In - 11.755 -
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cout Out 0.027 11.782 -
un1_pc_carry_22 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cin In - 11.782 -
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cout Out 0.027 11.809 -
un1_pc_carry_23 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cin In - 11.809 -
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cout Out 0.027 11.836 -
un1_pc_carry_24 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cin In - 11.836 -
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cout Out 0.027 11.863 -
un1_pc_carry_25 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cin In - 11.863 -
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cout Out 0.027 11.890 -
un1_pc_carry_26 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cin In - 11.890 -
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cout Out 0.027 11.917 -
un1_pc_carry_27 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cin In - 11.917 -
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cout Out 0.027 11.944 -
un1_pc_carry_28 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cin In - 11.944 -
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cout Out 0.027 11.971 -
un1_pc_carry_29 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cin In - 11.971 -
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cout Out 0.027 11.998 -
un1_pc_carry_30 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell cin In - 11.998 -
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell combout Out 0.478 12.476 -
un1_pc_add31 Net - - 0.274 - 2
pc.r32_o[31] cyclone_lcell_ff datad In - 12.751 -
=============================================================================================================================
Total path delay (propagation time + setup) of 12.780 is 4.910(38.4%) logic and 7.870(61.6%) route.
 
 
Path information for path number 4:
Requested Period: 10.881
- Setup time: 0.029
= Required time: 10.852
 
- Propagation time: 12.751
= Slack (non-critical) : -1.898
 
Number of logic level(s): 43
Starting point: rnd_pass1.r5_o[2] / regout
Ending point: pc.r32_o[31] / datad
The start point is clocked by mips_core|clk [rising] on pin clk
The end point is clocked by mips_core|clk [rising] on pin clk
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
rnd_pass1.r5_o[2] cyclone_lcell_ff regout Out 0.173 0.173 -
r5_o_2 Net - - 0.635 - 6
iforward.fw_alu_rs.un14_mux_fw_2 cyclone_lcell datab In - 0.808 -
iforward.fw_alu_rs.un14_mux_fw_2 cyclone_lcell combout Out 0.340 1.148 -
un14_mux_fw_2 Net - - 0.455 - 4
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell datad In - 1.603 -
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell combout Out 0.088 1.691 -
mux_fw_1_a Net - - 0.245 - 1
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell datad In - 1.936 -
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell combout Out 0.088 2.024 -
mux_fw_1 Net - - 1.253 - 34
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell datad In - 3.278 -
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell combout Out 0.088 3.366 -
un32_mux_fw Net - - 0.274 - 2
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell datad In - 3.640 -
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell combout Out 0.088 3.728 -
N_30_i_0_s2 Net - - 1.218 - 32
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell datac In - 4.946 -
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell combout Out 0.225 5.171 -
dout_iv_a_2 Net - - 0.274 - 2
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell datad In - 5.445 -
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell combout Out 0.088 5.533 -
iRF_stage.rs_fwd_rs.dout_iv[4] Net - - 0.364 - 3
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell dataa In - 5.898 -
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell combout Out 0.454 6.352 -
res_2_NE_6 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell dataa In - 6.597 -
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell combout Out 0.454 7.051 -
res_2_NE_10_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE cyclone_lcell dataa In - 7.296 -
iRF_stage.i_cmp.res_2_NE cyclone_lcell combout Out 0.454 7.750 -
res_2_NE Net - - 0.274 - 2
iRF_stage.i_cmp.res_6_0 cyclone_lcell datac In - 8.025 -
iRF_stage.i_cmp.res_6_0 cyclone_lcell combout Out 0.225 8.250 -
res_6_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_7_0 cyclone_lcell datad In - 8.495 -
iRF_stage.i_cmp.res_7_0 cyclone_lcell combout Out 0.088 8.583 -
res_7_0 Net - - 1.166 - 29
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell datad In - 9.748 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell combout Out 0.088 9.836 -
un1_pc_prectl_1_0_a4[0] Net - - 0.455 - 4
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[3] cyclone_lcell datad In - 10.291 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[3] cyclone_lcell combout Out 0.088 10.379 -
un1_pc_prectl_1_0_a2_0_a2[3] Net - - 0.245 - 1
iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell datab In - 10.624 -
iRF_stage.i_pc_gen.un1_pc_add3 cyclone_lcell cout Out 0.645 11.269 -
un1_pc_carry_3 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cin In - 11.269 -
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cout Out 0.027 11.296 -
un1_pc_carry_4 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cin In - 11.296 -
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cout Out 0.027 11.323 -
un1_pc_carry_5 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cin In - 11.323 -
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cout Out 0.027 11.350 -
un1_pc_carry_6 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cin In - 11.350 -
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cout Out 0.027 11.377 -
un1_pc_carry_7 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cin In - 11.377 -
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cout Out 0.027 11.404 -
un1_pc_carry_8 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cin In - 11.404 -
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cout Out 0.027 11.431 -
un1_pc_carry_9 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cin In - 11.431 -
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cout Out 0.027 11.458 -
un1_pc_carry_10 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cin In - 11.458 -
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cout Out 0.027 11.485 -
un1_pc_carry_11 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cin In - 11.485 -
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cout Out 0.027 11.512 -
un1_pc_carry_12 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cin In - 11.512 -
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cout Out 0.027 11.539 -
un1_pc_carry_13 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cin In - 11.539 -
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cout Out 0.027 11.566 -
un1_pc_carry_14 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cin In - 11.566 -
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cout Out 0.027 11.593 -
un1_pc_carry_15 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cin In - 11.593 -
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cout Out 0.027 11.620 -
un1_pc_carry_16 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cin In - 11.620 -
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cout Out 0.027 11.647 -
un1_pc_carry_17 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cin In - 11.647 -
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cout Out 0.027 11.674 -
un1_pc_carry_18 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cin In - 11.674 -
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cout Out 0.027 11.701 -
un1_pc_carry_19 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cin In - 11.701 -
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cout Out 0.027 11.728 -
un1_pc_carry_20 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cin In - 11.728 -
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cout Out 0.027 11.755 -
un1_pc_carry_21 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cin In - 11.755 -
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cout Out 0.027 11.782 -
un1_pc_carry_22 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cin In - 11.782 -
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cout Out 0.027 11.809 -
un1_pc_carry_23 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cin In - 11.809 -
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cout Out 0.027 11.836 -
un1_pc_carry_24 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cin In - 11.836 -
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cout Out 0.027 11.863 -
un1_pc_carry_25 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cin In - 11.863 -
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cout Out 0.027 11.890 -
un1_pc_carry_26 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cin In - 11.890 -
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cout Out 0.027 11.917 -
un1_pc_carry_27 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cin In - 11.917 -
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cout Out 0.027 11.944 -
un1_pc_carry_28 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cin In - 11.944 -
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cout Out 0.027 11.971 -
un1_pc_carry_29 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cin In - 11.971 -
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cout Out 0.027 11.998 -
un1_pc_carry_30 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell cin In - 11.998 -
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell combout Out 0.478 12.476 -
un1_pc_add31 Net - - 0.274 - 2
pc.r32_o[31] cyclone_lcell_ff datad In - 12.751 -
=============================================================================================================================
Total path delay (propagation time + setup) of 12.780 is 4.910(38.4%) logic and 7.870(61.6%) route.
 
 
Path information for path number 5:
Requested Period: 10.881
- Setup time: 0.029
= Required time: 10.852
 
- Propagation time: 12.746
= Slack (non-critical) : -1.893
 
Number of logic level(s): 42
Starting point: rnd_pass1.r5_o[3] / regout
Ending point: pc.r32_o[31] / datad
The start point is clocked by mips_core|clk [rising] on pin clk
The end point is clocked by mips_core|clk [rising] on pin clk
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
rnd_pass1.r5_o[3] cyclone_lcell_ff regout Out 0.173 0.173 -
r5_o_3 Net - - 0.635 - 6
iforward.fw_alu_rs.un14_mux_fw_0 cyclone_lcell datac In - 0.808 -
iforward.fw_alu_rs.un14_mux_fw_0 cyclone_lcell combout Out 0.225 1.033 -
un14_mux_fw_0 Net - - 0.455 - 4
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell datac In - 1.488 -
iforward.fw_cmp_rs.mux_fw_1_a cyclone_lcell combout Out 0.225 1.713 -
mux_fw_1_a Net - - 0.245 - 1
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell datad In - 1.958 -
iforward.fw_cmp_rs.mux_fw_1 cyclone_lcell combout Out 0.088 2.046 -
mux_fw_1 Net - - 1.253 - 34
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell datad In - 3.300 -
iforward.fw_cmp_rs.un32_mux_fw cyclone_lcell combout Out 0.088 3.388 -
un32_mux_fw Net - - 0.274 - 2
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell datad In - 3.662 -
iRF_stage.reg_bank.N_30_i_0_s2 cyclone_lcell combout Out 0.088 3.750 -
N_30_i_0_s2 Net - - 1.218 - 32
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell datac In - 4.968 -
iRF_stage.rs_fwd_rs.dout_iv_a[4] cyclone_lcell combout Out 0.225 5.193 -
dout_iv_a_2 Net - - 0.274 - 2
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell datad In - 5.467 -
retiRF_stage.rs_fwd_rs.dout_iv[4] cyclone_lcell combout Out 0.088 5.555 -
iRF_stage.rs_fwd_rs.dout_iv[4] Net - - 0.364 - 3
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell dataa In - 5.920 -
iRF_stage.i_cmp.res_2_NE_6 cyclone_lcell combout Out 0.454 6.374 -
res_2_NE_6 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell dataa In - 6.619 -
iRF_stage.i_cmp.res_2_NE_10_0 cyclone_lcell combout Out 0.454 7.073 -
res_2_NE_10_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_2_NE cyclone_lcell dataa In - 7.318 -
iRF_stage.i_cmp.res_2_NE cyclone_lcell combout Out 0.454 7.772 -
res_2_NE Net - - 0.274 - 2
iRF_stage.i_cmp.res_3_0 cyclone_lcell datad In - 8.047 -
iRF_stage.i_cmp.res_3_0 cyclone_lcell combout Out 0.088 8.135 -
res_3_0 Net - - 0.245 - 1
iRF_stage.i_cmp.res_7_0 cyclone_lcell datac In - 8.380 -
iRF_stage.i_cmp.res_7_0 cyclone_lcell combout Out 0.225 8.605 -
res_7_0 Net - - 1.166 - 29
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell datad In - 9.770 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a4[0] cyclone_lcell combout Out 0.088 9.858 -
un1_pc_prectl_1_0_a4[0] Net - - 0.455 - 4
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[4] cyclone_lcell datad In - 10.313 -
iRF_stage.i_pc_gen.un1_pc_prectl_1_0_a2_0_a2[4] cyclone_lcell combout Out 0.088 10.401 -
un1_pc_prectl_1_0_a2_0_a2[4] Net - - 0.245 - 1
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell datab In - 10.646 -
iRF_stage.i_pc_gen.un1_pc_add4 cyclone_lcell cout Out 0.645 11.291 -
un1_pc_carry_4 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cin In - 11.291 -
iRF_stage.i_pc_gen.un1_pc_add5 cyclone_lcell cout Out 0.027 11.318 -
un1_pc_carry_5 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cin In - 11.318 -
iRF_stage.i_pc_gen.un1_pc_add6 cyclone_lcell cout Out 0.027 11.345 -
un1_pc_carry_6 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cin In - 11.345 -
iRF_stage.i_pc_gen.un1_pc_add7 cyclone_lcell cout Out 0.027 11.372 -
un1_pc_carry_7 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cin In - 11.372 -
iRF_stage.i_pc_gen.un1_pc_add8 cyclone_lcell cout Out 0.027 11.399 -
un1_pc_carry_8 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cin In - 11.399 -
iRF_stage.i_pc_gen.un1_pc_add9 cyclone_lcell cout Out 0.027 11.426 -
un1_pc_carry_9 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cin In - 11.426 -
iRF_stage.i_pc_gen.un1_pc_add10 cyclone_lcell cout Out 0.027 11.453 -
un1_pc_carry_10 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cin In - 11.453 -
iRF_stage.i_pc_gen.un1_pc_add11 cyclone_lcell cout Out 0.027 11.480 -
un1_pc_carry_11 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cin In - 11.480 -
iRF_stage.i_pc_gen.un1_pc_add12 cyclone_lcell cout Out 0.027 11.507 -
un1_pc_carry_12 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cin In - 11.507 -
iRF_stage.i_pc_gen.un1_pc_add13 cyclone_lcell cout Out 0.027 11.534 -
un1_pc_carry_13 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cin In - 11.534 -
iRF_stage.i_pc_gen.un1_pc_add14 cyclone_lcell cout Out 0.027 11.561 -
un1_pc_carry_14 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cin In - 11.561 -
iRF_stage.i_pc_gen.un1_pc_add15 cyclone_lcell cout Out 0.027 11.588 -
un1_pc_carry_15 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cin In - 11.588 -
iRF_stage.i_pc_gen.un1_pc_add16 cyclone_lcell cout Out 0.027 11.615 -
un1_pc_carry_16 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cin In - 11.615 -
iRF_stage.i_pc_gen.un1_pc_add17 cyclone_lcell cout Out 0.027 11.642 -
un1_pc_carry_17 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cin In - 11.642 -
iRF_stage.i_pc_gen.un1_pc_add18 cyclone_lcell cout Out 0.027 11.669 -
un1_pc_carry_18 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cin In - 11.669 -
iRF_stage.i_pc_gen.un1_pc_add19 cyclone_lcell cout Out 0.027 11.696 -
un1_pc_carry_19 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cin In - 11.696 -
iRF_stage.i_pc_gen.un1_pc_add20 cyclone_lcell cout Out 0.027 11.723 -
un1_pc_carry_20 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cin In - 11.723 -
iRF_stage.i_pc_gen.un1_pc_add21 cyclone_lcell cout Out 0.027 11.750 -
un1_pc_carry_21 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cin In - 11.750 -
iRF_stage.i_pc_gen.un1_pc_add22 cyclone_lcell cout Out 0.027 11.777 -
un1_pc_carry_22 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cin In - 11.777 -
iRF_stage.i_pc_gen.un1_pc_add23 cyclone_lcell cout Out 0.027 11.804 -
un1_pc_carry_23 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cin In - 11.804 -
iRF_stage.i_pc_gen.un1_pc_add24 cyclone_lcell cout Out 0.027 11.831 -
un1_pc_carry_24 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cin In - 11.831 -
iRF_stage.i_pc_gen.un1_pc_add25 cyclone_lcell cout Out 0.027 11.858 -
un1_pc_carry_25 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cin In - 11.858 -
iRF_stage.i_pc_gen.un1_pc_add26 cyclone_lcell cout Out 0.027 11.885 -
un1_pc_carry_26 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cin In - 11.885 -
iRF_stage.i_pc_gen.un1_pc_add27 cyclone_lcell cout Out 0.027 11.912 -
un1_pc_carry_27 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cin In - 11.912 -
iRF_stage.i_pc_gen.un1_pc_add28 cyclone_lcell cout Out 0.027 11.939 -
un1_pc_carry_28 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cin In - 11.939 -
iRF_stage.i_pc_gen.un1_pc_add29 cyclone_lcell cout Out 0.027 11.966 -
un1_pc_carry_29 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cin In - 11.966 -
iRF_stage.i_pc_gen.un1_pc_add30 cyclone_lcell cout Out 0.027 11.993 -
un1_pc_carry_30 Net - - 0.000 - 1
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell cin In - 11.993 -
iRF_stage.i_pc_gen.un1_pc_add31 cyclone_lcell combout Out 0.478 12.471 -
un1_pc_add31 Net - - 0.274 - 2
pc.r32_o[31] cyclone_lcell_ff datad In - 12.746 -
=============================================================================================================================
Total path delay (propagation time + setup) of 12.775 is 4.905(38.4%) logic and 7.870(61.6%) route.
 
 
 
 
====================================
<a name=clockReport28>Detailed Report for Clock: System
====================================
 
 
 
<a name=startingSlack29>Starting Points with Worst Slack
********************************
 
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------
decoder_pipe.idecoder.fsm_dly_1[1] System SYNLPM_LATR1 Q[0] BUS197_1 0.173 -0.179
decoder_pipe.idecoder.fsm_dly_1[2] System SYNLPM_LATR1 Q[0] BUS197_2 0.173 -0.179
MEM_CTL.i_mem_dout_ctl.dout_1[0] System SYNLPM_LATR1 Q[0] BUS22401_0 0.173 10.434
MEM_CTL.i_mem_dout_ctl.dout_1[1] System SYNLPM_LATR1 Q[0] BUS22401_1 0.173 10.434
MEM_CTL.i_mem_dout_ctl.dout_1[2] System SYNLPM_LATR1 Q[0] BUS22401_2 0.173 10.434
MEM_CTL.i_mem_dout_ctl.dout_1[3] System SYNLPM_LATR1 Q[0] BUS22401_3 0.173 10.434
MEM_CTL.i_mem_dout_ctl.dout_1[4] System SYNLPM_LATR1 Q[0] BUS22401_4 0.173 10.434
MEM_CTL.i_mem_dout_ctl.dout_1[5] System SYNLPM_LATR1 Q[0] BUS22401_5 0.173 10.434
MEM_CTL.i_mem_dout_ctl.dout_1[6] System SYNLPM_LATR1 Q[0] BUS22401_6 0.173 10.434
MEM_CTL.i_mem_dout_ctl.dout_1[7] System SYNLPM_LATR1 Q[0] BUS22401_7 0.173 10.434
================================================================================================================
 
 
<a name=endingSlack30>Ending Points with Worst Slack
******************************
 
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------------------
decoder_pipe.idecoder.fsm_dly_1[1] System SYNLPM_LATR1 DATA[0] fsm_dly_2_i_m3_0[1] 0.986 -0.179
decoder_pipe.idecoder.fsm_dly_1[2] System SYNLPM_LATR1 DATA[0] fsm_dly_2_0_0[2] 0.986 -0.179
iRF_stage.MIAN_FSM.CurrState_Sreg0[1] System cyclone_lcell_ff datad CurrState_Sreg0_ns_0_0_a[1] 10.852 8.466
iRF_stage.MIAN_FSM.CurrState_Sreg0[1] System cyclone_lcell_ff datac CurrState_Sreg0_ns_0_0_a2[1] 10.852 9.074
iRF_stage.MIAN_FSM.CurrState_Sreg0[8] System cyclone_lcell_ff datac CurrState_Sreg0_ns_0_0_a_x[8] 10.852 9.436
iRF_stage.MIAN_FSM.CurrState_Sreg0[2] System cyclone_lcell_ff datab BUS197_1 10.852 10.021
iRF_stage.MIAN_FSM.CurrState_Sreg0[2] System cyclone_lcell_ff datac BUS197_2 10.852 10.021
iRF_stage.MIAN_FSM.CurrState_Sreg0[3] System cyclone_lcell_ff datab BUS197_1 10.852 10.021
iRF_stage.MIAN_FSM.CurrState_Sreg0[3] System cyclone_lcell_ff datac BUS197_2 10.852 10.021
iRF_stage.MIAN_FSM.CurrState_Sreg0[4] System cyclone_lcell_ff datab BUS197_2 10.852 10.021
==============================================================================================================================================
 
 
 
<a name=worstPaths31>Worst Path Information
<a href="F:\a\syn\mips_core\mips_core.srr:fp:563538:564246:@XP_NAMES">View Worst Path in Analyst</a>
***********************
 
 
Path information for path number 1:
Requested Period: 1.015
- Setup time: 0.029
= Required time: 0.986
 
- Propagation time: 1.165
= Slack (non-critical) : -0.179
 
Number of logic level(s): 1
Starting point: decoder_pipe.idecoder.fsm_dly_1[1] / Q[0]
Ending point: decoder_pipe.idecoder.fsm_dly_1[1] / DATA[0]
The start point is clocked by System [rising] on pin GATE
The end point is clocked by System [rising] on pin GATE
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
decoder_pipe.idecoder.fsm_dly_1[1] SYNLPM_LATR1 Q[0] Out 0.173 0.173 -
BUS197_1 Net - - 0.658 - 7
decoder_pipe.idecoder.fsm_dly_2_i_m3_0[1] cyclone_lcell datad In - 0.831 -
decoder_pipe.idecoder.fsm_dly_2_i_m3_0[1] cyclone_lcell combout Out 0.088 0.919 -
fsm_dly_2_i_m3_0[1] Net - - 0.245 - 1
decoder_pipe.idecoder.fsm_dly_1[1] SYNLPM_LATR1 DATA[0] In - 1.165 -
====================================================================================================================
Total path delay (propagation time + setup) of 1.194 is 0.290(24.3%) logic and 0.904(75.7%) route.
 
 
Path information for path number 2:
Requested Period: 1.015
- Setup time: 0.029
= Required time: 0.986
 
- Propagation time: 1.165
= Slack (non-critical) : -0.179
 
Number of logic level(s): 1
Starting point: decoder_pipe.idecoder.fsm_dly_1[2] / Q[0]
Ending point: decoder_pipe.idecoder.fsm_dly_1[2] / DATA[0]
The start point is clocked by System [rising] on pin GATE
The end point is clocked by System [rising] on pin GATE
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
decoder_pipe.idecoder.fsm_dly_1[2] SYNLPM_LATR1 Q[0] Out 0.173 0.173 -
BUS197_2 Net - - 0.658 - 7
decoder_pipe.idecoder.fsm_dly_2_0_0[2] cyclone_lcell datad In - 0.831 -
decoder_pipe.idecoder.fsm_dly_2_0_0[2] cyclone_lcell combout Out 0.088 0.919 -
fsm_dly_2_0_0[2] Net - - 0.245 - 1
decoder_pipe.idecoder.fsm_dly_1[2] SYNLPM_LATR1 DATA[0] In - 1.165 -
=================================================================================================================
Total path delay (propagation time + setup) of 1.194 is 0.290(24.3%) logic and 0.904(75.7%) route.
 
 
Path information for path number 3:
Requested Period: 10.881
- Setup time: 0.029
= Required time: 10.852
 
- Propagation time: 2.386
= Slack (non-critical) : 8.466
 
Number of logic level(s): 3
Starting point: decoder_pipe.idecoder.fsm_dly_1[1] / Q[0]
Ending point: iRF_stage.MIAN_FSM.CurrState_Sreg0[1] / datad
The start point is clocked by mips_core|clk [rising] on pin GATE
The end point is clocked by mips_core|clk [rising] on pin clk
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------
decoder_pipe.idecoder.fsm_dly_1[1] SYNLPM_LATR1 Q[0] Out 0.173 0.173 -
BUS197_1 Net - - 0.658 - 7
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_o2_x[1] cyclone_lcell datab In - 0.831 -
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_o2_x[1] cyclone_lcell combout Out 0.340 1.171 -
CurrState_Sreg0_ns_0_0_o2_x[1] Net - - 0.274 - 2
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a2_0_0[1] cyclone_lcell datac In - 1.446 -
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a2_0_0[1] cyclone_lcell combout Out 0.225 1.671 -
CurrState_Sreg0_ns_0_0_a2_0_0[1] Net - - 0.245 - 1
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a[1] cyclone_lcell datac In - 1.916 -
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a[1] cyclone_lcell combout Out 0.225 2.141 -
CurrState_Sreg0_ns_0_0_a[1] Net - - 0.245 - 1
iRF_stage.MIAN_FSM.CurrState_Sreg0[1] cyclone_lcell_ff datad In - 2.386 -
=================================================================================================================================
Total path delay (propagation time + setup) of 2.415 is 0.992(41.1%) logic and 1.423(58.9%) route.
 
 
Path information for path number 4:
Requested Period: 10.881
- Setup time: 0.029
= Required time: 10.852
 
- Propagation time: 2.271
= Slack (non-critical) : 8.581
 
Number of logic level(s): 3
Starting point: decoder_pipe.idecoder.fsm_dly_1[2] / Q[0]
Ending point: iRF_stage.MIAN_FSM.CurrState_Sreg0[1] / datad
The start point is clocked by mips_core|clk [rising] on pin GATE
The end point is clocked by mips_core|clk [rising] on pin clk
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------
decoder_pipe.idecoder.fsm_dly_1[2] SYNLPM_LATR1 Q[0] Out 0.173 0.173 -
BUS197_2 Net - - 0.658 - 7
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_o2_x[1] cyclone_lcell datac In - 0.831 -
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_o2_x[1] cyclone_lcell combout Out 0.225 1.056 -
CurrState_Sreg0_ns_0_0_o2_x[1] Net - - 0.274 - 2
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a2_0_0[1] cyclone_lcell datac In - 1.331 -
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a2_0_0[1] cyclone_lcell combout Out 0.225 1.556 -
CurrState_Sreg0_ns_0_0_a2_0_0[1] Net - - 0.245 - 1
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a[1] cyclone_lcell datac In - 1.801 -
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a[1] cyclone_lcell combout Out 0.225 2.026 -
CurrState_Sreg0_ns_0_0_a[1] Net - - 0.245 - 1
iRF_stage.MIAN_FSM.CurrState_Sreg0[1] cyclone_lcell_ff datad In - 2.271 -
=================================================================================================================================
Total path delay (propagation time + setup) of 2.300 is 0.877(38.1%) logic and 1.423(61.9%) route.
 
 
Path information for path number 5:
Requested Period: 10.881
- Setup time: 0.029
= Required time: 10.852
 
- Propagation time: 1.779
= Slack (non-critical) : 9.074
 
Number of logic level(s): 2
Starting point: decoder_pipe.idecoder.fsm_dly_1[1] / Q[0]
Ending point: iRF_stage.MIAN_FSM.CurrState_Sreg0[1] / datac
The start point is clocked by mips_core|clk [rising] on pin GATE
The end point is clocked by mips_core|clk [rising] on pin clk
 
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
decoder_pipe.idecoder.fsm_dly_1[1] SYNLPM_LATR1 Q[0] Out 0.173 0.173 -
BUS197_1 Net - - 0.658 - 7
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_o2_x[1] cyclone_lcell datab In - 0.831 -
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_o2_x[1] cyclone_lcell combout Out 0.340 1.171 -
CurrState_Sreg0_ns_0_0_o2_x[1] Net - - 0.274 - 2
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a2[1] cyclone_lcell datad In - 1.446 -
iRF_stage.MIAN_FSM.CurrState_Sreg0_ns_0_0_a2[1] cyclone_lcell combout Out 0.088 1.534 -
CurrState_Sreg0_ns_0_0_a2[1] Net - - 0.245 - 1
iRF_stage.MIAN_FSM.CurrState_Sreg0[1] cyclone_lcell_ff datac In - 1.779 -
===============================================================================================================================
Total path delay (propagation time + setup) of 1.808 is 0.630(34.8%) logic and 1.178(65.2%) route.
 
 
 
##### END OF TIMING REPORT #####]
 
<a name=areaReport32>##### START OF AREA REPORT #####[
Design view:work.mips_core(verilog)
Selecting part EP1C6Q240C6
@N:<a href="@N:FA174:@XP_HELP">FA174</a> : <!@TM:1190195874> | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
 
I/O ATOMs: 300
 
Total LUTs: 2992 of 5980 (50%)
Logic resources: 3054 ATOMs of 5980 (51%)
ATOM count by mode:
normal: 2706
arithmetic: 348
 
ShiftTap: 0 (0 registers)
Total ESB: 2048 bits (2% of 81920)
 
LPM latches: 73
 
ATOMs using regout pin: 603
also using enable pin: 203
also using combout pin: 167
ATOMs using combout pin: 2519
Number of Inputs on ATOMs: 11146
Number of Nets: 9381
 
##### END OF AREA REPORT #####]
 
Mapper successful!
Process took 0h:4m:24s realtime, 0h:4m:24s cputime
###########################################################]
/verif/mips_core.vif
0,0 → 1,606
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
 
# Set logfile options
vif_set_result_file mips_core.vlf
 
# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Altera
 
# RTL and technology files
vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -original -verilog ../../rtl/verilog/ctl_fsm.v
vif_add_file -original -verilog ../../rtl/verilog/decode_pipe.v
vif_add_file -original -verilog ../../rtl/verilog/dvc.v
vif_add_file -original -verilog ../../rtl/verilog/EXEC_stage.v
vif_add_file -original -verilog ../../rtl/verilog/fifo.v
vif_add_file -original -verilog ../../rtl/verilog/forward.v
vif_add_file -original -verilog ../../rtl/verilog/mem_module.v
vif_add_file -original -verilog ../../rtl/verilog/mips_core.v
vif_add_file -original -verilog ../../rtl/verilog/mips_dvc.v
vif_add_file -original -verilog ../../rtl/verilog/mips_sys.v
vif_add_file -original -verilog ../../rtl/verilog/mips_uart.v
vif_add_file -original -verilog ../../rtl/verilog/ram_module.v
vif_add_file -original -verilog ../../rtl/verilog/RF_components.v
vif_add_file -original -verilog ../../rtl/verilog/RF_stage.v
vif_add_file -original -verilog ../../rtl/verilog/sim_ram.v
vif_add_file -original -verilog ../../rtl/verilog/tools.v
vif_add_file -original -verilog ../../rtl/verilog/fifo512_cyclone.v
vif_set_top_module -original -top mips_core
vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -translated -verilog mips_core.vqm
vif_set_top_module -translated -top mips_core
# Read FSM encoding
vif_set_fsm -fsm fsm_0
vif_set_fsmreg -original -fsm fsm_0 iRF_stage/MIAN_FSM/CurrState_Sreg0[3:0]
vif_set_fsmreg -translated -fsm fsm_0 iRF_stage/MIAN_FSM/CurrState_Sreg0[8:0]
vif_set_state_map -fsm fsm_0 -original "0000" -translated "000000001"
vif_set_state_map -fsm fsm_0 -original "0001" -translated "000000010"
vif_set_state_map -fsm fsm_0 -original "0010" -translated "000000100"
vif_set_state_map -fsm fsm_0 -original "0011" -translated "000001000"
vif_set_state_map -fsm fsm_0 -original "0100" -translated "000010000"
vif_set_state_map -fsm fsm_0 -original "0101" -translated "000100000"
vif_set_state_map -fsm fsm_0 -original "0110" -translated "001000000"
vif_set_state_map -fsm fsm_0 -original "0111" -translated "010000000"
vif_set_state_map -fsm fsm_0 -original "1000" -translated "100000000"
 
# Memory map points
 
# SRL map points
 
# Compiler constant registers
 
# Compiler constant latches
 
# Compiler RTL sequential redundancies
 
# RTL sequential redundancies
vif_set_merge -original iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged iexec_stage/MIPS_alu/muldiv_ff/op2_reged[32]
vif_set_merge -original alu_pass0/r32_o[0] MEM_CTL/dmem_ctl_post/byte_addr_o[0]
vif_set_merge -original alu_pass0/r32_o[1] MEM_CTL/dmem_ctl_post/byte_addr_o[1]
 
# Technology sequential redundancies
 
# Inversion map points
vif_set_map_point -register -inverted -original iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
 
# Port mappping and directions
 
# Black box mapping
vif_set_black_box synplicity_altsyncram4_r_w
 
vif_set_map_point -blackbox -original iRF_stage/reg_bank/reg_bank/altsyncram -translated iRF_stage/reg_bank/reg_bank.I_1
vif_set_map_point -blackbox -original iRF_stage/reg_bank/reg_bank_1/altsyncram -translated iRF_stage/reg_bank/reg_bank_1.I_1
 
# Other sequential cells, including multidimensional arrays
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[7] -translated MEM_CTL/i_mem_dout_ctl/dout_1_7__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[6] -translated MEM_CTL/i_mem_dout_ctl/dout_1_6__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[5] -translated MEM_CTL/i_mem_dout_ctl/dout_1_5__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[4] -translated MEM_CTL/i_mem_dout_ctl/dout_1_4__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[3] -translated MEM_CTL/i_mem_dout_ctl/dout_1_3__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[2] -translated MEM_CTL/i_mem_dout_ctl/dout_1_2__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[1] -translated MEM_CTL/i_mem_dout_ctl/dout_1_1__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[0] -translated MEM_CTL/i_mem_dout_ctl/dout_1_0__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[15] -translated MEM_CTL/i_mem_dout_ctl/dout_1_15__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[14] -translated MEM_CTL/i_mem_dout_ctl/dout_1_14__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[13] -translated MEM_CTL/i_mem_dout_ctl/dout_1_13__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[12] -translated MEM_CTL/i_mem_dout_ctl/dout_1_12__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[11] -translated MEM_CTL/i_mem_dout_ctl/dout_1_11__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[10] -translated MEM_CTL/i_mem_dout_ctl/dout_1_10__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[9] -translated MEM_CTL/i_mem_dout_ctl/dout_1_9__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[8] -translated MEM_CTL/i_mem_dout_ctl/dout_1_8__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[31] -translated MEM_CTL/i_mem_dout_ctl/dout_1_31__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[30] -translated MEM_CTL/i_mem_dout_ctl/dout_1_30__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[29] -translated MEM_CTL/i_mem_dout_ctl/dout_1_29__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[28] -translated MEM_CTL/i_mem_dout_ctl/dout_1_28__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[27] -translated MEM_CTL/i_mem_dout_ctl/dout_1_27__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[26] -translated MEM_CTL/i_mem_dout_ctl/dout_1_26__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[25] -translated MEM_CTL/i_mem_dout_ctl/dout_1_25__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[24] -translated MEM_CTL/i_mem_dout_ctl/dout_1_24__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[23] -translated MEM_CTL/i_mem_dout_ctl/dout_1_23__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[22] -translated MEM_CTL/i_mem_dout_ctl/dout_1_22__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[21] -translated MEM_CTL/i_mem_dout_ctl/dout_1_21__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[20] -translated MEM_CTL/i_mem_dout_ctl/dout_1_20__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[19] -translated MEM_CTL/i_mem_dout_ctl/dout_1_19__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[18] -translated MEM_CTL/i_mem_dout_ctl/dout_1_18__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[17] -translated MEM_CTL/i_mem_dout_ctl/dout_1_17__Z
vif_set_map_point -latch -original MEM_CTL/i_mem_dout_ctl/dout[16] -translated MEM_CTL/i_mem_dout_ctl/dout_1_16__Z
vif_set_map_point -latch -original decoder_pipe/idecoder/fsm_dly[2] -translated decoder_pipe/idecoder/fsm_dly_1_2__Z
vif_set_map_point -latch -original decoder_pipe/idecoder/fsm_dly[1] -translated decoder_pipe/idecoder/fsm_dly_1_1__Z
 
# Constant Registers
 
# Retimed Registers
vif_set_sequential_verify -retimed -register -original MEM_CTL/dmem_ctl_post/ctl_o[0] -translated MEM_CTL/dmem_ctl_post/ctl_o_0__Z
vif_set_sequential_verify -retimed -register -original MEM_CTL/dmem_ctl_post/ctl_o[1] -translated MEM_CTL/dmem_ctl_post/ctl_o_1__Z
vif_set_sequential_verify -retimed -register -original MEM_CTL/dmem_ctl_post/ctl_o[2] -translated MEM_CTL/dmem_ctl_post/ctl_o_2__Z
vif_set_sequential_verify -retimed -register -original MEM_CTL/dmem_ctl_post/ctl_o[3] -translated MEM_CTL/dmem_ctl_post/ctl_o_3__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/delay_counter_Sreg0[2] -translated iRF_stage/MIAN_FSM/delay_counter_Sreg0_2__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/delay_counter_Sreg0[3] -translated iRF_stage/MIAN_FSM/delay_counter_Sreg0_3__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/delay_counter_Sreg0[4] -translated iRF_stage/MIAN_FSM/delay_counter_Sreg0_4__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/delay_counter_Sreg0[5] -translated iRF_stage/MIAN_FSM/delay_counter_Sreg0_5__Z
# Retimed registers from FSM not handled in VIF
//vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z
# Retimed registers from FSM not handled in VIF
//vif_set_sequential_verify -retimed -register -original iRF_stage/MIAN_FSM/CurrState_Sreg0[6] -translated iRF_stage/MIAN_FSM/CurrState_Sreg0_6__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[24] -translated iRF_stage/ins_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[23] -translated iRF_stage/ins_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[20] -translated iRF_stage/ins_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[19] -translated iRF_stage/ins_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[16] -translated iRF_stage/ins_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[15] -translated iRF_stage/ins_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[12] -translated iRF_stage/ins_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[11] -translated iRF_stage/ins_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[8] -translated iRF_stage/ins_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[7] -translated iRF_stage/ins_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[4] -translated iRF_stage/ins_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[3] -translated iRF_stage/ins_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[0] -translated iRF_stage/ins_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[25] -translated iRF_stage/ins_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[22] -translated iRF_stage/ins_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[21] -translated iRF_stage/ins_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[18] -translated iRF_stage/ins_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[17] -translated iRF_stage/ins_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[14] -translated iRF_stage/ins_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[13] -translated iRF_stage/ins_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[10] -translated iRF_stage/ins_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[9] -translated iRF_stage/ins_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[6] -translated iRF_stage/ins_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[5] -translated iRF_stage/ins_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[2] -translated iRF_stage/ins_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/ins_reg/r32_o[1] -translated iRF_stage/ins_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wren -translated iRF_stage/reg_bank/r_wren_Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[0] -translated iRF_stage/reg_bank/r_rdaddress_a_0__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[1] -translated iRF_stage/reg_bank/r_rdaddress_a_1__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[2] -translated iRF_stage/reg_bank/r_rdaddress_a_2__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[3] -translated iRF_stage/reg_bank/r_rdaddress_a_3__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_a[4] -translated iRF_stage/reg_bank/r_rdaddress_a_4__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[0] -translated iRF_stage/reg_bank/r_rdaddress_b_0__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[1] -translated iRF_stage/reg_bank/r_rdaddress_b_1__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[2] -translated iRF_stage/reg_bank/r_rdaddress_b_2__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[3] -translated iRF_stage/reg_bank/r_rdaddress_b_3__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_rdaddress_b[4] -translated iRF_stage/reg_bank/r_rdaddress_b_4__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[0] -translated iRF_stage/reg_bank/r_data_0__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[1] -translated iRF_stage/reg_bank/r_data_1__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[2] -translated iRF_stage/reg_bank/r_data_2__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[3] -translated iRF_stage/reg_bank/r_data_3__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[4] -translated iRF_stage/reg_bank/r_data_4__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[5] -translated iRF_stage/reg_bank/r_data_5__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[6] -translated iRF_stage/reg_bank/r_data_6__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[7] -translated iRF_stage/reg_bank/r_data_7__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[8] -translated iRF_stage/reg_bank/r_data_8__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[9] -translated iRF_stage/reg_bank/r_data_9__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[10] -translated iRF_stage/reg_bank/r_data_10__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[11] -translated iRF_stage/reg_bank/r_data_11__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[12] -translated iRF_stage/reg_bank/r_data_12__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[13] -translated iRF_stage/reg_bank/r_data_13__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[14] -translated iRF_stage/reg_bank/r_data_14__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[15] -translated iRF_stage/reg_bank/r_data_15__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[16] -translated iRF_stage/reg_bank/r_data_16__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[17] -translated iRF_stage/reg_bank/r_data_17__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[18] -translated iRF_stage/reg_bank/r_data_18__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[19] -translated iRF_stage/reg_bank/r_data_19__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[20] -translated iRF_stage/reg_bank/r_data_20__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[21] -translated iRF_stage/reg_bank/r_data_21__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[22] -translated iRF_stage/reg_bank/r_data_22__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[23] -translated iRF_stage/reg_bank/r_data_23__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[24] -translated iRF_stage/reg_bank/r_data_24__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[25] -translated iRF_stage/reg_bank/r_data_25__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[26] -translated iRF_stage/reg_bank/r_data_26__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[27] -translated iRF_stage/reg_bank/r_data_27__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[28] -translated iRF_stage/reg_bank/r_data_28__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[29] -translated iRF_stage/reg_bank/r_data_29__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[30] -translated iRF_stage/reg_bank/r_data_30__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_data[31] -translated iRF_stage/reg_bank/r_data_31__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[0] -translated iRF_stage/reg_bank/r_wraddress_0__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[1] -translated iRF_stage/reg_bank/r_wraddress_1__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[2] -translated iRF_stage/reg_bank/r_wraddress_2__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[3] -translated iRF_stage/reg_bank/r_wraddress_3__Z
vif_set_sequential_verify -retimed -register -original iRF_stage/reg_bank/r_wraddress[4] -translated iRF_stage/reg_bank/r_wraddress_4__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/add1 -translated iexec_stage/MIPS_alu/muldiv_ff/add1_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/addop2 -translated iexec_stage/MIPS_alu/muldiv_ff/addop2_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/addnop2 -translated iexec_stage/MIPS_alu/muldiv_ff/addnop2_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/overflow -translated iexec_stage/MIPS_alu/muldiv_ff/overflow_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/sub_or_yn -translated iexec_stage/MIPS_alu/muldiv_ff/sub_or_yn_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/finish -translated iexec_stage/MIPS_alu/muldiv_ff/finish_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged -translated iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op1_sign_reged -translated iexec_stage/MIPS_alu/muldiv_ff/op1_sign_reged_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/start -translated iexec_stage/MIPS_alu/muldiv_ff/start_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/sign -translated iexec_stage/MIPS_alu/muldiv_ff/sign_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/mul -translated iexec_stage/MIPS_alu/muldiv_ff/mul_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/rdy -translated iexec_stage/MIPS_alu/muldiv_ff/rdy_Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[0] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_0__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[1] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_1__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[2] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_2__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[3] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_3__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[4] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_4__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[5] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_5__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[6] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_6__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[7] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_7__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[8] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_8__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[9] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_9__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[10] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_10__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[11] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_11__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[12] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_12__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[13] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_13__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[14] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_14__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[15] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_15__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[16] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_16__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[17] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_17__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[18] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_18__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[19] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_19__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[20] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_20__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[21] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_21__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[22] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_22__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[23] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_23__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[24] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_24__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[25] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_25__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[26] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_26__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[27] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_27__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[28] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_28__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[29] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_29__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[30] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_30__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/MIPS_alu/muldiv_ff/op2_reged[31] -translated iexec_stage/MIPS_alu/muldiv_ff/op2_reged_31__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[2] -translated iexec_stage/pc_nxt/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[3] -translated iexec_stage/pc_nxt/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[4] -translated iexec_stage/pc_nxt/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[5] -translated iexec_stage/pc_nxt/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[6] -translated iexec_stage/pc_nxt/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[7] -translated iexec_stage/pc_nxt/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[8] -translated iexec_stage/pc_nxt/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[9] -translated iexec_stage/pc_nxt/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[10] -translated iexec_stage/pc_nxt/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[11] -translated iexec_stage/pc_nxt/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[12] -translated iexec_stage/pc_nxt/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[13] -translated iexec_stage/pc_nxt/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[14] -translated iexec_stage/pc_nxt/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[15] -translated iexec_stage/pc_nxt/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[16] -translated iexec_stage/pc_nxt/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[17] -translated iexec_stage/pc_nxt/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[18] -translated iexec_stage/pc_nxt/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[19] -translated iexec_stage/pc_nxt/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[20] -translated iexec_stage/pc_nxt/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[21] -translated iexec_stage/pc_nxt/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[22] -translated iexec_stage/pc_nxt/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[23] -translated iexec_stage/pc_nxt/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[24] -translated iexec_stage/pc_nxt/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[25] -translated iexec_stage/pc_nxt/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[26] -translated iexec_stage/pc_nxt/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[27] -translated iexec_stage/pc_nxt/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[28] -translated iexec_stage/pc_nxt/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[29] -translated iexec_stage/pc_nxt/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[30] -translated iexec_stage/pc_nxt/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[31] -translated iexec_stage/pc_nxt/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[1] -translated iexec_stage/pc_nxt/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/pc_nxt/r32_o[0] -translated iexec_stage/pc_nxt/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[0] -translated iexec_stage/spc/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[1] -translated iexec_stage/spc/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[2] -translated iexec_stage/spc/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[3] -translated iexec_stage/spc/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[4] -translated iexec_stage/spc/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[5] -translated iexec_stage/spc/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[6] -translated iexec_stage/spc/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[7] -translated iexec_stage/spc/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[8] -translated iexec_stage/spc/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[9] -translated iexec_stage/spc/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[10] -translated iexec_stage/spc/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[11] -translated iexec_stage/spc/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[12] -translated iexec_stage/spc/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[13] -translated iexec_stage/spc/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[14] -translated iexec_stage/spc/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[15] -translated iexec_stage/spc/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[16] -translated iexec_stage/spc/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[17] -translated iexec_stage/spc/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[18] -translated iexec_stage/spc/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[19] -translated iexec_stage/spc/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[20] -translated iexec_stage/spc/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[21] -translated iexec_stage/spc/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[22] -translated iexec_stage/spc/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[23] -translated iexec_stage/spc/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[24] -translated iexec_stage/spc/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[25] -translated iexec_stage/spc/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[26] -translated iexec_stage/spc/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[27] -translated iexec_stage/spc/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[28] -translated iexec_stage/spc/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[29] -translated iexec_stage/spc/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[30] -translated iexec_stage/spc/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original iexec_stage/spc/r32_o[31] -translated iexec_stage/spc/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[0] -translated alu_pass0/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[1] -translated alu_pass0/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[2] -translated alu_pass0/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[3] -translated alu_pass0/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[4] -translated alu_pass0/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[5] -translated alu_pass0/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[6] -translated alu_pass0/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[7] -translated alu_pass0/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[8] -translated alu_pass0/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[9] -translated alu_pass0/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[10] -translated alu_pass0/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[11] -translated alu_pass0/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[12] -translated alu_pass0/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[13] -translated alu_pass0/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[14] -translated alu_pass0/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[15] -translated alu_pass0/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[16] -translated alu_pass0/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[17] -translated alu_pass0/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[18] -translated alu_pass0/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[19] -translated alu_pass0/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[20] -translated alu_pass0/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[21] -translated alu_pass0/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[22] -translated alu_pass0/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[23] -translated alu_pass0/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[24] -translated alu_pass0/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[25] -translated alu_pass0/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[26] -translated alu_pass0/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[27] -translated alu_pass0/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[28] -translated alu_pass0/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[29] -translated alu_pass0/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[30] -translated alu_pass0/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original alu_pass0/r32_o[31] -translated alu_pass0/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[0] -translated alu_pass1/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[1] -translated alu_pass1/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[2] -translated alu_pass1/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[3] -translated alu_pass1/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[4] -translated alu_pass1/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[5] -translated alu_pass1/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[6] -translated alu_pass1/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[7] -translated alu_pass1/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[8] -translated alu_pass1/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[9] -translated alu_pass1/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[10] -translated alu_pass1/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[11] -translated alu_pass1/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[12] -translated alu_pass1/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[13] -translated alu_pass1/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[14] -translated alu_pass1/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[15] -translated alu_pass1/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[16] -translated alu_pass1/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[17] -translated alu_pass1/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[18] -translated alu_pass1/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[19] -translated alu_pass1/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[20] -translated alu_pass1/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[21] -translated alu_pass1/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[22] -translated alu_pass1/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[23] -translated alu_pass1/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[24] -translated alu_pass1/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[25] -translated alu_pass1/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[26] -translated alu_pass1/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[27] -translated alu_pass1/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[28] -translated alu_pass1/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[29] -translated alu_pass1/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[30] -translated alu_pass1/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original alu_pass1/r32_o[31] -translated alu_pass1/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[0] -translated cop_data_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[1] -translated cop_data_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[2] -translated cop_data_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[3] -translated cop_data_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[4] -translated cop_data_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[5] -translated cop_data_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[6] -translated cop_data_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[7] -translated cop_data_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[8] -translated cop_data_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[9] -translated cop_data_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[10] -translated cop_data_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[11] -translated cop_data_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[12] -translated cop_data_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[13] -translated cop_data_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[14] -translated cop_data_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[15] -translated cop_data_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[16] -translated cop_data_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[17] -translated cop_data_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[18] -translated cop_data_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[19] -translated cop_data_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[20] -translated cop_data_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[21] -translated cop_data_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[22] -translated cop_data_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[23] -translated cop_data_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[24] -translated cop_data_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[25] -translated cop_data_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[26] -translated cop_data_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[27] -translated cop_data_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[28] -translated cop_data_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[29] -translated cop_data_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[30] -translated cop_data_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original cop_data_reg/r32_o[31] -translated cop_data_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[0] -translated cop_dout_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[1] -translated cop_dout_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[2] -translated cop_dout_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[3] -translated cop_dout_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[4] -translated cop_dout_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[5] -translated cop_dout_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[6] -translated cop_dout_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[7] -translated cop_dout_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[8] -translated cop_dout_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[9] -translated cop_dout_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[10] -translated cop_dout_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[11] -translated cop_dout_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[12] -translated cop_dout_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[13] -translated cop_dout_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[14] -translated cop_dout_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[15] -translated cop_dout_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[16] -translated cop_dout_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[17] -translated cop_dout_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[18] -translated cop_dout_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[19] -translated cop_dout_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[20] -translated cop_dout_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[21] -translated cop_dout_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[22] -translated cop_dout_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[23] -translated cop_dout_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[24] -translated cop_dout_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[25] -translated cop_dout_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[26] -translated cop_dout_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[27] -translated cop_dout_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[28] -translated cop_dout_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[29] -translated cop_dout_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[30] -translated cop_dout_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original cop_dout_reg/r32_o[31] -translated cop_dout_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U12/wb_we_o[0] -translated decoder_pipe/pipereg/U12/wb_we_o_0__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U18/wb_mux_ctl_o[0] -translated decoder_pipe/pipereg/U18/wb_mux_ctl_o_0__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U20/wb_we_o[0] -translated decoder_pipe/pipereg/U20/wb_we_o_0__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U21/wb_mux_ctl_o[0] -translated decoder_pipe/pipereg/U21/wb_mux_ctl_o_0__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U22/wb_we_o[0] -translated decoder_pipe/pipereg/U22/wb_we_o_0__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U9/dmem_ctl_o[0] -translated decoder_pipe/pipereg/U9/dmem_ctl_o_0__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U9/dmem_ctl_o[1] -translated decoder_pipe/pipereg/U9/dmem_ctl_o_1__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U9/dmem_ctl_o[2] -translated decoder_pipe/pipereg/U9/dmem_ctl_o_2__Z
vif_set_sequential_verify -retimed -register -original decoder_pipe/pipereg/U9/dmem_ctl_o[3] -translated decoder_pipe/pipereg/U9/dmem_ctl_o_3__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[0] -translated ext_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[1] -translated ext_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[2] -translated ext_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[3] -translated ext_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[4] -translated ext_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[5] -translated ext_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[6] -translated ext_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[7] -translated ext_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[8] -translated ext_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[9] -translated ext_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[10] -translated ext_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[11] -translated ext_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[12] -translated ext_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[13] -translated ext_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[14] -translated ext_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[15] -translated ext_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[16] -translated ext_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[17] -translated ext_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[18] -translated ext_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[19] -translated ext_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[20] -translated ext_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[21] -translated ext_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[22] -translated ext_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[23] -translated ext_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[24] -translated ext_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[25] -translated ext_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[26] -translated ext_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[27] -translated ext_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[28] -translated ext_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[29] -translated ext_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[30] -translated ext_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original ext_reg/r32_o[31] -translated ext_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[0] -translated iforward/fw_reg_rns/q_0__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[1] -translated iforward/fw_reg_rns/q_1__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[2] -translated iforward/fw_reg_rns/q_2__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[3] -translated iforward/fw_reg_rns/q_3__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rns/q[4] -translated iforward/fw_reg_rns/q_4__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[0] -translated iforward/fw_reg_rnt/q_0__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[1] -translated iforward/fw_reg_rnt/q_1__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[2] -translated iforward/fw_reg_rnt/q_2__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[3] -translated iforward/fw_reg_rnt/q_3__Z
vif_set_sequential_verify -retimed -register -original iforward/fw_reg_rnt/q[4] -translated iforward/fw_reg_rnt/q_4__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[0] -translated pc/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[1] -translated pc/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[2] -translated pc/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[3] -translated pc/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[4] -translated pc/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[5] -translated pc/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[6] -translated pc/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[7] -translated pc/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[8] -translated pc/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[9] -translated pc/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[10] -translated pc/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[11] -translated pc/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[12] -translated pc/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[13] -translated pc/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[14] -translated pc/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[15] -translated pc/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[16] -translated pc/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[17] -translated pc/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[18] -translated pc/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[19] -translated pc/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[20] -translated pc/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[21] -translated pc/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[22] -translated pc/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[23] -translated pc/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[24] -translated pc/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[25] -translated pc/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[26] -translated pc/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[27] -translated pc/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[28] -translated pc/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[29] -translated pc/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[30] -translated pc/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original pc/r32_o[31] -translated pc/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[0] -translated rnd_pass0/r5_o_0__Z
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[1] -translated rnd_pass0/r5_o_1__Z
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[2] -translated rnd_pass0/r5_o_2__Z
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[3] -translated rnd_pass0/r5_o_3__Z
vif_set_sequential_verify -retimed -register -original rnd_pass0/r5_o[4] -translated rnd_pass0/r5_o_4__Z
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[0] -translated rnd_pass1/r5_o_0__Z
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[1] -translated rnd_pass1/r5_o_1__Z
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[2] -translated rnd_pass1/r5_o_2__Z
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[3] -translated rnd_pass1/r5_o_3__Z
vif_set_sequential_verify -retimed -register -original rnd_pass1/r5_o[4] -translated rnd_pass1/r5_o_4__Z
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[0] -translated rnd_pass2/r5_o_0__Z
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[1] -translated rnd_pass2/r5_o_1__Z
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[2] -translated rnd_pass2/r5_o_2__Z
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[3] -translated rnd_pass2/r5_o_3__Z
vif_set_sequential_verify -retimed -register -original rnd_pass2/r5_o[4] -translated rnd_pass2/r5_o_4__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[0] -translated rs_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[1] -translated rs_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[2] -translated rs_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[3] -translated rs_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[4] -translated rs_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[5] -translated rs_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[6] -translated rs_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[7] -translated rs_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[8] -translated rs_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[9] -translated rs_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[10] -translated rs_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[11] -translated rs_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[12] -translated rs_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[13] -translated rs_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[14] -translated rs_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[15] -translated rs_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[16] -translated rs_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[17] -translated rs_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[18] -translated rs_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[19] -translated rs_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[20] -translated rs_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[21] -translated rs_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[22] -translated rs_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[23] -translated rs_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[24] -translated rs_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[25] -translated rs_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[26] -translated rs_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[27] -translated rs_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[28] -translated rs_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[29] -translated rs_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[30] -translated rs_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original rs_reg/r32_o[31] -translated rs_reg/r32_o_31__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[0] -translated rt_reg/r32_o_0__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[1] -translated rt_reg/r32_o_1__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[2] -translated rt_reg/r32_o_2__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[3] -translated rt_reg/r32_o_3__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[4] -translated rt_reg/r32_o_4__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[5] -translated rt_reg/r32_o_5__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[6] -translated rt_reg/r32_o_6__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[7] -translated rt_reg/r32_o_7__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[8] -translated rt_reg/r32_o_8__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[9] -translated rt_reg/r32_o_9__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[10] -translated rt_reg/r32_o_10__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[11] -translated rt_reg/r32_o_11__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[12] -translated rt_reg/r32_o_12__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[13] -translated rt_reg/r32_o_13__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[14] -translated rt_reg/r32_o_14__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[15] -translated rt_reg/r32_o_15__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[16] -translated rt_reg/r32_o_16__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[17] -translated rt_reg/r32_o_17__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[18] -translated rt_reg/r32_o_18__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[19] -translated rt_reg/r32_o_19__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[20] -translated rt_reg/r32_o_20__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[21] -translated rt_reg/r32_o_21__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[22] -translated rt_reg/r32_o_22__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[23] -translated rt_reg/r32_o_23__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[24] -translated rt_reg/r32_o_24__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[25] -translated rt_reg/r32_o_25__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[26] -translated rt_reg/r32_o_26__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[27] -translated rt_reg/r32_o_27__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[28] -translated rt_reg/r32_o_28__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[29] -translated rt_reg/r32_o_29__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[30] -translated rt_reg/r32_o_30__Z
vif_set_sequential_verify -retimed -register -original rt_reg/r32_o[31] -translated rt_reg/r32_o_31__Z
 
# Altera MAC annotations
 
/verif/mips_core_bb.v
0,0 → 1,13
module synplicity_altsyncram4_r_w_reg_array (wren_a,wren_b,data_a,address_a,address_b,clock0,clock1,clocken0,clocken1,q_b);
input wren_a;
input wren_b;
input [31:0]data_a;
input [4:0]address_a;
input [4:0]address_b;
input clock0;
input clock1;
input clocken0;
input clocken1;
output [31:0]q_b;
endmodule
 

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