OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mips789/branches/avendor/synplify_prj/mips_sys
    from Rev 10 to Rev 51
    ↔ Reverse comparison
  •

Rev 10 → Rev 51

/syntmp/mips_sys_flink.htm
0,0 → 1,9
<table border="0" cellpadding="0" cellspacing="2">
<tr>
<td nowrap width="500" class="content" valign="top">
<body bgcolor="rgb(245,245,255)">
<font size=2 face="arial">
<a><b>Log File Links:</a></b><br>
<a href="C:\Program Files\Synplicity\fpga_81\examples\stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br>
<br><b>mips_sys</a></b><br>
<br><b>mips_sys\par_1</a></b><br>
/syntmp/mips_sys_toc.htm
0,0 → 1,10
<table border="0" cellpadding="0" cellspacing="2">
<tr>
<td nowrap width="500" class="content" valign="top">
<body bgcolor="rgb(245,245,255)">
<font size=2 face="arial">
<dl>
<font size=3><a><b>mips_sys (mips_sys)</a></b><br><br></font>
<dt><a href="mips_sys_srr.htm#error34" target="srrFrame">Error in report!</a></dt><br>
<br>
<b><dt><a href="mips_sys_srr.htm#compilerReport33" target="srrFrame">Compiler Report</a></dt></b><br>
/syntmp/mips_sys_srr.htm
0,0 → 1,569
<html>
<body><samp><pre>
<!@TC:1190196158>
#Program: Synplify Pro 8.1
#OS: Windows_NT
 
<a name=compilerReport33>$ Start of Compile
#Wed Sep 19 18:02:08 2007
 
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
 
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"
@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"
@I::"F:\a\rtl\verilog\ctl_fsm.v"
@I:"F:\a\rtl\verilog\ctl_fsm.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:43:58:56:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190196158> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:57:58:66:@N::@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190196158> | Read full_case directive
<font color=#A52A2A>@W:<a href="@W:CG286:@XP_HELP">CG286</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CG286:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190196158> | Case statement has both a full_case directive and a default clause. The full_case directive is ignored.</font>
@I::"F:\a\rtl\verilog\decode_pipe.v"
@I:"F:\a\rtl\verilog\decode_pipe.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:31:34:31:47:@N::@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:34:45:34:58:@N::@XP_MSG">decode_pipe.v(34)</a><!@TM:1190196158> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:533:47:533:60:@N::@XP_MSG">decode_pipe.v(533)</a><!@TM:1190196158> | Read parallel_case directive
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:835:49:835:62:@N::@XP_MSG">decode_pipe.v(835)</a><!@TM:1190196158> | Read parallel_case directive
@I::"F:\a\rtl\verilog\dvc.v"
@I:"F:\a\rtl\verilog\dvc.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\EXEC_stage.v"
@I:"F:\a\rtl\verilog\EXEC_stage.v":"F:\a\rtl\verilog\include.h"
@I:"F:\a\rtl\verilog\EXEC_stage.v":"F:\a\rtl\verilog\include.h"
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:694:80:694:93:@N::@XP_MSG">exec_stage.v(694)</a><!@TM:1190196158> | Read parallel_case directive
@I::"F:\a\rtl\verilog\fifo.v"
@I:"F:\a\rtl\verilog\fifo.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\forward.v"
@I:"F:\a\rtl\verilog\forward.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mem_module.v"
@I:"F:\a\rtl\verilog\mem_module.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_core.v"
@I:"F:\a\rtl\verilog\mips_core.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_dvc.v"
@I:"F:\a\rtl\verilog\mips_dvc.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_sys.v"
@I:"F:\a\rtl\verilog\mips_sys.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\mips_uart.v"
@I:"F:\a\rtl\verilog\mips_uart.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\ram_module.v"
@I:"F:\a\rtl\verilog\ram_module.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\RF_components.v"
@I:"F:\a\rtl\verilog\RF_components.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\RF_stage.v"
@I:"F:\a\rtl\verilog\RF_stage.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\sim_ram.v"
@I::"F:\a\rtl\verilog\tools.v"
@I:"F:\a\rtl\verilog\tools.v":"F:\a\rtl\verilog\include.h"
@I::"F:\a\rtl\verilog\altera\ram_module.v"
@I::"F:\a\rtl\verilog\altera\mips_top.v"
@I::"F:\a\rtl\verilog\altera\ram2048x8_0.v"
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:39:12:39:25:@N::@XP_MSG">ram2048x8_0.v(39)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:41:12:41:24:@N::@XP_MSG">ram2048x8_0.v(41)</a><!@TM:1190196158> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:78:16:78:29:@N::@XP_MSG">ram2048x8_0.v(78)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_0.v:90:16:90:28:@N::@XP_MSG">ram2048x8_0.v(90)</a><!@TM:1190196158> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\ram2048x8_1.v"
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:39:12:39:25:@N::@XP_MSG">ram2048x8_1.v(39)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:41:12:41:24:@N::@XP_MSG">ram2048x8_1.v(41)</a><!@TM:1190196158> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:78:16:78:29:@N::@XP_MSG">ram2048x8_1.v(78)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_1.v:90:16:90:28:@N::@XP_MSG">ram2048x8_1.v(90)</a><!@TM:1190196158> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\ram2048x8_2.v"
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:39:12:39:25:@N::@XP_MSG">ram2048x8_2.v(39)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:41:12:41:24:@N::@XP_MSG">ram2048x8_2.v(41)</a><!@TM:1190196158> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:78:16:78:29:@N::@XP_MSG">ram2048x8_2.v(78)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_2.v:90:16:90:28:@N::@XP_MSG">ram2048x8_2.v(90)</a><!@TM:1190196158> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\ram2048x8_3.v"
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:39:12:39:25:@N::@XP_MSG">ram2048x8_3.v(39)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:41:12:41:24:@N::@XP_MSG">ram2048x8_3.v(41)</a><!@TM:1190196158> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:78:16:78:29:@N::@XP_MSG">ram2048x8_3.v(78)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\ram2048x8_3.v:90:16:90:28:@N::@XP_MSG">ram2048x8_3.v(90)</a><!@TM:1190196158> | Read directive translate_on
@I::"F:\a\rtl\verilog\altera\mips_pll.v"
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:39:12:39:25:@N::@XP_MSG">mips_pll.v(39)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:41:12:41:24:@N::@XP_MSG">mips_pll.v(41)</a><!@TM:1190196158> | Read directive translate_on
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:59:16:59:29:@N::@XP_MSG">mips_pll.v(59)</a><!@TM:1190196158> | Read directive translate_off
@N: : <a href="f:\a\rtl\verilog\altera\mips_pll.v:84:16:84:28:@N::@XP_MSG">mips_pll.v(84)</a><!@TM:1190196158> | Read directive translate_on
Verilog syntax check successful!
File F:\a\rtl\verilog\fifo512_cyclone.v changed - recompiling
Selecting top level module mips_sys
@N: : <a href="f:\a\rtl\verilog\mem_module.v:78:7:78:26:@N::@XP_MSG">mem_module.v(78)</a><!@TM:1190196158> | Synthesizing module infile_dmem_ctl_reg
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <30> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <29> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <28> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <27> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <26> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <25> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <24> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <23> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <22> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <21> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <20> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <19> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <18> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <17> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <16> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <15> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <14> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <13> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <12> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <11> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <10> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <9> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <8> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <7> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <6> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <5> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <4> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <3> of dmem_addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:81:20:81:31:@W::@XP_MSG">mem_module.v(81)</a><!@TM:1190196158> | Input port bit <2> of dmem_addr_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\mem_module.v:96:7:96:19:@N::@XP_MSG">mem_module.v(96)</a><!@TM:1190196158> | Synthesizing module mem_addr_ctl
 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\mem_module.v:102:4:102:8:@W:CL118:@XP_MSG">mem_module.v(102)</a><!@TM:1190196158> | Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <31> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <30> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <29> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <28> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <27> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <26> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <25> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <24> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <23> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <22> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <21> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <20> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <19> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <18> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <17> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <16> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <15> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <14> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <13> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <12> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <11> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <10> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <9> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <8> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <7> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <6> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <5> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <4> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <3> of addr_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mem_module.v:98:20:98:26:@W::@XP_MSG">mem_module.v(98)</a><!@TM:1190196158> | Input port bit <2> of addr_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\mem_module.v:199:7:199:18:@N::@XP_MSG">mem_module.v(199)</a><!@TM:1190196158> | Synthesizing module mem_din_ctl
 
@N: : <a href="f:\a\rtl\verilog\mem_module.v:130:7:130:19:@N::@XP_MSG">mem_module.v(130)</a><!@TM:1190196158> | Synthesizing module mem_dout_ctl
 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\mem_module.v:161:4:161:8:@W:CL118:@XP_MSG">mem_module.v(161)</a><!@TM:1190196158> | Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt</font>
@N: : <a href="f:\a\rtl\verilog\mem_module.v:4:7:4:17:@N::@XP_MSG">mem_module.v(4)</a><!@TM:1190196158> | Synthesizing module mem_module
 
@N: : <a href="f:\a\rtl\verilog\tools.v:3:7:3:14:@N::@XP_MSG">tools.v(3)</a><!@TM:1190196158> | Synthesizing module cal_cpi
 
@N: : <a href="f:\a\rtl\verilog\ctl_fsm.v:2:7:2:14:@N::@XP_MSG">ctl_fsm.v(2)</a><!@TM:1190196158> | Synthesizing module ctl_FSM
 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190196158> | Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL113:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190196158> | Feedback mux created for signal iack.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190196158> | Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:58:8:58:12:@W:CL118:@XP_MSG">ctl_fsm.v(58)</a><!@TM:1190196158> | Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="f:\a\rtl\verilog\ctl_fsm.v:224:4:224:10:@N:CL201:@XP_MSG">ctl_fsm.v(224)</a><!@TM:1190196158> | Trying to extract state machine for register CurrState_Sreg0
Extracted state machine for register CurrState_Sreg0
State machine has 9 reachable states with original encodings of:
0000
0001
0010
0011
0100
0101
0110
0111
1000
@N: : <a href="f:\a\rtl\verilog\rf_components.v:50:7:50:13:@N::@XP_MSG">rf_components.v(50)</a><!@TM:1190196158> | Synthesizing module pc_gen
 
@N: : <a href="f:\a\rtl\verilog\rf_components.v:30:7:30:14:@N::@XP_MSG">rf_components.v(30)</a><!@TM:1190196158> | Synthesizing module compare
 
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="f:\a\rtl\verilog\rf_components.v:36:14:36:17:@W:CG133:@XP_MSG">rf_components.v(36)</a><!@TM:1190196158> | No assignment to sum</font>
@N: : <a href="f:\a\rtl\verilog\rf_components.v:2:7:2:10:@N::@XP_MSG">rf_components.v(2)</a><!@TM:1190196158> | Synthesizing module ext
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190196158> | Input port bit <31> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190196158> | Input port bit <30> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190196158> | Input port bit <29> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190196158> | Input port bit <28> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190196158> | Input port bit <27> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\rf_components.v:3:21:3:26:@W::@XP_MSG">rf_components.v(3)</a><!@TM:1190196158> | Input port bit <26> of ins_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\tools.v:104:7:104:22:@N::@XP_MSG">tools.v(104)</a><!@TM:1190196158> | Synthesizing module r32_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:104:167:104:172:@N:CG179:@XP_MSG">tools.v(104)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:30:7:30:11:@N::@XP_MSG">tools.v(30)</a><!@TM:1190196158> | Synthesizing module jack
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <31> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <30> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <29> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <28> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <27> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <26> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <10> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <9> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <8> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <7> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <6> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <5> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <4> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <3> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <2> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <1> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\tools.v:31:21:31:26:@W::@XP_MSG">tools.v(31)</a><!@TM:1190196158> | Input port bit <0> of ins_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\tools.v:64:7:64:13:@N::@XP_MSG">tools.v(64)</a><!@TM:1190196158> | Synthesizing module rd_sel
 
@N: : <a href="f:\a\rtl\verilog\rf_components.v:90:7:90:16:@N::@XP_MSG">rf_components.v(90)</a><!@TM:1190196158> | Synthesizing module reg_array
 
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="f:\a\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1190196158> | Found RAM reg_bank, depth=32, width=32
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="f:\a\rtl\verilog\rf_components.v:140:4:140:10:@N:CL134:@XP_MSG">rf_components.v(140)</a><!@TM:1190196158> | Found RAM reg_bank, depth=32, width=32
@N: : <a href="f:\a\rtl\verilog\forward.v:25:7:25:14:@N::@XP_MSG">forward.v(25)</a><!@TM:1190196158> | Synthesizing module fwd_mux
 
@N: : <a href="f:\a\rtl\verilog\rf_stage.v:3:7:3:15:@N::@XP_MSG">rf_stage.v(3)</a><!@TM:1190196158> | Synthesizing module rf_stage
 
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\rf_stage.v:91:24:91:30:@W:CS149:@XP_MSG">rf_stage.v(91)</a><!@TM:1190196158> | Port width mismatch for port ins_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CS149:@XP_HELP">CS149</a> : <a href="f:\a\rtl\verilog\rf_stage.v:90:24:90:30:@W:CS149:@XP_MSG">rf_stage.v(90)</a><!@TM:1190196158> | Port width mismatch for port clk_no. Formal has width 101, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="f:\a\rtl\verilog\rf_stage.v:87:12:87:19:@W:CL168:@XP_MSG">rf_stage.v(87)</a><!@TM:1190196158> | Pruning instance CAL_CPI - not in use ...</font>
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:521:7:521:16:@N::@XP_MSG">exec_stage.v(521)</a><!@TM:1190196158> | Synthesizing module muldiv_ff
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190196158> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2 </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190196158> | Pruning Register START_SECTION.over[32:0] </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190196158> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190196158> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqz </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190196158> | Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64 </font>
 
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="f:\a\rtl\verilog\exec_stage.v:572:4:572:10:@W:CL169:@XP_MSG">exec_stage.v(572)</a><!@TM:1190196158> | Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2 </font>
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:233:7:233:10:@N::@XP_MSG">exec_stage.v(233)</a><!@TM:1190196158> | Synthesizing module alu
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:238:16:238:17:@W::@XP_MSG">exec_stage.v(238)</a><!@TM:1190196158> | No assignment to wire c</font>
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:266:4:266:15:@N::@XP_MSG">exec_stage.v(266)</a><!@TM:1190196158> | Synthesizing module shifter_tak
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <31> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <30> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <29> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <28> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <27> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <26> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <25> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <24> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <23> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <22> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <21> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <20> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <19> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <18> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <17> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <16> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <15> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <14> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <13> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <12> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <11> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <10> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <9> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <8> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <7> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <6> of shift_amount[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\exec_stage.v:270:25:270:52:@W::@XP_MSG">exec_stage.v(270)</a><!@TM:1190196158> | Input port bit <5> of shift_amount[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:138:7:138:14:@N::@XP_MSG">exec_stage.v(138)</a><!@TM:1190196158> | Synthesizing module big_alu
 
@N: : <a href="f:\a\rtl\verilog\tools.v:22:7:22:12:@N::@XP_MSG">tools.v(22)</a><!@TM:1190196158> | Synthesizing module add32
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:188:7:188:15:@N::@XP_MSG">exec_stage.v(188)</a><!@TM:1190196158> | Synthesizing module alu_muxa
 
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:212:7:212:15:@N::@XP_MSG">exec_stage.v(212)</a><!@TM:1190196158> | Synthesizing module alu_muxb
 
@N: : <a href="f:\a\rtl\verilog\tools.v:150:7:150:14:@N::@XP_MSG">tools.v(150)</a><!@TM:1190196158> | Synthesizing module r32_reg
 
@N: : <a href="f:\a\rtl\verilog\tools.v:173:7:173:18:@N::@XP_MSG">tools.v(173)</a><!@TM:1190196158> | Synthesizing module r32_reg_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:173:132:173:137:@N:CG179:@XP_MSG">tools.v(173)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\exec_stage.v:3:7:3:17:@N::@XP_MSG">exec_stage.v(3)</a><!@TM:1190196158> | Synthesizing module exec_stage
 
@N: : <a href="f:\a\rtl\verilog\tools.v:54:7:54:11:@N::@XP_MSG">tools.v(54)</a><!@TM:1190196158> | Synthesizing module or32
 
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:2:7:2:14:@N::@XP_MSG">decode_pipe.v(2)</a><!@TM:1190196158> | Synthesizing module decoder
 
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="f:\a\rtl\verilog\decode_pipe.v:31:8:31:12:@W:CL118:@XP_MSG">decode_pipe.v(31)</a><!@TM:1190196158> | Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt</font>
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <15> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <14> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <13> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <12> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <11> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <10> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <9> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <8> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <7> of ins_i[31:0] is unused</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\decode_pipe.v:3:20:3:25:@W::@XP_MSG">decode_pipe.v(3)</a><!@TM:1190196158> | Input port bit <6> of ins_i[31:0] is unused</font>
 
@N: : <a href="f:\a\rtl\verilog\tools.v:90:7:90:27:@N::@XP_MSG">tools.v(90)</a><!@TM:1190196158> | Synthesizing module muxb_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:90:202:90:212:@N:CG179:@XP_MSG">tools.v(90)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:94:7:94:29:@N::@XP_MSG">tools.v(94)</a><!@TM:1190196158> | Synthesizing module wb_mux_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:94:216:94:228:@N:CG179:@XP_MSG">tools.v(94)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:95:7:95:24:@N::@XP_MSG">tools.v(95)</a><!@TM:1190196158> | Synthesizing module wb_we_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:95:181:95:188:@N:CG179:@XP_MSG">tools.v(95)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:141:7:141:16:@N::@XP_MSG">tools.v(141)</a><!@TM:1190196158> | Synthesizing module wb_we_reg
 
@N: : <a href="f:\a\rtl\verilog\tools.v:117:7:117:25:@N::@XP_MSG">tools.v(117)</a><!@TM:1190196158> | Synthesizing module wb_mux_ctl_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:113:7:113:23:@N::@XP_MSG">tools.v(113)</a><!@TM:1190196158> | Synthesizing module muxb_ctl_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:116:7:116:23:@N::@XP_MSG">tools.v(116)</a><!@TM:1190196158> | Synthesizing module dmem_ctl_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:114:7:114:23:@N::@XP_MSG">tools.v(114)</a><!@TM:1190196158> | Synthesizing module alu_func_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:112:7:112:23:@N::@XP_MSG">tools.v(112)</a><!@TM:1190196158> | Synthesizing module muxa_ctl_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:140:7:140:21:@N::@XP_MSG">tools.v(140)</a><!@TM:1190196158> | Synthesizing module wb_mux_ctl_reg
 
@N: : <a href="f:\a\rtl\verilog\tools.v:118:7:118:20:@N::@XP_MSG">tools.v(118)</a><!@TM:1190196158> | Synthesizing module wb_we_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:86:7:86:26:@N::@XP_MSG">tools.v(86)</a><!@TM:1190196158> | Synthesizing module cmp_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:86:195:86:204:@N:CG179:@XP_MSG">tools.v(86)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:115:7:115:21:@N::@XP_MSG">tools.v(115)</a><!@TM:1190196158> | Synthesizing module alu_we_reg_clr
 
@N: : <a href="f:\a\rtl\verilog\tools.v:91:7:91:27:@N::@XP_MSG">tools.v(91)</a><!@TM:1190196158> | Synthesizing module alu_func_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:91:202:91:212:@N:CG179:@XP_MSG">tools.v(91)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:93:7:93:27:@N::@XP_MSG">tools.v(93)</a><!@TM:1190196158> | Synthesizing module dmem_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:93:202:93:212:@N:CG179:@XP_MSG">tools.v(93)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:84:7:84:26:@N::@XP_MSG">tools.v(84)</a><!@TM:1190196158> | Synthesizing module ext_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:84:195:84:204:@N:CG179:@XP_MSG">tools.v(84)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:85:7:85:25:@N::@XP_MSG">tools.v(85)</a><!@TM:1190196158> | Synthesizing module rd_sel_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:85:188:85:196:@N:CG179:@XP_MSG">tools.v(85)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:92:7:92:25:@N::@XP_MSG">tools.v(92)</a><!@TM:1190196158> | Synthesizing module alu_we_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:92:188:92:196:@N:CG179:@XP_MSG">tools.v(92)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:89:7:89:27:@N::@XP_MSG">tools.v(89)</a><!@TM:1190196158> | Synthesizing module muxa_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:89:202:89:212:@N:CG179:@XP_MSG">tools.v(89)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:87:7:87:29:@N::@XP_MSG">tools.v(87)</a><!@TM:1190196158> | Synthesizing module pc_gen_ctl_reg_clr_cls
 
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\a\rtl\verilog\tools.v:87:216:87:228:@N:CG179:@XP_MSG">tools.v(87)</a><!@TM:1190196158> | Removing redundant assignment
@N: : <a href="f:\a\rtl\verilog\tools.v:139:7:139:19:@N::@XP_MSG">tools.v(139)</a><!@TM:1190196158> | Synthesizing module dmem_ctl_reg
 
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:1090:7:1090:20:@N::@XP_MSG">decode_pipe.v(1090)</a><!@TM:1190196158> | Synthesizing module pipelinedregs
 
@N: : <a href="f:\a\rtl\verilog\decode_pipe.v:1419:7:1419:18:@N::@XP_MSG">decode_pipe.v(1419)</a><!@TM:1190196158> | Synthesizing module decode_pipe
 
@N: : <a href="f:\a\rtl\verilog\forward.v:12:7:12:19:@N::@XP_MSG">forward.v(12)</a><!@TM:1190196158> | Synthesizing module forward_node
 
@N: : <a href="f:\a\rtl\verilog\forward.v:4:7:4:16:@N::@XP_MSG">forward.v(4)</a><!@TM:1190196158> | Synthesizing module fw_latch5
 
@N: : <a href="f:\a\rtl\verilog\forward.v:41:7:41:14:@N::@XP_MSG">forward.v(41)</a><!@TM:1190196158> | Synthesizing module forward
 
@N: : <a href="f:\a\rtl\verilog\tools.v:149:7:149:13:@N::@XP_MSG">tools.v(149)</a><!@TM:1190196158> | Synthesizing module r5_reg
 
@N: : <a href="f:\a\rtl\verilog\tools.v:43:7:43:13:@N::@XP_MSG">tools.v(43)</a><!@TM:1190196158> | Synthesizing module wb_mux
 
@N: : <a href="f:\a\rtl\verilog\mips_core.v:3:7:3:16:@N::@XP_MSG">mips_core.v(3)</a><!@TM:1190196158> | Synthesizing module mips_core
 
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:210:7:210:16:@N::@XP_MSG">mips_uart.v(210)</a><!@TM:1190196158> | Synthesizing module uart_read
 
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="f:\a\rtl\verilog\mips_uart.v:274:4:274:10:@N:CL201:@XP_MSG">mips_uart.v(274)</a><!@TM:1190196158> | Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 5 reachable states with original encodings of:
000
001
010
011
100
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:3:7:3:12:@N::@XP_MSG">mips_uart.v(3)</a><!@TM:1190196158> | Synthesizing module rxd_d
 
<a name=error34><font color=red>@E:<a href="@E:CG106:@XP_HELP">CG106</a> : <a href="f:\a\rtl\verilog\mips_uart.v:114:21:114:25:@E:CG106:@XP_MSG">mips_uart.v(114)</a><!@TM:1190196158> | Reference to undefined module fifo512_cyclone</font>
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:70:7:70:17:@N::@XP_MSG">mips_uart.v(70)</a><!@TM:1190196158> | Synthesizing module uart_write
 
<font color=#A52A2A>@W:<a href="@W:CG141:@XP_HELP">CG141</a> : <a href="f:\a\rtl\verilog\mips_uart.v:114:21:114:25:@W:CG141:@XP_MSG">mips_uart.v(114)</a><!@TM:1190196158> | Creating black_box for fifo512_cyclone</font>
Making port data a bidir
Making port wrreq a bidir
Making port rdreq a bidir
Making port clock a bidir
Making port q a bidir
Making port full a bidir
Making port empty a bidir
<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="f:\a\rtl\verilog\mips_uart.v:94:9:94:21:@W:CG133:@XP_MSG">mips_uart.v(94)</a><!@TM:1190196158> | No assignment to write_done_n</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="f:\a\rtl\verilog\mips_uart.v:168:4:168:10:@N:CL201:@XP_MSG">mips_uart.v(168)</a><!@TM:1190196158> | Trying to extract state machine for register ua_state
Extracted state machine for register ua_state
State machine has 8 reachable states with original encodings of:
000
001
010
011
100
101
110
111
<a name=error35><font color=red>@E:<a href="@E:CL175:@XP_HELP">CL175</a> : <a href="f:\a\rtl\verilog\mips_uart.v:80:17:80:29:@E:CL175:@XP_MSG">mips_uart.v(80)</a><!@TM:1190196158> | Multiple non-tristate drivers for net read_request in uart_write</font>
@N: : <a href="f:\a\rtl\verilog\mips_uart.v:12:7:12:12:@N::@XP_MSG">mips_uart.v(12)</a><!@TM:1190196158> | Synthesizing module uart0
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_uart.v:38:9:38:18:@W::@XP_MSG">mips_uart.v(38)</a><!@TM:1190196158> | No assignment to wire w_rxd_clr</font>
 
@N: : <a href="f:\a\rtl\verilog\dvc.v:52:7:52:17:@N::@XP_MSG">dvc.v(52)</a><!@TM:1190196158> | Synthesizing module seg7led_cv
 
@N: : <a href="f:\a\rtl\verilog\dvc.v:43:7:43:12:@N::@XP_MSG">dvc.v(43)</a><!@TM:1190196158> | Synthesizing module tmr_d
 
@N: : <a href="f:\a\rtl\verilog\dvc.v:3:7:3:11:@N::@XP_MSG">dvc.v(3)</a><!@TM:1190196158> | Synthesizing module tmr0
 
@N: : <a href="f:\a\rtl\verilog\mips_dvc.v:3:7:3:15:@N::@XP_MSG">mips_dvc.v(3)</a><!@TM:1190196158> | Synthesizing module mips_dvc
 
@N: : <a href="f:\a\rtl\verilog\mips_sys.v:4:7:4:15:@N::@XP_MSG">mips_sys.v(4)</a><!@TM:1190196158> | Synthesizing module mips_sys
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:78:16:78:25:@W::@XP_MSG">mips_sys.v(78)</a><!@TM:1190196158> | No assignment to wire data2core</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:79:16:79:24:@W::@XP_MSG">mips_sys.v(79)</a><!@TM:1190196158> | No assignment to wire data2mem</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:80:16:80:24:@W::@XP_MSG">mips_sys.v(80)</a><!@TM:1190196158> | No assignment to wire ins2core</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:81:16:81:24:@W::@XP_MSG">mips_sys.v(81)</a><!@TM:1190196158> | No assignment to wire mem_Addr</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:82:16:82:18:@W::@XP_MSG">mips_sys.v(82)</a><!@TM:1190196158> | No assignment to wire pc</font>
 
<font color=#A52A2A>@W: : <a href="f:\a\rtl\verilog\mips_sys.v:83:15:83:20:@W::@XP_MSG">mips_sys.v(83)</a><!@TM:1190196158> | No assignment to wire wr_en</font>
 
<a name=error36><font color=red>@E:<a href="@E:CL147:@XP_HELP">CL147</a> : <a href="f:\a\rtl\verilog\mips_uart.v:80:17:80:29:@E:CL147:@XP_MSG">mips_uart.v(80)</a><!@TM:1190196158> | Unresolved tristate drivers for net read_request in uart_write</font>
@END
Process took 0h:00m:27s realtime, 0h:00m:27s cputime
# Wed Sep 19 18:02:36 2007
 
/syntmp/mips_sys_cons_ui.tcl
0,0 → 1,5
source "C:/Program Files/Synplicity/fpga_81/lib/altera/quartus_cons.tcl"
syn_create_and_open_prj mips_sys
source $::quartus(binpath)/prj_asd_import.tcl
syn_create_and_open_csf mips_sys
syn_handle_cons mips_sys
/syntmp/mips_sys.plg
0,0 → 1,16
@P: Part : EP1C6QC240-6
@P: Worst Slack : -2.014
@P: mips_sys|clk - Estimated Frequency : 74.5 MHz
@P: mips_sys|clk - Requested Frequency : 87.6 MHz
@P: mips_sys|clk - Estimated Period : 13.424
@P: mips_sys|clk - Requested Period : 11.411
@P: mips_sys|clk - Slack : -2.014
@P: System - Estimated Frequency : 541.6 MHz
@P: System - Requested Frequency : 770.5 MHz
@P: System - Estimated Period : 1.846
@P: System - Requested Period : 1.298
@P: System - Slack : -0.549
@P: mips_sys Part : ep1c6qc240-6
@P: mips_sys I/O ATOMs : 197
@P: mips_sys Total LUTs: : 3412 of 5980 (57%)
@P: mips_sys Logic resources : 3545 ATOMs of 5980 (59%)
/syntmp/mips_sys.msg --- verif/mips_sys.vif (nonexistent) +++ verif/mips_sys.vif (revision 51) @@ -0,0 +1,250 @@ +# +# Synplicity Verification Interface File +# Generated using Synplify-pro +# +# Copyright (c) 1996-2005 Synplicity, Inc. +# All rights reserved +# + +# Set logfile options +vif_set_result_file mips_sys.vlf + +# Set technology for TCL script +vif_set_technology -architecture FPGA -vendor Altera + +# RTL and technology files +vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog +vif_add_file -original -verilog ../../rtl/verilog/ctl_fsm.v +vif_add_file -original -verilog ../../rtl/verilog/decode_pipe.v +vif_add_file -original -verilog ../../rtl/verilog/dvc.v +vif_add_file -original -verilog ../../rtl/verilog/EXEC_stage.v +vif_add_file -original -verilog ../../rtl/verilog/fifo.v +vif_add_file -original -verilog ../../rtl/verilog/forward.v +vif_add_file -original -verilog ../../rtl/verilog/mem_module.v +vif_add_file -original -verilog ../../rtl/verilog/mips_core.v +vif_add_file -original -verilog ../../rtl/verilog/mips_dvc.v +vif_add_file -original -verilog ../../rtl/verilog/mips_sys.v +vif_add_file -original -verilog ../../rtl/verilog/mips_uart.v +vif_add_file -original -verilog ../../rtl/verilog/ram_module.v +vif_add_file -original -verilog ../../rtl/verilog/RF_components.v +vif_add_file -original -verilog ../../rtl/verilog/RF_stage.v +vif_add_file -original -verilog ../../rtl/verilog/sim_ram.v +vif_add_file -original -verilog ../../rtl/verilog/tools.v +vif_add_file -original -verilog ../../rtl/verilog/fifo512_cyclone.v +vif_set_top_module -original -top mips_sys + +vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog +vif_add_file -translated -verilog mips_sys.vqm +vif_set_top_module -translated -top mips_sys +# Read FSM encoding +vif_set_fsm -fsm fsm_0 +vif_set_fsmreg -original -fsm fsm_0 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[3:0] +vif_set_fsmreg -translated -fsm fsm_0 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[8:0] +vif_set_state_map -fsm fsm_0 -original "0000" -translated "000000001" +vif_set_state_map -fsm fsm_0 -original "0001" -translated "000000010" +vif_set_state_map -fsm fsm_0 -original "0010" -translated "000000100" +vif_set_state_map -fsm fsm_0 -original "0011" -translated "000001000" +vif_set_state_map -fsm fsm_0 -original "0100" -translated "000010000" +vif_set_state_map -fsm fsm_0 -original "0101" -translated "000100000" +vif_set_state_map -fsm fsm_0 -original "0110" -translated "001000000" +vif_set_state_map -fsm fsm_0 -original "0111" -translated "010000000" +vif_set_state_map -fsm fsm_0 -original "1000" -translated "100000000" +vif_set_fsm -fsm fsm_9 +vif_set_fsmreg -original -fsm fsm_9 imips_dvc/iuart0/uart_rd_tak/ua_state[2:0] +vif_set_fsmreg -translated -fsm fsm_9 imips_dvc/iuart0/uart_rd_tak/ua_state[4:0] +vif_set_state_map -fsm fsm_9 -original "000" -translated "00001" +vif_set_state_map -fsm fsm_9 -original "001" -translated "00010" +vif_set_state_map -fsm fsm_9 -original "010" -translated "00100" +vif_set_state_map -fsm fsm_9 -original "011" -translated "01000" +vif_set_state_map -fsm fsm_9 -original "100" -translated "10000" +vif_set_fsm -fsm fsm_15 +vif_set_fsmreg -original -fsm fsm_15 imips_dvc/iuart0/uart_txd/ua_state[2:0] +vif_set_fsmreg -translated -fsm fsm_15 imips_dvc/iuart0/uart_txd/ua_state[7:0] +vif_set_state_map -fsm fsm_15 -original "000" -translated "00000001" +vif_set_state_map -fsm fsm_15 -original "001" -translated "00000010" +vif_set_state_map -fsm fsm_15 -original "010" -translated "00000100" +vif_set_state_map -fsm fsm_15 -original "011" -translated "00001000" +vif_set_state_map -fsm fsm_15 -original "100" -translated "00010000" +vif_set_state_map -fsm fsm_15 -original "101" -translated "00100000" +vif_set_state_map -fsm fsm_15 -original "110" -translated "01000000" +vif_set_state_map -fsm fsm_15 -original "111" -translated "10000000" + +# Memory map points + +# SRL map points + +# Compiler constant registers + +# Compiler constant latches + +# Compiler RTL sequential redundancies + +# RTL sequential redundancies +vif_set_merge -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[0] mips_core/alu_pass0/r32_o[0] +vif_set_merge -original mips_core/MEM_CTL/dmem_ctl_post/byte_addr_o[1] mips_core/alu_pass0/r32_o[1] +vif_set_merge -original mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_sign_reged mips_core/iexec_stage/MIPS_alu/muldiv_ff/op2_reged[32] + +# Technology sequential redundancies + +# Inversion map points +vif_set_map_point -register -inverted -original mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[0] -translated mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0_i_0__Z +vif_set_map_point -register -inverted -original imips_dvc/iuart0/uart_rd_tak/ua_state[0] -translated imips_dvc/iuart0/uart_rd_tak/ua_state_i_0__Z +vif_set_map_point -register -inverted -original imips_dvc/iuart0/uart_txd/ua_state[0] -translated imips_dvc/iuart0/uart_txd/ua_state_i_0__Z + +# Port mappping and directions + +# Black box mapping +vif_set_black_box synplicity_altsyncram4_r_w +vif_set_black_box scfifo + +vif_set_map_point -blackbox -original mips_core/iRF_stage/reg_bank/reg_bank/altsyncram -translated mips_core/iRF_stage/reg_bank/reg_bank.I_1 +vif_set_map_point -blackbox -original mips_core/iRF_stage/reg_bank/reg_bank_1/altsyncram -translated mips_core/iRF_stage/reg_bank/reg_bank_1.I_1 +vif_set_map_point -blackbox -original imips_dvc/iuart0/uart_txd/fifo/scfifo_component -translated imips_dvc/iuart0/uart_txd/fifo/scfifo_component + +# Other sequential cells, including multidimensional arrays +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[7] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_7__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[6] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_6__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[5] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_5__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[4] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_4__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[3] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_3__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[2] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_2__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[1] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_1__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[0] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_0__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[15] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_15__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[14] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_14__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[13] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_13__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[12] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_12__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[11] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_11__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[10] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_10__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[9] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_9__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[8] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_8__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[31] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_31__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[30] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_30__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[29] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_29__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[28] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_28__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[27] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_27__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[26] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_26__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[25] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_25__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[24] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_24__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[23] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_23__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[22] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_22__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[21] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_21__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[20] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_20__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[19] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_19__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[18] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_18__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[17] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_17__Z +vif_set_map_point -latch -original mips_core/MEM_CTL/i_mem_dout_ctl/dout[16] -translated mips_core/MEM_CTL/i_mem_dout_ctl/dout_1_16__Z +vif_set_map_point -latch -original mips_core/decoder_pipe/idecoder/fsm_dly[2] -translated mips_core/decoder_pipe/idecoder/fsm_dly_1_2__Z +vif_set_map_point -latch -original mips_core/decoder_pipe/idecoder/fsm_dly[1] -translated mips_core/decoder_pipe/idecoder/fsm_dly_1_1__Z + +# Constant Registers +vif_set_constant -original -1 mips_core/iRF_stage/MIAN_FSM/CurrState_Sreg0[5] +vif_set_transparent -original 1 mips_core/iRF_stage/MIAN_FSM/iack +vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[31] +vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[30] +vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[29] +vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[28] +vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[27] +vif_set_constant -original -1 mips_core/iRF_stage/ins_reg/r32_o[26] +vif_set_constant -original -1 imips_dvc/mips_tmr0/itmr_d/q +vif_set_constant -original -1 imips_dvc/key2_addr[31] +vif_set_constant -original -1 imips_dvc/key2_addr[30] +vif_set_constant -original -1 imips_dvc/key2_addr[29] +vif_set_constant -original -1 imips_dvc/key2_addr[28] +vif_set_constant -original -1 imips_dvc/key2_addr[27] +vif_set_constant -original -1 imips_dvc/key2_addr[26] +vif_set_constant -original -1 imips_dvc/key2_addr[25] +vif_set_constant -original -1 imips_dvc/key2_addr[24] +vif_set_constant -original -1 imips_dvc/key2_addr[23] +vif_set_constant -original -1 imips_dvc/key2_addr[22] +vif_set_constant -original -1 imips_dvc/key2_addr[21] +vif_set_constant -original -1 imips_dvc/key2_addr[20] +vif_set_constant -original -1 imips_dvc/key2_addr[19] +vif_set_constant -original -1 imips_dvc/key2_addr[18] +vif_set_constant -original -1 imips_dvc/key2_addr[17] +vif_set_constant -original -1 imips_dvc/key2_addr[16] +vif_set_constant -original -1 imips_dvc/key2_addr[15] +vif_set_constant -original -1 imips_dvc/key2_addr[14] +vif_set_constant -original -1 imips_dvc/key2_addr[13] +vif_set_constant -original -1 imips_dvc/key2_addr[12] +vif_set_constant -original -1 imips_dvc/key2_addr[11] +vif_set_constant -original -1 imips_dvc/key2_addr[10] +vif_set_constant -original -1 imips_dvc/key2_addr[9] +vif_set_constant -original -1 imips_dvc/key2_addr[8] +vif_set_constant -original -1 imips_dvc/key2_addr[7] +vif_set_constant -original -1 imips_dvc/key2_addr[6] +vif_set_constant -original -1 imips_dvc/key2_addr[5] +vif_set_constant -original -1 imips_dvc/key2_addr[4] +vif_set_constant -original -1 imips_dvc/key2_addr[3] +vif_set_constant -original -1 imips_dvc/key2_addr[2] +vif_set_constant -original -1 imips_dvc/key2_addr[1] +vif_set_constant -original -1 imips_dvc/key2_addr[0] +vif_set_constant -original -1 imips_dvc/key1_addr[31] +vif_set_constant -original -1 imips_dvc/key1_addr[30] +vif_set_constant -original -1 imips_dvc/key1_addr[29] +vif_set_constant -original -1 imips_dvc/key1_addr[28] +vif_set_constant -original -1 imips_dvc/key1_addr[27] +vif_set_constant -original -1 imips_dvc/key1_addr[26] +vif_set_constant -original -1 imips_dvc/key1_addr[25] +vif_set_constant -original -1 imips_dvc/key1_addr[24] +vif_set_constant -original -1 imips_dvc/key1_addr[23] +vif_set_constant -original -1 imips_dvc/key1_addr[22] +vif_set_constant -original -1 imips_dvc/key1_addr[21] +vif_set_constant -original -1 imips_dvc/key1_addr[20] +vif_set_constant -original -1 imips_dvc/key1_addr[19] +vif_set_constant -original -1 imips_dvc/key1_addr[18] +vif_set_constant -original -1 imips_dvc/key1_addr[17] +vif_set_constant -original -1 imips_dvc/key1_addr[16] +vif_set_constant -original -1 imips_dvc/key1_addr[15] +vif_set_constant -original -1 imips_dvc/key1_addr[14] +vif_set_constant -original -1 imips_dvc/key1_addr[13] +vif_set_constant -original -1 imips_dvc/key1_addr[12] +vif_set_constant -original -1 imips_dvc/key1_addr[11] +vif_set_constant -original -1 imips_dvc/key1_addr[10] +vif_set_constant -original -1 imips_dvc/key1_addr[9] +vif_set_constant -original -1 imips_dvc/key1_addr[8] +vif_set_constant -original -1 imips_dvc/key1_addr[7] +vif_set_constant -original -1 imips_dvc/key1_addr[6] +vif_set_constant -original -1 imips_dvc/key1_addr[5] +vif_set_constant -original -1 imips_dvc/key1_addr[4] +vif_set_constant -original -1 imips_dvc/key1_addr[3] +vif_set_constant -original -1 imips_dvc/key1_addr[2] +vif_set_constant -original -1 imips_dvc/key1_addr[1] +vif_set_constant -original -1 imips_dvc/key1_addr[0] +vif_set_constant -original -1 imips_dvc/tmr_addr[31] +vif_set_constant -original -1 imips_dvc/tmr_addr[30] +vif_set_constant -original -1 imips_dvc/tmr_addr[29] +vif_set_constant -original -1 imips_dvc/tmr_addr[28] +vif_set_constant -original -1 imips_dvc/tmr_addr[27] +vif_set_constant -original -1 imips_dvc/tmr_addr[26] +vif_set_constant -original -1 imips_dvc/tmr_addr[25] +vif_set_constant -original -1 imips_dvc/tmr_addr[24] +vif_set_constant -original -1 imips_dvc/tmr_addr[23] +vif_set_constant -original -1 imips_dvc/tmr_addr[22] +vif_set_constant -original -1 imips_dvc/tmr_addr[21] +vif_set_constant -original -1 imips_dvc/tmr_addr[20] +vif_set_constant -original -1 imips_dvc/tmr_addr[19] +vif_set_constant -original -1 imips_dvc/tmr_addr[18] +vif_set_constant -original -1 imips_dvc/tmr_addr[17] +vif_set_constant -original -1 imips_dvc/tmr_addr[16] +vif_set_constant -original -1 imips_dvc/tmr_addr[15] +vif_set_constant -original -1 imips_dvc/tmr_addr[14] +vif_set_constant -original -1 imips_dvc/tmr_addr[13] +vif_set_constant -original -1 imips_dvc/tmr_addr[12] +vif_set_constant -original -1 imips_dvc/tmr_addr[11] +vif_set_constant -original -1 imips_dvc/tmr_addr[10] +vif_set_constant -original -1 imips_dvc/tmr_addr[9] +vif_set_constant -original -1 imips_dvc/tmr_addr[8] +vif_set_constant -original -1 imips_dvc/tmr_addr[7] +vif_set_constant -original -1 imips_dvc/tmr_addr[6] +vif_set_constant -original -1 imips_dvc/tmr_addr[5] +vif_set_constant -original -1 imips_dvc/tmr_addr[4] +vif_set_constant -original -1 imips_dvc/tmr_addr[3] +vif_set_constant -original -1 imips_dvc/tmr_addr[2] +vif_set_constant -original -1 imips_dvc/tmr_addr[1] +vif_set_constant -original -1 imips_dvc/tmr_addr[0] + +# Retimed Registers + +# Altera MAC annotations +
/verif/mips_sys_bb.v
0,0 → 1,28
module synplicity_altsyncram4_r_w_reg_array (wren_a,wren_b,data_a,address_a,address_b,clock0,clock1,clocken0,clocken1,q_b);
input wren_a;
input wren_b;
input [31:0]data_a;
input [4:0]address_a;
input [4:0]address_b;
input clock0;
input clock1;
input clocken0;
input clocken1;
output [31:0]q_b;
endmodule
 
module scfifo_Z1 (data,clock,wrreq,rdreq,aclr,sclr,q,usedw,full,empty,almost_full,almost_empty);
input [7:0]data;
input clock;
input wrreq;
input rdreq;
input aclr;
input sclr;
output [7:0]q;
output [8:0]usedw;
output full;
output empty;
output almost_full;
output almost_empty;
endmodule
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.