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    /mips789/tags/arelease/rtl/verilog
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Rev 36 → Rev 51

/RF_components.v
0,0 → 1,161
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
module ext(
input [31:0] ins_i ,
output reg [31:0] res ,
input [2:0]ctl
);
 
wire [25:0] instr25_0;
assign instr25_0 = ins_i[25:0] ;
 
wire[15:0] sign = {
instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15]};
 
always @ (*)
case (ctl)
`EXT_SIGN :res ={sign,instr25_0[15:0]};//sign
`EXT_UNSIGN :res ={16'b0,instr25_0[15:0]};//zeroext
`EXT_J :res ={4'b0,instr25_0[25:0],2'b0};//jmp
`EXT_B :res ={sign[13:0],instr25_0[15:0],2'B0};//brach
`EXT_SA :res ={27'b0,instr25_0[10:6]} ;//sll,srl
`EXT_S2H :res ={instr25_0[15:0],16'B0};//shift to high
default: res=0;
endcase
endmodule
 
 
module compare (
input [31:0] s,
input [31:0] t,
input [2:0]ctl,
output reg res
);
always @ (*)
case (ctl)
`CMP_BEQ: res = (s==t);
`CMP_BNE: res = (s!=t);
`CMP_BLTZ: res = s[31];
`CMP_BGTZ: res = ~s[31] && (|s[30:0]);
`CMP_BLEZ: res = s[31] |(~|s);
`CMP_BGEZ: res = ~s[31];
default res=1'B0;
endcase
endmodule
 
 
module pc_gen(
input [2:0]ctl,
output reg [31:0]pc_next,
input [3:0] pc_prectl,
input check,
input [31:0]s,
input [31:0]pc,
input [31:0]zz_spc,
input [31:0]imm,
input [31:0]irq
);
 
wire [32:0] br_addr = pc + imm ;
 
always @ (*)
if(pc_prectl == `PC_IGN )
begin
case (ctl)
`PC_RET : pc_next = zz_spc ;
`PC_J : pc_next ={pc[31:28],imm[27:0]};
`PC_JR : pc_next = s;
`PC_BC : pc_next = (check)?({br_addr[31:0]}):(pc+4);
`PC_NEXT : pc_next = pc+ 4 ;
default pc_next = pc + 4;
endcase
end
else
begin
case (pc_prectl)
`PC_KEP : pc_next=pc;
`PC_IRQ : pc_next=irq;
`PC_RST : pc_next='d0;
default pc_next =0;
endcase
end
 
endmodule
 
 
 
module reg_array(
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
qa,
qb,
rd_clk_cls
);
 
input [31:0] data;
input [4:0] wraddress;
input [4:0] rdaddress_a;
input [4:0] rdaddress_b;
 
reg [31:0] r_data;
reg [4:0] r_wraddress;
reg [4:0] r_rdaddress_a;
reg [4:0] r_rdaddress_b;
input rd_clk_cls;
input wren;
reg r_wren;
input clock;
output [31:0] qa;
output [31:0] qb;
reg [31:0]reg_bank[0:31];
integer i;
initial
begin
for(i=0;i<32;i=i+1)
reg_bank[i]=0;
end
 
assign qa=(r_rdaddress_a==0)?0:
((r_wraddress==r_rdaddress_a)&&(1==r_wren))?r_data:
reg_bank[r_rdaddress_a];
 
assign qb=(r_rdaddress_b==0)?0:
((r_wraddress==r_rdaddress_b)&&(1==r_wren))?r_data:
reg_bank[r_rdaddress_b];
 
always@(posedge clock)
if (~rd_clk_cls)
begin
r_rdaddress_a <=rdaddress_a;
r_rdaddress_b<=rdaddress_b;
end
 
always@(posedge clock)
begin
r_data <=data;
r_wraddress<=wraddress;
r_wren<=wren;
end
always@(posedge clock)
if (r_wren)
reg_bank[r_wraddress] <= r_data ;
endmodule
/dvc.v
0,0 → 1,101
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
module tmr0 (
input clk,
input clr,
input[31:0] din ,
input ld,
input tmr_en,
output tmr_req,
output [31:0] cntr_o
);
 
reg [31:0]s_cntr;
reg [31:0]cntr;
 
assign cntr_o=cntr;
 
always @(posedge clk)
if (ld)
s_cntr<= din;
 
 
always @(posedge clk)
if (ld)
cntr<=din;
else if (cntr==0)
cntr<=s_cntr;
else if (tmr_en)
cntr<=cntr-1;
 
wire w_irq = cntr==0;
 
tmr_d itmr_d(
.clr(clr),
.clk(clk),
.d(w_irq),
.q(tmr_req)
);
endmodule
 
 
module tmr_d(input clr,input clk,input d,output reg q );
 
always @(posedge clk)
 
if (clr) q<=0;
else q<=d|q;
 
endmodule
 
module seg7led_cv(
input [7:0] data,
output reg [6:0] seg7led2,
output reg [6:0] seg7led1
);
 
always @(*)
begin
seg7led2= seg(data[3:0]) ;
seg7led1= seg(data[7:4]) ;
end
 
function [7:0] seg;
input [3:0] addr;
begin
case(addr)
0: seg = 7'b0111111;
1: seg = 7'b0000110;
2: seg = 7'b1011011;
3: seg = 7'b1001111;
4: seg = 7'b1100110;
5: seg = 7'b1101101;
6: seg = 7'b1111100;
7: seg = 7'b0000111;
8: seg = 7'b1111111;
9: seg = 7'b1100111;
10: seg = 7'b1110111;
11: seg = 7'b1111100;
12: seg = 7'b1011000;
13: seg = 7'b1011110;
14: seg = 7'b1111001;
15: seg = 7'b1110001;
default seg = 7'bx;
endcase
end
endfunction
 
endmodule
/ulit.v
0,0 → 1,185
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
module cal_cpi ( //just used to calculate CPI(Cycles Per Instruction) for stimulation
input clk,
input rst,
input is_nop,
output reg [100:0] ins_no,
output reg [100:0] clk_no);
 
always @(posedge clk )
if (~rst )clk_no=0;
else
clk_no = 1+clk_no;
 
always @(posedge clk )
if (~rst )ins_no=0;
else if (~is_nop)
ins_no = 1+ins_no;
endmodule
 
 
module add32(
input [31:0]d_i,
output [31:0]d_o
);
assign d_o = d_i + 4;
endmodule
 
 
module jack(
input [31:0] ins_i ,
output [4:0] rs_o,
output [4:0] rt_o,
output [4:0] rd_o
);
assign rs_o = ins_i[25:21];
assign rt_o = ins_i[20:16];
assign rd_o = ins_i[15:11];
endmodule
 
 
 
module wb_mux(
input [31:0]alu_i,
input [31:0]dmem_i,
input sel,
output [31:0]wb_o
);
 
assign wb_o = (sel==`WB_MEM)?dmem_i:alu_i;
 
endmodule
 
module or32(
input [31:0]a,
input [31:0]b,
output [31:0]c
);
 
assign c = a|b ;
 
endmodule
 
module rd_sel(
input [4:0]rd_i,
input [4:0]rt_i,
input[1:0] ctl,
output reg [4:0]rd_o
);
 
always @(*)
case (ctl)
`RD_RD:rd_o=rd_i;
`RD_RT:rd_o=rt_i;
`RD_R31:rd_o='d31;
default :
rd_o=0;
endcase
endmodule
 
//these modules below are genated automaticly by a software written in C language...
 
module ext_ctl_reg_clr_cls(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) ext_ctl_o<=0;else if(cls)ext_ctl_o<=ext_ctl_o;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr_cls(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr,input cls);always@(posedge clk)if(clr) rd_sel_o<=0;else if(cls)rd_sel_o<=rd_sel_o;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_clr_cls(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) cmp_ctl_o<=0;else if(cls)cmp_ctl_o<=cmp_ctl_o;else cmp_ctl_o<=cmp_ctl_i;endmodule
module pc_gen_ctl_reg_clr_cls(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) pc_gen_ctl_o<=0;else if(cls)pc_gen_ctl_o<=pc_gen_ctl_o;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule
module fsm_ctl_reg_clr_cls(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) fsm_ctl_o<=0;else if(cls)fsm_ctl_o<=fsm_ctl_o;else fsm_ctl_o<=fsm_ctl_i;endmodule
module muxa_ctl_reg_clr_cls(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) muxa_ctl_o<=0;else if(cls)muxa_ctl_o<=muxa_ctl_o;else muxa_ctl_o<=muxa_ctl_i;endmodule
module muxb_ctl_reg_clr_cls(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) muxb_ctl_o<=0;else if(cls)muxb_ctl_o<=muxb_ctl_o;else muxb_ctl_o<=muxb_ctl_i;endmodule
module alu_func_reg_clr_cls(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input clr,input cls);always@(posedge clk)if(clr) alu_func_o<=0;else if(cls)alu_func_o<=alu_func_o;else alu_func_o<=alu_func_i;endmodule
module alu_we_reg_clr_cls(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input clr,input cls);always@(posedge clk)if(clr) alu_we_o<=0;else if(cls)alu_we_o<=alu_we_o;else alu_we_o<=alu_we_i;endmodule
module dmem_ctl_reg_clr_cls(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) dmem_ctl_o<=0;else if(cls)dmem_ctl_o<=dmem_ctl_o;else dmem_ctl_o<=dmem_ctl_i;endmodule
module wb_mux_ctl_reg_clr_cls(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) wb_mux_ctl_o<=0;else if(cls)wb_mux_ctl_o<=wb_mux_ctl_o;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule
module wb_we_reg_clr_cls(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input clr,input cls);always@(posedge clk)if(clr) wb_we_o<=0;else if(cls)wb_we_o<=wb_we_o;else wb_we_o<=wb_we_i;endmodule
module ins_reg_clr_cls(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input clr,input cls);always@(posedge clk)if(clr) ins_o<=0;else if(cls)ins_o<=ins_o;else ins_o<=ins_i;endmodule
module pc_reg_clr_cls(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input clr,input cls);always@(posedge clk)if(clr) pc_o<=0;else if(cls)pc_o<=pc_o;else pc_o<=pc_i;endmodule
module spc_reg_clr_cls(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input clr,input cls);always@(posedge clk)if(clr) spc_o<=0;else if(cls)spc_o<=spc_o;else spc_o<=spc_i;endmodule
module r1_reg_clr_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r1_o<=0;else if(cls)r1_o<=r1_o;else r1_o<=r1_i;endmodule
module r2_reg_clr_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r2_o<=0;else if(cls)r2_o<=r2_o;else r2_o<=r2_i;endmodule
module r3_reg_clr_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r3_o<=0;else if(cls)r3_o<=r3_o;else r3_o<=r3_i;endmodule
module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule
module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule
module r32_reg_clr_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
 
 
module ext_ctl_reg_clr(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr);always@(posedge clk)if(clr)ext_ctl_o<=0;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr);always@(posedge clk)if(clr)rd_sel_o<=0;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_clr(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr);always@(posedge clk)if(clr)cmp_ctl_o<=0;else cmp_ctl_o<=cmp_ctl_i;endmodule
module pc_gen_ctl_reg_clr(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input clr);always@(posedge clk)if(clr)pc_gen_ctl_o<=0;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule
module fsm_ctl_reg_clr(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input clr);always@(posedge clk)if(clr)fsm_ctl_o<=0;else fsm_ctl_o<=fsm_ctl_i;endmodule
module muxa_ctl_reg_clr(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input clr);always@(posedge clk)if(clr)muxa_ctl_o<=0;else muxa_ctl_o<=muxa_ctl_i;endmodule
module muxb_ctl_reg_clr(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input clr);always@(posedge clk)if(clr)muxb_ctl_o<=0;else muxb_ctl_o<=muxb_ctl_i;endmodule
module alu_func_reg_clr(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input clr);always@(posedge clk)if(clr)alu_func_o<=0;else alu_func_o<=alu_func_i;endmodule
module alu_we_reg_clr(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input clr);always@(posedge clk)if(clr)alu_we_o<=0;else alu_we_o<=alu_we_i;endmodule
module dmem_ctl_reg_clr(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input clr);always@(posedge clk)if(clr)dmem_ctl_o<=0;else dmem_ctl_o<=dmem_ctl_i;endmodule
module wb_mux_ctl_reg_clr(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input clr);always@(posedge clk)if(clr)wb_mux_ctl_o<=0;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule
module wb_we_reg_clr(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input clr);always@(posedge clk)if(clr)wb_we_o<=0;else wb_we_o<=wb_we_i;endmodule
module ins_reg_clr(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input clr);always@(posedge clk)if(clr)ins_o<=0;else ins_o<=ins_i;endmodule
module pc_reg_clr(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input clr);always@(posedge clk)if(clr)pc_o<=0;else pc_o<=pc_i;endmodule
module spc_reg_clr(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input clr);always@(posedge clk)if(clr)spc_o<=0;else spc_o<=spc_i;endmodule
module r1_reg_clr(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr);always@(posedge clk)if(clr)r1_o<=0;else r1_o<=r1_i;endmodule
module r2_reg_clr(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr);always@(posedge clk)if(clr)r2_o<=0;else r2_o<=r2_i;endmodule
module r3_reg_clr(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr);always@(posedge clk)if(clr)r3_o<=0;else r3_o<=r3_i;endmodule
module r4_reg_clr(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr);always@(posedge clk)if(clr)r4_o<=0;else r4_o<=r4_i;endmodule
module r5_reg_clr(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr);always@(posedge clk)if(clr)r5_o<=0;else r5_o<=r5_i;endmodule
module r32_reg_clr(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr);always@(posedge clk)if(clr)r32_o<=0;else r32_o<=r32_i;endmodule
 
 
module ext_ctl_reg(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk);always@(posedge clk) ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk);always@(posedge clk) rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk);always@(posedge clk) cmp_ctl_o<=cmp_ctl_i;endmodule
module pc_gen_ctl_reg(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk);always@(posedge clk) pc_gen_ctl_o<=pc_gen_ctl_i;endmodule
module fsm_ctl_reg(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk);always@(posedge clk) fsm_ctl_o<=fsm_ctl_i;endmodule
module muxa_ctl_reg(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk);always@(posedge clk) muxa_ctl_o<=muxa_ctl_i;endmodule
module muxb_ctl_reg(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk);always@(posedge clk) muxb_ctl_o<=muxb_ctl_i;endmodule
module alu_func_reg(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk);always@(posedge clk) alu_func_o<=alu_func_i;endmodule
module alu_we_reg(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk);always@(posedge clk) alu_we_o<=alu_we_i;endmodule
module dmem_ctl_reg(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk);always@(posedge clk) dmem_ctl_o<=dmem_ctl_i;endmodule
module wb_mux_ctl_reg(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk);always@(posedge clk) wb_mux_ctl_o<=wb_mux_ctl_i;endmodule
module wb_we_reg(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk);always@(posedge clk) wb_we_o<=wb_we_i;endmodule
module ins_reg(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk);always@(posedge clk) ins_o<=ins_i;endmodule
module pc_reg(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk);always@(posedge clk) pc_o<=pc_i;endmodule
module spc_reg(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk);always@(posedge clk) spc_o<=spc_i;endmodule
module r1_reg(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk);always@(posedge clk) r1_o<=r1_i;endmodule
module r2_reg(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk);always@(posedge clk) r2_o<=r2_i;endmodule
module r3_reg(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk);always@(posedge clk) r3_o<=r3_i;endmodule
module r4_reg(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk);always@(posedge clk) r4_o<=r4_i;endmodule
module r5_reg(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk);always@(posedge clk) r5_o<=r5_i;endmodule
module r32_reg(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk);always@(posedge clk) r32_o<=r32_i;endmodule
 
 
module ext_ctl_reg_cls(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input cls);always@(posedge clk)if(cls) ext_ctl_o<=ext_ctl_o;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_cls(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input cls);always@(posedge clk)if(cls) rd_sel_o<=rd_sel_o;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_cls(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input cls);always@(posedge clk)if(cls) cmp_ctl_o<=cmp_ctl_o;else cmp_ctl_o<=cmp_ctl_i;endmodule
module pc_gen_ctl_reg_cls(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input cls);always@(posedge clk)if(cls) pc_gen_ctl_o<=pc_gen_ctl_o;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule
module fsm_ctl_reg_cls(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input cls);always@(posedge clk)if(cls) fsm_ctl_o<=fsm_ctl_o;else fsm_ctl_o<=fsm_ctl_i;endmodule
module muxa_ctl_reg_cls(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input cls);always@(posedge clk)if(cls) muxa_ctl_o<=muxa_ctl_o;else muxa_ctl_o<=muxa_ctl_i;endmodule
module muxb_ctl_reg_cls(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input cls);always@(posedge clk)if(cls) muxb_ctl_o<=muxb_ctl_o;else muxb_ctl_o<=muxb_ctl_i;endmodule
module alu_func_reg_cls(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input cls);always@(posedge clk)if(cls) alu_func_o<=alu_func_o;else alu_func_o<=alu_func_i;endmodule
module alu_we_reg_cls(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input cls);always@(posedge clk)if(cls) alu_we_o<=alu_we_o;else alu_we_o<=alu_we_i;endmodule
module dmem_ctl_reg_cls(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input cls);always@(posedge clk)if(cls) dmem_ctl_o<=dmem_ctl_o;else dmem_ctl_o<=dmem_ctl_i;endmodule
module wb_mux_ctl_reg_cls(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input cls);always@(posedge clk)if(cls) wb_mux_ctl_o<=wb_mux_ctl_o;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule
module wb_we_reg_cls(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input cls);always@(posedge clk)if(cls) wb_we_o<=wb_we_o;else wb_we_o<=wb_we_i;endmodule
module ins_reg_cls(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input cls);always@(posedge clk)if(cls) ins_o<=ins_o;else ins_o<=ins_i;endmodule
module pc_reg_cls(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input cls);always@(posedge clk)if(cls) pc_o<=pc_o;else pc_o<=pc_i;endmodule
module spc_reg_cls(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input cls);always@(posedge clk)if(cls) spc_o<=spc_o;else spc_o<=spc_i;endmodule
module r1_reg_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input cls);always@(posedge clk)if(cls) r1_o<=r1_o;else r1_o<=r1_i;endmodule
module r2_reg_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input cls);always@(posedge clk)if(cls) r2_o<=r2_o;else r2_o<=r2_i;endmodule
module r3_reg_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input cls);always@(posedge clk)if(cls) r3_o<=r3_o;else r3_o<=r3_i;endmodule
module r4_reg_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input cls);always@(posedge clk)if(cls) r4_o<=r4_o;else r4_o<=r4_i;endmodule
module r5_reg_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input cls);always@(posedge clk)if(cls) r5_o<=r5_o;else r5_o<=r5_i;endmodule
module r32_reg_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input cls);always@(posedge clk)if(cls) r32_o<=r32_o;else r32_o<=r32_i;endmodule
/mips_core.v
0,0 → 1,332
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
module mips_core (
clk,irq_i,rst,cop_dout,irq_addr,
zz_din,zz_ins_i,iack_o,cop_addr_o,
cop_data_o,cop_mem_ctl_o,zz_addr_o,
zz_dout,zz_pc_o,zz_wr_en_o
);
 
input clk;
wire clk;
input irq_i;
wire irq_i;
input rst;
wire rst;
input [31:0] cop_dout;
wire [31:0] cop_dout;
input [31:0] irq_addr;
wire [31:0] irq_addr;
input [31:0] zz_din;
wire [31:0] zz_din;
input [31:0] zz_ins_i;
wire [31:0] zz_ins_i;
output [31:0] zz_addr_o;
wire [31:0] zz_addr_o;
output [31:0] zz_dout;
wire [31:0] zz_dout;
output [31:0] zz_pc_o;
wire [31:0] zz_pc_o;
output [3:0] zz_wr_en_o;
wire [3:0] zz_wr_en_o;
output iack_o;
wire iack_o;
output [31:0] cop_addr_o;
wire [31:0] cop_addr_o;
output [31:0] cop_data_o;
wire [31:0] cop_data_o;
output [3:0] cop_mem_ctl_o;
wire [3:0] cop_mem_ctl_o;
 
 
wire NET1375;
wire NET1572;
wire NET1606;
wire NET1640;
wire NET21531;
wire NET457;
wire NET767;
wire [2:0] BUS109;
wire [2:0] BUS1158;
wire [2:0] BUS117;
wire [2:0] BUS1196;
wire [31:0] BUS15471;
wire [4:0] BUS1724;
wire [4:0] BUS1726;
wire [4:0] BUS18211;
wire [2:0] BUS197;
wire [2:0] BUS2140;
wire [2:0] BUS2156;
wire [31:0] BUS22401;
wire [31:0] BUS24839;
wire [31:0] BUS27031;
wire [2:0] BUS271;
wire [31:0] BUS28013;
wire [1:0] BUS371;
wire [31:0] BUS422;
wire [1:0] BUS5832;
wire [1:0] BUS5840;
wire [3:0] BUS5985;
wire [2:0] BUS5993;
wire [4:0] BUS6275;
wire [31:0] BUS7101;
wire [31:0] BUS7117;
wire [31:0] BUS7160;
wire [31:0] BUS7219;
wire [31:0] BUS7231;
wire [4:0] BUS748;
wire [4:0] BUS756;
wire [4:0] BUS775;
wire [31:0] BUS7772;
wire [31:0] BUS7780;
wire [31:0] BUS9589;
wire [31:0] BUS9884;
 
 
mem_module MEM_CTL
(
.Zz_addr(zz_addr_o),
.Zz_dout(zz_dout),
.Zz_wr_en(zz_wr_en_o),
.clk(clk),
.din(BUS9884),
.dmem_addr_i(BUS9589),
.dmem_ctl(BUS5985),
.dout(BUS22401),
.zZ_din(zz_din)
);
 
assign NET21531 = NET1572 | iack_o;
 
rf_stage iRF_stage
(
.clk(clk),
.cmp_ctl_i(BUS109),
.ext_ctl_i(BUS117),
.ext_o(BUS7219),
.fw_alu_i(cop_addr_o),
.fw_cmp_rs(BUS2140),
.fw_cmp_rt(BUS2156),
.fw_mem_i(BUS15471),
.iack_o(iack_o),
.id2ra_ctl_clr_o(NET1606),
.id2ra_ctl_cls_o(NET1572),
.id_cmd(BUS197),
.ins_i(zz_ins_i),
.irq_addr_i(irq_addr),
.irq_i(irq_i),
.pc_gen_ctl(BUS271),
.pc_i(BUS27031),
.pc_next(zz_pc_o),
.ra2ex_ctl_clr_o(NET1640),
.rd_index_o(BUS775),
.rd_sel_i(BUS371),
.rs_n_o(BUS748),
.rs_o(BUS24839),
.rst_i(rst),
.rt_n_o(BUS756),
.rt_o(BUS7160),
.wb_addr_i(BUS18211),
.wb_din_i(BUS15471),
.wb_we_i(NET1375),
.zz_spc_i(BUS28013)
);
 
 
 
exec_stage iexec_stage
(
.alu_func(BUS6275),
.alu_ur_o(BUS9589),
.clk(clk),
.dmem_data_ur_o(BUS9884),
.dmem_fw_ctl(BUS5993),
.ext_i(BUS7231),
.fw_alu(cop_addr_o),
.fw_dmem(BUS15471),
.muxa_ctl_i(BUS5832),
.muxa_fw_ctl(BUS1158),
.muxb_ctl_i(BUS5840),
.muxb_fw_ctl(BUS1196),
.pc_i(BUS27031),
.rs_i(BUS7101),
.rst(rst),
.rt_i(BUS7117),
.spc_cls_i(NET21531),
.zz_spc_o(BUS28013)
);
 
 
 
r32_reg alu_pass0
(
.clk(clk),
.r32_i(BUS9589),
.r32_o(cop_addr_o)
);
 
 
 
r32_reg alu_pass1
(
.clk(clk),
.r32_i(cop_addr_o),
.r32_o(BUS422)
);
 
 
 
or32 cop_data_or
(
.a(cop_dout),
.b(BUS7772),
.c(BUS7780)
);
 
 
 
r32_reg cop_data_reg
(
.clk(clk),
.r32_i(BUS9884),
.r32_o(cop_data_o)
);
 
 
 
r32_reg cop_dout_reg
(
.clk(clk),
.r32_i(BUS22401),
.r32_o(BUS7772)
);
 
 
 
decode_pipe decoder_pipe
(
.alu_func_o(BUS6275),
.alu_we_o(NET767),
.clk(clk),
.cmp_ctl_o(BUS109),
.dmem_ctl_o(cop_mem_ctl_o),
.dmem_ctl_ur_o(BUS5985),
.ext_ctl_o(BUS117),
.fsm_dly(BUS197),
.id2ra_ctl_clr(NET1606),
.id2ra_ctl_cls(NET1572),
.ins_i(zz_ins_i),
.muxa_ctl_o(BUS5832),
.muxb_ctl_o(BUS5840),
.pc_gen_ctl_o(BUS271),
.ra2ex_ctl_clr(NET1640),
.rd_sel_o(BUS371),
.wb_mux_ctl_o(NET457),
.wb_we_o(NET1375)
);
 
 
 
r32_reg ext_reg
(
.clk(clk),
.r32_i(BUS7219),
.r32_o(BUS7231)
);
 
 
 
forward iforward
(
.alu_rs_fw(BUS1158),
.alu_rt_fw(BUS1196),
.alu_we(NET767),
.clk(clk),
.cmp_rs_fw(BUS2140),
.cmp_rt_fw(BUS2156),
.dmem_fw(BUS5993),
.fw_alu_rn(BUS1724),
.fw_mem_rn(BUS18211),
.mem_We(NET1375),
.rns_i(BUS748),
.rnt_i(BUS756)
);
 
 
 
r32_reg pc
(
.clk(clk),
.r32_i(zz_pc_o),
.r32_o(BUS27031)
);
 
 
 
r5_reg rnd_pass0
(
.clk(clk),
.r5_i(BUS775),
.r5_o(BUS1726)
);
 
 
 
r5_reg rnd_pass1
(
.clk(clk),
.r5_i(BUS1726),
.r5_o(BUS1724)
);
 
 
 
r5_reg rnd_pass2
(
.clk(clk),
.r5_i(BUS1724),
.r5_o(BUS18211)
);
 
 
 
r32_reg rs_reg
(
.clk(clk),
.r32_i(BUS24839),
.r32_o(BUS7101)
);
 
 
 
r32_reg rt_reg
(
.clk(clk),
.r32_i(BUS7160),
.r32_o(BUS7117)
);
 
 
 
wb_mux wb_mux
(
.alu_i(BUS422),
.dmem_i(BUS7780),
.sel(NET457),
.wb_o(BUS15471)
);
 
endmodule
/mips789_defs.v
0,0 → 1,184
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`ifndef INCLUDE_H
`define INCLUDE_H
 
`define FRQ 50000000
`define SER_RATE 19200
 
`define FW_ALU 3'b001
`define FW_MEM 3'b010
`define FW_NOP 3'b100
 
`define ALU_MFHI 6
`define ALU_MFLO 7
`define ALU_MULTTU 8
`define ALU_MULT 9
`define ALU_DIVU 10
`define ALU_DIV 11
 
 
`define DMEM_SB 1
`define DMEM_LBS 2
`define DMEM_LB 3
`define DMEM_LBU 4
`define DMEM_SW 5
`define DMEM_LW 6
`define DMEM_SH 7
`define DMEM_LHS 8
`define DMEM_LH 9
`define DMEM_LHU 10
`define DMEM_NOP 0
 
`define ALU_SRL 1
`define ALU_SLL 2
`define ALU_SRA 4
 
`define WB_ALU 0
`define WB_MEM 1
`define WB_NOP 0
 
`define RD_RD 1
`define RD_RT 2
`define RD_R31 3
`define RD_NOP 0
`define RD_ZR 0
 
`define EXT_CTL_LEN 3
`define RD_SEL_LEN 2
`define CMP_CTL_LEN 3
`define PC_GEN_CTL_LEN 3
`define FSM_CTL_LEN 3
`define MUXA_CTL_LEN 2
`define MUXB_CTL_LEN 2
`define ALU_FUNC_LEN 5
`define ALU_WE_LEN 1
`define DMEM_CTL_LEN 4
`define WB_MUX_CTL_LEN 1
`define WB_WE_LEN 1
`define INS_LEN 32
`define PC_LEN 32
`define SPC_LEN 32
`define R32_LEN 32
`define R5_LEN 5
`define R1_LEN 1
`define R2_LEN 2
`define R3_LEN 3
`define R4_LEN 4
 
`define ALU_ADD 12
`define ALU_ADDU 13
`define ALU_SUB 14
`define ALU_SUBU 15
`define ALU_SLTU 16
`define ALU_SLT 17
`define ALU_OR 18
`define ALU_AND 19
`define ALU_XOR 20
`define ALU_NOR 21
`define ALU_PA 22
`define ALU_PB 23
 
`define D2_MUL_DLY 4'b0000
`define IDLE 4'b0001
`define MUL 4'b0010
`define CUR 4'b0011
`define RET 4'b0100
`define IRQ 4'b0101
`define RST 4'b0110
`define LD 4'b0111
`define NOI 4'b1000
 
 
`define ALU_NOP 0
`define ALU_MTLO 30
`define ALU_MTHI 31
`define ALU_MULTU 8
`define PC_IGN 1
`define PC_KEP 2
`define PC_IRQ 4
`define PC_RST 8
`define PC_J 1
`define PC_JR 2
`define PC_BC 4
`define PC_NEXT 5
`define PC_NOP 0
`define PC_RET 6
`define PC_SPC 6
`define RF 13
`define EXEC 10
`define DMEM 4
`define WB 2
`define MUXA_PC 1
`define MUXA_RS 2
`define MUXA_EXT 3
`define MUXA_SPC 0
`define MUXA_NOP 0
`define MUXB_RT 1
`define MUXB_EXT 2
`define MUXB_NOP 0
 
`define CMP_BEQ 1
`define CMP_BNE 2
`define CMP_BLEZ 3
`define CMP_BGEZ 4
`define CMP_BGTZ 5
`define CMP_BLTZ 6
`define CMP_NOP 0
 
`define FSM_CUR 1
`define FSM_MUL 2
`define FSM_RET 4
`define FSM_NOP 0
`define FSM_LD 5
`define FSM_NOI 6
 
`define REG_NOP 0
`define REG_CLR 1
`define REG_KEP 2
 
`define EXT_SIGN 1
`define EXT_UNSIGN 2
`define EXT_J 3
`define EXT_B 4
`define EXT_SA 5
`define EXT_S2H 6
`define EXT_NOP 0
 
`define EN 1
`define DIS 0
`define IGN 0
 
`define UART_DATA_ADDR 'H80_00_00_28
`define CMD_ADDR 'H80_00_00_14
`define STATUS_ADDR 'H80_00_00_18
`define SEG7LED_ADDR 'H80_00_00_1C
`define SIM_DIS_ADDR 'H80_00_00_20
`define LCD_DATA_ADDR 'H80_00_00_24
`define IRQ_MASK_ADDR 'H80_00_00_34
`define TMR_IRQ_ADDR 'H80_00_00_28
`define TMR_DATA_ADDR 'H80_00_00_34
`define KEY1_IRQ_ADDR 'H80_00_00_2C
`define KEY2_IRQ_ADDR 'H80_00_00_30
 
`define COUNTER_VALUE1 (`FRQ/`SER_RATE/2-1)
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
 
`define ALTERA
 
`else
 
 
`endif
/mem_module.v
0,0 → 1,234
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
 
module mem_module (
clk,din,dmem_addr_i,dmem_ctl,
zZ_din,Zz_addr,Zz_dout,Zz_wr_en,dout
) ;
 
input clk;
wire clk;
input [31:0] din;
wire [31:0] din;
input [31:0] dmem_addr_i;
wire [31:0] dmem_addr_i;
input [3:0] dmem_ctl;
wire [3:0] dmem_ctl;
input [31:0] zZ_din;
wire [31:0] zZ_din;
output [31:0] Zz_addr;
wire [31:0] Zz_addr;
output [31:0] Zz_dout;
wire [31:0] Zz_dout;
output [3:0] Zz_wr_en;
wire [3:0] Zz_wr_en;
output [31:0] dout;
wire [31:0] dout;
 
wire [3:0] BUS512;
wire [1:0] BUS629;
wire [31:0] BUS650;
 
 
infile_dmem_ctl_reg dmem_ctl_post
(
.byte_addr_o(BUS629),
.clk(clk),
.ctl_i(dmem_ctl),
.ctl_o(BUS512),
.dmem_addr_i(BUS650)
);
 
 
 
mem_addr_ctl i_mem_addr_ctl
(
.addr_i(BUS650),
.ctl(dmem_ctl),
.wr_en(Zz_wr_en)
);
 
 
 
mem_din_ctl i_mem_din_ctl
(
.ctl(dmem_ctl),
.din(din),
.dout(Zz_dout)
);
 
 
 
mem_dout_ctl i_mem_dout_ctl
(
.byte_addr(BUS629),
.ctl(BUS512),
.din(zZ_din),
.dout(dout)
);
 
 
 
assign BUS650[31:0] = dmem_addr_i[31:0];
 
assign Zz_addr[31:0] = BUS650[31:0];
 
endmodule
 
 
module infile_dmem_ctl_reg(
input clk,
input [3:0]ctl_i,
input [31:0]dmem_addr_i,
output reg [1:0]byte_addr_o,
output reg [3:0]ctl_o
);
 
wire [1:0]byte_addr_i;
assign byte_addr_i = dmem_addr_i[1:0] ;
always @(posedge clk)
begin
ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0;
byte_addr_o<=byte_addr_i;
end
 
endmodule
 
module mem_addr_ctl(
input [3:0]ctl,
input [31:0]addr_i,
output reg[3:0]wr_en
);
always@(*)
case (ctl)
`DMEM_SB:
begin
case(addr_i[1:0])
0:wr_en = 4'b1000;
1:wr_en = 4'b0100;
2:wr_en = 4'b0010;
3:wr_en = 4'b0001;
default :wr_en = 4'b000;
endcase
end
`DMEM_SH :
begin
case(addr_i[1:0])
'd0:wr_en=4'b1100;
'd2:wr_en=4'b0011;
default :wr_en = 4'b0000;
endcase
end
`DMEM_SW :
begin
wr_en=4'b1111;
end
default wr_en=4'b0000;
endcase
 
endmodule
 
 
 
module mem_dout_ctl(
input [1:0]byte_addr,
input [3:0]ctl,
input [31:0] din,
output reg [31:0] dout
);
 
wire [31:0] w31 = {
din[31],din[31],din[31],din[31],din[31],din[31],din[31],din[31],
din[31],din[31],din[31],din[31],din[31],din[31],din[31],din[31],
din[31],din[31],din[31],din[31],din[31],din[31],din[31],din[31],
din[31],din[31],din[31],din[31],din[31],din[31],din[31],din[31]} ;
 
wire [31:0] w23 = {
din[23],din[23],din[23],din[23],din[23],din[23],din[23],din[23],
din[23],din[23],din[23],din[23],din[23],din[23],din[23],din[23],
din[23],din[23],din[23],din[23],din[23],din[23],din[23],din[23],
din[23],din[23],din[23],din[23],din[23],din[23],din[23],din[23]} ;
 
wire [31:0] w15 = {
din[15],din[15],din[15],din[15],din[15],din[15],din[15],din[15],
din[15],din[15],din[15],din[15],din[15],din[15],din[15],din[15],
din[15],din[15],din[15],din[15],din[15],din[15],din[15],din[15],
din[15],din[15],din[15],din[15],din[15],din[15],din[15],din[15]} ;
wire [31:0] w7 = {
din[7],din[7],din[7],din[7],din[7],din[7],din[7],din[7],
din[7],din[7],din[7],din[7],din[7],din[7],din[7],din[7],
din[7],din[7],din[7],din[7],din[7],din[7],din[7],din[7],
din[7],din[7],din[7],din[7],din[7],din[7],din[7],din[7]} ;
 
always @(*)
case (ctl)
 
`DMEM_LBS :
case (byte_addr)
'd0:dout={w31[23:0],din[31:24]};
'd1:dout={w23[23:0],din[23:16]};
'd2:dout={w15[23:0],din[15:8]};
'd3:dout={w7[23:0],din[7:0] };
default :
dout=32'b0;
endcase//checked
`DMEM_LBU :
case (byte_addr)
'd3:dout={24'b0,din[7:0]};
'd2:dout={24'b0,din[15:8]};
'd1:dout={24'b0,din[23:16]};
'd0:dout={24'b0,din[31:24]};
default :
dout=32'b0;
endcase
`DMEM_LHU :
case (byte_addr)
'd0:dout={16'b0,din[31:24],din[23:16]};
'd2:dout={16'b0,din[15:8],din[7 :0]};
default:dout=0;
endcase
`DMEM_LHS :
case (byte_addr)
'd0 :dout={w31[15:0],din[31:24],din[23:16]};
'd2 :dout={w15[15:0],din[15:8],din[7 :0]};
default:dout=0;
endcase
`DMEM_LW :
dout=din;
default :
dout=0;
endcase
endmodule
 
module mem_din_ctl(
input [3:0]ctl,
input [31:0]din,
output reg [31:0]dout
);
 
always @(*)
 
case (ctl)
`DMEM_SB :
dout={din[7:0],din[7:0],din[7:0],din[7:0]};
`DMEM_SH :
dout = {din[15:0],din[15:0]};
`DMEM_SW :
dout =din;
default dout=din;
endcase
 
endmodule
/ram_module.v
0,0 → 1,79
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
 
module mem_array
(
input clk,
input [31:0] pc_i,
output [31:0] ins_o,
input [3:0] wren,
input [31:0]din,
input [31:0]data_addr_i,
output [31:0]dout
);
wire [31:0] data_addr;
wire [31:0]dout_w;
assign dout = dout_w;
assign data_addr=data_addr_i[31:2];
wire [29:0]pc= pc_i[31:2];
 
ram2048x8_3 ram3(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(pc),
.data_b(din[31:24]),
.address_b(data_addr),
.wren_b(wren[3]),
.clock(clk),
.q_a(ins_o[31:24]),
.q_b(dout_w[31:24])
);
 
ram2048x8_2 ram2(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(pc),
.data_b(din[23:16]),
.address_b(data_addr),
.wren_b(wren[2]),
.clock(clk),
.q_a(ins_o[23:16]),
.q_b(dout_w[23:16])
);
 
ram2048x8_1 ram1(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(pc),
.data_b(din[15:8]),
.address_b(data_addr),
.wren_b(wren[1]),
.clock(clk),
.q_a(ins_o[15:8]),
.q_b(dout_w[15:8])
);
 
ram2048x8_0 ram0(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(pc),
.data_b(din[7:0]),
.address_b(data_addr),
.wren_b(wren[0]),
.clock(clk),
.q_a(ins_o[7:0]),
.q_b(dout_w[7:0])
);
 
endmodule
/ctl_fsm.v
0,0 → 1,285
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
module ctl_FSM (
clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop
);
 
parameter
 
ID_CUR = 1,
ID_LD = 5,
ID_MUL = 2,
ID_NOI = 6,
ID_RET = 4,
ONE = 1,
PC_IGN = 1,
PC_IRQ = 4,
PC_KEP = 2,
PC_RST = 8,
ZERO = 0;
 
input clk;
input [2:0] id_cmd;
input irq;
input rst;
output iack;
output zz_is_nop;
output id2ra_ctl_clr;
output id2ra_ctl_cls;
output id2ra_ins_clr;
output id2ra_ins_cls;
output [3:0] pc_prectl;
output ra2exec_ctl_clr;
 
wire clk;
reg iack;
reg zz_is_nop;
reg id2ra_ctl_clr;
reg id2ra_ctl_cls;
reg id2ra_ins_clr;
reg id2ra_ins_cls;
wire [2:0] id_cmd;
wire irq;
reg [3:0] pc_prectl;
reg ra2exec_ctl_clr;
wire rst;
reg riack;
 
reg [5:0]delay_counter_Sreg0, next_delay_counter_Sreg0;
 
reg [3:0] CurrState_Sreg0;
reg [3:0] NextState_Sreg0;
 
always @ (*)
begin : Sreg0_NextState
case (CurrState_Sreg0)
`IDLE:
begin
id2ra_ins_clr=ZERO;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ZERO;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr =ZERO;
pc_prectl=PC_IGN;
iack = riack;
if (~rst)
NextState_Sreg0 = `RST;
else
if ((irq)&&(~iack))
NextState_Sreg0 = `IRQ;
else
if (id_cmd ==ID_NOI)
NextState_Sreg0 = `NOI;
else
if (id_cmd==ID_CUR)
NextState_Sreg0 = `CUR;
else
if (id_cmd==ID_MUL)
NextState_Sreg0 = `MUL;
else
if (id_cmd==ID_LD)
NextState_Sreg0 = `LD;
else
if (id_cmd==ID_RET)
NextState_Sreg0 = `RET;
else
NextState_Sreg0 = `IDLE;
end
`MUL:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ZERO;
pc_prectl =PC_KEP;
iack = riack;
if (~rst)
NextState_Sreg0 = `RST;
else
NextState_Sreg0 = `D2_MUL_DLY;
next_delay_counter_Sreg0 = 34;
zz_is_nop =0;
end
`CUR:
begin
id2ra_ins_clr=ZERO;
id2ra_ins_cls=ONE;
id2ra_ctl_clr=ZERO;
id2ra_ctl_cls=ONE;
ra2exec_ctl_clr=ONE;
pc_prectl =PC_KEP;
iack = riack;
if (~rst)
NextState_Sreg0 = `RST;
else
NextState_Sreg0 = `NOI;
zz_is_nop = 1;
end
`RET:
begin
id2ra_ins_clr=ZERO;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ZERO;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr =ZERO;
pc_prectl =PC_IGN;
iack =ZERO;
riack =ZERO;
if (~rst)
NextState_Sreg0 = `RST;
else
NextState_Sreg0 = `IDLE;
zz_is_nop = ZERO;
end
`IRQ:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ONE;
pc_prectl =PC_IRQ;
iack =ONE;
riack=ONE;
if (~rst)
NextState_Sreg0 = `RST;
else
NextState_Sreg0 = `IDLE;
zz_is_nop = ZERO;
end
`RST:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ONE;
pc_prectl=PC_RST;
iack=ZERO;
zz_is_nop = ONE;
riack=ZERO;
if (~rst)
NextState_Sreg0 = `RST;
else
NextState_Sreg0 = `IDLE;
end
`LD:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ZERO;
pc_prectl =PC_KEP;
iack=riack;
if (~rst)
NextState_Sreg0 = `RST;
else
NextState_Sreg0 = `IDLE;
zz_is_nop = ZERO;
end
`NOI:
begin
id2ra_ins_clr=ZERO;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ZERO;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr =ZERO;
iack=riack;
pc_prectl=PC_IGN;
zz_is_nop = ZERO;
if (~rst)
NextState_Sreg0 = `RST;
else
if (id_cmd ==ID_NOI)
NextState_Sreg0 = `NOI;
else if (id_cmd==ID_CUR)
NextState_Sreg0 = `CUR;
else if (id_cmd==ID_MUL)
NextState_Sreg0 = `MUL;
else if (id_cmd==ID_LD)
NextState_Sreg0 = `LD;
else if (id_cmd==ID_RET)
NextState_Sreg0 = `RET;
else
NextState_Sreg0 = `IDLE;
end
`D2_MUL_DLY:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ZERO;
pc_prectl =PC_KEP;
iack=riack;
zz_is_nop = ONE;
if (~rst)
NextState_Sreg0 = `RST;
else
if (delay_counter_Sreg0 == 0)
NextState_Sreg0 = `IDLE;
else
begin
NextState_Sreg0 = `D2_MUL_DLY;
// if (delay_counter_Sreg0 != 0)
next_delay_counter_Sreg0 = delay_counter_Sreg0 - 1;
end
end
 
default : //the same as RST
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ONE;
pc_prectl=PC_RST;
iack=ZERO;
riack=ZERO;
zz_is_nop = ONE;
if (~rst)
NextState_Sreg0 = `RST;
else
NextState_Sreg0 =`IDLE;
end
 
endcase
end
 
always @ (posedge clk)
begin : Sreg0_CurrentState
if (~rst)
CurrState_Sreg0 <= `RST;
else
CurrState_Sreg0 <= NextState_Sreg0;
end
 
always @ (posedge clk )
begin : Sreg0_RegOutput
if (~rst)
begin
delay_counter_Sreg0 <=40; // Initialization in the reset state or default value required!!
end
else
begin
delay_counter_Sreg0 <= next_delay_counter_Sreg0;
end
end
endmodule
 
/RF_stage.v
0,0 → 1,233
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
module rf_stage (
clk,irq_i,rst_i,wb_we_i,cmp_ctl_i,
ext_ctl_i,fw_alu_i,fw_cmp_rs,fw_cmp_rt,
fw_mem_i,id_cmd,ins_i,irq_addr_i,pc_gen_ctl,
pc_i,rd_sel_i,wb_addr_i,wb_din_i,zz_spc_i,iack_o,
id2ra_ctl_clr_o,id2ra_ctl_cls_o,ra2ex_ctl_clr_o,ext_o,
pc_next,rd_index_o,rs_n_o,rs_o,rt_n_o,rt_o
) ;
 
input clk;
wire clk;
input irq_i;
wire irq_i;
input rst_i;
wire rst_i;
input wb_we_i;
wire wb_we_i;
input [2:0] cmp_ctl_i;
wire [2:0] cmp_ctl_i;
input [2:0] ext_ctl_i;
wire [2:0] ext_ctl_i;
input [31:0] fw_alu_i;
wire [31:0] fw_alu_i;
input [2:0] fw_cmp_rs;
wire [2:0] fw_cmp_rs;
input [2:0] fw_cmp_rt;
wire [2:0] fw_cmp_rt;
input [31:0] fw_mem_i;
wire [31:0] fw_mem_i;
input [2:0] id_cmd;
wire [2:0] id_cmd;
input [31:0] ins_i;
wire [31:0] ins_i;
input [31:0] irq_addr_i;
wire [31:0] irq_addr_i;
input [2:0] pc_gen_ctl;
wire [2:0] pc_gen_ctl;
input [31:0] pc_i;
wire [31:0] pc_i;
input [1:0] rd_sel_i;
wire [1:0] rd_sel_i;
input [4:0] wb_addr_i;
wire [4:0] wb_addr_i;
input [31:0] wb_din_i;
wire [31:0] wb_din_i;
input [31:0] zz_spc_i;
wire [31:0] zz_spc_i;
output iack_o;
wire iack_o;
output id2ra_ctl_clr_o;
wire id2ra_ctl_clr_o;
output id2ra_ctl_cls_o;
wire id2ra_ctl_cls_o;
output ra2ex_ctl_clr_o;
wire ra2ex_ctl_clr_o;
output [31:0] ext_o;
wire [31:0] ext_o;
output [31:0] pc_next;
wire [31:0] pc_next;
output [4:0] rd_index_o;
wire [4:0] rd_index_o;
output [4:0] rs_n_o;
wire [4:0] rs_n_o;
output [31:0] rs_o;
wire [31:0] rs_o;
output [4:0] rt_n_o;
wire [4:0] rt_n_o;
output [31:0] rt_o;
wire [31:0] rt_o;
 
 
wire NET6609;
wire NET6658;
wire NET7774;
wire NET904;
 
wire [3:0] BUS1013;
wire [31:0] BUS2085;
wire [4:0] BUS3236;
wire [4:0] BUS3237;
wire [4:0] BUS5421;
wire [31:0] BUS6061;
wire [31:0] BUS6095;
 
wire [100:0] CLK_NO;
wire [100:0] INS_NO;
 
cal_cpi CAL_CPI
(
.clk(clk),
.clk_no(CLK_NO),
.ins_no(INS_NO),
.is_nop(NET7774),
.rst(rst_i)
);
 
 
 
ctl_FSM MAIN_FSM
(
.clk(clk),
.iack(iack_o),
.id2ra_ctl_clr(id2ra_ctl_clr_o),
.id2ra_ctl_cls(id2ra_ctl_cls_o),
.id2ra_ins_clr(NET6609),
.id2ra_ins_cls(NET6658),
.id_cmd(id_cmd),
.irq(irq_i),
.pc_prectl(BUS1013),
.ra2exec_ctl_clr(ra2ex_ctl_clr_o),
.rst(rst_i),
.zz_is_nop(NET7774)
);
 
 
 
pc_gen i_pc_gen
(
.check(NET904),
.ctl(pc_gen_ctl),
.imm(ext_o),
.irq(irq_addr_i),
.pc(pc_i),
.pc_next(pc_next),
.pc_prectl(BUS1013),
.s(rs_o),
.zz_spc(zz_spc_i)
);
 
 
 
compare i_cmp
(
.ctl(cmp_ctl_i),
.res(NET904),
.s(rs_o),
.t(rt_o)
);
 
 
 
ext i_ext
(
.ctl(ext_ctl_i),
.ins_i(BUS2085),
.res(ext_o)
);
 
 
 
r32_reg_clr_cls ins_reg
(
.clk(clk),
.clr(NET6609),
.cls(NET6658),
.r32_i(ins_i),
.r32_o(BUS2085)
);
 
 
 
jack jack1
(
.ins_i(BUS2085),
.rd_o(BUS5421),
.rs_o(rs_n_o),
.rt_o(rt_n_o)
);
 
 
 
jack jack2
(
.ins_i(ins_i),
.rs_o(BUS3237),
.rt_o(BUS3236)
);
 
rd_sel rd_sel
(
.ctl(rd_sel_i),
.rd_i(BUS5421),
.rd_o(rd_index_o),
.rt_i(rt_n_o)
);
 
reg_array reg_bank
(
.clock(clk),
.data(wb_din_i),
.qa(BUS6061),
.qb(BUS6095),
.rd_clk_cls(NET6658),
.rdaddress_a(BUS3237),
.rdaddress_b(BUS3236),
.wraddress(wb_addr_i),
.wren(wb_we_i)
);
 
fwd_mux rf_fwd_rt
(
.din(BUS6095),
.dout(rt_o),
.fw_alu(fw_alu_i),
.fw_ctl(fw_cmp_rt),
.fw_dmem(fw_mem_i)
);
 
fwd_mux rs_fwd_rs
(
.din(BUS6061),
.dout(rs_o),
.fw_alu(fw_alu_i),
.fw_ctl(fw_cmp_rs),
.fw_dmem(fw_mem_i)
);
 
endmodule
/mips_top.v
0,0 → 1,122
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
module mips_top (
input clk,
input rst,
input ser_rxd,
output ser_txd,
output [6:0]seg7led1,
output [6:0]seg7led2,
output [7:0] lcd_data,
output lcd_rs,
output lcd_rw,
output lcd_en,
output led1,
output led2,
input key1,
input key2
);
 
wire [31:0] data2core;
wire [31:0] data2mem;
wire [31:0] ins2core;
wire [31:0] mem_Addr;
wire [31:0] pc;
wire [3:0] wr_en;
wire CLK;
reg r_rst;
 
 
//wire sys_rst=rst;
always @(posedge CLK)
if (rst) r_rst<=1'b1; else r_rst<=1'b0;
//wire sys_rst = r_rst;
 
reg rr_rst;
always @(posedge CLK)
rr_rst<=r_rst;
 
wire sys_rst = rr_rst;
 
//assign CLK = clk;
`ifdef ALTERA
 
pll50 Ipll(
.inclk0(clk),
.c0(CLK)
);
`else
assign CLK = clk;
`endif
 
`ifdef ALTERA
 
mem_array ram_8k
(
.clk(CLK),
.din(data2mem),
.dout(data2core),
.ins_o(ins2core),
.pc_i(pc),
.data_addr_i(mem_Addr),
.wren(wr_en)
);
 
`else
 
sim_mem_array sim_array (
.clk(CLK),
.pc_i(pc),
.ins_o(ins2core),
.wren(wr_en),
.din(data2mem),
.data_addr_i(mem_Addr),
.dout(data2core)
);
`endif
 
mips_sys isys
(
 
.zz_addr_o(mem_Addr),
.zz_din(data2core),
.zz_dout(data2mem),
.zz_ins_i(ins2core),
.zz_pc_o(pc),
.zz_wr_en_o(wr_en),
 
.clk(CLK),
.rst(sys_rst),
 
.ser_rxd(ser_rxd),
.ser_txd(ser_txd),
 
.seg7led1(seg7led1),
.seg7led2(seg7led2),
 
.lcd_data(lcd_data),
.lcd_rs(lcd_rs),
.lcd_rw(lcd_rw),
.lcd_en(lcd_en),
 
.led1(led1),
.led2(led2),
 
.key1(key1),
.key2(key2)
);
 
endmodule
/decode_pipe.v
0,0 → 1,1603
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
module decoder(
input [31:0]ins_i,
output reg [`EXT_CTL_LEN-1:0] ext_ctl,
output reg [`RD_SEL_LEN-1:0] rd_sel,
output reg [`CMP_CTL_LEN-1:0]cmp_ctl,
output reg [`PC_GEN_CTL_LEN-1:0]pc_gen_ctl,
output reg [`FSM_CTL_LEN-1:0]fsm_dly,
output reg [`MUXA_CTL_LEN-1:0]muxa_ctl,
output reg [`MUXB_CTL_LEN-1:0]muxb_ctl,
output reg [`ALU_FUNC_LEN-1:0]alu_func,
output reg [`DMEM_CTL_LEN-1:0]dmem_ctl,
output reg [`ALU_WE_LEN-1:0] alu_we,
output reg [`WB_MUX_CTL_LEN-1:0]wb_mux,
output reg [`WB_WE_LEN-1:0]wb_we
);
 
wire [5:0] inst_op,inst_func;
wire [4:0] inst_regimm;//,inst_rs,inst_rt,inst_rd,inst_sa;
wire [4:0] inst_cop0_func;//cop0's function code filed
wire [25:0] inst_cop0_code;//cop0's code field
 
assign inst_op = ins_i[31:26];
assign inst_func = ins_i[5:0];
assign inst_regimm = ins_i[20:16];
assign inst_cop0_func = ins_i[25:21];
assign inst_cop0_code = ins_i[25:0];
 
always @(*)
begin
case (inst_op)//synthesis parallel_case
'd0://special operation
begin
case (inst_func) //synthesis parallel_case
'd0://SLL rd,rt,sa
begin
//replaceID = `SLL ;
ext_ctl = `EXT_SA;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_EXT;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SLL;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLL ;
end
'd2://SRL rd,rt,sa
begin
//replaceID = `SRL ;
ext_ctl = `EXT_SA;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_EXT;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SRL;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SRL ;
end
'd3://SRA rd,rt,sa
begin
//replaceID = `SRA ;
ext_ctl = `EXT_SA;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_EXT;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SRA;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SRA ;
end
'd4://SLLV rd,rt,rs
begin
//replaceID = `SLLV ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = 1'bx;//`IGN;
//end of `SLLV ;
end
'd6://SRLV rd,rt,rs
begin
//replaceID = `SRLV ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SRLV ;
end
'd7://SRAV rd,rt,rs
begin
//replaceID = `SRAV ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SRAV ;
end
'd8://JR rs
begin
//replaceID = `JR ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_JR;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `JR ;
end
'd9://JALR jalr rs(rd=31) or jalr rd,rs
begin
//replaceID = `JALR ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `JALR ;
end
'd12://SYSCALL
begin
//replaceID = `SYSCALL ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SYSCALL ;
end
'd13://BREAK
begin
//replaceID = `BREAK ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `BREAK ;
end
'd16://MFHI rd
begin
//replaceID = `MFHI ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_MFHI;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `MFHI ;
end
'd17://MTHI rs
begin
//replaceID = `MTHI ;
ext_ctl = `EXT_NOP ;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_MTHI;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `MTHI ;
end
'd18://MFLO rd
begin
//replaceID = `MFLO ;
ext_ctl = `EXT_NOP ;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_MFLO;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `MFLO ;
end
'd19://MTLO rs
begin
//replaceID = `MTLO ;
ext_ctl = `EXT_NOP ;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_MFLO;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
 
//end of `MTLO ;
end
'd24://MULT rs,rt
begin
//replaceID = `MULT ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_MUL;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_MULT;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `MULT ;
end
'd25://MULTU rs,rt
begin
//replaceID = `MULTU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_MUL;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_MULTU;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `MULTU ;
end
'd26://DIV rs,rt
begin
//replaceID = `DIV ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_MUL;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_DIV;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `DIV ;
end
'd27://DIVU rs,rt
begin
//replaceID = `DIVU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_MUL;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_DIVU;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `DIVU ;
end
'd32://ADD rd,rs,rt
begin
//replaceID = `ADD ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_ADD;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ADD ;
end
'd33://ADDU rd,rs,rt
begin
//replaceID = `ADDU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_ADD;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ADDU ;
end
'd34://SUB rd,rs,rt
begin
//replaceID = `SUB ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SUB;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SUB ;
end
'd35://SUBU rd,rs,rt
begin
//replaceID = `SUBU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SUBU;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SUBU ;
end
'd36://AND rd,rs,rt
begin
//replaceID = `AND ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_AND;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `AND ;
end
'd37://OR rd,rs,rt
begin
//replaceID = `OR ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_OR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `OR ;
end
'd38://XOR rd,rs,rt
begin
//replaceID = `XOR ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_XOR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `XOR ;
end
'd39://NOR rd,rs,rt
begin
//replaceID = `NOR ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_NOR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `NOR ;
end
'd42://SLT rd,rs,rt
begin
//replaceID = `SLT ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SLT;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLT ;
end
'd43://SLTU rd,rs,rt
begin
//replaceID = `SLTU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SLTU;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLTU ;
end
default:
begin
//replaceID = `INVALID ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `INVALID ;
end
endcase
end
'd1://regimm opreation
begin
case (inst_regimm) //synthesis parallel_case
'd0://BLTZ rs,offset(signed)
begin
//replaceID = `BLTZ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BLTZ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BLTZ ;
end
'd1://BGEZ rs,offset(signed)
begin
//replaceID = `BGEZ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BGEZ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BGEZ ;
end
'd16://BLTZAL rs,offset(signed)
begin
//replaceID = `BLTZAL ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `BLTZAL ;
end
'd17://BGEZAL rs,offset(signed)
begin
//replaceID = `BGEZAL ;
//replaceID = `INVALID ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `INVALID ;
end
default:
begin
//replaceID = `INVALID ;
//replaceID = `INVALID ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `INVALID ;
end
endcase
end
'd2://J imm26({pc[31:28],imm26,00})
begin
//replaceID = `J ;
ext_ctl = `EXT_J;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_J;
fsm_dly = `FSM_NOI;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `J ;
end
'd3://JAL imm26({pc[31:28],imm26,00})
begin
//replaceID = `JAL ;
ext_ctl = `EXT_J;
rd_sel = `RD_R31;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_J;
fsm_dly = `FSM_NOI;
muxa_ctl = `MUXA_PC;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_PA;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `JAL ;
end
'd4://BEQ rs,rt,offset(signed)
begin
//replaceID = `BEQ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BEQ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BEQ ;
end
'd5://BNE rs,rt,offset(signed)
begin
//replaceID = `BNE ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BNE;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BNE ;
end
'd6://BLEZ rs,offset(signed)
begin
//replaceID = `BLEZ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BLEZ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BLEZ ;
end
'd7://BGTZ rs,offset(signed)
begin
//replaceID = `BGTZ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BGTZ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BGTZ ;
end
'd8://ADDI rt,rs,imm16(singed)
begin
//replaceID = `ADDI ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ADDI ;
end
'd9://ADDIU rt,rs,imm16(singed)
begin
//replaceID = `ADDIU ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ADDIU ;
end
'd10://SLTI rt,rs,imm16(singed)
begin
//replaceID = `SLTI ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_SLT;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLTI ;
end
'd11://SLTIU rt,rs,imm16(singed)
begin
//replaceID = `SLTIU ;
ext_ctl = `EXT_UNSIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_SLTU;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLTIU ;
end
'd12://ANDI rt,rs,imm16(singed)
begin
//replaceID = `ANDI ;
ext_ctl = `EXT_UNSIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_AND;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ANDI ;
end
'd13://ORI rt,rs,imm16(singed)
begin
//replaceID = `ORI ;
ext_ctl = `EXT_UNSIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_OR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `ORI ;
end
'd14://XORI rt,rs,imm16(singed)
begin
//replaceID = `XORI ;
ext_ctl = `EXT_UNSIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_XOR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `EN;
wb_mux = `WB_ALU;
//end of `XORI ;
end
'd15://LUI rt,imm16
begin
//replaceID = `LUI ;
ext_ctl = `EXT_S2H;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_PB;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `LUI ;
end
'd16://COP0 func
begin
case(inst_cop0_func) //synthesis parallel_case
'd0://mfc0 rt,rd // GPR[rd] = CPR[rt] //differ to mips32 definition
//read saved PC
begin
//replaceID = `MFC0;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_SPC;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_PA;
alu_we = `EN;
dmem_ctl = `DMEM_LB;
wb_we = `DIS;
wb_mux = `WB_ALU;
end
 
'd4://mtc0 rt,rd // CPR[rd] = GPR[rt] //follow the mips32 definition
begin //return from interrupt
//replaceID = `MTC0;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_SPC;
fsm_dly = `FSM_RET;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
end
default:
begin
//replaceID = `INVALID ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `INVALID ;
end
endcase
end
'd32://LB rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LB ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LBS;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LB ;
end
'd33://LH rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LH ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LHS;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LH ;
end
'd34://LWL rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LWL ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `LWL ;
end
'd35://LW rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LW ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LW;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LW ;
end
'd36://LBU rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LBU ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LBU;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LBU ;
end
'd37://LHU rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LHU ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LHU;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LHU ;
end
'd38://LWR rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LWR ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `LWR ;
end
'd40://SB rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SB ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_SB;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `SB ;
end
'd41://SH rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SH ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_SH;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `SH ;
end
'd42://SWL rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SWL ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SWL ;
end
'd43://SW rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SW ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_SW;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `SW ;
end
'd46://SWR rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SWR ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SWR ;
end
default:
begin
//replaceID = `INVALID ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `INVALID ; //replaceID = `INVALID ;
end
endcase
end
endmodule
 
 
 
module pipelinedregs (
clk,id2ra_ctl_clr,id2ra_ctl_cls,ra2ex_ctl_clr,
alu_func_i,alu_we_i,cmp_ctl_i,dmem_ctl_i,ext_ctl_i,
muxa_ctl_i,muxb_ctl_i,pc_gen_ctl_i,rd_sel_i,wb_mux_ctl_i,
wb_we_i,alu_func_o,alu_we_o,cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,
ext_ctl,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,wb_mux_ctl_o,wb_we_o
) ;
 
input clk;
wire clk;
input id2ra_ctl_clr;
wire id2ra_ctl_clr;
input id2ra_ctl_cls;
wire id2ra_ctl_cls;
input ra2ex_ctl_clr;
wire ra2ex_ctl_clr;
input [4:0] alu_func_i;
wire [4:0] alu_func_i;
input [0:0] alu_we_i;
wire [0:0] alu_we_i;
input [2:0] cmp_ctl_i;
wire [2:0] cmp_ctl_i;
input [3:0] dmem_ctl_i;
wire [3:0] dmem_ctl_i;
input [2:0] ext_ctl_i;
wire [2:0] ext_ctl_i;
input [1:0] muxa_ctl_i;
wire [1:0] muxa_ctl_i;
input [1:0] muxb_ctl_i;
wire [1:0] muxb_ctl_i;
input [2:0] pc_gen_ctl_i;
wire [2:0] pc_gen_ctl_i;
input [1:0] rd_sel_i;
wire [1:0] rd_sel_i;
input [0:0] wb_mux_ctl_i;
wire [0:0] wb_mux_ctl_i;
input [0:0] wb_we_i;
wire [0:0] wb_we_i;
output [4:0] alu_func_o;
wire [4:0] alu_func_o;
output [0:0] alu_we_o;
wire [0:0] alu_we_o;
output [2:0] cmp_ctl_o;
wire [2:0] cmp_ctl_o;
output [3:0] dmem_ctl_o;
wire [3:0] dmem_ctl_o;
output [3:0] dmem_ctl_ur_o;
wire [3:0] dmem_ctl_ur_o;
output [2:0] ext_ctl;
wire [2:0] ext_ctl;
output [1:0] muxa_ctl_o;
wire [1:0] muxa_ctl_o;
output [1:0] muxb_ctl_o;
wire [1:0] muxb_ctl_o;
output [2:0] pc_gen_ctl_o;
wire [2:0] pc_gen_ctl_o;
output [1:0] rd_sel_o;
wire [1:0] rd_sel_o;
output [0:0] wb_mux_ctl_o;
wire [0:0] wb_mux_ctl_o;
output [0:0] wb_we_o;
wire [0:0] wb_we_o;
 
 
wire NET7643;
wire [0:0] BUS4987;
wire [1:0] BUS5008;
wire [1:0] BUS5483;
wire [0:0] BUS5639;
wire [0:0] BUS5651;
wire [3:0] BUS5666;
wire [4:0] BUS5674;
wire [0:0] BUS5682;
wire [0:0] BUS5690;
wire [0:0] BUS5790;
wire [0:0] BUS7299;
wire [0:0] BUS7822;
 
 
muxb_ctl_reg_clr_cls U1
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.muxb_ctl_i(muxb_ctl_i),
.muxb_ctl_o(BUS5483)
);
 
 
 
wb_mux_ctl_reg_clr_cls U10
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.wb_mux_ctl_i(wb_mux_ctl_i),
.wb_mux_ctl_o(BUS5651)
);
 
 
 
wb_we_reg_clr_cls U11
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.wb_we_i(wb_we_i),
.wb_we_o(BUS5639)
);
 
 
 
wb_we_reg U12
(
.clk(clk),
.wb_we_i(NET7643),
.wb_we_o(wb_we_o)
);
 
 
 
wb_mux_ctl_reg_clr U13
(
.clk(clk),
.clr(ra2ex_ctl_clr),
.wb_mux_ctl_i(BUS5651),
.wb_mux_ctl_o(BUS5690)
);
 
 
 
muxb_ctl_reg_clr U14
(
.clk(clk),
.clr(ra2ex_ctl_clr),
.muxb_ctl_i(BUS5483),
.muxb_ctl_o(muxb_ctl_o)
);
 
 
 
dmem_ctl_reg_clr U15
(
.clk(clk),
.clr(ra2ex_ctl_clr),
.dmem_ctl_i(BUS5666),
.dmem_ctl_o(dmem_ctl_ur_o)
);
 
 
 
alu_func_reg_clr U16
(
.alu_func_i(BUS5674),
.alu_func_o(alu_func_o),
.clk(clk),
.clr(ra2ex_ctl_clr)
);
 
 
 
muxa_ctl_reg_clr U17
(
.clk(clk),
.clr(ra2ex_ctl_clr),
.muxa_ctl_i(BUS5008),
.muxa_ctl_o(muxa_ctl_o)
);
 
 
 
wb_mux_ctl_reg U18
(
.clk(clk),
.wb_mux_ctl_i(BUS5790),
.wb_mux_ctl_o(wb_mux_ctl_o)
);
 
 
 
wb_we_reg_clr U19
(
.clk(clk),
.clr(ra2ex_ctl_clr),
.wb_we_i(BUS5639),
.wb_we_o(BUS5682)
);
 
 
 
cmp_ctl_reg_clr_cls U2
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cmp_ctl_i(cmp_ctl_i),
.cmp_ctl_o(cmp_ctl_o)
);
 
 
 
wb_we_reg U20
(
.clk(clk),
.wb_we_i(BUS5682),
.wb_we_o(BUS7822)
);
 
 
 
wb_mux_ctl_reg U21
(
.clk(clk),
.wb_mux_ctl_i(BUS5690),
.wb_mux_ctl_o(BUS5790)
);
 
 
 
wb_we_reg U22
(
.clk(clk),
.wb_we_i(BUS7299),
.wb_we_o(alu_we_o)
);
 
 
 
assign NET7643 = alu_we_o[0] | BUS7822[0];
 
 
alu_we_reg_clr U24
(
.alu_we_i(BUS4987),
.alu_we_o(BUS7299),
.clk(clk),
.clr(ra2ex_ctl_clr)
);
 
 
 
alu_func_reg_clr_cls U26
(
.alu_func_i(alu_func_i),
.alu_func_o(BUS5674),
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls)
);
 
 
 
dmem_ctl_reg_clr_cls U3
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.dmem_ctl_i(dmem_ctl_i),
.dmem_ctl_o(BUS5666)
);
 
 
 
ext_ctl_reg_clr_cls U4
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.ext_ctl_i(ext_ctl_i),
.ext_ctl_o(ext_ctl)
);
 
 
 
rd_sel_reg_clr_cls U5
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.rd_sel_i(rd_sel_i),
.rd_sel_o(rd_sel_o)
);
 
 
 
alu_we_reg_clr_cls U6
(
.alu_we_i(alu_we_i),
.alu_we_o(BUS4987),
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls)
);
 
 
 
muxa_ctl_reg_clr_cls U7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.muxa_ctl_i(muxa_ctl_i),
.muxa_ctl_o(BUS5008)
);
 
 
 
pc_gen_ctl_reg_clr_cls U8
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.pc_gen_ctl_i(pc_gen_ctl_i),
.pc_gen_ctl_o(pc_gen_ctl_o)
);
 
 
 
dmem_ctl_reg U9
(
.clk(clk),
.dmem_ctl_i(dmem_ctl_ur_o),
.dmem_ctl_o(dmem_ctl_o)
);
 
 
 
endmodule
 
module decode_pipe
(
clk,id2ra_ctl_clr,id2ra_ctl_cls,
ra2ex_ctl_clr,ins_i,alu_func_o,alu_we_o,
cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,ext_ctl_o,
fsm_dly,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,
wb_mux_ctl_o,wb_we_o
) ;
 
input clk;
wire clk;
input id2ra_ctl_clr;
wire id2ra_ctl_clr;
input id2ra_ctl_cls;
wire id2ra_ctl_cls;
input ra2ex_ctl_clr;
wire ra2ex_ctl_clr;
input [31:0] ins_i;
wire [31:0] ins_i;
output [4:0] alu_func_o;
wire [4:0] alu_func_o;
output [0:0] alu_we_o;
wire [0:0] alu_we_o;
output [2:0] cmp_ctl_o;
wire [2:0] cmp_ctl_o;
output [3:0] dmem_ctl_o;
wire [3:0] dmem_ctl_o;
output [3:0] dmem_ctl_ur_o;
wire [3:0] dmem_ctl_ur_o;
output [2:0] ext_ctl_o;
wire [2:0] ext_ctl_o;
output [2:0] fsm_dly;
wire [2:0] fsm_dly;
output [1:0] muxa_ctl_o;
wire [1:0] muxa_ctl_o;
output [1:0] muxb_ctl_o;
wire [1:0] muxb_ctl_o;
output [2:0] pc_gen_ctl_o;
wire [2:0] pc_gen_ctl_o;
output [1:0] rd_sel_o;
wire [1:0] rd_sel_o;
output [0:0] wb_mux_ctl_o;
wire [0:0] wb_mux_ctl_o;
output [0:0] wb_we_o;
wire [0:0] wb_we_o;
 
 
wire [4:0] BUS2040;
wire [0:0] BUS2048;
wire [2:0] BUS2056;
wire [3:0] BUS2064;
wire [2:0] BUS2072;
wire [1:0] BUS2086;
wire [1:0] BUS2094;
wire [2:0] BUS2102;
wire [1:0] BUS2110;
wire [0:0] BUS2118;
wire [0:0] BUS2126;
 
 
decoder idecoder
(
.alu_func(BUS2040),
.alu_we(BUS2048),
.cmp_ctl(BUS2056),
.dmem_ctl(BUS2064),
.ext_ctl(BUS2072),
.fsm_dly(fsm_dly),
.ins_i(ins_i),
.muxa_ctl(BUS2086),
.muxb_ctl(BUS2094),
.pc_gen_ctl(BUS2102),
.rd_sel(BUS2110),
.wb_mux(BUS2118),
.wb_we(BUS2126)
);
 
 
 
pipelinedregs pipereg
(
.alu_func_i(BUS2040),
.alu_func_o(alu_func_o),
.alu_we_i(BUS2048),
.alu_we_o(alu_we_o),
.clk(clk),
.cmp_ctl_i(BUS2056),
.cmp_ctl_o(cmp_ctl_o),
.dmem_ctl_i(BUS2064),
.dmem_ctl_o(dmem_ctl_o),
.dmem_ctl_ur_o(dmem_ctl_ur_o),
.ext_ctl(ext_ctl_o),
.ext_ctl_i(BUS2072),
.id2ra_ctl_clr(id2ra_ctl_clr),
.id2ra_ctl_cls(id2ra_ctl_cls),
.muxa_ctl_i(BUS2086),
.muxa_ctl_o(muxa_ctl_o),
.muxb_ctl_i(BUS2094),
.muxb_ctl_o(muxb_ctl_o),
.pc_gen_ctl_i(BUS2102),
.pc_gen_ctl_o(pc_gen_ctl_o),
.ra2ex_ctl_clr(ra2ex_ctl_clr),
.rd_sel_i(BUS2110),
.rd_sel_o(rd_sel_o),
.wb_mux_ctl_i(BUS2118),
.wb_mux_ctl_o(wb_mux_ctl_o),
.wb_we_i(BUS2126),
.wb_we_o(wb_we_o)
);
 
 
 
endmodule
 
 
 
 
 
/mips_uart.v
0,0 → 1,322
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
module rxd_d(input clr,input clk,input d,output reg q );
 
always @(posedge clk)
 
if (clr) q<=0;
else q<=d|q;
 
endmodule
 
module uart0 (
clk,rst,rxd_ft,ser_rxd,txd_ld,
din,rxd_rdy,ser_txd,txd_busy,dout) ;
input clk;
wire clk;
input rst;
wire rst;
input rxd_ft;
wire rxd_ft;
input ser_rxd;
wire ser_rxd;
input txd_ld;
wire txd_ld;
input [7:0] din;
wire [7:0] din;
output rxd_rdy;
wire rxd_rdy;
output ser_txd;
wire ser_txd;
output txd_busy;
wire txd_busy;
output [7:0] dout;
wire [7:0] dout;
 
wire clk_uart=clk;
wire w_rxd_rdy;
 
uart_read uart_rd_tak(
.sync_reset(rst),
.clk(clk),
.rxd(ser_rxd),
.buffer_reg(dout),
.int_req(w_rxd_rdy)
);
 
rxd_d rxd_rdy_hold_lw
(
.clk(clk_uart),
.clr(rxd_ft),
.d(w_rxd_rdy),
.q(rxd_rdy)
);
 
uart_write uart_txd
(
.sync_reset(rst),
.clk(clk),
.txd(ser_txd),
.data_in(din) ,
.write_request(txd_ld),
//.write_done(),
.write_busy(txd_busy)
);
 
endmodule
 
//These modules below are modified slight by Liwei based on YACC,an CPU core in opencores.
//Thank you TAK
 
module uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);
input sync_reset,clk;
input [7:0] data_in;
input write_request;
output txd,write_done;
output write_busy;
 
 
 
wire queue_full;
wire queing, read_request;
wire [7:0] queue_data;
reg read_request_ff;
 
 
//________|--|___write_request (upper module : its period should be 1clock time.)
//__________________________|-|______write_done (Responds by this module posedge interrupt)
//With 512Bytes FIFO.
//No error handling is supported.
 
reg [15:0] clk_ctr;//liwei
reg [2:0] bit_ctr;
reg [2:0] ua_state;
reg [7:0] tx_sr;
reg txd;
 
wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
clk_ctr_enable_state, bit_ctr_enable_state ;
wire tx_state;
wire empty;
assign write_busy=queue_full;//Apr.2.2005
 
always @ (posedge clk) begin
if (~sync_reset) read_request_ff<=1'b0;
else read_request_ff<=read_request;
end
 
assign queing= !empty;
assign read_request = queing && ua_state==3'b000;//Jul.14.2004
 
assign write_done=ua_state==3'b101;
 
`ifdef ALTERA
fifo512_cyclone alt_fifo(
.data(data_in),
.wrreq(write_request),
.rdreq(read_request),
.clock(clk),
.q(queue_data),
.full(queue_full),
.empty(empty));
`else//debug model in simulations
 
sim_fifo512_cyclone sim_fifo(
.data(data_in),
.wrreq(write_request),
.rdreq(read_request),
.clock(clk),
.q(queue_data),
.full(queue_full),
.empty(empty),
.rst(sync_reset));
`endif
 
 
 
// 7bit counter
// I set the regerster lenth as 16 .Sufficent but not waste.Liwei
always @(posedge clk ) begin
if (~sync_reset)
clk_ctr <= 0;
else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
else clk_ctr <= 0;
end
 
 
assign clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1;
assign clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2;
 
// 3bit counter
always @(posedge clk) begin
if (~sync_reset)
bit_ctr <= 0;
else if (bit_ctr_enable_state) begin
if (clk_ctr_equ15)
bit_ctr <= bit_ctr + 1;
end
else
bit_ctr <= 0;
end
 
assign bit_ctr_equ7 = (bit_ctr==7);
 
assign clk_ctr_enable_state = bit_ctr_enable_state ||ua_state==3'b110 || ua_state==3'b001 || ua_state==3'b100||ua_state==3'b101;
assign bit_ctr_enable_state = ua_state==3'b010 || ua_state==3'b011;
 
 
always @(posedge clk ) begin
if (~sync_reset) ua_state <= 3'b000;
else begin
case (ua_state)
3'b000: if (queing) ua_state <= 3'b001; //wait write_request
3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send
3'b011: if (clk_ctr_equ15) ua_state <= 3'b100; // bit7 data send
3'b100: if (clk_ctr_equ15) ua_state <= 3'b101; // stop bit // stop bit send
3'b101: if (clk_ctr_equ15) ua_state <= 3'b110; //LIWEI // stop bit send
3'b110: if (clk_ctr_equ15) ua_state <= 3'b111; //LIWEI
3'b111: ua_state <= 3'h0; // TAK // byte read cycle end
default: ua_state <= 3'h0;
endcase
end
end
 
 
 
 
// tx shift reg.
always @(posedge clk ) begin
if (~sync_reset) tx_sr<=0;
else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load
else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};
end
 
assign tx_state=( ua_state==3'h2 || ua_state==3'h3) && clk_ctr_equ15;
 
 
// tx
always @(posedge clk ) begin
if (~sync_reset) txd <=1'b1;
else if (~sync_reset) txd<=1'b1;
else if (ua_state==3'h0) txd<=1'b1;
else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0; // start bit
else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];
else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1; // stop bit
end
endmodule
 
 
module uart_read( sync_reset, clk, rxd,buffer_reg, int_req);
input sync_reset;
input clk, rxd;
output [7:0] buffer_reg;
output int_req;
 
 
//________|-|______int_req (This module,, posedge interrupt)
//
//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...
//
//No error handling (overrun ) is supported.
 
reg rxq1;
reg [15:0] clk_ctr;
reg [2:0] bit_ctr;
reg [2:0] ua_state;
reg [7:0] rx_sr; //.,tx_sr;
reg int_req;
reg [7:0] buffer_reg;
 
wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
clk_ctr_enable_state, bit_ctr_enable_state ;
wire clk_ctr_equ0;
 
//sync_reset
 
//synchronization
always @(posedge clk ) begin
rxq1 <=rxd ;
end
 
// 7bit counter
always @(posedge clk ) begin
if (~sync_reset)
clk_ctr <= 0;
else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
else clk_ctr <= 0;
end
assign clk_ctr_equ15 = (clk_ctr==`COUNTER_VALUE1) ;//
assign clk_ctr_equ31 = (clk_ctr==`COUNTER_VALUE2) ;//
assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
 
 
// 3bit counter
always @(posedge clk) begin
if (~sync_reset)
bit_ctr <= 0;
else if (bit_ctr_enable_state) begin
if (clk_ctr_equ15)
bit_ctr <= bit_ctr + 1;
end
else
bit_ctr <= 0;
end
 
assign bit_ctr_equ7 = (bit_ctr==7);
 
 
assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
assign bit_ctr_enable_state = ua_state==3'h2;
 
always @(posedge clk ) begin
if (~sync_reset) ua_state <= 3'h0;
else begin
case (ua_state)
3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive
3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
3'h3: if (clk_ctr_equ15) ua_state <=3'h4; // stop bit receive
3'h4: ua_state <= 3'b000;
default: ua_state <= 3'b000;
endcase
end
end
 
 
//reg_we
always @(posedge clk ) begin
if (~sync_reset) buffer_reg<=8'h00;
else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;
end
 
//int_req
always @(posedge clk ) begin
if (~sync_reset) int_req<=1'b0;
else if (ua_state==3'h4 ) int_req<=1'b1;
else int_req<=1'b0;
end
 
 
// rx shift reg.
always @(posedge clk ) begin
if (~sync_reset) rx_sr <= 0;
else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
end
 
endmodule
/mips_dvc.v
0,0 → 1,206
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
module mips_dvc (
 
input [31:0]din,
input clk,
input rst,
input [31:0]addr ,
input [3:0]mem_ctl,
 
output reg [31:0]dout ,
 
output reg[7:0] lcd_data,
output lcd_rs,
output lcd_rw,
output lcd_en,
 
input ser_rxd,
output ser_txd,
 
output [6:0]seg7led1,
output [6:0]seg7led2 ,
output led1,
output led2 ,
input key1,
input key2 ,
 
output reg[31:0]irq_addr_o, //not registed
output reg irq_req_o
);
 
reg r_key1;
reg r_key2;
 
reg rr_key1;
reg rr_key2;
 
always @(posedge clk)
begin
r_key1<=key1;
r_key2<=key2;
end
 
always @(posedge clk)
begin
rr_key1<=r_key1;
rr_key2<=r_key2;
end
 
initial
begin
lcd_data<=0;
end
wire sv_byte = (mem_ctl==`DMEM_SB);
wire ld_byte = mem_ctl==`DMEM_LBS||mem_ctl==`DMEM_LBU;
 
wire sv_wd = (mem_ctl==`DMEM_SW);
wire ld_wd = (mem_ctl==`DMEM_LW);
 
 
wire wr_uartdata = addr==`UART_DATA_ADDR && sv_byte;
wire wr_lcddata = addr==`LCD_DATA_ADDR && sv_byte;
wire rd_uartdata = addr==`UART_DATA_ADDR && ld_byte;
wire rd_status = addr==`STATUS_ADDR && ld_wd;
wire wr_cmd = addr==`CMD_ADDR && sv_wd;
wire rd_cmd = addr==`CMD_ADDR && ld_wd;
wire wr_seg7 = addr==`SEG7LED_ADDR && sv_byte ;
 
wire set_tmr_addr = addr==`TMR_IRQ_ADDR && sv_wd;
wire set_key1_addr = addr==`KEY1_IRQ_ADDR && sv_wd;
wire set_key2_addr = addr==`KEY2_IRQ_ADDR && sv_wd;
wire wr_tmr_data = addr==`TMR_DATA_ADDR && sv_wd;
wire rd_tmr_data = addr==`TMR_DATA_ADDR && ld_wd;
 
wire w_tmr_req;
wire [31:0]w_tmr_data;
 
reg [31:0] tmr_addr;
reg [31:0] key1_addr;
reg [31:0] key2_addr;
 
reg [31:0] cmd ;
 
wire global_mask = cmd[0] ;
wire w_rxd_ft = cmd[1] ;
 
assign lcd_rs = cmd[2] ;
assign lcd_rw = cmd[3] ;
assign lcd_en = cmd[4] ;
 
assign led1 = cmd[5] ;
assign led2 = cmd[6] ;
 
wire tmr_clr = cmd[7] ;
wire tmr_en = cmd[8] ;
 
reg [7:0] seg7data;
wire [7:0] uart_dout;
wire w_txd_busy;
wire w_rx_rdy;
 
always@(posedge clk )
if (~rst)
begin
dout<=0;
end
else
begin
if (rd_status) dout<={28'b0,/*added here*/w_rx_rdy,w_txd_busy,rr_key1,rr_key2};else
if (rd_cmd)dout<=cmd;else
if (rd_uartdata)dout<={24'b0,uart_dout};else
if ( rd_tmr_data )dout<=w_tmr_data; else
dout<=0;
end
 
always @(posedge clk)
if (~rst)
begin
cmd<=0;
seg7data<=0;
tmr_addr<=32'bX;
key1_addr<=32'BX;
key2_addr<=32'BX;
end
else
begin
 
if (wr_cmd) cmd<=din;
if (wr_seg7) seg7data<=din[7:0];
if (wr_lcddata) lcd_data<=din[7:0];
 
if (set_tmr_addr)tmr_addr<=din;
if (set_key1_addr)key1_addr<=din;
if (set_key2_addr)key2_addr<=din;
 
end
 
uart0 iuart0(
 
.clk(clk),
.rst(rst),
.ser_rxd(ser_rxd),
.ser_txd(ser_txd),
 
.rxd_ft(w_rxd_ft),
.txd_ld(wr_uartdata),
 
.din(din[7:0]),
 
.rxd_rdy(w_rx_rdy),
.txd_busy(w_txd_busy),
 
.dout(uart_dout)
) ;
 
seg7led_cv iseg7_cv (
.data(seg7data),
.seg7led1(seg7led1),
.seg7led2(seg7led2)
);
 
tmr0 mips_tmr0(
.clk(clk),
.clr(tmr_clr),
.din(din) ,
.ld(wr_tmr_data),
.tmr_en(tmr_en),
.tmr_req(w_tmr_req),
.cntr_o(w_tmr_data)
);
 
 
//interrupt control
wire tmr_irq_bit = cmd[31] ;
wire key1_irq_bit = cmd[30] ;
wire key2_irq_bit = cmd[29] ;
 
wire tmr_req_do = w_tmr_req & tmr_irq_bit;
wire key1_req_do = rr_key1 & key1_irq_bit;
wire key2_req_do = rr_key2 & key2_irq_bit;
 
wire irq_req = tmr_req_do | key1_req_do | key2_req_do ;
 
always @(posedge clk)
irq_req_o = global_mask & irq_req;
 
always @(posedge clk)
if (tmr_req_do) irq_addr_o = tmr_addr;else
if (key1_req_do) irq_addr_o = key1_addr;else
if (key2_req_do) irq_addr_o = key2_addr ;
else irq_addr_o =32'bx;
 
endmodule
/forward.v
0,0 → 1,156
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
 
module fw_latch5(input clk,input[4:0]d,output reg [4:0]q);
always @ (posedge clk) q<=d;
endmodule
 
module fw_latch1(input clk,input d,output reg q);
always @ (posedge clk) q<=d;
endmodule
 
module forward_node (
input [4:0]rn,
input [4:0]alu_wr_rn,
input alu_we,
input [4:0]mem_wr_rn,
input mem_we,
output wire[2:0]mux_fw
);
assign mux_fw = ((alu_we)&&(alu_wr_rn==rn)&&(alu_wr_rn!=0))?`FW_ALU:
((mem_we)&&(mem_wr_rn==rn)&&(mem_wr_rn!=0))?`FW_MEM:
`FW_NOP;
endmodule
 
module fwd_mux(
input [31:0]din,
output reg [31:0]dout,
input [31:0]fw_alu ,
input [2:0]fw_ctl,
input [31:0]fw_dmem
);
always@(*)
case (fw_ctl)
`FW_ALU :dout=fw_alu;
`FW_MEM :dout=fw_dmem;
`FW_NOP :dout=din;
default dout=din;
endcase
endmodule
 
module forward (alu_we,clk,mem_We,fw_alu_rn,fw_mem_rn,rns_i,rnt_i,alu_rs_fw,alu_rt_fw,cmp_rs_fw,
cmp_rt_fw,dmem_fw) ;
 
input alu_we;
wire alu_we;
input clk;
wire clk;
input mem_We;
wire mem_We;
input [4:0] fw_alu_rn;
wire [4:0] fw_alu_rn;
input [4:0] fw_mem_rn;
wire [4:0] fw_mem_rn;
input [4:0] rns_i;
wire [4:0] rns_i;
input [4:0] rnt_i;
wire [4:0] rnt_i;
output [2:0] alu_rs_fw;
wire [2:0] alu_rs_fw;
output [2:0] alu_rt_fw;
wire [2:0] alu_rt_fw;
output [2:0] cmp_rs_fw;
wire [2:0] cmp_rs_fw;
output [2:0] cmp_rt_fw;
wire [2:0] cmp_rt_fw;
output [2:0] dmem_fw;
wire [2:0] dmem_fw;
 
wire [2:0] BUS1345;
wire [4:0] BUS82;
wire [4:0] BUS937;
 
forward_node fw_alu_rs
(
.alu_we(alu_we),
.alu_wr_rn(fw_alu_rn),
.mem_we(mem_We),
.mem_wr_rn(fw_mem_rn),
.mux_fw(alu_rs_fw),
.rn(BUS82)
);
 
 
 
forward_node fw_alu_rt
(
.alu_we(alu_we),
.alu_wr_rn(fw_alu_rn),
.mem_we(mem_We),
.mem_wr_rn(fw_mem_rn),
.mux_fw(BUS1345),
.rn(BUS937)
);
 
 
 
forward_node fw_cmp_rs
(
.alu_we(alu_we),
.alu_wr_rn(fw_alu_rn),
.mem_we(mem_We),
.mem_wr_rn(fw_mem_rn),
.mux_fw(cmp_rs_fw),
.rn(rns_i)
);
 
 
 
forward_node fw_cmp_rt
(
.alu_we(alu_we),
.alu_wr_rn(fw_alu_rn),
.mem_we(mem_We),
.mem_wr_rn(fw_mem_rn),
.mux_fw(cmp_rt_fw),
.rn(rnt_i)
);
 
 
 
fw_latch5 fw_reg_rns
(
.clk(clk),
.d(rns_i),
.q(BUS82)
);
 
 
 
fw_latch5 fw_reg_rnt
(
.clk(clk),
.d(rnt_i),
.q(BUS937)
);
 
 
assign alu_rt_fw[2:0] = BUS1345[2:0];
assign dmem_fw[2:0] = BUS1345[2:0];
 
endmodule
 
 
/mips_sys.v
0,0 → 1,147
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
 
`include "mips789_defs.v"
 
 
module mips_sys (
 
zz_addr_o,
zz_din,
zz_dout,
zz_ins_i,
zz_pc_o,
zz_wr_en_o ,
 
clk,
rst,
 
ser_rxd,
ser_txd,
 
seg7led1,
seg7led2 ,
 
lcd_data,
lcd_rs,
lcd_rw,
lcd_en,
 
led1,
led2,
 
key1,
key2
 
) ;
input key1;
input key2;
 
input clk;
wire clk;
 
input rst;
wire rst;
 
 
output [6:0] seg7led1;
wire [6:0] seg7led1;
output [6:0] seg7led2;
wire [6:0] seg7led2;
 
output [7:0]lcd_data;
output lcd_rs;
output lcd_rw ;
output lcd_en ;
output led1;
output led2;
 
 
input [31:0] zz_din;
wire [31:0] zz_din;
input [31:0] zz_ins_i;
wire [31:0] zz_ins_i;
output [31:0] zz_addr_o;
wire [31:0] zz_addr_o;
output [31:0] zz_dout;
wire [31:0] zz_dout;
output [31:0] zz_pc_o;
wire [31:0] zz_pc_o;
output [3:0] zz_wr_en_o;
wire [3:0] zz_wr_en_o;
 
input ser_rxd;
output ser_txd;
 
wire [31:0] cop_addr;
wire [3:0] cop_mem_ctl;
wire [31:0] data2cop;
wire [31:0]cop_data;
wire clk_sys=clk;
wire [31:0]irq_addr;
wire w_irq;
 
mips_core i_mips_core
(
.clk(clk_sys),
.cop_addr_o(cop_addr),
.cop_data_o(data2cop),
.cop_dout(cop_data),
.cop_mem_ctl_o(cop_mem_ctl),
.irq_addr(irq_addr),
.irq_i(w_irq),
.rst(rst),
 
 
.zz_addr_o(zz_addr_o),
.zz_din(zz_din),
.zz_dout(zz_dout),
.zz_ins_i(zz_ins_i),
.zz_pc_o(zz_pc_o),
.zz_wr_en_o(zz_wr_en_o)
 
);
 
mips_dvc imips_dvc(
.din(data2cop),
.clk(clk_sys),
.rst(rst),
.addr(cop_addr) ,
.mem_ctl(cop_mem_ctl),
.dout(cop_data),
 
.lcd_data(lcd_data),
.lcd_rs(lcd_rs),
.lcd_rw(lcd_rw),
.lcd_en(lcd_en),
 
.ser_rxd(ser_rxd),
.ser_txd(ser_txd),
 
.seg7led1(seg7led1),
.seg7led2(seg7led2),
 
.led1(led1),
.led2(led2),
 
.key1(key1),
.key2(key2) ,
 
.irq_addr_o(irq_addr), //not registed
.irq_req_o(w_irq)
);
 
endmodule
 
 
/EXEC_stage.v
0,0 → 1,718
/******************************************************************
* *
* Author: Liwei *
* *
* This file is part of the "mips789" project. *
* Downloaded from: *
* http://www.opencores.org/pdownloads.cgi/list/mips789 *
* *
* If you encountered any problem, please contact me via *
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`include "mips789_defs.v"
 
module exec_stage
(
clk,rst,spc_cls_i,alu_func,
dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
dmem_data_ur_o,zz_spc_o
);
 
input clk;
wire clk;
input rst;
wire rst;
input spc_cls_i;
wire spc_cls_i;
input [4:0] alu_func;
wire [4:0] alu_func;
input [2:0] dmem_fw_ctl;
wire [2:0] dmem_fw_ctl;
input [31:0] ext_i;
wire [31:0] ext_i;
input [31:0] fw_alu;
wire [31:0] fw_alu;
input [31:0] fw_dmem;
wire [31:0] fw_dmem;
input [1:0] muxa_ctl_i;
wire [1:0] muxa_ctl_i;
input [2:0] muxa_fw_ctl;
wire [2:0] muxa_fw_ctl;
input [1:0] muxb_ctl_i;
wire [1:0] muxb_ctl_i;
input [2:0] muxb_fw_ctl;
wire [2:0] muxb_fw_ctl;
input [31:0] pc_i;
wire [31:0] pc_i;
input [31:0] rs_i;
wire [31:0] rs_i;
input [31:0] rt_i;
wire [31:0] rt_i;
output [31:0] alu_ur_o;
wire [31:0] alu_ur_o;
output [31:0] dmem_data_ur_o;
wire [31:0] dmem_data_ur_o;
output [31:0] zz_spc_o;
wire [31:0] zz_spc_o;
 
wire [31:0] BUS2332;
wire [31:0] BUS2446;
wire [31:0] BUS468;
wire [31:0] BUS476;
 
 
big_alu MIPS_alu
(
.a(BUS476),
.b(BUS468),
.c(alu_ur_o),
.clk(clk),
.ctl(alu_func),
.rst(rst)
);
 
add32 add4
(
.d_i(pc_i),
.d_o(BUS2446)
);
 
 
fwd_mux dmem_fw_mux
(
.dout(dmem_data_ur_o),
.fw_alu(fw_alu),
.fw_ctl(dmem_fw_ctl),
.fw_dmem(fw_dmem),
.din(rt_i)
);
 
 
 
alu_muxa i_alu_muxa
(
.a_o(BUS476),
.ctl(muxa_ctl_i),
.ext(ext_i),
.fw_alu(fw_alu),
.fw_ctl(muxa_fw_ctl),
.fw_mem(fw_dmem),
.pc(BUS2332),
.rs(rs_i),
.spc(zz_spc_o)
);
 
 
 
alu_muxb i_alu_muxb
(
.b_o(BUS468),
.ctl(muxb_ctl_i),
.ext(ext_i),
.fw_alu(fw_alu),
.fw_ctl(muxb_fw_ctl),
.fw_mem(fw_dmem),
.rt(rt_i)
);
 
 
 
r32_reg pc_nxt
(
.clk(clk),
.r32_i(BUS2446),
.r32_o(BUS2332)
);
 
 
 
r32_reg_cls spc
(
.clk(clk),
.cls(spc_cls_i),
.r32_i(pc_i),
.r32_o(zz_spc_o)
);
 
endmodule
 
module big_alu(clk,rst,a,b,c,ctl);
input clk,rst ;
input [31:0] a,b ;
output [31:0] c ;
input [4:0]ctl ;
 
wire [31:0] mul_div_c;
wire [31:0] alu_c;
wire [31:0] shift_c;
 
assign c =mul_div_c | alu_c | shift_c ;//save the pc to register
 
muldiv_ff muldiv_ff(
.clk_i(clk),
.rst_i(rst),//sys signal
.op_type(ctl),
.op1(a),
.op2(b),
// .busy_o(busy),
.res(mul_div_c)
);
 
/*
muldiv mips_muldiv(
.ready(busy),
.rst(rst),
.op1(a),
.op2(b),
.clk(clk),
.dout(mul_div_c),
.func(ctl)
);
*/
alu mips_alu(
.a(a),
.b(b),
.alu_out(alu_c),
.alu_func(ctl)
 
);
 
shifter_tak mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
 
endmodule
 
module alu_muxa(
input [31:0]spc,
input [31:0]pc,
input [31:0]fw_mem,
input [31:0]rs,
input [31:0]fw_alu,
input [31:0]ext,
input [1:0] ctl,
input [2:0] fw_ctl,
output reg [31:0]a_o
);
 
always @(*)
begin
case (ctl)
`MUXA_RS: a_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rs;
`MUXA_PC: a_o = pc;
`MUXA_EXT: a_o = ext;
`MUXA_SPC: a_o = spc;
default : a_o = rs;
endcase
end
endmodule
 
module alu_muxb(
input [31:0] rt,
input [31:0]fw_alu,
input [31:0]fw_mem,
input [31:0]ext ,
input [1:0]ctl ,
input [2:0]fw_ctl ,
output reg [31:0] b_o
);
always@(*)
case (ctl)
`MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
`MUXB_EXT : b_o=ext;
default b_o=rt;
endcase
endmodule
 
 
 
//This file is based on YACC ->alu.v and UCORE ->alu.v
 
module alu (a,b,alu_out,alu_func);
 
input [31:0] a,b;
output reg [31:0] alu_out;
input [4:0] alu_func;
reg [32:0] sum;
 
always @(*)
begin
case (alu_func)
 
`ALU_PA : alu_out=a;
`ALU_PB : alu_out=b;
`ALU_ADD : alu_out=a+b;
`ALU_SUB ,
`ALU_SUBU : alu_out=a + (~b)+1;
`ALU_OR : alu_out=a | b;
`ALU_AND : alu_out=a & b;
`ALU_XOR : alu_out=a ^ b;
`ALU_NOR : alu_out=~(a | b);
`ALU_SLTU : alu_out=(a < b)?1:0;
`ALU_SLT :
begin
sum={a[31],a}+~{b[31],b}+33'h0_0000_0001;
alu_out={31'h0000_0000,sum[32]};
end
default : alu_out=32'h0;
endcase
end
endmodule
 
module
shifter_tak(
input [31:0] a,
output reg [31:0] shift_out,
input [4:0] shift_func,//connect to alu_func_ctl
input [31:0] shift_amount//connect to b
);
 
always @ (*)
begin
if( shift_func == `ALU_SLL )
begin
case ( shift_amount[4:0] )
5'b00000: shift_out=a;
5'b00001: shift_out={a[30:0],1'b0};
5'b00010: shift_out={a[29:0],2'b0};
5'b00011: shift_out={a[28:0],3'b0};
5'b00100: shift_out={a[27:0],4'b0};
5'b00101: shift_out={a[26:0],5'b0};
5'b00110: shift_out={a[25:0],6'b0};
5'b00111: shift_out={a[24:0],7'b0};
5'b01000: shift_out={a[23:0],8'b0};
5'b01001: shift_out={a[22:0],9'b0};
5'b01010: shift_out={a[21:0],10'b0};
5'b01011: shift_out={a[20:0],11'b0};
5'b01100: shift_out={a[19:0],12'b0};
5'b01101: shift_out={a[18:0],13'b0};
5'b01110: shift_out={a[17:0],14'b0};
5'b01111: shift_out={a[16:0],15'b0};
5'b10000: shift_out={a[15:0],16'b0};
5'b10001: shift_out={a[14:0],17'b0};
5'b10010: shift_out={a[13:0],18'b0};
5'b10011: shift_out={a[12:0],19'b0};
5'b10100: shift_out={a[11:0],20'b0};
5'b10101: shift_out={a[10:0],21'b0};
5'b10110: shift_out={a[9:0],22'b0};
5'b10111: shift_out={a[8:0],23'b0};
5'b11000: shift_out={a[7:0],24'b0};
5'b11001: shift_out={a[6:0],25'b0};
5'b11010: shift_out={a[5:0],26'b0};
5'b11011: shift_out={a[4:0],27'b0};
5'b11100: shift_out={a[3:0],28'b0};
5'b11101: shift_out={a[2:0],29'b0};
5'b11110: shift_out={a[1:0],30'b0};
5'b11111: shift_out={a[0],31'b0};
default shift_out ='d0;
endcase
end else if (shift_func== `ALU_SRL) begin
case (shift_amount[4:0])
5'b00000: shift_out=a;
5'b00001: shift_out={1'b0,a[31:1]};
5'b00010: shift_out={2'b0,a[31:2]};
5'b00011: shift_out={3'b0,a[31:3]};
5'b00100: shift_out={4'b0,a[31:4]};
5'b00101: shift_out={5'b0,a[31:5]};
5'b00110: shift_out={6'b0,a[31:6]};
5'b00111: shift_out={7'b0,a[31:7]};
5'b01000: shift_out={8'b0,a[31:8]};
5'b01001: shift_out={9'b0,a[31:9]};
5'b01010: shift_out={10'b0,a[31:10]};
5'b01011: shift_out={11'b0,a[31:11]};
5'b01100: shift_out={12'b0,a[31:12]};
5'b01101: shift_out={13'b0,a[31:13]};
5'b01110: shift_out={14'b0,a[31:14]};
5'b01111: shift_out={15'b0,a[31:15]};
5'b10000: shift_out={16'b0,a[31:16]};
5'b10001: shift_out={17'b0,a[31:17]};
5'b10010: shift_out={18'b0,a[31:18]};
5'b10011: shift_out={19'b0,a[31:19]};
5'b10100: shift_out={20'b0,a[31:20]};
5'b10101: shift_out={21'b0,a[31:21]};
5'b10110: shift_out={22'b0,a[31:22]};
5'b10111: shift_out={23'b0,a[31:23]};
5'b11000: shift_out={24'b0,a[31:24]};
5'b11001: shift_out={25'b0,a[31:25]};
5'b11010: shift_out={26'b0,a[31:26]};
5'b11011: shift_out={27'b0,a[31:27]};
5'b11100: shift_out={28'b0,a[31:28]};
5'b11101: shift_out={29'b0,a[31:29]};
5'b11110: shift_out={30'b0,a[31:30]};
5'b11111: shift_out={31'b0,a[31:31]};
default : shift_out = 0;
endcase
end else
if (shift_func==`ALU_SRA)
begin// SHIFT_RIGHT_SIGNED
case ( shift_amount[4:0])
5'b00000: shift_out=a;
5'b00001: shift_out={a[31],a[31:1]};
5'b00010: shift_out={{2{a[31]}},a[31:2]};
5'b00011: shift_out={{3{a[31]}},a[31:3]};
5'b00100: shift_out={{4{a[31]}},a[31:4]};
5'b00101: shift_out={{5{a[31]}},a[31:5]};
5'b00110: shift_out={{6{a[31]}},a[31:6]};
5'b00111: shift_out={{7{a[31]}},a[31:7]};
5'b01000: shift_out={{8{a[31]}},a[31:8]};
5'b01001: shift_out={{9{a[31]}},a[31:9]};
5'b01010: shift_out={{10{a[31]}},a[31:10]};
5'b01011: shift_out={{11{a[31]}},a[31:11]};
5'b01100: shift_out={{12{a[31]}},a[31:12]};
5'b01101: shift_out={{13{a[31]}},a[31:13]};
5'b01110: shift_out={{14{a[31]}},a[31:14]};
5'b01111: shift_out={{15{a[31]}},a[31:15]};
5'b10000: shift_out={{16{a[31]}},a[31:16]};
5'b10001: shift_out={{17{a[31]}},a[31:17]};
5'b10010: shift_out={{18{a[31]}},a[31:18]};
5'b10011: shift_out={{19{a[31]}},a[31:19]};
5'b10100: shift_out={{20{a[31]}},a[31:20]};
5'b10101: shift_out={{21{a[31]}},a[31:21]};
5'b10110: shift_out={{22{a[31]}},a[31:22]};
5'b10111: shift_out={{23{a[31]}},a[31:23]};
5'b11000: shift_out={{24{a[31]}},a[31:24]};
5'b11001: shift_out={{25{a[31]}},a[31:25]};
5'b11010: shift_out={{26{a[31]}},a[31:26]};
5'b11011: shift_out={{27{a[31]}},a[31:27]};
5'b11100: shift_out={{28{a[31]}},a[31:28]};
5'b11101: shift_out={{29{a[31]}},a[31:29]};
5'b11110: shift_out={{30{a[31]}},a[31:30]};
5'b11111: shift_out={{31{a[31]}},a[31:31]};
default shift_out='d0;
endcase
end
else shift_out='d0;
end
endmodule
 
module muldiv(ready,rst,op1,op2,clk,dout,func);
input clk,rst;
wire sign;
input [4:0] func ;
input [31:0] op2, op1;
output [31:0] dout;
output ready;
reg [31:0] quotient, quotient_temp;
reg [63:0] dividend_copy, divider_copy, diff;
reg negative_output;
 
reg [63:0] product, product_temp;
 
reg [31:0] multiplier_copy;
reg [63:0] multiplicand_copy;
 
reg [6:0] mul_bit,div_bit;
wire ready = ((mul_bit==0)&&(div_bit==0));
 
wire [31:0] dividend, divider;
 
wire [31:0] remainder;
wire [31:0] multiplier,multiplicand;
 
reg [31:0] hi,lo;
 
assign dout = (func==`ALU_MFHI)?hi:(func==`ALU_MFLO)?lo:0;
 
assign remainder = (!negative_output) ?
dividend_copy[31:0] :
~dividend_copy[31:0] + 1'b1;
 
assign multiplier=op2;
assign multiplicand=op1;
assign dividend=op1;
assign divider = op2;
assign sign = ((func==`ALU_MULT)||(func==`ALU_DIV));
 
initial
begin
hi=0;
lo=0;
end
always @( posedge clk /*or negedge rst */)
if (~rst)
begin
mul_bit=0;
div_bit=0;
/*
hi=0;
lo=0;
*/
negative_output = 0;
end
else
begin
if((ready)&&((func==`ALU_MULT)||(func==`ALU_MULTTU)))
begin
mul_bit = 33;
product = 0;
product_temp = 0;
multiplicand_copy = (!sign || !multiplicand[31]) ?
{ 32'd0, multiplicand } :
{ 32'd0, ~multiplicand + 1'b1};
multiplier_copy = (!sign || !multiplier[31]) ?multiplier :~multiplier + 1'b1;
 
negative_output = sign &&
((multiplier[31] && !multiplicand[31])
||(!multiplier[31] && multiplicand[31]));
end
if ( mul_bit > 1 )
begin
 
if( multiplier_copy[0] == 1'b1 )
product_temp = product_temp +multiplicand_copy;
 
 
product = (!negative_output) ?
product_temp :
~product_temp + 1'b1;
 
multiplier_copy = multiplier_copy >> 1;
multiplicand_copy = multiplicand_copy << 1;
mul_bit = mul_bit - 1'b1;
end
else if (mul_bit == 1)
begin
hi = product[63:32];
lo = product[31:0];
mul_bit=0;
end
 
if((ready)&&((func==`ALU_DIV)||(func==`ALU_DIVU)))
begin
div_bit = 33;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[31]) ?
{32'd0,dividend} :
{32'd0,~dividend + 1'b1};
 
divider_copy = (!sign || !divider[31]) ?
{1'b0,divider,31'd0} :
{1'b0,~divider + 1'b1,31'd0};
 
negative_output = sign &&
((divider[31] && !dividend[31])
||(!divider[31] && dividend[31]));
end
else if (div_bit > 1)
begin
diff = dividend_copy - divider_copy;
quotient_temp = quotient_temp << 1;
if( !diff[63] )
begin
dividend_copy = diff;
quotient_temp[0] = 1'd1;
end
quotient = (!negative_output) ?quotient_temp :~quotient_temp + 1'b1;
divider_copy = divider_copy >> 1;
div_bit = div_bit - 1'b1;
end
else if (div_bit == 1)
begin
lo = quotient;
hi = remainder;
div_bit=0;
end
end
 
endmodule
 
//creatied by Zhangfeifei
//modified by Liwei
module muldiv_ff
(
clk_i,rst_i,
op_type,op1,op2,
rdy,res
);
 
parameter OP_MULT = `ALU_MULT;
parameter OP_MULTU = `ALU_MULTU;
parameter OP_DIV = `ALU_DIV;
parameter OP_DIVU = `ALU_DIVU;
parameter OP_MFHI = `ALU_MFHI;
parameter OP_MFLO = `ALU_MFLO;
 
parameter OP_MTHI = `ALU_MTHI;
parameter OP_MTLO = `ALU_MTLO;
 
parameter OP_NONE = `ALU_NOP;
 
input clk_i;
input rst_i;
input [4:0] op_type;
input [31:0] op1;
input [31:0] op2;
output [31:0] res;
output rdy;
 
reg rdy;
 
reg [64:0] hilo;
reg [32:0] op2_reged;
reg [5:0] count;
reg op1_sign_reged;
reg op2_sign_reged;
reg sub_or_yn;
 
wire [32:0] nop2_reged;
assign nop2_reged = ~op2_reged +1;
 
reg sign;
reg mul;
reg start;
 
assign res = (op_type == OP_MFLO )?hilo[31:0]:((op_type == OP_MFHI))?hilo[63:32]:0;//op_type == OP_MFHI or other
 
reg overflow;
reg finish;
reg add1; //if the quotient will add 1 at the end of the divide operation
reg addop2; //if the remainder will add op2 at the end of the divide operation
reg addnop2;//if the remainder will add ~op2+1 at the end of the divide operation
 
 
always @( posedge clk_i /*or negedge rst_i*/)
begin
if(~rst_i)
begin
count = 6'bx;
hilo = 65'b0;
op2_reged = 33'bx;
op1_sign_reged = 1'bx;
op2_sign_reged = 1'bx;
sub_or_yn = 1'bx;
rdy = 1'b1;
start = 1'bx;
sign = 1'bx;
mul = 1'bx;
 
finish = 1'bx;
add1 = 1'bx;
addop2 = 1'bx;
addnop2 = 1'bx;
end
else begin
 
if(op_type == OP_MTHI || op_type == OP_MTLO)
begin
if(op_type == OP_MTHI) hilo[64:32] = {1'b0,op1};
if(op_type == OP_MTLO) hilo[31:0] = op1;
rdy = 1;
end
else if(rdy)
begin
start = (op_type == OP_MULT) || (op_type == OP_MULTU) || (op_type == OP_DIV) || (op_type == OP_DIVU);
mul = (op_type == OP_MULT) || (op_type == OP_MULTU);
sign = (op_type == OP_MULT) || (op_type == OP_DIV);
 
if(start)
begin:START_SECTION
reg [32:0] over;
 
op2_reged = {sign ?op2[31] :1'b0 ,op2};
hilo = {~mul && sign?{33{op1[31]}}:33'b0,op1};
count = 6'b000000;
rdy = 0;
op1_sign_reged = sign?op1[31]:0;
op2_sign_reged = sign?op2[31]:0;
sub_or_yn = 0;
 
over = ~op2_reged + {op1[31],op1};
overflow = sign && ~mul ? op1_sign_reged && op2_sign_reged && ~over[32] : 0;
 
finish = 0;
end
end
else if(start)
begin
if(overflow)
begin
hilo[63:0] = {hilo[31:0],32'b0};
rdy = 1;
end
else if(!count[5])
begin
if(mul)
begin
if(sign)
begin
case({hilo[0],sub_or_yn})
2'b10:hilo[64:32] = hilo[64:32] + nop2_reged;
2'b01:hilo[64:32] = hilo[64:32] + op2_reged;
default:;
endcase
{hilo[63:0],sub_or_yn} = hilo[64:0];
end
else begin
if(hilo[0]) hilo[64:32] = hilo[64:32] + op2_reged;
hilo = {1'b0,hilo[64:1]};
end
end
else begin
sub_or_yn = hilo[64]== op2_sign_reged;
hilo[64:1] = hilo[63:0];
 
hilo[64:32] = sub_or_yn ? hilo[64:32] + nop2_reged : hilo[64:32] + op2_reged;
 
hilo[0] = hilo[64]== op2_sign_reged;
end
 
count = count + 1'b1;
end
else begin
if(finish)
begin
if(add1) hilo[31:0] = hilo[31:0] + 1;
case({addop2,addnop2})
2'b10: hilo[64:32] = hilo[64:32] + op2_reged;
2'b01: hilo[64:32] = hilo[64:32] + nop2_reged;
default: ;
endcase
rdy = 1;
end
else begin
{add1,addop2,addnop2} = 3'b000;
finish = 1;
 
if(~mul)
begin:LAST_CYCLE_DEAL_SECTION
reg eqz,eqop2,eqnop2;
eqz = hilo[64:32] == 0;
eqop2 = hilo[64:32] == op2_reged;
eqnop2 = hilo[64:32] == nop2_reged;
casex({op1_sign_reged,op2_sign_reged,eqz,eqop2,eqnop2})
5'b101xx : {add1,addop2,addnop2} = 3'b000;
5'b100x1 : {add1,addop2,addnop2} = 3'b010;
5'b111xx : {add1,addop2,addnop2} = 3'b100;
5'b1101x : {add1,addop2,addnop2} = 3'b101;
default :
begin:LAST_CYCLE_DEAL_SECTION_DEFAULT
 
reg op1s_eq_op2s,op1s_eq_h64;
op1s_eq_op2s = op1_sign_reged == op2_sign_reged;
op1s_eq_h64 = op1_sign_reged == hilo[64];
 
add1 = ~op1s_eq_op2s;
case({op1s_eq_op2s,op1s_eq_h64})//synthesis parallel_case
2'b00: {addop2,addnop2} = 2'b01;
2'b10: {addop2,addnop2} = 2'b10;
default: {addop2,addnop2} = 2'b00;
endcase
end
endcase
end
end
end
end
end
end
endmodule
 
 
/fifo.v
0,0 → 1,98
`include "include.h"
 
module fifo
(
clk_i,
rst_i,
clear_i,
data_i,
wen_i,
ren_i,
data_o,
almost_full_o,
full_o,
almost_empty_o,
empty_o,
cnt_o
);
 
parameter DATA_WIDTH = 8;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
 
 
input clk_i;
input rst_i;
input clear_i;
 
input wen_i;
input [DATA_WIDTH-1:0] data_i;
 
input ren_i;
output [DATA_WIDTH-1:0] data_o;
output almost_full_o;
output full_o;
output almost_empty_o;
output empty_o;
output [CNT_WIDTH-1:0] cnt_o;
 
reg [DATA_WIDTH-1:0] mem[0:DEPTH-1];
 
reg [CNT_WIDTH-1:0] cnt;
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
assign cnt_o = cnt;
 
always @(posedge clk_i /*or posedge rst_i*/)
begin
if(~rst_i)
cnt <= 0;
else if(clear_i)
cnt <= {{(CNT_WIDTH-1){1'b0}},ren_i^wen_i};
else if(ren_i ^ wen_i)
begin
if(ren_i & ~empty_o)
cnt <= cnt - 1'b1;
else if( wen_i & ~full_o)
cnt <= cnt + 1'b1;
end
end
 
always @(posedge clk_i/* or posedge rst_i*/)
begin
if(~rst_i)
read_pointer <= 0;
else if(clear_i)
read_pointer <= { {(CNT_WIDTH-2){1'b0}}, ren_i};
else if(ren_i & ~empty_o)
read_pointer <= read_pointer + 1'b1;
end
 
always @ (posedge clk_i /*or posedge rst_i*/)
begin
if(~rst_i)
write_pointer <= 0;
else if(clear_i)
write_pointer <= { {(CNT_WIDTH-2){1'b0}}, wen_i};
else if(wen_i & ~full_o)
write_pointer <= write_pointer + 1'b1;
end
 
assign empty_o = ~(|cnt);
assign almost_empty_o = cnt == 1;
assign full_o = cnt == DEPTH;
assign almost_full_o = &cnt[CNT_WIDTH-2:0];
 
always @ (posedge clk_i)
begin
if(wen_i & clear_i)
mem[0] <= data_i;
else if(wen_i & ~full_o)
mem[write_pointer] <= data_i;
end
 
assign data_o = clear_i ? mem[0] : mem[read_pointer];
 
endmodule
 
 
/altera/pll40.v
0,0 → 1,198
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: pll40.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll40 (
inclk0,
c0);
 
input inclk0;
output c0;
 
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 8,
altpll_component.inclk0_input_frequency = 40000,
altpll_component.clk0_divide_by = 5,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40_bb.v FALSE FALSE
/altera/pll50.v
0,0 → 1,198
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: pll50.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll50 (
inclk0,
c0);
 
input inclk0;
output c0;
 
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 40000,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50_bb.v FALSE FALSE
/altera/pll25.v
0,0 → 1,198
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: pll25.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll25 (
inclk0,
c0);
 
input inclk0;
output c0;
 
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 40000,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll25.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll25.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll25.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll25.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll25_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll25_bb.v FALSE FALSE
/altera/pll45.v
0,0 → 1,198
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: pll45.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll45 (
inclk0,
c0);
 
input inclk0;
output c0;
 
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 40000,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll45.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll45.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll45.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll45.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll45_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll45_bb.v FALSE FALSE
/altera/pll75.v
0,0 → 1,198
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: pll75.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll75 (
inclk0,
c0);
 
input inclk0;
output c0;
 
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 10000,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll75.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll75.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll75.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll75.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll75_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll75_bb.v FALSE FALSE
/altera/mips_top.v
0,0 → 1,89
module mips_top (
input clk,
input rst,
input ser_rxd,
output ser_txd,
output [6:0]seg7led1,
output [6:0]seg7led2,
output [7:0] lcd_data,
output lcd_rs,
output lcd_rw,
output lcd_en,
output led1,
output led2,
input key1,
input key2
);
 
wire [31:0] data2core;
wire [31:0] data2mem;
wire [31:0] ins2core;
wire [31:0] mem_Addr;
wire [31:0] pc;
wire [3:0] wr_en;
wire CLK;
reg r_rst;
 
//wire sys_rst=rst;
always @(posedge CLK)
if (rst) r_rst<=1'b1; else r_rst<=1'b0;
//wire sys_rst = r_rst;
reg rr_rst;
always @(posedge CLK)
rr_rst<=r_rst;
 
wire sys_rst = rr_rst;
 
//assign CLK = clk;
 
pll50 Ipll(
.inclk0(clk),
.c0(CLK)
);
mem_array ram_8k
(
.clk(CLK),
.din(data2mem),
.dout(data2core),
.ins_o(ins2core),
.pc_i(pc),
.rd_addr_i(mem_Addr),
.wr_addr_i(mem_Addr),
.wren(wr_en)
);
 
mips_sys isys
(
 
.zz_addr_o(mem_Addr),
.zz_din(data2core),
.zz_dout(data2mem),
.zz_ins_i(ins2core),
.zz_pc_o(pc),
.zz_wr_en_o(wr_en),
.clk(CLK),
.rst(sys_rst),
 
.ser_rxd(ser_rxd),
.ser_txd(ser_txd),
 
.seg7led1(seg7led1),
.seg7led2(seg7led2),
 
.lcd_data(lcd_data),
.lcd_rs(lcd_rs),
.lcd_rw(lcd_rw),
.lcd_en(lcd_en),
 
.led1(led1),
.led2(led2),
 
.key1(key1),
.key2(key2)
);
 
endmodule
/altera/ram2048x8_0.v
0,0 → 1,240
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram2048x8_0.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram2048x8_0 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [10:0] address_a;
input [7:0] data_b;
input [10:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 11,
altsyncram_component.numwords_a = 2048,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 11,
altsyncram_component.numwords_b = 2048,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_b = "NONE",
altsyncram_component.wrcontrol_aclr_b = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.init_file = "qu2_ram0.mif";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "qu2_ram0.mif"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "qu2_ram0.mif"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_0_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_0.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_0_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_0_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_0_wave*.jpg FALSE
/altera/ram2048x8_1.v
0,0 → 1,240
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram2048x8_1.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram2048x8_1 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [10:0] address_a;
input [7:0] data_b;
input [10:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 11,
altsyncram_component.numwords_a = 2048,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 11,
altsyncram_component.numwords_b = 2048,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_b = "NONE",
altsyncram_component.wrcontrol_aclr_b = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.init_file = "qu2_ram1.mif";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "qu2_ram1.mif"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "qu2_ram1.mif"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_1_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_1_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_1_wave*.jpg FALSE
/altera/pin_set.tcl
0,0 → 1,133
#EP1C3T144C8 Setup.tcl
# Setup pin setting for evaluaton board V1.0
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
 
set_location_assignment PIN_28 -to clk
set_location_assignment PIN_159 -to rst
set_location_assignment PIN_156 -to key1
set_location_assignment PIN_158 -to key2
 
set_location_assignment PIN_1 -to led1
set_location_assignment PIN_2 -to led2
set_location_assignment PIN_177 -to ser_rxd
set_location_assignment PIN_176 -to ser_txd
 
set_location_assignment PIN_135 -to lcd_en
set_location_assignment PIN_133 -to lcd_rs
set_location_assignment PIN_134 -to lcd_rw
set_location_assignment PIN_136 -to lcd_data\[0\]
set_location_assignment PIN_137 -to lcd_data\[1\]
set_location_assignment PIN_138 -to lcd_data\[2\]
set_location_assignment PIN_139 -to lcd_data\[3\]
set_location_assignment PIN_140 -to lcd_data\[4\]
set_location_assignment PIN_141 -to lcd_data\[5\]
set_location_assignment PIN_143 -to lcd_data\[6\]
set_location_assignment PIN_144 -to lcd_data\[7\]
set_location_assignment PIN_169 -to seg7led1\[0\]
set_location_assignment PIN_166 -to seg7led1\[1\]
set_location_assignment PIN_161 -to seg7led1\[2\]
set_location_assignment PIN_160 -to seg7led1\[3\]
set_location_assignment PIN_164 -to seg7led1\[4\]
set_location_assignment PIN_168 -to seg7led1\[5\]
set_location_assignment PIN_167 -to seg7led1\[6\]
set_location_assignment PIN_175 -to seg7led2\[0\]
set_location_assignment PIN_170 -to seg7led2\[1\]
set_location_assignment PIN_163 -to seg7led2\[2\]
set_location_assignment PIN_165 -to seg7led2\[3\]
set_location_assignment PIN_162 -to seg7led2\[4\]
set_location_assignment PIN_174 -to seg7led2\[5\]
set_location_assignment PIN_173 -to seg7led2\[6\]
set_location_assignment PIN_128 -to uart_rxd_usb
set_location_assignment PIN_131 -to uart_txd_usb
 
set_location_assignment PIN_60 -to sd_data\[0\]
set_location_assignment PIN_59 -to sd_data\[1\]
set_location_assignment PIN_58 -to sd_data\[2\]
set_location_assignment PIN_57 -to sd_data\[3\]
set_location_assignment PIN_56 -to sd_data\[4\]
set_location_assignment PIN_55 -to sd_data\[5\]
set_location_assignment PIN_54 -to sd_data\[6\]
set_location_assignment PIN_53 -to sd_data\[7\]
set_location_assignment PIN_12 -to sd_data\[8\]
set_location_assignment PIN_11 -to sd_data\[9\]
set_location_assignment PIN_8 -to sd_data\[10\]
set_location_assignment PIN_7 -to sd_data\[11\]
set_location_assignment PIN_6 -to sd_data\[12\]
set_location_assignment PIN_5 -to sd_data\[13\]
set_location_assignment PIN_4 -to sd_data\[14\]
set_location_assignment PIN_3 -to sd_data\[15\]
 
set_location_assignment PIN_42 -to sd_addr\[0\]
set_location_assignment PIN_41 -to sd_addr\[1\]
set_location_assignment PIN_39 -to sd_addr\[2\]
set_location_assignment PIN_38 -to sd_addr\[3\]
set_location_assignment PIN_23 -to sd_addr\[4\]
set_location_assignment PIN_21 -to sd_addr\[5\]
set_location_assignment PIN_20 -to sd_addr\[6\]
set_location_assignment PIN_19 -to sd_addr\[7\]
set_location_assignment PIN_18 -to sd_addr\[8\]
set_location_assignment PIN_17 -to sd_addr\[9\]
set_location_assignment PIN_43 -to sd_addr\[10\]
set_location_assignment PIN_16 -to sd_addr\[11\]
 
set_location_assignment PIN_45 -to sd_ba\[0\]
set_location_assignment PIN_44 -to sd_ba\[1\]
 
set_location_assignment PIN_50 -to sd_dqm\[0\]
set_location_assignment PIN_13 -to sd_dqm\[1\]
 
set_location_assignment PIN_46 -to sd_cs
set_location_assignment PIN_47 -to sd_ras
set_location_assignment PIN_48 -to sd_cas
set_location_assignment PIN_49 -to sd_we
set_location_assignment PIN_15 -to sd_cke
set_location_assignment PIN_14 -to sd_clk
 
 
set_location_assignment PIN_208 -to FLASH_CE
set_location_assignment PIN_213 -to FLASH_OE
set_location_assignment PIN_206 -to FLASH_WE
 
set_location_assignment PIN_196 -to FLASH_RESET
set_location_assignment PIN_223 -to FLASH_BYTE
 
set_location_assignment PIN_207 -to FLASH_ADDR\[0\]
set_location_assignment PIN_181 -to FLASH_ADDR\[1\]
set_location_assignment PIN_182 -to FLASH_ADDR\[2\]
set_location_assignment PIN_183 -to FLASH_ADDR\[3\]
set_location_assignment PIN_184 -to FLASH_ADDR\[4\]
set_location_assignment PIN_185 -to FLASH_ADDR\[5\]
set_location_assignment PIN_186 -to FLASH_ADDR\[6\]
set_location_assignment PIN_187 -to FLASH_ADDR\[7\]
set_location_assignment PIN_204 -to FLASH_ADDR\[8\]
set_location_assignment PIN_203 -to FLASH_ADDR\[9\]
set_location_assignment PIN_202 -to FLASH_ADDR\[10\]
set_location_assignment PIN_201 -to FLASH_ADDR\[11\]
set_location_assignment PIN_200 -to FLASH_ADDR\[12\]
set_location_assignment PIN_199 -to FLASH_ADDR\[13\]
set_location_assignment PIN_198 -to FLASH_ADDR\[14\]
set_location_assignment PIN_197 -to FLASH_ADDR\[15\]
set_location_assignment PIN_222 -to FLASH_ADDR\[16\]
set_location_assignment PIN_188 -to FLASH_ADDR\[17\]
set_location_assignment PIN_193 -to FLASH_ADDR\[18\]
set_location_assignment PIN_205 -to FLASH_ADDR\[19\]
 
set_location_assignment PIN_214 -to FLASH_DQ\[0\]
set_location_assignment PIN_216 -to FLASH_DQ\[1\]
set_location_assignment PIN_218 -to FLASH_DQ\[2\]
set_location_assignment PIN_220 -to FLASH_DQ\[3\]
set_location_assignment PIN_235 -to FLASH_DQ\[4\]
set_location_assignment PIN_233 -to FLASH_DQ\[5\]
set_location_assignment PIN_227 -to FLASH_DQ\[6\]
set_location_assignment PIN_225 -to FLASH_DQ\[7\]
set_location_assignment PIN_215 -to FLASH_DQ\[8\]
set_location_assignment PIN_217 -to FLASH_DQ\[9\]
set_location_assignment PIN_219 -to FLASH_DQ\[10\]
set_location_assignment PIN_221 -to FLASH_DQ\[11\]
set_location_assignment PIN_234 -to FLASH_DQ\[12\]
set_location_assignment PIN_228 -to FLASH_DQ\[13\]
set_location_assignment PIN_226 -to FLASH_DQ\[14\]
set_location_assignment PIN_224 -to FLASH_DQ\[15\]
/altera/ram2048x8_2.v
0,0 → 1,232
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram2048x8_2.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram2048x8_2 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [10:0] address_a;
input [7:0] data_b;
input [10:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 11,
altsyncram_component.numwords_a = 2048,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 11,
altsyncram_component.numwords_b = 2048,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_b = "NONE",
altsyncram_component.wrcontrol_aclr_b = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.init_file = "qu2_ram2.mif";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "qu2_ram2.mif"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "qu2_ram2.mif"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_2_wave*.jpg FALSE
/altera/mips_pll.v
0,0 → 1,204
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: pll45mhz.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mips_pll (
inclk0,
c0);
 
input inclk0;
output c0;
 
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 50000,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50mhz.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50mhz.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50mhz.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50mhz.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50mhz_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll50mhz_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40mhz.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40mhz.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40mhz.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40mhz.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40mhz_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll40mhz_bb.v TRUE FALSE
/altera/ram2048x8_3.v
0,0 → 1,232
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
 
// ============================================================
// File Name: ram2048x8_3.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram2048x8_3 (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
clock,
q_a,
q_b);
 
input [7:0] data_a;
input wren_a;
input [10:0] address_a;
input [7:0] data_b;
input [10:0] address_b;
input wren_b;
input clock;
output [7:0] q_a;
output [7:0] q_b;
 
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
 
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.width_a = 8,
altsyncram_component.widthad_a = 11,
altsyncram_component.numwords_a = 2048,
altsyncram_component.width_b = 8,
altsyncram_component.widthad_b = 11,
altsyncram_component.numwords_b = 2048,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_b = "NONE",
altsyncram_component.wrcontrol_aclr_b = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.init_file = "qu2_ram3.mif";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "qu2_ram3.mif"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: INIT_FILE STRING "qu2_ram3.mif"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x8_3_wave*.jpg FALSE
/altera/ram_module.v
0,0 → 1,68
 
module mem_array
(
input clk,
input [31:0] pc_i,
output [31:0] ins_o,
input [3:0] wren,
input [31:0]din,
input [31:0]wr_addr_i,
input [31:0]rd_addr_i,
output [31:0]dout
);
wire [31:0] rd_addr,pc,wr_addr;
wire [31:0]dout_w;
assign dout = dout_w;
assign rd_addr=rd_addr_i[31:2];
assign wr_addr=wr_addr_i[31:2];
assign pc= pc_i[31:2];
ram2048x8_3 ram3(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(pc),
.data_b(din[31:24]),
.address_b(wr_addr),
.wren_b(wren[3]),
.clock(clk),
.q_a(ins_o[31:24]),
.q_b(dout_w[31:24])
);
 
ram2048x8_2 ram2(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(pc),
.data_b(din[23:16]),
.address_b(wr_addr),
.wren_b(wren[2]),
.clock(clk),
.q_a(ins_o[23:16]),
.q_b(dout_w[23:16])
);
 
ram2048x8_1 ram1(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(pc),
.data_b(din[15:8]),
.address_b(wr_addr),
.wren_b(wren[1]),
.clock(clk),
.q_a(ins_o[15:8]),
.q_b(dout_w[15:8])
);
 
ram2048x8_0 ram0(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(pc),
.data_b(din[7:0]),
.address_b(wr_addr),
.wren_b(wren[0]),
.clock(clk),
.q_a(ins_o[7:0]),
.q_b(dout_w[7:0])
);
endmodule
/altera/fifo512_cyclone.v
0,0 → 1,166
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
 
// ============================================================
// File Name: fifo512_cyclone.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 190 1/28/2004 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo512_cyclone (
data,
wrreq,
rdreq,
clock,
q,
full,
empty);
 
input [7:0] data;
input wrreq;
input rdreq;
input clock;
output [7:0] q;
output full;
output empty;
 
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire empty = sub_wire0;
wire [7:0] q = sub_wire1[7:0];
wire full = sub_wire2;
 
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.empty (sub_wire0),
.q (sub_wire1),
.full (sub_wire2)
// synopsys translate_off
,
.aclr (),
.sclr (),
.almost_full (),
.almost_empty (),
.usedw ()
// synopsys translate_on
 
);
defparam
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_widthu = 9,
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_showahead = "OFF",
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=AUTO";
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "data;wrreq;rdreq;clock;aclr"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "sclr;q;empty;full;almost_full"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "almost_empty;usedw"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=AUTO"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo512_cyclone_wave*.jpg FALSE
/ram_module.v.bak
0,0 → 1,121
`include "include.h"
/*
module mem_array
(
input clk,
input [31:0] pc_i,
output [31:0] ins_o,
input [3:0] wren,
input [31:0]din,
input [31:0]wr_addr_i,
input [31:0]rd_addr_i,
output [31:0]dout
);
wire [29:0] rd_addr,pc,wr_addr;
wire [31:0]dout_w;
assign dout = dout_w;
assign rd_addr=rd_addr_i[31:2];
assign wr_addr=wr_addr_i[31:2];
assign pc= pc_i[31:2];
`ifdef DEBUG
 
sim_syn_ram3 ram3 (
.data(din[31:31-7]),
.wraddress(wr_addr),
.rdaddress_a(pc),
.rdaddress_b(rd_addr),
.wren(wren[3]),
.clock(clk),
.qa(ins_o[31:31-7]),
.qb(dout_w[31:31-7])
);
 
sim_syn_ram2 ram2(
.data(din[31-8:31-8-7]),
.wraddress(wr_addr),
.rdaddress_a(pc),
.rdaddress_b(rd_addr),
.wren(wren[2]),
.clock(clk),
.qa(ins_o[31-8:31-8-7]),
.qb(dout_w[31-8:31-7-8])
);
 
sim_syn_ram1 ram1(
.data(din[31-16:31-16-7]),
.wraddress(wr_addr),
.rdaddress_a(pc),
.rdaddress_b(rd_addr),
.wren(wren[1]),
.clock(clk),
.qa(ins_o[31-16:31-7-16]),
.qb(dout_w[31-16:31-7-16])
);
 
sim_syn_ram0 ram0(
.data(din[31-24:31-7-24]),
.wraddress(wr_addr),
.rdaddress_a(pc),
.rdaddress_b(rd_addr),
.wren(wren[0]),
.clock(clk),
.qa(ins_o[31-24:31-7-24]),
.qb(dout_w[31-24:31-7-24])
);
 
 
`else
ram4096x8_3 ram3(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(32'b0),
.data_b(din[31:24]),
.address_b(wr_addr),
.wren_b(wren[3]),
.clock(clk),
.q_a(ins_o[31:24]),
.q_b(dout_w[31:24])
);
 
ram4096x8_2 ram2(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(32'b0),
.data_b(din[23:16]),
.address_b(wr_addr),
.wren_b(wren[2]),
.clock(clk),
.q_a(ins_o[23:16]),
.q_b(dout_w[23:16])
);
 
ram4096x8_1 ram1(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(32'b0),
.data_b(din[15:8]),
.address_b(wr_addr),
.wren_b(wren[1]),
.clock(clk),
.q_a(ins_o[15:8]),
.q_b(dout_w[15:8])
);
 
ram4096x8_0 ram0(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(32'b0),
.data_b(din[7:0]),
.address_b(wr_addr),
.wren_b(wren[0]),
.clock(clk),
.q_a(ins_o[7:0]),
.q_b(dout_w[7:0])
);
// `endif
 
endmodule
*/
/sim_ram.v
0,0 → 1,184
module sim_syn_ram0(
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
qa,
qb);
 
input [7:0] data;
input [10:0] wraddress;
input [10:0] rdaddress_a;
input [10:0] rdaddress_b;
input wren;
reg [7:0] r_data;
reg [10:0] r_wraddress;
reg [10:0] r_rdaddress_a;
reg [10:0] r_rdaddress_b;
reg r_wren;
input clock;
output [7:0] qa;
output [7:0] qb;
reg [7:0] mem_bank [0:2047] ;
initial begin
mem_bank[0] = 'h00 ; mem_bank[1] = 'hac ; mem_bank[2] = 'h00 ; mem_bank[3] = 'hc0 ; mem_bank[4] = 'h00 ; mem_bank[5] = 'hc4 ; mem_bank[6] = 'h00 ; mem_bank[7] = 'hc0 ; mem_bank[8] = 'h00 ; mem_bank[9] = 'h2a ;
mem_bank[10] = 'hfd ; mem_bank[11] = 'h04 ; mem_bank[12] = 'h17 ; mem_bank[13] = 'h00 ; mem_bank[14] = 'h0e ; mem_bank[15] = 'h7f ; mem_bank[16] = 'h14 ; mem_bank[17] = 'hff ; mem_bank[18] = 'hff ; mem_bank[19] = 'hff ;
mem_bank[20] = 'hff ; mem_bank[21] = 'h08 ; mem_bank[22] = 'h01 ; mem_bank[23] = 'he8 ; mem_bank[24] = 'h14 ; mem_bank[25] = 'h10 ; mem_bank[26] = 'h25 ; mem_bank[27] = 'h25 ; mem_bank[28] = 'h01 ; mem_bank[29] = 'hff ;
mem_bank[30] = 'h24 ; mem_bank[31] = 'h25 ; mem_bank[32] = 'h0f ; mem_bank[33] = 'h00 ; mem_bank[34] = 'hf9 ; mem_bank[35] = 'h25 ; mem_bank[36] = 'hff ; mem_bank[37] = 'h00 ; mem_bank[38] = 'h10 ; mem_bank[39] = 'h08 ;
mem_bank[40] = 'h00 ; mem_bank[41] = 'h00 ; mem_bank[42] = 'h00 ; mem_bank[43] = 'h00 ; mem_bank[44] = 'h00 ; mem_bank[45] = 'h00 ; mem_bank[46] = 'h00 ; mem_bank[47] = 'h00 ; mem_bank[48] = 'h00 ;
end
always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;
always @ (posedge clock)
begin
r_data<=data;
r_wraddress<=wraddress;
r_rdaddress_a<=rdaddress_a;
r_rdaddress_b<=rdaddress_b;
r_wren<=wren;
end
assign qa =mem_bank[r_rdaddress_a];
assign qb =mem_bank[r_rdaddress_b];
endmodule
 
 
 
module sim_syn_ram1(
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
qa,
qb);
 
input [7:0] data;
input [10:0] wraddress;
input [10:0] rdaddress_a;
input [10:0] rdaddress_b;
input wren;
reg [7:0] r_data;
reg [10:0] r_wraddress;
reg [10:0] r_rdaddress_a;
reg [10:0] r_rdaddress_b;
reg r_wren;
input clock;
output [7:0] qa;
output [7:0] qb;
reg [7:0] mem_bank [0:2047] ;
initial begin
mem_bank[0] = 'h00 ; mem_bank[1] = 'h80 ; mem_bank[2] = 'h00 ; mem_bank[3] = 'h00 ; mem_bank[4] = 'h00 ; mem_bank[5] = 'h00 ; mem_bank[6] = 'h00 ; mem_bank[7] = 'h02 ; mem_bank[8] = 'h00 ; mem_bank[9] = 'h18 ;
mem_bank[10] = 'hff ; mem_bank[11] = 'h00 ; mem_bank[12] = 'h00 ; mem_bank[13] = 'h00 ; mem_bank[14] = 'h00 ; mem_bank[15] = 'h00 ; mem_bank[16] = 'h28 ; mem_bank[17] = 'hff ; mem_bank[18] = 'hff ; mem_bank[19] = 'hff ;
mem_bank[20] = 'hff ; mem_bank[21] = 'h00 ; mem_bank[22] = 'h00 ; mem_bank[23] = 'hff ; mem_bank[24] = 'h00 ; mem_bank[25] = 'h00 ; mem_bank[26] = 'h80 ; mem_bank[27] = 'h20 ; mem_bank[28] = 'h00 ; mem_bank[29] = 'h00 ;
mem_bank[30] = 'h00 ; mem_bank[31] = 'h80 ; mem_bank[32] = 'h00 ; mem_bank[33] = 'h00 ; mem_bank[34] = 'hff ; mem_bank[35] = 'h20 ; mem_bank[36] = 'h00 ; mem_bank[37] = 'h80 ; mem_bank[38] = 'h00 ; mem_bank[39] = 'h00 ;
mem_bank[40] = 'h00 ; mem_bank[41] = 'h00 ; mem_bank[42] = 'h00 ; mem_bank[43] = 'h00 ; mem_bank[44] = 'h00 ; mem_bank[45] = 'h00 ; mem_bank[46] = 'h00 ; mem_bank[47] = 'h00 ; mem_bank[48] = 'h00 ;
end
always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;
always @ (posedge clock)
begin
r_data<=data;
r_wraddress<=wraddress;
r_rdaddress_a<=rdaddress_a;
r_rdaddress_b<=rdaddress_b;
r_wren<=wren;
end
assign qa =mem_bank[r_rdaddress_a];
assign qb =mem_bank[r_rdaddress_b];
endmodule
 
 
 
module sim_syn_ram2(
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
qa,
qb);
 
input [7:0] data;
input [10:0] wraddress;
input [10:0] rdaddress_a;
input [10:0] rdaddress_b;
input wren;
reg [7:0] r_data;
reg [10:0] r_wraddress;
reg [10:0] r_rdaddress_a;
reg [10:0] r_rdaddress_b;
reg r_wren;
input clock;
output [7:0] qa;
output [7:0] qb;
reg [7:0] mem_bank [0:2047] ;
initial begin
mem_bank[0] = 'h1c ; mem_bank[1] = 'h9c ; mem_bank[2] = 'h04 ; mem_bank[3] = 'h84 ; mem_bank[4] = 'h05 ; mem_bank[5] = 'ha5 ; mem_bank[6] = 'h1d ; mem_bank[7] = 'hbd ; mem_bank[8] = 'h80 ; mem_bank[9] = 'h85 ;
mem_bank[10] = 'h60 ; mem_bank[11] = 'h84 ; mem_bank[12] = 'h00 ; mem_bank[13] = 'h00 ; mem_bank[14] = 'h00 ; mem_bank[15] = 'h02 ; mem_bank[16] = 'h42 ; mem_bank[17] = 'h03 ; mem_bank[18] = 'h42 ; mem_bank[19] = 'h43 ;
mem_bank[20] = 'h42 ; mem_bank[21] = 'he0 ; mem_bank[22] = 'h42 ; mem_bank[23] = 'hbd ; mem_bank[24] = 'hbf ; mem_bank[25] = 'hb0 ; mem_bank[26] = 'h00 ; mem_bank[27] = 'h00 ; mem_bank[28] = 'h02 ; mem_bank[29] = 'h42 ;
mem_bank[30] = 'h00 ; mem_bank[31] = 'h40 ; mem_bank[32] = 'h00 ; mem_bank[33] = 'h00 ; mem_bank[34] = 'h00 ; mem_bank[35] = 'h00 ; mem_bank[36] = 'h84 ; mem_bank[37] = 'h02 ; mem_bank[38] = 'h42 ; mem_bank[39] = 'he0 ;
mem_bank[40] = 'h44 ; mem_bank[41] = 'h00 ; mem_bank[42] = 'h00 ; mem_bank[43] = 'h00 ; mem_bank[44] = 'h00 ; mem_bank[45] = 'h00 ; mem_bank[46] = 'h00 ; mem_bank[47] = 'h00 ; mem_bank[48] = 'h00 ;
end
always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;
always @ (posedge clock)
begin
r_data<=data;
r_wraddress<=wraddress;
r_rdaddress_a<=rdaddress_a;
r_rdaddress_b<=rdaddress_b;
r_wren<=wren;
end
assign qa =mem_bank[r_rdaddress_a];
assign qb =mem_bank[r_rdaddress_b];
endmodule
 
 
 
module sim_syn_ram3(
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
qa,
qb);
 
input [7:0] data;
input [10:0] wraddress;
input [10:0] rdaddress_a;
input [10:0] rdaddress_b;
input wren;
reg [7:0] r_data;
reg [10:0] r_wraddress;
reg [10:0] r_rdaddress_a;
reg [10:0] r_rdaddress_b;
reg r_wren;
input clock;
output [7:0] qa;
output [7:0] qb;
reg [7:0] mem_bank [0:2047] ;
initial begin
mem_bank[0] = 'h3c ; mem_bank[1] = 'h37 ; mem_bank[2] = 'h3c ; mem_bank[3] = 'h34 ; mem_bank[4] = 'h3c ; mem_bank[5] = 'h34 ; mem_bank[6] = 'h3c ; mem_bank[7] = 'h37 ; mem_bank[8] = 'hac ; mem_bank[9] = 'h00 ;
mem_bank[10] = 'h14 ; mem_bank[11] = 'h24 ; mem_bank[12] = 'h0c ; mem_bank[13] = 'h00 ; mem_bank[14] = 'h08 ; mem_bank[15] = 'h3c ; mem_bank[16] = 'h34 ; mem_bank[17] = 'h24 ; mem_bank[18] = 'h24 ; mem_bank[19] = 'h14 ;
mem_bank[20] = 'h24 ; mem_bank[21] = 'h03 ; mem_bank[22] = 'h24 ; mem_bank[23] = 'h27 ; mem_bank[24] = 'haf ; mem_bank[25] = 'haf ; mem_bank[26] = 'h00 ; mem_bank[27] = 'h02 ; mem_bank[28] = 'h26 ; mem_bank[29] = 'h30 ;
mem_bank[30] = 'h0c ; mem_bank[31] = 'h00 ; mem_bank[32] = 'h0c ; mem_bank[33] = 'h00 ; mem_bank[34] = 'h10 ; mem_bank[35] = 'h02 ; mem_bank[36] = 'h30 ; mem_bank[37] = 'h3c ; mem_bank[38] = 'h34 ; mem_bank[39] = 'h03 ;
mem_bank[40] = 'ha0 ; mem_bank[41] = 'h00 ; mem_bank[42] = 'h00 ; mem_bank[43] = 'h00 ; mem_bank[44] = 'h00 ; mem_bank[45] = 'h00 ; mem_bank[46] = 'h00 ; mem_bank[47] = 'h00 ; mem_bank[48] = 'h00 ;
end
always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;
always @ (posedge clock)
begin
r_data<=data;
r_wraddress<=wraddress;
r_rdaddress_a<=rdaddress_a;
r_rdaddress_b<=rdaddress_b;
r_wren<=wren;
end
assign qa =mem_bank[r_rdaddress_a];
assign qb =mem_bank[r_rdaddress_b];
endmodule
 
 
 
/include.h
0,0 → 1,171
`ifndef INCLUDE_H
`define INCLUDE_H
 
`define FRQ 50000000
`define SER_RATE 19200
`define FW_ALU 3'b001
`define FW_MEM 3'b010
`define FW_NOP 3'b100
`define ALU_MFHI 6
`define ALU_MFLO 7
`define ALU_MULTTU 8
`define ALU_MULT 9
`define ALU_DIVU 10
`define ALU_DIV 11
`define DMEM_SB 1
`define DMEM_LBS 2
`define DMEM_LB 3
`define DMEM_LBU 4
`define DMEM_SW 5
`define DMEM_LW 6
`define DMEM_SH 7
`define DMEM_LHS 8
`define DMEM_LH 9
`define DMEM_LHU 10
`define DMEM_NOP 0
`define ALU_SRL 1
`define ALU_SLL 2
`define ALU_SRA 4
`define WB_ALU 0
`define WB_MEM 1
`define WB_NOP 0
`define RD_RD 1
`define RD_RT 2
`define RD_R31 3
`define RD_NOP 0
`define RD_ZR 0
`define EXT_CTL_LEN 3
`define RD_SEL_LEN 2
`define CMP_CTL_LEN 3
`define PC_GEN_CTL_LEN 3
`define FSM_CTL_LEN 3
`define MUXA_CTL_LEN 2
`define MUXB_CTL_LEN 2
`define ALU_FUNC_LEN 5
`define ALU_WE_LEN 1
`define DMEM_CTL_LEN 4
`define WB_MUX_CTL_LEN 1
`define WB_WE_LEN 1
`define INS_LEN 32
`define PC_LEN 32
`define SPC_LEN 32
`define R32_LEN 32
`define R5_LEN 5
`define R1_LEN 1
`define R2_LEN 2
`define R3_LEN 3
`define R4_LEN 4
`define ALU_ADD 12
`define ALU_ADDU 13
`define ALU_SUB 14
`define ALU_SUBU 15
`define ALU_SLTU 16
`define ALU_SLT 17
`define ALU_OR 18
`define ALU_AND 19
`define ALU_XOR 20
`define ALU_NOR 21
`define ALU_PA 22
`define ALU_PB 23
`define D2_MUL_DLY 4'b0000
`define IDLE 4'b0001
`define MUL 4'b0010
`define CUR 4'b0011
`define RET 4'b0100
`define IRQ 4'b0101
`define RST 4'b0110
`define LD 4'b0111
`define NOI 4'b1000
`define ALU_NOP 0
`define ALU_MTLO 30
`define ALU_MTHI 31
`define ALU_MULTU 8
`define PC_IGN 1
`define PC_KEP 2
`define PC_IRQ 4
`define PC_RST 8
`define PC_J 1
`define PC_JR 2
`define PC_BC 4
`define PC_NEXT 5
`define PC_NOP 0
`define PC_RET 6
`define PC_SPC 6
`define RF 13
`define EXEC 10
`define DMEM 4
`define WB 2
`define MUXA_PC 1
`define MUXA_RS 2
`define MUXA_EXT 3
`define MUXA_SPC 0
`define MUXA_NOP 0
`define MUXB_RT 1
`define MUXB_EXT 2
`define MUXB_NOP 0
`define CMP_BEQ 1
`define CMP_BNE 2
`define CMP_BLEZ 3
`define CMP_BGEZ 4
`define CMP_BGTZ 5
`define CMP_BLTZ 6
`define CMP_NOP 0
`define FSM_CUR 1
`define FSM_MUL 2
`define FSM_RET 4
`define FSM_NOP 0
`define FSM_LD 5
`define FSM_NOI 6
`define REG_NOP 0
`define REG_CLR 1
`define REG_KEP 2
`define EXT_SIGN 1
`define EXT_UNSIGN 2
`define EXT_J 3
`define EXT_B 4
`define EXT_SA 5
`define EXT_S2H 6
`define EXT_NOP 0
`define EN 1
`define DIS 0
`define IGN 0
`define UART_DATA_ADDR 'H80_00_00_28
`define CMD_ADDR 'H80_00_00_14
`define STATUS_ADDR 'H80_00_00_18
`define SEG7LED_ADDR 'H80_00_00_1C
`define SIM_DIS_ADDR 'H80_00_00_20
`define LCD_DATA_ADDR 'H80_00_00_24
`define IRQ_MASK_ADDR 'H80_00_00_34
`define TMR_IRQ_ADDR 'H80_00_00_28
`define TMR_DATA_ADDR 'H80_00_00_34
`define KEY1_IRQ_ADDR 'H80_00_00_2C
`define KEY2_IRQ_ADDR 'H80_00_00_30
`define COUNTER_VALUE1 (`FRQ/`SER_RATE/2-1)
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
`define ALTERA
`else
 
 
`endif

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