OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /mips789/tags/v001/verilog/mips_core
    from Rev 6 to Rev 51
    ↔ Reverse comparison
  •

Rev 6 → Rev 51

/cal_cpi.v
0,0 → 1,72
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: For simulations only to calculate the CPI ////
//// Cycles Per Instruction ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
 
module cal_cpi (
input clk,
input rst,
input is_nop,
output reg [100:0] ins_no,
output reg [100:0] clk_no);
 
always @(posedge clk or negedge rst )
if (~rst )clk_no=0;
else
clk_no = 1+clk_no;
 
always @(posedge clk or negedge rst)
if (~rst )ins_no=0;
else if (~is_nop)
ins_no = 1+ins_no;
endmodule
/regfile.v
0,0 → 1,106
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
module reg_array2(
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
qa,
qb,
rd_clk_cls
);
 
input [31:0] data;
input [4:0] wraddress;
input [4:0] rdaddress_a;
input [4:0] rdaddress_b;
 
reg [31:0] r_data;
reg [4:0] r_wraddress;
reg [4:0] r_rdaddress_a;
reg [4:0] r_rdaddress_b;
input rd_clk_cls;
input wren;
reg r_wren;
input clock;
output [31:0] qa;
output [31:0] qb;
reg [31:0]reg_bank[0:31];
 
assign qa=(r_rdaddress_a==0)?0:
((r_wraddress==r_rdaddress_a)&&(r_wren))?r_data:
reg_bank[r_rdaddress_a];
 
assign qb=(r_rdaddress_b==0)?0:
((r_wraddress==r_rdaddress_b)&&(r_wren))?r_data:
reg_bank[r_rdaddress_b];
 
always@(posedge clock)
if (~rd_clk_cls)
begin
r_rdaddress_a <=rdaddress_a;
r_rdaddress_b<=rdaddress_b;
end
always@(posedge clock)
begin
r_data <=data;
r_wraddress<=wraddress;
r_wren<=wren;
end
always@(posedge clock)
if (r_wren)
reg_bank[r_wraddress] <= r_data ;
endmodule
/mem_ctl.v
0,0 → 1,203
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
`define DMEM_SB 1
`define DMEM_LBS 2
`define DMEM_LB 3
`define DMEM_LBU 4
`define DMEM_SW 5
`define DMEM_LW 6
`define DMEM_SH 7
`define DMEM_LHS 8
`define DMEM_LH 9
`define DMEM_LHU 10
`define DMEM_NOP 0
 
 
module infile_dmem_ctl_reg(
input clk,
input [3:0]ctl_i,
input [31:0]dmem_addr_i,
output reg [1:0]byte_addr_o,
output reg [3:0]ctl_o
);
 
wire [1:0]byte_addr_i;
assign byte_addr_i = dmem_addr_i[1:0] ;
always @(posedge clk)
begin
ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0;
byte_addr_o<=byte_addr_i;
end
 
endmodule
 
module mem_addr_ctl(
input [3:0]ctl,
input [31:0]addr_i,
output reg[3:0]wr_en
);
always@(*)
case (ctl)
`DMEM_SB:
begin
case(addr_i[1:0])
0:wr_en = 4'b1000;
1:wr_en = 4'b0100;
2:wr_en = 4'b0010;
3:wr_en = 4'b0001;
endcase
end
`DMEM_SH :
begin
case(addr_i[1:0])
'd0:wr_en=4'b1100;
'd2:wr_en=4'b0011;
endcase
end
`DMEM_SW :
begin
wr_en=4'b1111;
end
default wr_en=4'b0000;
endcase
 
endmodule
 
 
 
module mem_dout_ctl(
input [1:0]byte_addr,
input [3:0]ctl,
input [31:0] din,
output reg [31:0] dout
);
 
always @(*)
case (ctl)
 
`DMEM_LBS :
case (byte_addr)
'd0:dout={{24{din[31]}},din[31:24]};
'd1:dout={{24{din[23]}},din[23:16]};
'd2:dout={{24{din[15]}},din[15:8]};
'd3:dout={{24{din[7]}},din[7:0] };
default :
dout=32'b0;
endcase//checked
`DMEM_LBU :
case (byte_addr)
'd3:dout={24'b0,din[7:0]};
'd2:dout={24'b0,din[15:8]};
'd1:dout={24'b0,din[23:16]};
'd0:dout={24'b0,din[31:24]};
default :
dout=32'b0;
endcase
`DMEM_LHU :
case (byte_addr)
'd0:dout={16'b0,din[23:16],din[31:24]};
'd2:dout={16'b0,din[7:0],din[15:8]};
endcase
`DMEM_LHS :
case (byte_addr)
'd0 :dout={{16{din[23]}},din[23:16],din[31:24]};
'd2 :dout={{16{din[7 ]}},din[7 :0],din[15:8]};
default:dout=0;
endcase
`DMEM_LW :
dout=din;
default :
dout=32'b0;
endcase
endmodule
 
module mem_din_ctl(
input [3:0]ctl,
input [31:0]din,
output reg [31:0]dout
);
 
always @(*)
 
case (ctl)
`DMEM_SB :
dout={din[7:0],din[7:0],din[7:0],din[7:0]};
`DMEM_SH :
dout = {din[15:0],din[15:0]};
`DMEM_SW :
dout =din;
default dout=din;
endcase
 
endmodule
 
/*
 
ex. 1,
unsigned short a[4]={0,1,2,3};
00000001
00020003
 
ex. 2
unsigned char a[4]={0,1,2,3};
00010203
 
 
ex. 3
unsigned int b[3]={0x12345678,0,0x12345678};
12345678
00000000
12345678
 
*/
/mips_core.v
0,0 → 1,368
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
module mips_core1 (
clk,irq_i,rst,cop_dout,irq_addr,
zz_din,zz_ins_i,iack_o,cop_addr_o,
cop_data_o,cop_mem_ctl_o,zz_addr_o,
zz_dout,zz_pc_o,zz_wr_en_o
);
 
input clk;
wire clk;
input irq_i;
wire irq_i;
input rst;
wire rst;
input [31:0] cop_dout;
wire [31:0] cop_dout;
input [31:0] irq_addr;
wire [31:0] irq_addr;
input [31:0] zz_din;
wire [31:0] zz_din;
input [31:0] zz_ins_i;
wire [31:0] zz_ins_i;
output iack_o;
wire iack_o;
output [31:0] cop_addr_o;
wire [31:0] cop_addr_o;
output [31:0] cop_data_o;
wire [31:0] cop_data_o;
output [3:0] cop_mem_ctl_o;
wire [3:0] cop_mem_ctl_o;
output [31:0] zz_addr_o;
wire [31:0] zz_addr_o;
output [31:0] zz_dout;
wire [31:0] zz_dout;
output [31:0] zz_pc_o;
wire [31:0] zz_pc_o;
output [3:0] zz_wr_en_o;
wire [3:0] zz_wr_en_o;
 
wire NET1375;
wire NET1572;
wire NET1606;
wire NET1640;
wire NET21531;
wire NET457;
wire NET767;
wire [2:0] BUS109;
wire [2:0] BUS1158;
wire [2:0] BUS117;
wire [2:0] BUS1196;
wire [31:0] BUS15471;
wire [4:0] BUS1724;
wire [4:0] BUS1726;
wire [4:0] BUS18211;
wire [2:0] BUS197;
wire [2:0] BUS2140;
wire [2:0] BUS2156;
wire [31:0] BUS22401;
wire [31:0] BUS24839;
wire [31:0] BUS27031;
wire [2:0] BUS271;
wire [31:0] BUS28013;
wire [1:0] BUS371;
wire [31:0] BUS422;
wire [1:0] BUS5832;
wire [1:0] BUS5840;
wire [3:0] BUS5985;
wire [2:0] BUS5993;
wire [4:0] BUS6275;
wire [31:0] BUS7101;
wire [31:0] BUS7117;
wire [31:0] BUS7160;
wire [31:0] BUS7219;
wire [31:0] BUS7231;
wire [4:0] BUS748;
wire [4:0] BUS756;
wire [4:0] BUS775;
wire [31:0] BUS7772;
wire [31:0] BUS7780;
wire [31:0] BUS9589;
wire [31:0] BUS9884;
 
 
mem_module1 MEM_CTL
(
.Zz_addr(zz_addr_o),
.Zz_dout(zz_dout),
.Zz_wr_en(zz_wr_en_o),
.clk(clk),
.din(BUS9884),
.dmem_addr_i(BUS9589),
.dmem_ctl(BUS5985),
.dout(BUS22401),
.zZ_din(zz_din)
);
 
assign NET21531 = NET1572 | iack_o;
 
rf_stage8 U2
(
.clk(clk),
.cmp_ctl_i(BUS109),
.ext_ctl_i(BUS117),
.ext_o(BUS7219),
.fw_alu_i(cop_addr_o),
.fw_cmp_rs(BUS2140),
.fw_cmp_rt(BUS2156),
.fw_mem_i(BUS15471),
.iack_o(iack_o),
.id2ra_ctl_clr_o(NET1606),
.id2ra_ctl_cls_o(NET1572),
.id_cmd(BUS197),
.ins_i(zz_ins_i),
.irq_addr_i(irq_addr),
.irq_i(irq_i),
.pc_gen_ctl(BUS271),
.pc_i(BUS27031),
.pc_next(zz_pc_o),
.ra2ex_ctl_clr_o(NET1640),
.rd_index_o(BUS775),
.rd_sel_i(BUS371),
.rs_n_o(BUS748),
.rs_o(BUS24839),
.rst_i(rst),
.rt_n_o(BUS756),
.rt_o(BUS7160),
.wb_addr_i(BUS18211),
.wb_din_i(BUS15471),
.wb_we_i(NET1375),
.zz_spc_i(BUS28013)
);
 
 
 
exec_stage1 U3
(
.alu_func(BUS6275),
.alu_ur_o(BUS9589),
.clk(clk),
.dmem_data_ur_o(BUS9884),
.dmem_fw_ctl(BUS5993),
.ext_i(BUS7231),
.fw_alu(cop_addr_o),
.fw_dmem(BUS15471),
.muxa_ctl_i(BUS5832),
.muxa_fw_ctl(BUS1158),
.muxb_ctl_i(BUS5840),
.muxb_fw_ctl(BUS1196),
.pc_i(BUS27031),
.rs_i(BUS7101),
.rst(rst),
.rt_i(BUS7117),
.spc_cls_i(NET21531),
.zz_spc_o(BUS28013)
);
 
 
 
r32_reg alu_pass0
(
.clk(clk),
.r32_i(BUS9589),
.r32_o(cop_addr_o)
);
 
 
 
r32_reg alu_pass1
(
.clk(clk),
.r32_i(cop_addr_o),
.r32_o(BUS422)
);
 
 
 
or32 cop_data_or
(
.a(cop_dout),
.b(BUS7772),
.c(BUS7780)
);
 
 
 
r32_reg cop_data_reg
(
.clk(clk),
.r32_i(BUS9884),
.r32_o(cop_data_o)
);
 
 
 
r32_reg cop_dout_reg
(
.clk(clk),
.r32_i(BUS22401),
.r32_o(BUS7772)
);
 
 
 
decode_pipe3 decoder_pipe
(
.alu_func_o(BUS6275),
.alu_we_o(NET767),
.clk(clk),
.cmp_ctl_o(BUS109),
.dmem_ctl_o(cop_mem_ctl_o),
.dmem_ctl_ur_o(BUS5985),
.ext_ctl_o(BUS117),
.fsm_dly(BUS197),
.id2ra_ctl_clr(NET1606),
.id2ra_ctl_cls(NET1572),
.ins_i(zz_ins_i),
.muxa_ctl_o(BUS5832),
.muxb_ctl_o(BUS5840),
.pc_gen_ctl_o(BUS271),
.ra2ex_ctl_clr(NET1640),
.rd_sel_o(BUS371),
.wb_mux_ctl_o(NET457),
.wb_we_o(NET1375)
);
 
 
 
r32_reg ext_reg
(
.clk(clk),
.r32_i(BUS7219),
.r32_o(BUS7231)
);
 
 
 
forward2 forward
(
.alu_rs_fw(BUS1158),
.alu_rt_fw(BUS1196),
.alu_we(NET767),
.clk(clk),
.cmp_rs_fw(BUS2140),
.cmp_rt_fw(BUS2156),
.dmem_fw(BUS5993),
.fw_alu_rn(BUS1724),
.fw_mem_rn(BUS18211),
.mem_We(NET1375),
.rns_i(BUS748),
.rnt_i(BUS756)
);
 
 
 
r32_reg pc
(
.clk(clk),
.r32_i(zz_pc_o),
.r32_o(BUS27031)
);
 
 
 
r5_reg rnd_pass0
(
.clk(clk),
.r5_i(BUS775),
.r5_o(BUS1726)
);
 
 
 
r5_reg rnd_pass1
(
.clk(clk),
.r5_i(BUS1726),
.r5_o(BUS1724)
);
 
 
 
r5_reg rnd_pass2
(
.clk(clk),
.r5_i(BUS1724),
.r5_o(BUS18211)
);
 
 
 
r32_reg rs_reg
(
.clk(clk),
.r32_i(BUS24839),
.r32_o(BUS7101)
);
 
 
 
r32_reg rt_reg
(
.clk(clk),
.r32_i(BUS7160),
.r32_o(BUS7117)
);
 
 
 
wb_mux wb_mux
(
.alu_i(BUS422),
.dmem_i(BUS7780),
.sel(NET457),
.wb_o(BUS15471)
);
 
endmodule
/alu.v
0,0 → 1,106
//This file is based on YACC ->alu.v
 
 
 
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
`define ALU_ADD 12
`define ALU_ADDU 13
`define ALU_SUB 14
`define ALU_SUBU 15
`define ALU_SLTU 16
`define ALU_SLT 17
`define ALU_OR 18
`define ALU_AND 19
`define ALU_XOR 20
`define ALU_NOR 21
`define ALU_PA 22
`define ALU_PB 23
 
module alu (a,b,alu_out,alu_func);
 
input [31:0] a,b;
output reg [31:0] alu_out;
input [4:0] alu_func;
 
wire [31:0] c;
 
reg [32:0] sum;
 
always @(*)
begin
case (alu_func)
`ALU_PA : alu_out=a;
`ALU_PB : alu_out=b;
`ALU_ADD : alu_out=a+b;
`ALU_SUB ,
`ALU_SUBU : alu_out=a + (~b)+1;
`ALU_OR : alu_out=a | b;
`ALU_AND : alu_out=a & b;
`ALU_XOR : alu_out=a ^ b;
`ALU_NOR : alu_out=~(a | b);
`ALU_SLTU : alu_out=(a < b)?1:0;
`ALU_SLT :
begin
sum={a[31],a}+~{b[31],b}+33'h0_0000_0001;
alu_out={31'h0000_0000,sum[32]};
end
default : alu_out=32'h0;
endcase
end
endmodule
 
/*
this file is based on YACC's alu.v
*/
/mem_module.v
0,0 → 1,131
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
 
module mem_module1 (clk,din,dmem_addr_i,dmem_ctl,zZ_din,Zz_addr,Zz_dout,Zz_wr_en,dout) ;
 
// ------------ Port declarations --------- //
input clk;
wire clk;
input [31:0] din;
wire [31:0] din;
input [31:0] dmem_addr_i;
wire [31:0] dmem_addr_i;
input [3:0] dmem_ctl;
wire [3:0] dmem_ctl;
input [31:0] zZ_din;
wire [31:0] zZ_din;
output [31:0] Zz_addr;
wire [31:0] Zz_addr;
output [31:0] Zz_dout;
wire [31:0] Zz_dout;
output [3:0] Zz_wr_en;
wire [3:0] Zz_wr_en;
output [31:0] dout;
wire [31:0] dout;
 
// ----------- Signal declarations -------- //
wire [3:0] BUS512;
wire [1:0] BUS629;
wire [31:0] BUS650;
 
// -------- Component instantiations -------//
 
infile_dmem_ctl_reg dmem_ctl_post
(
.byte_addr_o(BUS629),
.clk(clk),
.ctl_i(dmem_ctl),
.ctl_o(BUS512),
.dmem_addr_i(BUS650)
);
 
 
 
mem_addr_ctl i_mem_addr_ctl
(
.addr_i(BUS650),
.ctl(dmem_ctl),
.wr_en(Zz_wr_en)
);
 
 
 
mem_din_ctl i_mem_din_ctl
(
.ctl(dmem_ctl),
.din(din),
.dout(Zz_dout)
);
 
 
 
mem_dout_ctl i_mem_dout_ctl
(
.byte_addr(BUS629),
.ctl(BUS512),
.din(zZ_din),
.dout(dout)
);
 
 
 
// ----------- Terminals assignment --------//
// ---- Input terminals --- //
assign BUS650[31:0] = dmem_addr_i[31:0];
 
// ---- Output terminals --- //
assign Zz_addr[31:0] = BUS650[31:0];
 
endmodule
/ram_module.v
0,0 → 1,172
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
`define DEBUG
 
module mem_array
(
input clk,
input [31:0] pc_i,
output [31:0] ins_o,
input [3:0] wren,
input [31:0]din,
input [31:0]wr_addr_i,
input [31:0]rd_addr_i,
output [31:0]dout
);
wire [31:0] rd_addr,pc,wr_addr;
wire [31:0]dout_w;
assign dout = dout_w;
assign rd_addr=rd_addr_i[31:2];
assign wr_addr=wr_addr_i[31:2];
assign pc= pc_i[31:2];
 
`ifdef DEBUG
 
sim_syn_ram3 ram3 (
.data(din[31:31-7]),
.wraddress(wr_addr),
.rdaddress_a(pc),
.rdaddress_b(rd_addr),
.wren(wren[3]),
.clock(clk),
.qa(ins_o[31:31-7]),
.qb(dout_w[31:31-7])
);
 
sim_syn_ram2 ram2(
.data(din[31-8:31-8-7]),
.wraddress(wr_addr),
.rdaddress_a(pc),
.rdaddress_b(rd_addr),
.wren(wren[2]),
.clock(clk),
.qa(ins_o[31-8:31-8-7]),
.qb(dout_w[31-8:31-7-8])
);
 
sim_syn_ram1 ram1(
.data(din[31-16:31-16-7]),
.wraddress(wr_addr),
.rdaddress_a(pc),
.rdaddress_b(rd_addr),
.wren(wren[1]),
.clock(clk),
.qa(ins_o[31-16:31-7-16]),
.qb(dout_w[31-16:31-7-16])
);
 
sim_syn_ram0 ram0(
.data(din[31-24:31-7-24]),
.wraddress(wr_addr),
.rdaddress_a(pc),
.rdaddress_b(rd_addr),
.wren(wren[0]),
.clock(clk),
.qa(ins_o[31-24:31-7-24]),
.qb(dout_w[31-24:31-7-24])
);
 
 
`else
ram4096x8_3 ram3(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(32'b0),
.data_b(din[31:24]),
.address_b(wr_addr),
.wren_b(wren[3]),
.clock(clk),
.q_a(ins_o[31:24]),
.q_b(dout_w[31:24])
);
 
ram4096x8_2 ram2(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(32'b0),
.data_b(din[23:16]),
.address_b(wr_addr),
.wren_b(wren[2]),
.clock(clk),
.q_a(ins_o[23:16]),
.q_b(dout_w[23:16])
);
 
ram4096x8_1 ram1(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(32'b0),
.data_b(din[15:8]),
.address_b(wr_addr),
.wren_b(wren[1]),
.clock(clk),
.q_a(ins_o[15:8]),
.q_b(dout_w[15:8])
);
 
ram4096x8_0 ram0(
.data_a(32'b0),
.wren_a(1'b0),
.address_a(32'b0),
.data_b(din[7:0]),
.address_b(wr_addr),
.wren_b(wren[0]),
.clock(clk),
.q_a(ins_o[7:0]),
.q_b(dout_w[7:0])
);
`endif
 
endmodule
 
/CTL_FSM.v
0,0 → 1,291
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
module ctl_FSM8 (
clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop
);
 
parameter
ID_CUR = 1,
ID_LD = 5,
ID_MUL = 2,
ID_NOI = 6,
ID_RET = 4,
ONE = 1,
PC_IGN = 1,
PC_IRQ = 4,
PC_KEP = 2,
PC_RST = 8,
ZERO = 0;
input clk;
input [2:0] id_cmd;
input irq;
input rst;
output iack;
output zz_is_nop;
output id2ra_ctl_clr;
output id2ra_ctl_cls;
output id2ra_ins_clr;
output id2ra_ins_cls;
output [3:0] pc_prectl;
output ra2exec_ctl_clr;
 
wire clk;
reg iack;
reg zz_is_nop;
reg id2ra_ctl_clr;
reg id2ra_ctl_cls;
reg id2ra_ins_clr;
reg id2ra_ins_cls;
wire [2:0] id_cmd;
wire irq;
reg [3:0] pc_prectl;
reg ra2exec_ctl_clr;
wire rst;
reg [0:5]delay_counter_Sreg0, next_delay_counter_Sreg0;
`define D2_MUL_DLY 4'b0000
`define IDLE 4'b0001
`define MUL 4'b0010
`define CUR 4'b0011
`define RET 4'b0100
`define IRQ 4'b0101
`define RST 4'b0110
`define LD 4'b0111
`define NOI 4'b1000
 
reg [3:0] CurrState_Sreg0;
reg [3:0] NextState_Sreg0;
reg riack;
always @ (*)
begin : Sreg0_NextState
case (CurrState_Sreg0) // synopsys parallel_case full_case
`IDLE:
begin
id2ra_ins_clr=ZERO;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ZERO;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr =ZERO;
pc_prectl=PC_IGN;
iack = riack;
if ((irq)&&(~iack))
NextState_Sreg0 <= `IRQ;
else if (id_cmd ==ID_NOI)
NextState_Sreg0 <= `NOI;
else if (id_cmd==ID_CUR)
NextState_Sreg0 <= `CUR;
else if (id_cmd==ID_MUL)
NextState_Sreg0 <= `MUL;
else if (id_cmd==ID_LD)
NextState_Sreg0 <= `LD;
else if (id_cmd==ID_RET)
NextState_Sreg0 <= `RET;
else
NextState_Sreg0 <= `IDLE;
end
`MUL:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ZERO;
pc_prectl =PC_KEP;
iack = riack;
NextState_Sreg0 <= `D2_MUL_DLY;
next_delay_counter_Sreg0 <= 34 - 1;
zz_is_nop =0;
end
`CUR:
begin
id2ra_ins_clr=ZERO;
id2ra_ins_cls=ONE;
id2ra_ctl_clr=ZERO;
id2ra_ctl_cls=ONE;
ra2exec_ctl_clr=ONE;
pc_prectl =PC_KEP;
iack = riack;
NextState_Sreg0 <= `NOI;
zz_is_nop = 1;
end
`RET:
begin
id2ra_ins_clr=ZERO;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ZERO;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr =ZERO;
pc_prectl =PC_IGN;
iack =ZERO;
riack =ZERO;
NextState_Sreg0 <= `IDLE;
zz_is_nop = ZERO;
end
`IRQ:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ONE;
pc_prectl =PC_IRQ;
iack =ONE;
riack=ONE;
NextState_Sreg0 <= `IDLE;
zz_is_nop = ZERO;
end
`RST:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ONE;
pc_prectl=PC_RST;
iack=ZERO;
riack=ZERO;
NextState_Sreg0 <= `IDLE;
zz_is_nop = ONE;
end
`LD:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ZERO;
pc_prectl =PC_KEP;
iack=riack;
NextState_Sreg0 <= `IDLE;
zz_is_nop = ZERO;
end
`NOI:
begin
id2ra_ins_clr=ZERO;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ZERO;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr =ZERO;
iack=riack;
pc_prectl=PC_IGN;
NextState_Sreg0 <= `IDLE;
zz_is_nop = ZERO;
end
`D2_MUL_DLY:
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ZERO;
pc_prectl =PC_KEP;
iack=riack;
zz_is_nop = ONE;
if (delay_counter_Sreg0 == 0)
NextState_Sreg0 <= `IDLE;
else
begin
NextState_Sreg0 <= `D2_MUL_DLY;
if (delay_counter_Sreg0 != 0) next_delay_counter_Sreg0 <= delay_counter_Sreg0 - 1;
end
end
default :
begin
id2ra_ins_clr=ONE;
id2ra_ins_cls=ZERO;
id2ra_ctl_clr=ONE;
id2ra_ctl_cls=ZERO;
ra2exec_ctl_clr=ONE;
pc_prectl=PC_RST;
iack=ZERO;
riack=ZERO;
zz_is_nop = ONE;
NextState_Sreg0 <= `IDLE;
end
endcase
end
 
always @ (posedge clk or negedge rst)
begin : Sreg0_CurrentState
if (~rst)
CurrState_Sreg0 <= `RST;
else
CurrState_Sreg0 <= NextState_Sreg0;
end
always @ (posedge clk or negedge rst)
begin : Sreg0_RegOutput
if (~rst)
begin
delay_counter_Sreg0 <= 0 ; // Initialization in the reset state or default value required!!
end
else
begin
delay_counter_Sreg0 <= next_delay_counter_Sreg0;
end
end
 
endmodule
 
 
/*
how to modify this module
1,add riack
2,change the `RST action as default
3,set `IRQ has highest pority.
*/
/RF_stage.v
0,0 → 1,286
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
module rf_stage8 (
clk,irq_i,rst_i,wb_we_i,cmp_ctl_i,
ext_ctl_i,fw_alu_i,fw_cmp_rs,fw_cmp_rt,
fw_mem_i,id_cmd,ins_i,irq_addr_i,pc_gen_ctl,
pc_i,rd_sel_i,wb_addr_i,wb_din_i,zz_spc_i,iack_o,
id2ra_ctl_clr_o,id2ra_ctl_cls_o,ra2ex_ctl_clr_o,ext_o,
pc_next,rd_index_o,rs_n_o,rs_o,rt_n_o,rt_o
) ;
 
// ------------ Port declarations --------- //
input clk;
wire clk;
input irq_i;
wire irq_i;
input rst_i;
wire rst_i;
input wb_we_i;
wire wb_we_i;
input [2:0] cmp_ctl_i;
wire [2:0] cmp_ctl_i;
input [2:0] ext_ctl_i;
wire [2:0] ext_ctl_i;
input [31:0] fw_alu_i;
wire [31:0] fw_alu_i;
input [2:0] fw_cmp_rs;
wire [2:0] fw_cmp_rs;
input [2:0] fw_cmp_rt;
wire [2:0] fw_cmp_rt;
input [31:0] fw_mem_i;
wire [31:0] fw_mem_i;
input [2:0] id_cmd;
wire [2:0] id_cmd;
input [31:0] ins_i;
wire [31:0] ins_i;
input [31:0] irq_addr_i;
wire [31:0] irq_addr_i;
input [2:0] pc_gen_ctl;
wire [2:0] pc_gen_ctl;
input [31:0] pc_i;
wire [31:0] pc_i;
input [1:0] rd_sel_i;
wire [1:0] rd_sel_i;
input [4:0] wb_addr_i;
wire [4:0] wb_addr_i;
input [31:0] wb_din_i;
wire [31:0] wb_din_i;
input [31:0] zz_spc_i;
wire [31:0] zz_spc_i;
output iack_o;
wire iack_o;
output id2ra_ctl_clr_o;
wire id2ra_ctl_clr_o;
output id2ra_ctl_cls_o;
wire id2ra_ctl_cls_o;
output ra2ex_ctl_clr_o;
wire ra2ex_ctl_clr_o;
output [31:0] ext_o;
wire [31:0] ext_o;
output [31:0] pc_next;
wire [31:0] pc_next;
output [4:0] rd_index_o;
wire [4:0] rd_index_o;
output [4:0] rs_n_o;
wire [4:0] rs_n_o;
output [31:0] rs_o;
wire [31:0] rs_o;
output [4:0] rt_n_o;
wire [4:0] rt_n_o;
output [31:0] rt_o;
wire [31:0] rt_o;
 
// ----------------- Constants ------------ //
parameter DANGLING_INPUT_CONSTANT = 1'bZ;
 
// ----------- Signal declarations -------- //
wire NET6609;
wire NET6658;
wire NET7774;
wire NET904;
wire [3:0] BUS1013;
wire [31:0] BUS2085;
wire [4:0] BUS3236;
wire [4:0] BUS3237;
wire [4:0] BUS5421;
wire [31:0] BUS6061;
wire [31:0] BUS6095;
 
// ---- Declaration for Dangling inputs ----//
wire Dangling_Input_Signal = DANGLING_INPUT_CONSTANT;
 
// -------- Component instantiations -------//
 
cal_cpi CAL_CPI
(
.clk(clk),
.clk_no(CLK_NO),
.ins_no(INS_NO),
.is_nop(NET7774),
.rst(rst_i)
);
 
 
 
ctl_FSM8 RF_STAGE
(
.clk(clk),
.iack(iack_o),
.id2ra_ctl_clr(id2ra_ctl_clr_o),
.id2ra_ctl_cls(id2ra_ctl_cls_o),
.id2ra_ins_clr(NET6609),
.id2ra_ins_cls(NET6658),
.id_cmd(id_cmd),
.irq(irq_i),
.pc_prectl(BUS1013),
.ra2exec_ctl_clr(ra2ex_ctl_clr_o),
.rst(rst_i),
.zz_is_nop(NET7774)
);
 
 
 
pc_gen2 i_pc_gen
(
.check(NET904),
.ctl(pc_gen_ctl),
.imm(ext_o),
.irq(irq_addr_i),
.pc(pc_i),
.pc_next(pc_next),
.pc_prectl(BUS1013),
.s(rs_o),
.zz_spc(zz_spc_i)
);
 
 
 
compare i_cmp
(
.ctl(cmp_ctl_i),
.res(NET904),
.s(rs_o),
.t(rt_o)
);
 
 
 
ext i_ext
(
.ctl(ext_ctl_i),
.ins_i(BUS2085),
.res(ext_o)
);
 
 
 
r32_reg_clr_cls ins_reg
(
.clk(clk),
.clr(NET6609),
.cls(NET6658),
.r32_i(ins_i),
.r32_o(BUS2085)
);
 
 
 
jack jack1
(
.ins_i(BUS2085),
.rd_o(BUS5421),
.rs_o(rs_n_o),
.rt_o(rt_n_o)
);
 
 
 
jack jack2
(
.ins_i(ins_i),
.rs_o(BUS3237),
.rt_o(BUS3236)
);
 
 
 
rd_sel rd_sel
(
.ctl(rd_sel_i),
.rd_i(BUS5421),
.rd_o(rd_index_o),
.rt_i(rt_n_o)
);
 
 
 
reg_array2 reg_bank
(
.clock(clk),
.data(wb_din_i),
.qa(BUS6061),
.qb(BUS6095),
.rd_clk_cls(NET6658),
.rdaddress_a(BUS3237),
.rdaddress_b(BUS3236),
.wraddress(wb_addr_i),
.wren(wb_we_i)
);
 
 
 
fwd_mux rf_fwd_rt
(
.din(BUS6095),
.dout(rt_o),
.fw_alu(fw_alu_i),
.fw_ctl(fw_cmp_rt),
.fw_dmem(fw_mem_i)
);
 
 
 
fwd_mux rs_fwd_rs
(
.din(BUS6061),
.dout(rs_o),
.fw_alu(fw_alu_i),
.fw_ctl(fw_cmp_rs),
.fw_dmem(fw_mem_i)
);
 
 
 
endmodule
/pc_gen.v
0,0 → 1,102
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
`define PC_IGN 1
`define PC_KEP 2
`define PC_IRQ 4
`define PC_RST 8
 
`define PC_J 1
`define PC_JR 2
`define PC_BC 4
`define PC_NEXT 5
`define PC_SPC 6
`define PC_RET 6
`define PC_NOP 0
 
module pc_gen2 (
input [2:0]ctl,
output reg [31:0]pc_next,
input [3:0] pc_prectl,
input check,
input [31:0]s,
input [31:0]pc,
input [31:0]zz_spc,
input [31:0]imm,
input [31:0]irq
);
 
wire [32:0] br_addr = pc + imm ;
 
always @ (*)
if(pc_prectl == `PC_IGN )
begin
case (ctl)
`PC_RET : pc_next = zz_spc ;
`PC_J:pc_next ={pc[31:28],imm[27:0]};
`PC_JR: pc_next = s;
`PC_BC: pc_next = (check)?({br_addr[31:0]}):(pc+4);
`PC_NEXT:pc_next = pc+ 4 ;
default pc_next = pc + 4;
endcase
end
else
begin
case (pc_prectl)
`PC_KEP : pc_next=pc;
`PC_IRQ : pc_next=irq;
`PC_RST : pc_next='d0;
default:pc_next =0;
endcase
end
 
endmodule
/tools.v
0,0 → 1,238
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
module add32(
input [31:0]d_i,
output [31:0]d_o
);
assign d_o = d_i + 4;
endmodule
 
 
module jack(
input [31:0] ins_i ,
output [4:0] rs_o,
output [4:0] rt_o,
output [4:0] rd_o
);
assign rs_o = ins_i[25:21];
assign rt_o = ins_i[20:16];
assign rd_o = ins_i[15:11];
endmodule
 
 
 
`define WB_ALU 0
`define WB_MEM 1
`define WB_NOP 0
 
 
module wb_mux(
input [31:0]alu_i,
input [31:0]dmem_i,
input sel,
output [31:0]wb_o
);
 
assign wb_o = (sel==`WB_MEM)?dmem_i:alu_i;
 
endmodule
 
module or32(
input [31:0]a,
input [31:0]b,
output [31:0]c
);
assign c = a|b ;
 
endmodule
 
`define RD_RD 1
`define RD_RT 2
`define RD_R31 3
`define RD_NOP 0
`define RD_ZR 0
 
module rd_sel(
input [4:0]rd_i,
input [4:0]rt_i,
input[1:0] ctl,
output reg [4:0]rd_o
);
 
always @(*)
case (ctl)
`RD_RD:rd_o=rd_i;
`RD_RT:rd_o=rt_i;
`RD_R31:rd_o='d31;
default :
rd_o=0;
endcase
 
endmodule
 
//these modules below are genated automaticly by a software written in C language...
 
`define EXT_CTL_LEN 3
`define RD_SEL_LEN 2
`define CMP_CTL_LEN 3
`define PC_GEN_CTL_LEN 3
`define FSM_CTL_LEN 3
`define MUXA_CTL_LEN 2
`define MUXB_CTL_LEN 2
`define ALU_FUNC_LEN 5
`define ALU_WE_LEN 1
`define DMEM_CTL_LEN 4
`define WB_MUX_CTL_LEN 1
`define WB_WE_LEN 1
`define INS_LEN 32
`define PC_LEN 32
`define SPC_LEN 32
`define R32_LEN 32
`define R5_LEN 5
`define R1_LEN 1
`define R2_LEN 2
`define R3_LEN 3
`define R4_LEN 4
 
module ext_ctl_reg_clr_cls(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) ext_ctl_o<=0;else if(cls)ext_ctl_o<=ext_ctl_o;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr_cls(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr,input cls);always@(posedge clk)if(clr) rd_sel_o<=0;else if(cls)rd_sel_o<=rd_sel_o;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_clr_cls(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) cmp_ctl_o<=0;else if(cls)cmp_ctl_o<=cmp_ctl_o;else cmp_ctl_o<=cmp_ctl_i;endmodule
module pc_gen_ctl_reg_clr_cls(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) pc_gen_ctl_o<=0;else if(cls)pc_gen_ctl_o<=pc_gen_ctl_o;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule
module fsm_ctl_reg_clr_cls(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) fsm_ctl_o<=0;else if(cls)fsm_ctl_o<=fsm_ctl_o;else fsm_ctl_o<=fsm_ctl_i;endmodule
module muxa_ctl_reg_clr_cls(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) muxa_ctl_o<=0;else if(cls)muxa_ctl_o<=muxa_ctl_o;else muxa_ctl_o<=muxa_ctl_i;endmodule
module muxb_ctl_reg_clr_cls(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) muxb_ctl_o<=0;else if(cls)muxb_ctl_o<=muxb_ctl_o;else muxb_ctl_o<=muxb_ctl_i;endmodule
module alu_func_reg_clr_cls(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input clr,input cls);always@(posedge clk)if(clr) alu_func_o<=0;else if(cls)alu_func_o<=alu_func_o;else alu_func_o<=alu_func_i;endmodule
module alu_we_reg_clr_cls(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input clr,input cls);always@(posedge clk)if(clr) alu_we_o<=0;else if(cls)alu_we_o<=alu_we_o;else alu_we_o<=alu_we_i;endmodule
module dmem_ctl_reg_clr_cls(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) dmem_ctl_o<=0;else if(cls)dmem_ctl_o<=dmem_ctl_o;else dmem_ctl_o<=dmem_ctl_i;endmodule
module wb_mux_ctl_reg_clr_cls(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) wb_mux_ctl_o<=0;else if(cls)wb_mux_ctl_o<=wb_mux_ctl_o;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule
module wb_we_reg_clr_cls(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input clr,input cls);always@(posedge clk)if(clr) wb_we_o<=0;else if(cls)wb_we_o<=wb_we_o;else wb_we_o<=wb_we_i;endmodule
module ins_reg_clr_cls(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input clr,input cls);always@(posedge clk)if(clr) ins_o<=0;else if(cls)ins_o<=ins_o;else ins_o<=ins_i;endmodule
module pc_reg_clr_cls(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input clr,input cls);always@(posedge clk)if(clr) pc_o<=0;else if(cls)pc_o<=pc_o;else pc_o<=pc_i;endmodule
module spc_reg_clr_cls(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input clr,input cls);always@(posedge clk)if(clr) spc_o<=0;else if(cls)spc_o<=spc_o;else spc_o<=spc_i;endmodule
module r1_reg_clr_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r1_o<=0;else if(cls)r1_o<=r1_o;else r1_o<=r1_i;endmodule
module r2_reg_clr_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r2_o<=0;else if(cls)r2_o<=r2_o;else r2_o<=r2_i;endmodule
module r3_reg_clr_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r3_o<=0;else if(cls)r3_o<=r3_o;else r3_o<=r3_i;endmodule
module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule
module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule
module r32_reg_clr_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
 
 
module ext_ctl_reg_clr(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr);always@(posedge clk)if(clr)ext_ctl_o<=0;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr);always@(posedge clk)if(clr)rd_sel_o<=0;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_clr(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr);always@(posedge clk)if(clr)cmp_ctl_o<=0;else cmp_ctl_o<=cmp_ctl_i;endmodule
module pc_gen_ctl_reg_clr(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input clr);always@(posedge clk)if(clr)pc_gen_ctl_o<=0;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule
module fsm_ctl_reg_clr(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input clr);always@(posedge clk)if(clr)fsm_ctl_o<=0;else fsm_ctl_o<=fsm_ctl_i;endmodule
module muxa_ctl_reg_clr(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input clr);always@(posedge clk)if(clr)muxa_ctl_o<=0;else muxa_ctl_o<=muxa_ctl_i;endmodule
module muxb_ctl_reg_clr(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input clr);always@(posedge clk)if(clr)muxb_ctl_o<=0;else muxb_ctl_o<=muxb_ctl_i;endmodule
module alu_func_reg_clr(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input clr);always@(posedge clk)if(clr)alu_func_o<=0;else alu_func_o<=alu_func_i;endmodule
module alu_we_reg_clr(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input clr);always@(posedge clk)if(clr)alu_we_o<=0;else alu_we_o<=alu_we_i;endmodule
module dmem_ctl_reg_clr(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input clr);always@(posedge clk)if(clr)dmem_ctl_o<=0;else dmem_ctl_o<=dmem_ctl_i;endmodule
module wb_mux_ctl_reg_clr(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input clr);always@(posedge clk)if(clr)wb_mux_ctl_o<=0;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule
module wb_we_reg_clr(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input clr);always@(posedge clk)if(clr)wb_we_o<=0;else wb_we_o<=wb_we_i;endmodule
module ins_reg_clr(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input clr);always@(posedge clk)if(clr)ins_o<=0;else ins_o<=ins_i;endmodule
module pc_reg_clr(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input clr);always@(posedge clk)if(clr)pc_o<=0;else pc_o<=pc_i;endmodule
module spc_reg_clr(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input clr);always@(posedge clk)if(clr)spc_o<=0;else spc_o<=spc_i;endmodule
module r1_reg_clr(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr);always@(posedge clk)if(clr)r1_o<=0;else r1_o<=r1_i;endmodule
module r2_reg_clr(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input clr);always@(posedge clk)if(clr)r2_o<=0;else r2_o<=r2_i;endmodule
module r3_reg_clr(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input clr);always@(posedge clk)if(clr)r3_o<=0;else r3_o<=r3_i;endmodule
module r4_reg_clr(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr);always@(posedge clk)if(clr)r4_o<=0;else r4_o<=r4_i;endmodule
module r5_reg_clr(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr);always@(posedge clk)if(clr)r5_o<=0;else r5_o<=r5_i;endmodule
module r32_reg_clr(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr);always@(posedge clk)if(clr)r32_o<=0;else r32_o<=r32_i;endmodule
 
 
module ext_ctl_reg(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk);always@(posedge clk) ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk);always@(posedge clk) rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk);always@(posedge clk) cmp_ctl_o<=cmp_ctl_i;endmodule
module pc_gen_ctl_reg(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk);always@(posedge clk) pc_gen_ctl_o<=pc_gen_ctl_i;endmodule
module fsm_ctl_reg(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk);always@(posedge clk) fsm_ctl_o<=fsm_ctl_i;endmodule
module muxa_ctl_reg(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk);always@(posedge clk) muxa_ctl_o<=muxa_ctl_i;endmodule
module muxb_ctl_reg(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk);always@(posedge clk) muxb_ctl_o<=muxb_ctl_i;endmodule
module alu_func_reg(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk);always@(posedge clk) alu_func_o<=alu_func_i;endmodule
module alu_we_reg(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk);always@(posedge clk) alu_we_o<=alu_we_i;endmodule
module dmem_ctl_reg(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk);always@(posedge clk) dmem_ctl_o<=dmem_ctl_i;endmodule
module wb_mux_ctl_reg(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk);always@(posedge clk) wb_mux_ctl_o<=wb_mux_ctl_i;endmodule
module wb_we_reg(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk);always@(posedge clk) wb_we_o<=wb_we_i;endmodule
module ins_reg(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk);always@(posedge clk) ins_o<=ins_i;endmodule
module pc_reg(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk);always@(posedge clk) pc_o<=pc_i;endmodule
module spc_reg(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk);always@(posedge clk) spc_o<=spc_i;endmodule
module r1_reg(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk);always@(posedge clk) r1_o<=r1_i;endmodule
module r2_reg(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk);always@(posedge clk) r2_o<=r2_i;endmodule
module r3_reg(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk);always@(posedge clk) r3_o<=r3_i;endmodule
module r4_reg(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk);always@(posedge clk) r4_o<=r4_i;endmodule
module r5_reg(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk);always@(posedge clk) r5_o<=r5_i;endmodule
module r32_reg(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk);always@(posedge clk) r32_o<=r32_i;endmodule
 
 
module ext_ctl_reg_cls(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input cls);always@(posedge clk)if(cls) ext_ctl_o<=ext_ctl_o;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_cls(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input cls);always@(posedge clk)if(cls) rd_sel_o<=rd_sel_o;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_cls(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input cls);always@(posedge clk)if(cls) cmp_ctl_o<=cmp_ctl_o;else cmp_ctl_o<=cmp_ctl_i;endmodule
module pc_gen_ctl_reg_cls(input[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_i,output reg[`PC_GEN_CTL_LEN-1:0] pc_gen_ctl_o,input clk,input cls);always@(posedge clk)if(cls) pc_gen_ctl_o<=pc_gen_ctl_o;else pc_gen_ctl_o<=pc_gen_ctl_i;endmodule
module fsm_ctl_reg_cls(input[`FSM_CTL_LEN-1:0] fsm_ctl_i,output reg[`FSM_CTL_LEN-1:0] fsm_ctl_o,input clk,input cls);always@(posedge clk)if(cls) fsm_ctl_o<=fsm_ctl_o;else fsm_ctl_o<=fsm_ctl_i;endmodule
module muxa_ctl_reg_cls(input[`MUXA_CTL_LEN-1:0] muxa_ctl_i,output reg[`MUXA_CTL_LEN-1:0] muxa_ctl_o,input clk,input cls);always@(posedge clk)if(cls) muxa_ctl_o<=muxa_ctl_o;else muxa_ctl_o<=muxa_ctl_i;endmodule
module muxb_ctl_reg_cls(input[`MUXB_CTL_LEN-1:0] muxb_ctl_i,output reg[`MUXB_CTL_LEN-1:0] muxb_ctl_o,input clk,input cls);always@(posedge clk)if(cls) muxb_ctl_o<=muxb_ctl_o;else muxb_ctl_o<=muxb_ctl_i;endmodule
module alu_func_reg_cls(input[`ALU_FUNC_LEN-1:0] alu_func_i,output reg[`ALU_FUNC_LEN-1:0] alu_func_o,input clk,input cls);always@(posedge clk)if(cls) alu_func_o<=alu_func_o;else alu_func_o<=alu_func_i;endmodule
module alu_we_reg_cls(input[`ALU_WE_LEN-1:0] alu_we_i,output reg[`ALU_WE_LEN-1:0] alu_we_o,input clk,input cls);always@(posedge clk)if(cls) alu_we_o<=alu_we_o;else alu_we_o<=alu_we_i;endmodule
module dmem_ctl_reg_cls(input[`DMEM_CTL_LEN-1:0] dmem_ctl_i,output reg[`DMEM_CTL_LEN-1:0] dmem_ctl_o,input clk,input cls);always@(posedge clk)if(cls) dmem_ctl_o<=dmem_ctl_o;else dmem_ctl_o<=dmem_ctl_i;endmodule
module wb_mux_ctl_reg_cls(input[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_i,output reg[`WB_MUX_CTL_LEN-1:0] wb_mux_ctl_o,input clk,input cls);always@(posedge clk)if(cls) wb_mux_ctl_o<=wb_mux_ctl_o;else wb_mux_ctl_o<=wb_mux_ctl_i;endmodule
module wb_we_reg_cls(input[`WB_WE_LEN-1:0] wb_we_i,output reg[`WB_WE_LEN-1:0] wb_we_o,input clk,input cls);always@(posedge clk)if(cls) wb_we_o<=wb_we_o;else wb_we_o<=wb_we_i;endmodule
module ins_reg_cls(input[`INS_LEN-1:0] ins_i,output reg[`INS_LEN-1:0] ins_o,input clk,input cls);always@(posedge clk)if(cls) ins_o<=ins_o;else ins_o<=ins_i;endmodule
module pc_reg_cls(input[`PC_LEN-1:0] pc_i,output reg[`PC_LEN-1:0] pc_o,input clk,input cls);always@(posedge clk)if(cls) pc_o<=pc_o;else pc_o<=pc_i;endmodule
module spc_reg_cls(input[`SPC_LEN-1:0] spc_i,output reg[`SPC_LEN-1:0] spc_o,input clk,input cls);always@(posedge clk)if(cls) spc_o<=spc_o;else spc_o<=spc_i;endmodule
module r1_reg_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input cls);always@(posedge clk)if(cls) r1_o<=r1_o;else r1_o<=r1_i;endmodule
module r2_reg_cls(input[`R2_LEN-1:0] r2_i,output reg[`R2_LEN-1:0] r2_o,input clk,input cls);always@(posedge clk)if(cls) r2_o<=r2_o;else r2_o<=r2_i;endmodule
module r3_reg_cls(input[`R3_LEN-1:0] r3_i,output reg[`R3_LEN-1:0] r3_o,input clk,input cls);always@(posedge clk)if(cls) r3_o<=r3_o;else r3_o<=r3_i;endmodule
module r4_reg_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input cls);always@(posedge clk)if(cls) r4_o<=r4_o;else r4_o<=r4_i;endmodule
module r5_reg_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input cls);always@(posedge clk)if(cls) r5_o<=r5_o;else r5_o<=r5_i;endmodule
module r32_reg_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input cls);always@(posedge clk)if(cls) r32_o<=r32_o;else r32_o<=r32_i;endmodule
/decode_pipe.v
0,0 → 1,168
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
 
module decode_pipe3
(
clk,id2ra_ctl_clr,id2ra_ctl_cls,
ra2ex_ctl_clr,ins_i,alu_func_o,alu_we_o,
cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,ext_ctl_o,
fsm_dly,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,
wb_mux_ctl_o,wb_we_o
) ;
 
input clk;
wire clk;
input id2ra_ctl_clr;
wire id2ra_ctl_clr;
input id2ra_ctl_cls;
wire id2ra_ctl_cls;
input ra2ex_ctl_clr;
wire ra2ex_ctl_clr;
input [31:0] ins_i;
wire [31:0] ins_i;
output [4:0] alu_func_o;
wire [4:0] alu_func_o;
output [0:0] alu_we_o;
wire [0:0] alu_we_o;
output [2:0] cmp_ctl_o;
wire [2:0] cmp_ctl_o;
output [3:0] dmem_ctl_o;
wire [3:0] dmem_ctl_o;
output [3:0] dmem_ctl_ur_o;
wire [3:0] dmem_ctl_ur_o;
output [2:0] ext_ctl_o;
wire [2:0] ext_ctl_o;
output [2:0] fsm_dly;
wire [2:0] fsm_dly;
output [1:0] muxa_ctl_o;
wire [1:0] muxa_ctl_o;
output [1:0] muxb_ctl_o;
wire [1:0] muxb_ctl_o;
output [2:0] pc_gen_ctl_o;
wire [2:0] pc_gen_ctl_o;
output [1:0] rd_sel_o;
wire [1:0] rd_sel_o;
output [0:0] wb_mux_ctl_o;
wire [0:0] wb_mux_ctl_o;
output [0:0] wb_we_o;
wire [0:0] wb_we_o;
 
 
wire [4:0] BUS2040;
wire [0:0] BUS2048;
wire [2:0] BUS2056;
wire [3:0] BUS2064;
wire [2:0] BUS2072;
wire [1:0] BUS2086;
wire [1:0] BUS2094;
wire [2:0] BUS2102;
wire [1:0] BUS2110;
wire [0:0] BUS2118;
wire [0:0] BUS2126;
 
 
decoder3 decoder
(
.alu_func(BUS2040),
.alu_we(BUS2048),
.cmp_ctl(BUS2056),
.dmem_ctl(BUS2064),
.ext_ctl(BUS2072),
.fsm_dly(fsm_dly),
.ins_i(ins_i),
.muxa_ctl(BUS2086),
.muxb_ctl(BUS2094),
.pc_gen_ctl(BUS2102),
.rd_sel(BUS2110),
.wb_mux(BUS2118),
.wb_we(BUS2126)
);
 
 
 
pipelinedregs pipereg
(
.alu_func_i(BUS2040),
.alu_func_o(alu_func_o),
.alu_we_i(BUS2048),
.alu_we_o(alu_we_o),
.clk(clk),
.cmp_ctl_i(BUS2056),
.cmp_ctl_o(cmp_ctl_o),
.dmem_ctl_i(BUS2064),
.dmem_ctl_o(dmem_ctl_o),
.dmem_ctl_ur_o(dmem_ctl_ur_o),
.ext_ctl(ext_ctl_o),
.ext_ctl_i(BUS2072),
.id2ra_ctl_clr(id2ra_ctl_clr),
.id2ra_ctl_cls(id2ra_ctl_cls),
.muxa_ctl_i(BUS2086),
.muxa_ctl_o(muxa_ctl_o),
.muxb_ctl_i(BUS2094),
.muxb_ctl_o(muxb_ctl_o),
.pc_gen_ctl_i(BUS2102),
.pc_gen_ctl_o(pc_gen_ctl_o),
.ra2ex_ctl_clr(ra2ex_ctl_clr),
.rd_sel_i(BUS2110),
.rd_sel_o(rd_sel_o),
.wb_mux_ctl_i(BUS2118),
.wb_mux_ctl_o(wb_mux_ctl_o),
.wb_we_i(BUS2126),
.wb_we_o(wb_we_o)
);
 
 
 
endmodule
/decodr.v
0,0 → 1,1289
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
/*
AT :
we assume WB_EN as MEM_WE
*/
`define ALU_NOP 0
`define ALU_SRL 1
`define ALU_SLL 2
`define ALU_SRA 4
 
 
`define ALU_MFHI 6
`define ALU_MFLO 7
`define ALU_MTLO 30
`define ALU_MTHI 31
`define ALU_MULTU 8
`define ALU_MULT 9
`define ALU_DIVU 10
`define ALU_DIV 11
`define ALU_ADD 12
`define ALU_ADDU 13
`define ALU_SUB 14
`define ALU_SUBU 15
`define ALU_SLTU 16
`define ALU_SLT 17
`define ALU_OR 18
`define ALU_AND 19
`define ALU_XOR 20
`define ALU_NOR 21
`define ALU_PA 22
`define ALU_PB 23
 
`define PC_IGN 1
`define PC_KEP 2
`define PC_IRQ 4
`define PC_RST 8
 
`define PC_J 1
`define PC_JR 2
`define PC_BC 4
`define PC_NEXT 5
`define PC_NOP 0
`define PC_RET 6
`define PC_SPC 6
 
`define RD_RD 1
`define RD_RT 2
`define RD_R31 3
`define RD_NOP 0
`define RD_ZR 0
 
`define RD_NOP 0
 
`define RF 13
`define EXEC 10
`define DMEM 4
`define WB 2
 
`define WB_ALU 0
`define WB_MEM 1
`define WB_NOP 0
 
`define WB_NOP 0
 
`define MUXA_PC 1
`define MUXA_RS 2
`define MUXA_EXT 3
`define MUXA_SPC 0
`define MUXA_NOP 0
 
`define MUXB_RT 1
`define MUXB_EXT 2
`define MUXB_NOP 0
 
`define MUXB_NOP 0
`define FW_ALU 3'b001
`define FW_MEM 3'b010
`define FW_NOP 3'b100
 
`define CMP_BEQ 1
`define CMP_BNE 2
`define CMP_BLEZ 3
`define CMP_BGEZ 4
`define CMP_BGTZ 5
`define CMP_BLTZ 6
`define CMP_NOP 0
 
`define FSM_CUR 1
`define FSM_MUL 2
`define FSM_RET 4
`define FSM_NOP 0
`define FSM_LD 5
`define FSM_NOI 6
 
`define REG_NOP 0
`define REG_CLR 1
`define REG_KEP 2
 
`define REG_KEP 2
`define EXT_SIGN 1
`define EXT_UNSIGN 2
`define EXT_J 3
`define EXT_B 4
`define EXT_SA 5
`define EXT_S2H 6
`define EXT_NOP 0
/*
`define EXT_CTL_LEN 3
`define RD_SEL_LEN 1
`define CMP_CTL_LEN 3
`define PC_GEN_CTL_LEN 3
`define FSM_CTL_LEN 3
`define MUXA_CTL_LEN 2
`define MUXB_CTL_LEN 2
`define ALU_FUNC_LEN 5
`define ALU_WE_LEN 1
`define DMEM_CTL_LEN 4
`define WB_MUX_CTL_LEN 1
`define WB_WE_LEN 1
*/
`define EN 1
`define DIS 0
`define IGN 0
 
`define DMEM_SB 1
`define DMEM_LBS 2
`define DMEM_LB 3
`define DMEM_LBU 4
`define DMEM_SW 5
`define DMEM_LW 6
`define DMEM_SH 7
`define DMEM_LHS 8
`define DMEM_LH 9
`define DMEM_LHU 10
`define DMEM_NOP 0
 
`define DMEM_NOP 0
 
 
`define EXT_CTL_LEN 3
`define RD_SEL_LEN 2
`define CMP_CTL_LEN 3
`define PC_GEN_CTL_LEN 3
`define FSM_CTL_LEN 3
`define MUXA_CTL_LEN 2
`define MUXB_CTL_LEN 2
`define ALU_FUNC_LEN 5
`define ALU_WE_LEN 1
`define DMEM_CTL_LEN 4
`define WB_MUX_CTL_LEN 1
`define WB_WE_LEN 1
 
module decoder3(
input [31:0]ins_i,
output reg [`EXT_CTL_LEN-1:0] ext_ctl,
output reg [`RD_SEL_LEN-1:0] rd_sel,
output reg [`CMP_CTL_LEN-1:0]cmp_ctl,
output reg [`PC_GEN_CTL_LEN-1:0]pc_gen_ctl,
output reg [`FSM_CTL_LEN-1:0]fsm_dly,
output reg [`MUXA_CTL_LEN-1:0]muxa_ctl,
output reg [`MUXB_CTL_LEN-1:0]muxb_ctl,
output reg [`ALU_FUNC_LEN-1:0]alu_func,
output reg [`DMEM_CTL_LEN-1:0]dmem_ctl,
output reg [`ALU_WE_LEN-1:0] alu_we,
output reg [`WB_MUX_CTL_LEN-1:0]wb_mux,
output reg [`WB_WE_LEN-1:0]wb_we
);
 
wire [5:0] inst_op,inst_func;
wire [4:0] inst_regimm;//,inst_rs,inst_rt,inst_rd,inst_sa;
wire [4:0] inst_cop0_func;//cop0's function code filed
wire [25:0] inst_cop0_code;//cop0's code field
 
assign inst_op = ins_i[31:26];
assign inst_func = ins_i[5:0];
assign inst_regimm = ins_i[20:16];
assign inst_cop0_func = ins_i[25:21];
assign inst_cop0_code = ins_i[25:0];
 
always @(*)
begin
case (inst_op)//synthesis parallel_case
'd0://special operation
begin
case (inst_func) //synthesis parallel_case
'd0://SLL rd,rt,sa
begin
//replaceID = `SLL ;
ext_ctl = `EXT_SA;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_EXT;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SLL;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLL ;
end
'd2://SRL rd,rt,sa
begin
//replaceID = `SRL ;
ext_ctl = `EXT_SA;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_EXT;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SRL;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SRL ;
end
'd3://SRA rd,rt,sa
begin
//replaceID = `SRA ;
ext_ctl = `EXT_SA;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_EXT;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SRA;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SRA ;
end
'd4://SLLV rd,rt,rs
begin
//replaceID = `SLLV ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SLLV ;
end
'd6://SRLV rd,rt,rs
begin
//replaceID = `SRLV ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SRLV ;
end
'd7://SRAV rd,rt,rs
begin
//replaceID = `SRAV ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SRAV ;
end
'd8://JR rs
begin
//replaceID = `JR ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_JR;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `JR ;
end
'd9://JALR jalr rs(rd=31) or jalr rd,rs
begin
//replaceID = `JALR ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `JALR ;
end
'd12://SYSCALL
begin
//replaceID = `SYSCALL ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SYSCALL ;
end
'd13://BREAK
begin
//replaceID = `BREAK ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `BREAK ;
end
'd16://MFHI rd
begin
//replaceID = `MFHI ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_MFHI;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `MFHI ;
end
'd17://MTHI rs
begin
//replaceID = `MTHI ;
ext_ctl = `EXT_NOP ;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_MTHI;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `MTHI ;
end
'd18://MFLO rd
begin
//replaceID = `MFLO ;
ext_ctl = `EXT_NOP ;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_MFLO;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `MFLO ;
end
'd19://MTLO rs
begin
//replaceID = `MTLO ;
ext_ctl = `EXT_NOP ;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_MFLO;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
 
//end of `MTLO ;
end
'd24://MULT rs,rt
begin
//replaceID = `MULT ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_MUL;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_MULT;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `MULT ;
end
'd25://MULTU rs,rt
begin
//replaceID = `MULTU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_MUL;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_MULTU;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `MULTU ;
end
'd26://DIV rs,rt
begin
//replaceID = `DIV ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_MUL;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_DIV;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `DIV ;
end
'd27://DIVU rs,rt
begin
//replaceID = `DIVU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_MUL;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_DIVU;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `DIVU ;
end
'd32://ADD rd,rs,rt
begin
//replaceID = `ADD ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_ADD;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ADD ;
end
'd33://ADDU rd,rs,rt
begin
//replaceID = `ADDU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_ADD;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ADDU ;
end
'd34://SUB rd,rs,rt
begin
//replaceID = `SUB ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SUB;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SUB ;
end
'd35://SUBU rd,rs,rt
begin
//replaceID = `SUBU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SUBU;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SUBU ;
end
'd36://AND rd,rs,rt
begin
//replaceID = `AND ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_AND;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `AND ;
end
'd37://OR rd,rs,rt
begin
//replaceID = `OR ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_OR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `OR ;
end
'd38://XOR rd,rs,rt
begin
//replaceID = `XOR ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_XOR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `XOR ;
end
'd39://NOR rd,rs,rt
begin
//replaceID = `NOR ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_NOR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `NOR ;
end
'd42://SLT rd,rs,rt
begin
//replaceID = `SLT ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SLT;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLT ;
end
'd43://SLTU rd,rs,rt
begin
//replaceID = `SLTU ;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_SLTU;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLTU ;
end
default:
begin
//replaceID = `INVALID ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `INVALID ;
end
endcase
end
'd1://regimm opreation
begin
case (inst_regimm) //synthesis parallel_case
'd0://BLTZ rs,offset(signed)
begin
//replaceID = `BLTZ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BLTZ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BLTZ ;
end
'd1://BGEZ rs,offset(signed)
begin
//replaceID = `BGEZ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BGEZ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BGEZ ;
end
'd16://BLTZAL rs,offset(signed)
begin
//replaceID = `BLTZAL ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `BLTZAL ;
end
'd17://BGEZAL rs,offset(signed)
begin
//replaceID = `BGEZAL ;
end
default:
begin
//replaceID = `INVALID ;
end
endcase
end
'd2://J imm26({pc[31:28],imm26,00})
begin
//replaceID = `J ;
ext_ctl = `EXT_J;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_J;
fsm_dly = `FSM_NOI;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `J ;
end
'd3://JAL imm26({pc[31:28],imm26,00})
begin
//replaceID = `JAL ;
ext_ctl = `EXT_J;
rd_sel = `RD_R31;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_J;
fsm_dly = `FSM_NOI;
muxa_ctl = `MUXA_PC;
muxb_ctl = `MUXB_RT;
alu_func = `ALU_PA;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `JAL ;
end
'd4://BEQ rs,rt,offset(signed)
begin
//replaceID = `BEQ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BEQ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BEQ ;
end
'd5://BNE rs,rt,offset(signed)
begin
//replaceID = `BNE ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BNE;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BNE ;
end
'd6://BLEZ rs,offset(signed)
begin
//replaceID = `BLEZ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BLEZ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BLEZ ;
end
'd7://BGTZ rs,offset(signed)
begin
//replaceID = `BGTZ ;
ext_ctl = `EXT_B;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_BGTZ;
pc_gen_ctl = `PC_BC;
fsm_dly = `FSM_CUR;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `BGTZ ;
end
'd8://ADDI rt,rs,imm16(singed)
begin
//replaceID = `ADDI ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ADDI ;
end
'd9://ADDIU rt,rs,imm16(singed)
begin
//replaceID = `ADDIU ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ADDIU ;
end
'd10://SLTI rt,rs,imm16(singed)
begin
//replaceID = `SLTI ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_SLT;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLTI ;
end
'd11://SLTIU rt,rs,imm16(singed)
begin
//replaceID = `SLTIU ;
ext_ctl = `EXT_UNSIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_SLTU;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `SLTIU ;
end
'd12://ANDI rt,rs,imm16(singed)
begin
//replaceID = `ANDI ;
ext_ctl = `EXT_UNSIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_AND;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `ANDI ;
end
'd13://ORI rt,rs,imm16(singed)
begin
//replaceID = `ORI ;
ext_ctl = `EXT_UNSIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_OR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `ORI ;
end
'd14://XORI rt,rs,imm16(singed)
begin
//replaceID = `XORI ;
ext_ctl = `EXT_UNSIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_XOR;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `EN;
wb_mux = `WB_ALU;
//end of `XORI ;
end
'd15://LUI rt,imm16
begin
//replaceID = `LUI ;
ext_ctl = `EXT_S2H;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_PB;
alu_we = `EN;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_ALU;
//end of `LUI ;
end
'd16://COP0 func
begin
case(inst_cop0_func) //synthesis parallel_case
'd0://mfc0 rt,rd // GPR[rd] = CPR[rt] //differ to mips32 definition
//read saved PC
begin
//replaceID = `MFC0;
ext_ctl = `EXT_NOP;
rd_sel = `RD_RD;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_SPC;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_PA;
alu_we = `EN;
dmem_ctl = `DMEM_LB;
wb_we = `DIS;
wb_mux = `WB_ALU;
end
 
'd4://mtc0 rt,rd // CPR[rd] = GPR[rt] //follow the mips32 definition
begin //return from interrupt
//replaceID = `MTC0;
ext_ctl = `EXT_NOP;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_SPC;
fsm_dly = `FSM_RET;
muxa_ctl = `MUXA_NOP;
muxb_ctl = `MUXB_NOP;
alu_func = `ALU_NOP;
alu_we = `DIS;
dmem_ctl = `DMEM_NOP;
wb_we = `DIS;
wb_mux = `WB_NOP;
end
default:
begin
 
end
endcase
end
'd32://LB rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LB ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LB;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LB ;
end
'd33://LH rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LH ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LH;
wb_we = `EN;
wb_mux = `WB_NOP;
//end of `LH ;
end
'd34://LWL rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LWL ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `LWL ;
end
'd35://LW rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LW ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LW;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LW ;
end
'd36://LBU rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LBU ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LBU;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LBU ;
end
'd37://LHU rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LHU ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_LHU;
wb_we = `EN;
wb_mux = `WB_MEM;
//end of `LHU ;
end
'd38://LWR rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LWR ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `LWR ;
end
'd40://SB rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SB ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_SB;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `SB ;
end
'd41://SH rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SH ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_SH;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `SH ;
end
'd42://SWL rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SWL ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SWL ;
end
'd43://SW rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SW ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
fsm_dly = `FSM_NOP;
muxa_ctl = `MUXA_RS;
muxb_ctl = `MUXB_EXT;
alu_func = `ALU_ADD;
alu_we = `DIS;
dmem_ctl = `DMEM_SW;
wb_we = `DIS;
wb_mux = `WB_NOP;
//end of `SW ;
end
'd46://SWR rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SWR ;
ext_ctl = `IGN;
rd_sel = `IGN;
cmp_ctl = `IGN;
pc_gen_ctl = `IGN;
fsm_dly = `IGN;
muxa_ctl = `IGN;
muxb_ctl = `IGN;
alu_func = `IGN;
alu_we = `IGN;
dmem_ctl = `IGN;
wb_we = `IGN;
wb_mux = `IGN;
//end of `SWR ;
end
default:
begin
//replaceID = `INVALID ;
end
endcase
end
endmodule
/ext.v
0,0 → 1,82
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
`define EXT_SIGN 1
`define EXT_UNSIGN 2
`define EXT_J 3
`define EXT_B 4
`define EXT_SA 5
`define EXT_S2H 6
`define EXT_NOP 0
 
module ext(
input [31:0] ins_i ,
output reg [31:0] res ,
input [2:0]ctl);
wire [25:0] instr25_0;
assign instr25_0 = ins_i[25:0] ;
 
wire[15:0] sign = {instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15]} ;
 
always @ (*)
case (ctl)
`EXT_SIGN :res ={sign,instr25_0[15:0]};//sign
`EXT_UNSIGN :res ={16'b0,instr25_0[15:0]};//zeroext
`EXT_J :res ={4'b0,instr25_0[25:0],2'b0};//jmp
`EXT_B :res ={sign[13:0],instr25_0[15:0],2'B0};//brach
`EXT_SA :res ={27'b0,instr25_0[10:6]} ;//sll,srl
`EXT_S2H :res ={instr25_0[15:0],16'B0};//shift to high
default: res=0;
endcase
endmodule
/muldiv.v
0,0 → 1,330
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
`define ALU_MFHI 6
`define ALU_MFLO 7
`define ALU_MULTTU 8
`define ALU_MULT 9
`define ALU_DIVU 10
`define ALU_DIV 11
`define ALU_MTHI 31
`define ALU_MTLO 30
 
 
 
module muldiv
(
ready,rst,op1,op2,
clk,dout,func
);
input clk,rst;
wire sign;
input [4:0] func ;
input [31:0] op2, op1;
output [31:0] dout;
output ready;
reg [31:0] quotient, quotient_temp;
reg [63:0] dividend_copy, divider_copy, diff;
reg negative_output;
 
reg [63:0] product, product_temp;
 
reg [31:0] multiplier_copy;
reg [63:0] multiplicand_copy;
 
reg [6:0] mul_bit,div_bit;
wire ready = ((mul_bit==0)&&(div_bit==0));
 
wire [31:0] dividend, divider;
 
wire [31:0] remainder;
wire [31:0] multiplier,multiplicand;
 
reg [31:0] hi,lo;
 
assign dout = (func==`ALU_MFHI)?hi:(func==`ALU_MFLO)?lo:0;
 
assign remainder = (!negative_output) ?
dividend_copy[31:0] :
~dividend_copy[31:0] + 1'b1;
 
assign multiplier=op2;
assign multiplicand=op1;
assign dividend=op1;
assign divider = op2;
assign sign = ((func==`ALU_MULT)||(func==`ALU_DIV));
 
always @( posedge clk or negedge rst)
if (~rst)
begin
mul_bit=0;
div_bit=0;
hi = 0;
lo = 0;
negative_output = 0;
end
else
begin
if((ready)&&((func==`ALU_MULT)||(func==`ALU_MULTTU)))
begin
mul_bit = 33;
product = 0;
product_temp = 0;
multiplicand_copy = (!sign || !multiplicand[31]) ?
{ 32'd0, multiplicand } :
{ 32'd0, ~multiplicand + 1'b1};
multiplier_copy = (!sign || !multiplier[31]) ?multiplier :~multiplier + 1'b1;
 
negative_output = sign &&
((multiplier[31] && !multiplicand[31])
||(!multiplier[31] && multiplicand[31]));
end
if ( mul_bit > 1 )
begin
 
if( multiplier_copy[0] == 1'b1 )
product_temp = product_temp +multiplicand_copy;
 
 
product = (!negative_output) ?
product_temp :
~product_temp + 1'b1;
 
multiplier_copy = multiplier_copy >> 1;
multiplicand_copy = multiplicand_copy << 1;
mul_bit = mul_bit - 1'b1;
end
else if (mul_bit == 1)
begin
hi = product[63:32];
lo = product[31:0];
mul_bit=0;
end
 
if((ready)&&((func==`ALU_DIV)||(func==`ALU_DIVU)))
begin
div_bit = 33;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[31]) ?
{32'd0,dividend} :
{32'd0,~dividend + 1'b1};
 
divider_copy = (!sign || !divider[31]) ?
{1'b0,divider,31'd0} :
{1'b0,~divider + 1'b1,31'd0};
 
negative_output = sign &&
((divider[31] && !dividend[31])
||(!divider[31] && dividend[31]));
end
else if (div_bit > 1)
begin
diff = dividend_copy - divider_copy;
quotient_temp = quotient_temp << 1;
if( !diff[63] )
begin
dividend_copy = diff;
quotient_temp[0] = 1'd1;
end
quotient = (!negative_output) ?quotient_temp :~quotient_temp + 1'b1;
divider_copy = divider_copy >> 1;
div_bit = div_bit - 1'b1;
end
else if (div_bit == 1)
begin
lo = quotient;
hi = remainder;
div_bit=0;
end
 
if (func==`ALU_MTHI)
hi=op1 ;
if (func==`ALU_MTLO)
lo=op1 ;
 
end
 
endmodule
 
 
 
/* I search the multiply and divide module in
http://www.answers.google.com/answers
and find the two below modules ,
what I have done is combining the two modules and making it work in the mips_core.
original link is (I've no idear whether the link now works or not)
http://www.answers.google.com/answers/threadview?id=109219
and the original modules is list as below.
 
module multiply(ready,product,multiplier,multiplicand,sign,clk);
 
input clk;
input sign;
input [31:0] multiplier, multiplicand;
output [63:0] product;
output ready;
 
reg [63:0] product, product_temp;
 
reg [31:0] multiplier_copy;
reg [63:0] multiplicand_copy;
reg negative_output;
reg [5:0] bit;
wire ready = !bit;
 
initial bit = 0;
initial negative_output = 0;
 
always @( posedge clk )
 
if( ready ) begin
 
bit = 6'd32;
product = 0;
product_temp = 0;
multiplicand_copy = (!sign || !multiplicand[31]) ?
{ 32'd0, multiplicand } :
{ 32'd0, ~multiplicand + 1'b1};
multiplier_copy = (!sign || !multiplier[31]) ?
multiplier :
~multiplier + 1'b1;
 
negative_output = sign &&
((multiplier[31] && !multiplicand[31])
||(!multiplier[31] && multiplicand[31]));
end
else if ( bit > 0 ) begin
 
if( multiplier_copy[0] == 1'b1 ) product_temp = product_temp +
multiplicand_copy;
 
product = (!negative_output) ?
product_temp :
~product_temp + 1'b1;
 
multiplier_copy = multiplier_copy >> 1;
multiplicand_copy = multiplicand_copy << 1;
bit = bit - 1'b1;
 
end
endmodule
 
 
module divide(ready,quotient,remainder,dividend,divider,sign,clk);
 
input clk;
input sign;
input [31:0] dividend, divider;
output [31:0] quotient, remainder;
output ready;
 
reg [31:0] quotient, quotient_temp;
reg [63:0] dividend_copy, divider_copy, diff;
reg negative_output;
wire [31:0] remainder = (!negative_output) ?
dividend_copy[31:0] :
~dividend_copy[31:0] + 1'b1;
 
reg [5:0] bit;
wire ready = !bit;
 
initial bit = 0;
initial negative_output = 0;
 
always @( posedge clk )
 
if( ready ) begin
 
bit = 6'd32;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[31]) ?
{32'd0,dividend} :
{32'd0,~dividend + 1'b1};
divider_copy = (!sign || !divider[31]) ?
{1'b0,divider,31'd0} :
{1'b0,~divider + 1'b1,31'd0};
 
negative_output = sign &&
((divider[31] && !dividend[31])
||(!divider[31] && dividend[31]));
end
else if ( bit > 0 ) begin
 
diff = dividend_copy - divider_copy;
 
quotient_temp = quotient_temp << 1;
 
if( !diff[63] ) begin
 
dividend_copy = diff;
quotient_temp[0] = 1'd1;
 
end
 
quotient = (!negative_output) ?
quotient_temp :
~quotient_temp + 1'b1;
 
divider_copy = divider_copy >> 1;
bit = bit - 1'b1;
 
end
endmodule
*/
/big_alu.v
0,0 → 1,105
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
module big_alu(clk,rst,a,b,c,ctl,busy);
input clk,rst ;
input [31:0] a,b ;
output [31:0] c ;
output busy ;
input [4:0]ctl ;
 
wire [31:0] mul_div_c;
wire [31:0] alu_c;
wire [31:0] shift_c;
 
assign c =mul_div_c | alu_c | shift_c ;//save the pc to register
 
/*
muldiv_ff muldiv_ff(
.clk_i(clk),
.rst_i(rst),//sys signal
.op_type(ctl),
.op1(a),
.op2(b),
// .busy_o(busy),
.res(mul_div_c)
);
*/
 
muldiv mips_muldiv(
.ready(busy),
.rst(rst),
.op1(a),
.op2(b),
.clk(clk),
.dout(mul_div_c),
.func(ctl)
);
 
alu mips_alu(
.a(a),
.b(b),
.alu_out(alu_c),
.alu_func(ctl)
 
);
 
shifter mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
 
endmodule
/forward.v
0,0 → 1,184
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
 
 
`define FW_ALU 3'b001
`define FW_MEM 3'b010
`define FW_NOP 3'b100
 
module fw_latch5(input clk,input[4:0]d,output reg [4:0]q);
always @ (posedge clk) q<=d;
endmodule
 
module fw_latch1(input clk,input d,output reg q);
always @ (posedge clk) q<=d;
endmodule
 
module forward_node (
input [4:0]rn,
input [4:0]alu_wr_rn,
input alu_we,
input [4:0]mem_wr_rn,
input mem_we,
output wire[2:0]mux_fw
);
assign mux_fw = ((alu_we)&&(alu_wr_rn==rn)&&(alu_wr_rn!=0))?`FW_ALU:
((mem_we)&&(mem_wr_rn==rn)&&(mem_wr_rn!=0))?`FW_MEM:
`FW_NOP;
endmodule
 
module forward2 (alu_we,clk,mem_We,fw_alu_rn,fw_mem_rn,rns_i,rnt_i,alu_rs_fw,alu_rt_fw,cmp_rs_fw,
cmp_rt_fw,dmem_fw) ;
 
input alu_we;
wire alu_we;
input clk;
wire clk;
input mem_We;
wire mem_We;
input [4:0] fw_alu_rn;
wire [4:0] fw_alu_rn;
input [4:0] fw_mem_rn;
wire [4:0] fw_mem_rn;
input [4:0] rns_i;
wire [4:0] rns_i;
input [4:0] rnt_i;
wire [4:0] rnt_i;
output [2:0] alu_rs_fw;
wire [2:0] alu_rs_fw;
output [2:0] alu_rt_fw;
wire [2:0] alu_rt_fw;
output [2:0] cmp_rs_fw;
wire [2:0] cmp_rs_fw;
output [2:0] cmp_rt_fw;
wire [2:0] cmp_rt_fw;
output [2:0] dmem_fw;
wire [2:0] dmem_fw;
 
wire [2:0] BUS1345;
wire [4:0] BUS82;
wire [4:0] BUS937;
 
forward_node fw_alu_rs
(
.alu_we(alu_we),
.alu_wr_rn(fw_alu_rn),
.mem_we(mem_We),
.mem_wr_rn(fw_mem_rn),
.mux_fw(alu_rs_fw),
.rn(BUS82)
);
 
 
 
forward_node fw_alu_rt
(
.alu_we(alu_we),
.alu_wr_rn(fw_alu_rn),
.mem_we(mem_We),
.mem_wr_rn(fw_mem_rn),
.mux_fw(BUS1345),
.rn(BUS937)
);
 
 
 
forward_node fw_cmp_rs
(
.alu_we(alu_we),
.alu_wr_rn(fw_alu_rn),
.mem_we(mem_We),
.mem_wr_rn(fw_mem_rn),
.mux_fw(cmp_rs_fw),
.rn(rns_i)
);
 
 
 
forward_node fw_cmp_rt
(
.alu_we(alu_we),
.alu_wr_rn(fw_alu_rn),
.mem_we(mem_We),
.mem_wr_rn(fw_mem_rn),
.mux_fw(cmp_rt_fw),
.rn(rnt_i)
);
 
 
 
fw_latch5 fw_reg_rns
(
.clk(clk),
.d(rns_i),
.q(BUS82)
);
 
 
 
fw_latch5 fw_reg_rnt
(
.clk(clk),
.d(rnt_i),
.q(BUS937)
);
 
 
assign alu_rt_fw[2:0] = BUS1345[2:0];
assign dmem_fw[2:0] = BUS1345[2:0];
 
endmodule
 
 
/shifter.v
0,0 → 1,183
//This file is based YACC ->shifter.v
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
`define ALU_SRL 1
`define ALU_SLL 2
`define ALU_SRA 4
 
module
shifter(
input [31:0] a,
output reg [31:0] shift_out,
input [4:0] shift_func,//connect to alu_func_ctl
input [31:0] shift_amount//connect to b
);
 
always @ (*)
begin
if( shift_func == `ALU_SLL )
begin
case ( shift_amount[4:0] )
5'b00000: shift_out=a;
5'b00001: shift_out={a[30:0],1'b0};
5'b00010: shift_out={a[29:0],2'b0};
5'b00011: shift_out={a[28:0],3'b0};
5'b00100: shift_out={a[27:0],4'b0};
5'b00101: shift_out={a[26:0],5'b0};
5'b00110: shift_out={a[25:0],6'b0};
5'b00111: shift_out={a[24:0],7'b0};
5'b01000: shift_out={a[23:0],8'b0};
5'b01001: shift_out={a[22:0],9'b0};
5'b01010: shift_out={a[21:0],10'b0};
5'b01011: shift_out={a[20:0],11'b0};
5'b01100: shift_out={a[19:0],12'b0};
5'b01101: shift_out={a[18:0],13'b0};
5'b01110: shift_out={a[17:0],14'b0};
5'b01111: shift_out={a[16:0],15'b0};
5'b10000: shift_out={a[15:0],16'b0};
5'b10001: shift_out={a[14:0],17'b0};
5'b10010: shift_out={a[13:0],18'b0};
5'b10011: shift_out={a[12:0],19'b0};
5'b10100: shift_out={a[11:0],20'b0};
5'b10101: shift_out={a[10:0],21'b0};
5'b10110: shift_out={a[9:0],22'b0};
5'b10111: shift_out={a[8:0],23'b0};
5'b11000: shift_out={a[7:0],24'b0};
5'b11001: shift_out={a[6:0],25'b0};
5'b11010: shift_out={a[5:0],26'b0};
5'b11011: shift_out={a[4:0],27'b0};
5'b11100: shift_out={a[3:0],28'b0};
5'b11101: shift_out={a[2:0],29'b0};
5'b11110: shift_out={a[1:0],30'b0};
5'b11111: shift_out={a[0],31'b0};
default shift_out ='d0;
endcase
end else if (shift_func== `ALU_SRL) begin
case (shift_amount[4:0])
5'b00000: shift_out=a;
5'b00001: shift_out={1'b0,a[31:1]};
5'b00010: shift_out={2'b0,a[31:2]};
5'b00011: shift_out={3'b0,a[31:3]};
5'b00100: shift_out={4'b0,a[31:4]};
5'b00101: shift_out={5'b0,a[31:5]};
5'b00110: shift_out={6'b0,a[31:6]};
5'b00111: shift_out={7'b0,a[31:7]};
5'b01000: shift_out={8'b0,a[31:8]};
5'b01001: shift_out={9'b0,a[31:9]};
5'b01010: shift_out={10'b0,a[31:10]};
5'b01011: shift_out={11'b0,a[31:11]};
5'b01100: shift_out={12'b0,a[31:12]};
5'b01101: shift_out={13'b0,a[31:13]};
5'b01110: shift_out={14'b0,a[31:14]};
5'b01111: shift_out={15'b0,a[31:15]};
5'b10000: shift_out={16'b0,a[31:16]};
5'b10001: shift_out={17'b0,a[31:17]};
5'b10010: shift_out={18'b0,a[31:18]};
5'b10011: shift_out={19'b0,a[31:19]};
5'b10100: shift_out={20'b0,a[31:20]};
5'b10101: shift_out={21'b0,a[31:21]};
5'b10110: shift_out={22'b0,a[31:22]};
5'b10111: shift_out={23'b0,a[31:23]};
5'b11000: shift_out={24'b0,a[31:24]};
5'b11001: shift_out={25'b0,a[31:25]};
5'b11010: shift_out={26'b0,a[31:26]};
5'b11011: shift_out={27'b0,a[31:27]};
5'b11100: shift_out={28'b0,a[31:28]};
5'b11101: shift_out={29'b0,a[31:29]};
5'b11110: shift_out={30'b0,a[31:30]};
5'b11111: shift_out={31'b0,a[31:31]};
default : shift_out = 0;
endcase
end else
if (shift_func==`ALU_SRA)
begin// SHIFT_RIGHT_SIGNED
case ( shift_amount[4:0])
5'b00000: shift_out=a;
5'b00001: shift_out={a[31],a[31:1]};
5'b00010: shift_out={{2{a[31]}},a[31:2]};
5'b00011: shift_out={{3{a[31]}},a[31:3]};
5'b00100: shift_out={{4{a[31]}},a[31:4]};
5'b00101: shift_out={{5{a[31]}},a[31:5]};
5'b00110: shift_out={{6{a[31]}},a[31:6]};
5'b00111: shift_out={{7{a[31]}},a[31:7]};
5'b01000: shift_out={{8{a[31]}},a[31:8]};
5'b01001: shift_out={{9{a[31]}},a[31:9]};
5'b01010: shift_out={{10{a[31]}},a[31:10]};
5'b01011: shift_out={{11{a[31]}},a[31:11]};
5'b01100: shift_out={{12{a[31]}},a[31:12]};
5'b01101: shift_out={{13{a[31]}},a[31:13]};
5'b01110: shift_out={{14{a[31]}},a[31:14]};
5'b01111: shift_out={{15{a[31]}},a[31:15]};
5'b10000: shift_out={{16{a[31]}},a[31:16]};
5'b10001: shift_out={{17{a[31]}},a[31:17]};
5'b10010: shift_out={{18{a[31]}},a[31:18]};
5'b10011: shift_out={{19{a[31]}},a[31:19]};
5'b10100: shift_out={{20{a[31]}},a[31:20]};
5'b10101: shift_out={{21{a[31]}},a[31:21]};
5'b10110: shift_out={{22{a[31]}},a[31:22]};
5'b10111: shift_out={{23{a[31]}},a[31:23]};
5'b11000: shift_out={{24{a[31]}},a[31:24]};
5'b11001: shift_out={{25{a[31]}},a[31:25]};
5'b11010: shift_out={{26{a[31]}},a[31:26]};
5'b11011: shift_out={{27{a[31]}},a[31:27]};
5'b11100: shift_out={{28{a[31]}},a[31:28]};
5'b11101: shift_out={{29{a[31]}},a[31:29]};
5'b11110: shift_out={{30{a[31]}},a[31:30]};
5'b11111: shift_out={{31{a[31]}},a[31:31]};
default shift_out='d0;
endcase
end
else shift_out='d0;
end
endmodule
/cmpare.v
0,0 → 1,80
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
`define CMP_BEQ 1
`define CMP_BNE 2
`define CMP_BLEZ 3
`define CMP_BGEZ 4
`define CMP_BGTZ 5
`define CMP_BLTZ 6
`define CMP_NOP 0
 
module compare (
input [31:0] s,
input [31:0] t,
input [2:0]ctl,
output reg res
);
reg [32:0]sum;
always @ (*)
case (ctl)
`CMP_BEQ: res = s==t;
`CMP_BNE: res = s!=t;
`CMP_BLTZ: res = s[31];
`CMP_BGTZ: res = ~s[31] && (|s[30:0]);
`CMP_BLEZ: res = s[31] |(~|s);
`CMP_BGEZ: res = ~s[31];
default res=1'B0;
endcase
endmodule
/EXEC_stage.v
0,0 → 1,186
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
 
module exec_stage1
(
clk,rst,spc_cls_i,alu_func,
dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
dmem_data_ur_o,zz_spc_o
);
 
input clk;
wire clk;
input rst;
wire rst;
input spc_cls_i;
wire spc_cls_i;
input [4:0] alu_func;
wire [4:0] alu_func;
input [2:0] dmem_fw_ctl;
wire [2:0] dmem_fw_ctl;
input [31:0] ext_i;
wire [31:0] ext_i;
input [31:0] fw_alu;
wire [31:0] fw_alu;
input [31:0] fw_dmem;
wire [31:0] fw_dmem;
input [1:0] muxa_ctl_i;
wire [1:0] muxa_ctl_i;
input [2:0] muxa_fw_ctl;
wire [2:0] muxa_fw_ctl;
input [1:0] muxb_ctl_i;
wire [1:0] muxb_ctl_i;
input [2:0] muxb_fw_ctl;
wire [2:0] muxb_fw_ctl;
input [31:0] pc_i;
wire [31:0] pc_i;
input [31:0] rs_i;
wire [31:0] rs_i;
input [31:0] rt_i;
wire [31:0] rt_i;
output [31:0] alu_ur_o;
wire [31:0] alu_ur_o;
output [31:0] dmem_data_ur_o;
wire [31:0] dmem_data_ur_o;
output [31:0] zz_spc_o;
wire [31:0] zz_spc_o;
 
wire [31:0] BUS2332;
wire [31:0] BUS2446;
wire [31:0] BUS468;
wire [31:0] BUS476;
 
 
big_alu MIPS_alu
(
.a(BUS476),
.b(BUS468),
.c(alu_ur_o),
.clk(clk),
.ctl(alu_func),
.rst(rst)
);
 
 
 
add32 add4
(
.d_i(pc_i),
.d_o(BUS2446)
);
 
 
 
dmem_data_mux dmem_data_mux
(
.data_o(dmem_data_ur_o),
.fw_alu(fw_alu),
.fw_ctl(dmem_fw_ctl),
.fw_dmem(fw_dmem),
.rt(rt_i)
);
 
 
 
alu_muxa i_alu_muxa
(
.a_o(BUS476),
.ctl(muxa_ctl_i),
.ext(ext_i),
.fw_alu(fw_alu),
.fw_ctl(muxa_fw_ctl),
.fw_mem(fw_dmem),
.pc(BUS2332),
.rs(rs_i),
.spc(zz_spc_o)
);
 
 
 
alu_muxb i_alu_muxb
(
.b_o(BUS468),
.ctl(muxb_ctl_i),
.ext(ext_i),
.fw_alu(fw_alu),
.fw_ctl(muxb_fw_ctl),
.fw_mem(fw_dmem),
.rt(rt_i)
);
 
 
 
r32_reg pc_nxt
(
.clk(clk),
.r32_i(BUS2446),
.r32_o(BUS2332)
);
 
 
 
r32_reg_cls spc
(
.clk(clk),
.cls(spc_cls_i),
.r32_i(pc_i),
.r32_o(zz_spc_o)
);
 
 
 
endmodule
/alu_mux.v
0,0 → 1,111
/////////////////////////////////////////////////////////////////////
//// Author: Liwei ////
//// ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Liwei ////
//// mcupro@yahoo.com.hk ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2007.8.1 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
 
`define MUXA_PC 1
`define MUXA_RS 2
`define MUXA_EXT 3
`define MUXA_SPC 0
`define MUXA_NOP 0
 
`define MUXB_RT 1
`define MUXB_EXT 2
`define MUXB_NOP 0
 
 
`define FW_ALU 3'b001
`define FW_MEM 3'b010
`define FW_NOP 3'b100
 
 
module alu_muxa(
input [31:0]spc,
input [31:0]pc,
input [31:0]fw_mem,
input [31:0]rs,
input [31:0]fw_alu,
input [31:0]ext,
input [1:0] ctl,
input [2:0] fw_ctl,
output reg [31:0]a_o
);
 
always @(*)
begin
case (ctl)
`MUXA_RS: a_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rs;
`MUXA_PC: a_o = pc;
`MUXA_EXT: a_o = ext;
`MUXA_SPC: a_o = spc;
default : a_o = rs;
endcase
end
endmodule
 
module alu_muxb(
input [31:0] rt,
input [31:0]fw_alu,
input [31:0]fw_mem,
input [31:0]ext ,
input [1:0]ctl ,
input [2:0]fw_ctl ,
output reg [31:0] b_o
);
always@(*)
case (ctl)
`MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
`MUXB_EXT : b_o=ext;
default b_o=rt;
endcase
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.