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https://opencores.org/ocsvn/mips_16/mips_16/trunk
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Rev 1 → Rev 2
/trunk/bench/EX_stage/EX_stage_tb_0.do
0,0 → 1,11
quit -sim |
vlib work |
vlog +incdir+../rtl ../rtl/EX_stage.v |
vlog +incdir+../rtl ../bench/EX_stage/EX_stage_tb_0.v |
|
vsim -t 1ps -novopt -lib work EX_stage_tb_0_v |
view wave |
add wave * |
view structure |
view signals |
run -all |
/trunk/bench/EX_stage/alu_tb_0.do
0,0 → 1,14
quit -sim |
vlib work |
vlog +incdir+../rtl ../rtl/alu.v |
vlog +incdir+../rtl ../bench/EX_stage/alu_tb_0.v |
|
vsim -t 1ps -novopt -lib work alu_tb_0_v |
view wave |
add wave -radix unsigned /alu_tb_0_v/cmd |
add wave -radix decimal /alu_tb_0_v/a |
add wave -radix decimal /alu_tb_0_v/b |
add wave -radix decimal /alu_tb_0_v/r |
view structure |
view signals |
run -all |
/trunk/bench/EX_stage/EX_stage_tb_0.v
0,0 → 1,82
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 20:27:50 02/08/2012 |
// Design Name: EX_stage |
// Module Name: F:/Projects/My_MIPS/mips_16/bench/EX_stage/EX_stage_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: EX_stage |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns/1ps |
`include "mips_16_defs.v" |
module EX_stage_tb_0_v; |
|
// Inputs |
reg clk; |
reg rst; |
reg [56:0] pipeline_reg_in; |
|
// Outputs |
wire [37:0] pipeline_reg_out; |
wire [2:0] ex_op_dest; |
|
// Instantiate the Unit Under Test (UUT) |
EX_stage uut ( |
.clk(clk), |
.rst(rst), |
.pipeline_reg_in(pipeline_reg_in), |
.pipeline_reg_out(pipeline_reg_out), |
.ex_op_dest(ex_op_dest) |
); |
|
parameter CLK_PERIOD = 10; |
always #(CLK_PERIOD /2) |
clk =~clk; |
|
initial begin |
// Initialize Inputs |
clk = 0; |
rst = 0; |
pipeline_reg_in = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
// Add stimulus here |
#(CLK_PERIOD/2) |
#1 |
#(CLK_PERIOD*1) rst = 1; |
#(CLK_PERIOD*1) rst = 0; |
|
#(CLK_PERIOD*10) |
pipeline_reg_in = {`ALU_ADD, 16'd12345, 16'd12345, 22'hcad28}; |
|
#(CLK_PERIOD*0.5) |
if (ex_op_dest == 3'b100) |
$display("ok1 "); |
else |
$display("error1, %x ", ex_op_dest); |
|
#(CLK_PERIOD*0.5) |
if( pipeline_reg_out == {16'd24690, 22'hcad28} ) |
$display("ok2 "); |
else |
$display("error2, %x ", pipeline_reg_out); |
|
#(CLK_PERIOD*10) |
$stop; |
end |
|
endmodule |
|
/trunk/bench/EX_stage/alu_tb_0.v
0,0 → 1,225
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 18:23:03 02/08/2012 |
// Design Name: alu |
// Module Name: F:/Projects/My_MIPS/mips_16/bench/EX_stage/alu_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: alu |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "mips_16_defs.v" |
|
module alu_tb_0_v; |
|
// Inputs |
reg [15:0] a; |
reg [15:0] b; |
reg [2:0] cmd; |
|
// Outputs |
wire [15:0] r; |
reg [15:0] rand; |
integer i; |
|
// Instantiate the Unit Under Test (UUT) |
alu uut ( |
.a(a), |
.b(b), |
.cmd(cmd), |
.r(r) |
); |
|
initial begin |
// Initialize Inputs |
a = 0; |
b = 0; |
cmd = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
i=0; |
while(i<10) begin |
test_NC; |
test_ADD; |
test_SUB; |
test_AND; |
test_OR; |
test_XOR; |
test_SL; |
test_SR; |
test_SRU; |
i = i+1; |
end |
$stop; |
$finish; |
end |
|
task test_NC; |
begin |
$write(" ALU_NC \t"); |
a = $random % 32768; |
b = $random % 32768; |
cmd = `ALU_NC; |
#10 |
// if(r == 16'bxxxxxxxxxxxxxxxx) |
$write("ok "); |
// else |
// $write("error @ %t , get %d, expect %d", $time, r, a b); |
$write("\n"); |
end |
endtask |
|
task test_ADD; |
begin |
$write(" ALU_ADD \t"); |
a = $random % 32768; |
b = $random % 32768; |
cmd = `ALU_ADD; |
#10 |
if(r == a + b) |
$write("ok "); |
else |
$write("error @ %t , get %d, expect %d", $time, r, a+b); |
$write("\n"); |
end |
endtask |
|
task test_SUB; |
begin |
$write(" ALU_SUB \t"); |
a = $random % 32768; |
b = $random % 32768; |
cmd = `ALU_SUB; |
#10 |
if(r == a - b) |
$write("ok "); |
else |
$write("error @ %t , get %d, expect %d", $time, r, a-b); |
$write("\n"); |
end |
endtask |
|
task test_AND; |
begin |
$write(" ALU_AND \t"); |
// a = $random % 32768; |
// b = $random % 32768; |
a = 16'b0101010101010101; |
b = 16'b1010101001010101; |
cmd = `ALU_AND; |
#10 |
if(r == 16'b0000000001010101) |
// if(r == 16'd85) |
$write("ok "); |
else |
$write("error @ %t , get %d, expect %d", $time, r, a&b); |
$write("\n"); |
end |
endtask |
|
task test_OR; |
begin |
$write(" ALU_OR \t"); |
a = $random % 32768; |
b = $random % 32768; |
cmd = `ALU_OR; |
#10 |
if(r == a | b) |
$write("ok "); |
else |
$write("error @ %t , get %d, expect %d", $time, r, a|b); |
$write("\n"); |
end |
endtask |
|
task test_XOR; |
begin |
$write(" ALU_XOR \t"); |
a = $random % 32768; |
b = $random % 32768; |
cmd = `ALU_XOR; |
#10 |
if(r == a ^ b) |
$write("ok "); |
else |
$write("error @ %t , get %d, expect %d", $time, r, a^b); |
$write("\n"); |
end |
endtask |
|
task test_SL; |
begin |
$write(" ALU_SL \t"); |
a = $random % 32768; |
b = {$random} % 16; |
cmd = `ALU_SL; |
#10 |
if(r == a << b) |
$write("ok "); |
else |
$write("error @ %t , get %d, expect %d", $time, r, a<<b); |
$write("\n"); |
end |
endtask |
|
// task test_SR; |
// begin |
// $write(" ALU_SR \t"); |
// a = $random % 32768; |
// b = {$random} % 16; |
// cmd = `ALU_SR; |
// #10 |
// if(r == a / 2**b ) |
// $write("ok "); |
// else |
// $write("error @ %t , get %d, expect %d", $time, r, (a/(2**b))); |
// $write("\n"); |
// end |
// endtask |
task test_SR; |
begin |
$write(" ALU_SR \t"); |
a = 16'b1111000011110000; |
b = 7; |
cmd = `ALU_SR; |
#10 |
if(r == 16'b1111111111100001 ) |
$write("ok "); |
else |
$write("error @ %t , get %d, expect %d", $time, r, 16'b1111111111100001); |
$write("\n"); |
end |
endtask |
|
task test_SRU; |
begin |
$write(" ALU_SRU \t"); |
a = $random % 32768; |
b = {$random} % 16; |
cmd = `ALU_SRU; |
#10 |
if(r == a >> b ) |
$write("ok "); |
else |
$write("error @ %t , get %d, expect %d", $time, r, a >> b); |
$write("\n"); |
end |
endtask |
|
endmodule |
|
/trunk/bench/ID_stage/ID_stage_tb_0.do
0,0 → 1,11
vlib work |
vlog +incdir+../rtl ../rtl/ID_stage.v |
vlog +incdir+../rtl ../bench/ID_stage/ID_stage_tb_0.v |
|
vsim -t 1ps -novopt -lib work ID_stage_tb_0_v |
view wave |
add wave * |
add wave /ID_stage_tb_0_v/uut/instruction_reg |
view structure |
view signals |
run -all |
/trunk/bench/ID_stage/ID_stage_tb_0.v
0,0 → 1,251
/*************************************************** |
* Module: ID_stage_tb_0_v |
* Project: mips_16 |
* Author: fzy |
* Description: |
* |
* |
* Revise history: |
* |
***************************************************/ |
`timescale 1ns/1ps |
`include "mips_16_defs.v" |
|
module ID_stage_tb_0_v; |
reg clk; |
reg rst; |
reg instruction_decode_en; |
|
// to EX_stage |
wire [56:0] pipeline_reg_out; // [56:22],35bits: ex_alu_cmd[2:0], ex_alu_src1[15:0], ex_alu_src2[15:0] |
// [21:5],17bits: mem_write_en, mem_write_data[15:0] |
// [4:0],5bits: write_back_en, write_back_dest[2:0], write_back_result_mux, |
|
// to IF_stage |
reg [15:0] instruction; |
wire [5:0] branch_offset_imm; |
wire branch_taken; |
|
// to register file |
wire [2:0] reg_read_addr_1; // register file read port 1 address |
wire [2:0] reg_read_addr_2; // register file read port 2 address |
reg [15:0] reg_read_data_1; // register file read port 1 data |
reg [15:0] reg_read_data_2; // register file read port 2 data |
|
// to hazard detection unit |
wire [2:0] decoding_op_src1; //source_1 register number |
wire [2:0] decoding_op_src2; //source_2 register number |
|
|
|
|
parameter CLK_PERIOD = 10; |
integer test; |
|
ID_stage uut( |
.clk(clk), |
.rst(rst), |
.instruction_decode_en(instruction_decode_en), |
.pipeline_reg_out(pipeline_reg_out), |
.instruction(instruction), |
.branch_offset_imm(branch_offset_imm), |
.branch_taken(branch_taken), |
.reg_read_addr_1(reg_read_addr_1), // |
.reg_read_addr_2(reg_read_addr_2), // |
.reg_read_data_1(reg_read_data_1), // |
.reg_read_data_2(reg_read_data_2), // |
.decoding_op_src1(decoding_op_src1), |
.decoding_op_src2(decoding_op_src2) |
); |
|
always #(CLK_PERIOD /2) |
clk =~clk; |
|
initial begin |
// Initialize Inputs |
clk = 0; |
rst = 0; |
instruction_decode_en = 0; |
instruction = 0; |
reg_read_data_1 = 0; |
reg_read_data_2 = 0; |
test = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
display_debug_message; |
#(CLK_PERIOD/2) |
test1; |
|
$stop; |
|
$finish; |
|
end |
|
|
task display_debug_message; |
begin |
$display("\n***************************"); |
$display("ID_stage test"); |
$display("***************************\n"); |
end |
endtask |
|
task sys_reset; |
begin |
rst = 0; |
#(CLK_PERIOD*1) rst = 1; |
#(CLK_PERIOD*1) rst = 0; |
end |
endtask |
|
task test1; |
begin |
|
sys_reset; |
#1 |
instruction_decode_en = 1; |
#(CLK_PERIOD) test = 1; |
|
#(CLK_PERIOD*100) test = 0; |
sys_reset; |
|
end |
endtask |
|
// register file behavior |
always@(*) begin |
reg_read_data_1 = 0; |
reg_read_data_2 = 0; |
|
if(reg_read_addr_1 == 1) |
reg_read_data_1 = 31; |
if(reg_read_addr_1 == 5) |
reg_read_data_1 = 7; |
if(reg_read_addr_1 == 7) |
reg_read_data_1 = 0;// ==0, BZ will taken |
// reg_read_data_1 = 3; // !=0, BZ will not taken |
|
if(reg_read_addr_2 == 2) |
reg_read_data_2 = 28; |
if(reg_read_addr_2 == 4) |
reg_read_data_2 = 16'h9a3c; |
if(reg_read_addr_2 == 6) |
reg_read_data_2 = 16'hc32e; |
end |
|
always @ (test) begin |
case(test) |
1: begin |
$display("running test1\n"); |
$display("check datapath control logic S1~S6 correct or not\n"); |
//while(test == 1) begin |
// NOP |
#(CLK_PERIOD) instruction = { `OP_NOP, 12'b0}; |
$display("OP_NOP\n"); |
|
// ADD |
#(CLK_PERIOD) instruction = { `OP_ADD, 3'd0, 3'd1, 3'd2, 3'd0}; |
$display("OP_ADD\n"); |
#(CLK_PERIOD) |
if( |
uut.write_back_en != 1 || // S3 |
uut.write_back_result_mux != 0 || // S1 |
uut.ex_alu_cmd != `ALU_ADD || // S2 |
uut.alu_src2_mux != 0 || // S4 |
uut.decoding_op_is_branch != 0 || // S5 |
uut.decoding_op_is_store != 0 || // S6 |
decoding_op_src1 != 1 || |
decoding_op_src2 != 2 || |
branch_taken != 0 || |
branch_offset_imm != 6'b010000|| |
reg_read_addr_1 != 1 || |
reg_read_addr_2 != 2 |
) |
$display("error1\n"); |
#(CLK_PERIOD) |
if( |
pipeline_reg_out[56:54] != `ALU_ADD || // S2 ex_alu_cmd |
pipeline_reg_out[53:38] != 31 || // alu src1 |
pipeline_reg_out[37:22] != 28 || // alu src2 |
pipeline_reg_out[21] != 0 || // mem_write_en |
pipeline_reg_out[20:5] != 28 || // mem_write_data |
pipeline_reg_out[4] != 1 || // S3 write_back_en |
pipeline_reg_out[3:1] != 0 || // write_back_dest |
pipeline_reg_out[0] != 0 // S1 write_back_result_mux |
|
) |
$display("error2\n"); |
|
// ST |
#(CLK_PERIOD) instruction = { `OP_ST, 3'd4, 3'd5, 6'd31}; |
$display("OP_ST\n"); |
#(CLK_PERIOD) |
if( |
uut.write_back_en != 0 || // S3 |
uut.write_back_result_mux != 1'bx || // S1 |
uut.ex_alu_cmd != `ALU_ADD || // S2 |
uut.alu_src2_mux != 1 || // S4 |
uut.decoding_op_is_branch != 0 || // S5 |
uut.decoding_op_is_store != 1 || // S6 |
decoding_op_src1 != 5 || |
decoding_op_src2 != 4 || |
branch_taken != 0 || |
branch_offset_imm != 6'd31 || |
reg_read_addr_1 != 5 || |
reg_read_addr_2 != 4 |
) |
$display("error1\n"); |
#(CLK_PERIOD) |
if( |
pipeline_reg_out[53:38] != 7 || // ex_alu_src1 |
pipeline_reg_out[37:22] != 31 || // ex_alu_src2 |
pipeline_reg_out[21] != 1 || // mem_write_en |
pipeline_reg_out[20:5] != 16'h9a3c || // mem_write_data |
pipeline_reg_out[3:1] != 4 // write_back_dest |
) |
$display("error2\n"); |
|
// BZ |
#(CLK_PERIOD) instruction = { `OP_BZ, 3'd0, 3'd7, -6'd10}; |
$display("OP_BZ\n"); |
#(CLK_PERIOD) |
if( |
uut.write_back_en != 0 || // S3 |
uut.write_back_result_mux != 1'bx || // S1 |
uut.ex_alu_cmd != `ALU_NC || // S2 |
uut.alu_src2_mux != 1 || // S4 |
uut.decoding_op_is_branch != 1 || // S5 |
uut.decoding_op_is_store != 0 || // S6 |
decoding_op_src1 != 7 || |
decoding_op_src2 != 0 || |
branch_taken != 1 || |
// branch_taken != 0 || |
branch_offset_imm != -6'd10 || |
reg_read_addr_1 != 7 || |
reg_read_addr_2 != 3'b110 |
) |
$display("error1\n"); |
#(CLK_PERIOD) |
if( |
pipeline_reg_out[53:38] != 0 || // ex_alu_src1 |
// pipeline_reg_out[53:38] != 3 || // ex_alu_src1 |
pipeline_reg_out[37:22] != -6'd10 || // ex_alu_src2 |
pipeline_reg_out[21] != 0 || // mem_write_en |
pipeline_reg_out[20:5] != 16'hc32e || // mem_write_data |
pipeline_reg_out[3:1] != 0 // write_back_dest |
) |
$display("error2\n"); |
|
//end |
end |
|
|
|
endcase |
end |
|
|
|
endmodule |
/trunk/bench/IF_stage/IF_stage_tb_0.do
0,0 → 1,14
vlib work |
##vlog +incdir+F:/Projects/My_MIPS/mips_16/rtl ../rtl/*.v |
vlog +incdir+../rtl ../rtl/IF_stage.v |
vlog +incdir+../rtl ../rtl/instruction_mem.v |
vlog +incdir+../rtl ../bench/IF_stage/IF_stage_tb_0.v |
|
vsim -t 1ps -novopt -L xilinxcorelib_ver -L unisims_ver -lib work IF_stage_tb_0_v |
view wave |
add wave * |
## add wave /glbl/GSR |
## do {dds_tb_v.udo} |
view structure |
view signals |
run -all |
/trunk/bench/IF_stage/test1.prog
0,0 → 1,50
|
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
a |
b |
c |
d |
e |
f |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
1a |
1b |
1c |
1d |
1e |
1f |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
2a |
2b |
2c |
2d |
2e |
2f |
30 |
31 |
/trunk/bench/IF_stage/IF_stage_tb_0.v
0,0 → 1,168
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 01:51:48 02/06/2012 |
// Design Name: IF_stage |
// Module Name: F:/Projects/My_MIPS/mips_16/sim/IF_stage/IF_stage_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: IF_stage |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns/1ps |
`include "mips_16_defs.v" |
|
module IF_stage_tb_0_v; |
|
// Inputs |
reg clk; |
reg rst; |
reg instruction_fetch_en; |
reg [5:0] branch_offset_imm; |
reg branch_taken; |
|
// Outputs |
wire [`PC_WIDTH-1:0] pc; |
wire [15:0] instruction; |
|
parameter CLK_PERIOD = 10; |
integer test; |
|
// Instantiate the Unit Under Test (UUT) |
IF_stage uut ( |
.clk(clk), |
.rst(rst), |
.instruction_fetch_en(instruction_fetch_en), |
.branch_offset_imm(branch_offset_imm), |
.branch_taken(branch_taken), |
.pc(pc), |
.instruction(instruction) |
); |
|
always #(CLK_PERIOD /2) |
clk =~clk; |
|
initial begin |
// Initialize Inputs |
clk = 0; |
rst = 0; |
instruction_fetch_en = 0; |
branch_offset_imm = 0; |
branch_taken = 0; |
test = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
display_debug_message; |
#(CLK_PERIOD/2) |
test1; |
test2; |
$stop; |
|
$finish; |
|
end |
|
task display_debug_message; |
begin |
$display("\n***************************"); |
$display("IF_stage test"); |
$display("***************************\n"); |
end |
endtask |
|
task sys_reset; |
begin |
rst = 0; |
#(CLK_PERIOD*1) rst = 1; |
#(CLK_PERIOD*1) rst = 0; |
end |
endtask |
|
task test1; |
begin |
$readmemh("../bench/IF_stage/test1.prog",uut.imem.rom); |
$display("rom load successfully\n"); |
|
sys_reset; |
#1 |
instruction_fetch_en = 1; |
#(CLK_PERIOD) test = 1; |
|
#(CLK_PERIOD*5) |
sys_reset; |
|
#(CLK_PERIOD*100) test = 0; |
sys_reset; |
|
end |
endtask |
|
task test2; |
begin |
$readmemh("../bench/IF_stage/test1.prog",uut.imem.rom); |
$display("rom load successfully\n"); |
|
sys_reset; |
instruction_fetch_en = 1; |
#1 |
#(CLK_PERIOD) test = 2; |
|
#(CLK_PERIOD*20) |
instruction_fetch_en = 0; |
branch_taken = 1; |
branch_offset_imm = -30; |
|
#(CLK_PERIOD*3) |
instruction_fetch_en = 1; |
#(CLK_PERIOD*1) |
branch_taken = 0; |
branch_offset_imm = 0; |
|
#(CLK_PERIOD*100) test = 0; |
sys_reset; |
|
end |
endtask |
|
always @ (test) begin |
case(test) |
1: begin |
$display("running test1\n"); |
while(test == 1) begin |
@(uut.pc) |
$display("current pc : %d",uut.pc); |
if(uut.pc == 40) begin |
#1 |
branch_taken = 1; |
branch_offset_imm = -30; |
#(CLK_PERIOD*1) |
branch_taken =0; |
branch_offset_imm = 0; |
end |
end |
end |
|
2: begin |
$display("running test2\n"); |
while(test == 2) begin |
@(uut.pc) |
$display("current pc : %d",uut.pc); |
end |
end |
|
endcase |
end |
|
endmodule |
|
/trunk/bench/MEM_stage/data_mem_tb_0.v
0,0 → 1,128
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 13:50:26 02/09/2012 |
// Design Name: data_mem |
// Module Name: F:/Projects/My_MIPS/mips_16/bench/MEM_stage/data_mem_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: data_mem |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns/1ps |
`include "mips_16_defs.v" |
module data_mem_tb_0_v; |
|
// Inputs |
reg clk; |
reg [15:0] mem_access_addr; |
reg [15:0] mem_write_data; |
reg mem_write_en; |
|
// Outputs |
wire [15:0] mem_read_data; |
|
parameter CLK_PERIOD = 10; |
always #(CLK_PERIOD /2) |
clk =~clk; |
reg [15:0] rand; |
integer i; |
|
// Instantiate the Unit Under Test (UUT) |
data_mem uut ( |
.clk(clk), |
.mem_access_addr(mem_access_addr), |
.mem_write_data(mem_write_data), |
.mem_write_en(mem_write_en), |
.mem_read_data(mem_read_data) |
); |
|
initial begin |
// Initialize Inputs |
clk = 0; |
mem_access_addr = 0; |
mem_write_data = 0; |
mem_write_en = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
#(CLK_PERIOD/2) |
#1 |
|
|
write_mem; |
read_mem; |
//read_write_mem; |
$stop; |
end |
|
reg [`DATA_MEM_ADDR_WIDTH-1 : 0] addr_temp [7:0]; |
reg [15 : 0] data_temp [7:0]; |
task write_mem; |
begin |
$display("write_memory. random_addr, random data:"); |
|
i=0; |
while(i<8) begin |
addr_temp[i] = {$random} % (2**`DATA_MEM_ADDR_WIDTH); |
data_temp[i] = $random % 32768; |
i = i+1; |
end |
$display("------------------------------"); |
$display("wrote address:"); |
i=0; |
while(i<8) begin |
$write("%d\t", addr_temp[i]); |
i = i+1; |
end |
|
$display("\n------------------------------"); |
$display("wrote data:"); |
i=0; |
while(i<8) begin |
mem_write_en = 1; |
mem_access_addr = addr_temp[i]; |
mem_write_data = data_temp[i]; |
#(CLK_PERIOD*1) |
$write("%d\t", uut.ram[mem_access_addr]); |
mem_write_en = 0; |
i = i+1; |
end |
$display("\n------------------------------"); |
end |
endtask |
|
integer err_num = 0; |
task read_mem; |
begin |
$display("read data from addresses above and check"); |
i=0; |
while(i<8) begin |
mem_access_addr = addr_temp[i]; |
#(CLK_PERIOD*0.5) |
if( mem_read_data != data_temp[i]) begin |
$display("error @ %d, expect %d, read %d", |
mem_access_addr, data_temp[i], mem_read_data); |
err_num = err_num +1; |
end |
#(CLK_PERIOD*0.5) |
i = i+1; |
end |
$display("check over, %d errors", err_num); |
$display("\n------------------------------"); |
end |
endtask |
endmodule |
|
/trunk/bench/MEM_stage/MEM_stage_tb_0.do
0,0 → 1,11
quit -sim |
vlib work |
vlog +incdir+../rtl ../rtl/MEM_stage.v |
vlog +incdir+../rtl ../bench/MEM_stage/MEM_stage_tb_0.v |
|
vsim -t 1ps -novopt -lib work MEM_stage_tb_0_v |
view wave |
add wave * |
view structure |
view signals |
run -all |
/trunk/bench/MEM_stage/MEM_stage_tb_0.v
0,0 → 1,86
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 15:00:04 02/09/2012 |
// Design Name: MEM_stage |
// Module Name: F:/Projects/My_MIPS/mips_16/backend/Xilinx/mips_16/MEM_stage_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: MEM_stage |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns/1ps |
`include "mips_16_defs.v" |
|
module MEM_stage_tb_0_v; |
|
// Inputs |
reg clk; |
reg rst; |
reg [37:0] pipeline_reg_in; |
|
// Outputs |
wire [36:0] pipeline_reg_out; |
wire [2:0] mem_op_dest; |
|
parameter CLK_PERIOD = 10; |
always #(CLK_PERIOD /2) |
clk =~clk; |
|
// Instantiate the Unit Under Test (UUT) |
MEM_stage uut ( |
.clk(clk), |
.rst(rst), |
.pipeline_reg_in(pipeline_reg_in), |
.pipeline_reg_out(pipeline_reg_out), |
.mem_op_dest(mem_op_dest) |
); |
|
initial begin |
// Initialize Inputs |
clk = 0; |
rst = 0; |
pipeline_reg_in = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
#(CLK_PERIOD/2) |
#1 |
#(CLK_PERIOD*1) rst = 1; |
#(CLK_PERIOD*1) rst = 0; |
|
#(CLK_PERIOD*10) |
|
uut.dmem.ram[128] = 16'h69fe; |
pipeline_reg_in = {16'd128, 1'b1, 16'h69fe, 5'b10101}; |
|
#(CLK_PERIOD*0.5) |
if (mem_op_dest == 3'b010) |
$display("ok1 "); |
else |
$display("error1, %x ", mem_op_dest); |
|
#(CLK_PERIOD*0.5) |
if( pipeline_reg_out == {16'd128, 16'h69fe, 5'b10101} ) |
$display("ok2 "); |
else |
$display("error2, %x ", pipeline_reg_out); |
|
#(CLK_PERIOD*10) |
$stop; |
end |
|
endmodule |
|
/trunk/bench/MEM_stage/data_mem_tb_0.do
0,0 → 1,11
quit -sim |
vlib work |
vlog +incdir+../rtl ../rtl/data_mem.v |
vlog +incdir+../rtl ../bench/MEM_stage/data_mem_tb_0.v |
|
vsim -t 1ps -novopt -lib work data_mem_tb_0_v |
view wave |
add wave * |
view structure |
view signals |
run -all |
/trunk/bench/register_file/register_file_tb_0.do
0,0 → 1,11
quit -sim |
vlib work |
vlog +incdir+../rtl ../rtl/register_file.v |
vlog +incdir+../rtl ../bench/register_file/register_file_tb_0.v |
|
vsim -t 1ps -novopt -lib work register_file_tb_0_v |
view wave |
add wave * |
view structure |
view signals |
run -all |
/trunk/bench/register_file/register_file_tb_0.v
0,0 → 1,204
|
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 15:38:17 02/08/2012 |
// Design Name: register_file |
// Module Name: F:/Projects/My_MIPS/mips_16/bench/register_file/register_file_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: register_file |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "mips_16_defs.v" |
|
module register_file_tb_0_v; |
|
// Inputs |
reg clk; |
reg rst; |
reg reg_write_en; |
reg [2:0] reg_write_dest; |
reg [15:0] reg_write_data; |
reg [2:0] reg_read_addr_1; |
reg [2:0] reg_read_addr_2; |
|
// Outputs |
wire [15:0] reg_read_data_1; |
wire [15:0] reg_read_data_2; |
|
// Instantiate the Unit Under Test (UUT) |
register_file uut ( |
.clk(clk), |
.rst(rst), |
.reg_write_en(reg_write_en), |
.reg_write_dest(reg_write_dest), |
.reg_write_data(reg_write_data), |
.reg_read_addr_1(reg_read_addr_1), |
.reg_read_data_1(reg_read_data_1), |
.reg_read_addr_2(reg_read_addr_2), |
.reg_read_data_2(reg_read_data_2) |
); |
|
parameter CLK_PERIOD = 10; |
always #(CLK_PERIOD /2) |
clk =~clk; |
integer i; |
reg [15:0] rand; |
|
initial begin |
// Initialize Inputs |
clk = 0; |
rst = 0; |
reg_write_en = 0; |
reg_write_dest = 0; |
reg_write_data = 0; |
reg_read_addr_1 = 0; |
reg_read_addr_2 = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
#(CLK_PERIOD/2) |
#1 |
#(CLK_PERIOD*1) rst = 1; |
#(CLK_PERIOD*1) rst = 0; |
|
#(CLK_PERIOD*10) |
display_all_regs; |
write_all_regs; |
read_all_regs_from_read_port_1; |
read_all_regs_from_read_port_2; |
write_and_read_all_regs; |
$stop; |
$finish; |
end |
|
task display_all_regs; |
begin |
$display("display_all_regs:"); |
$display("------------------------------"); |
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7"); |
for(i=0; i<8; i=i+1) |
$write("%d\t",uut.reg_array[i]); |
$display("\n------------------------------"); |
end |
endtask |
|
task read_all_regs_from_read_port_1; |
begin |
$display("read_all_regs_from_read_port_1:"); |
$display("------------------------------"); |
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7"); |
i=0; |
while(i<8) begin |
reg_read_addr_1 = i; |
#(CLK_PERIOD*1) |
$write("%d\t",reg_read_data_1); |
i=i+1; |
end |
$display("\n------------------------------"); |
end |
endtask |
|
task read_all_regs_from_read_port_2; |
begin |
$display("read_all_regs_from_read_port_2:"); |
$display("------------------------------"); |
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7"); |
i=0; |
while(i<8) begin |
reg_read_addr_2 = i; |
#(CLK_PERIOD*1) |
$write("%d\t",reg_read_data_2); |
i=i+1; |
end |
$display("\n------------------------------"); |
end |
endtask |
|
task write_all_regs; |
begin |
$display("write_all_regs(random):"); |
$display("------------------------------"); |
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7"); |
i=0; |
while(i<8) begin |
reg_write_en=1; |
reg_write_dest = i; |
reg_write_data = $random % 32768; |
#(CLK_PERIOD*1) |
$write("%d\t",uut.reg_array[i]); |
reg_write_en=0; |
i=i+1; |
end |
$display("\n------------------------------"); |
end |
endtask |
|
reg [15:0] read_tmp_1[7:0]; |
reg [15:0] read_tmp_2[7:0]; |
|
task write_and_read_all_regs; |
begin |
$display("write_and_read_all_regs(random):"); |
$display("------------------------------"); |
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7"); |
$display("newly wrote values:"); |
$display("------------------------------"); |
i=0; |
while(i<8) begin |
reg_write_en=1; |
reg_write_dest = i; |
reg_write_data = $random % 32768; |
reg_read_addr_1 = i; |
reg_read_addr_2 = i-1; |
#(CLK_PERIOD*0.5) |
read_tmp_1[i]=reg_read_data_1; |
if(reg_read_data_1 > 0) |
read_tmp_2[i-1]=reg_read_data_2; |
#(CLK_PERIOD*0.5) |
$write("%d\t",uut.reg_array[i]); |
reg_write_en=0; |
i=i+1; |
end |
reg_read_addr_2 = i-1; |
#(CLK_PERIOD*0.5) |
read_tmp_2[i-1]=reg_read_data_2; |
#(CLK_PERIOD*0.5) |
$display("\n------------------------------"); |
|
$display("read from port 1 (read regs being wrote will hold its value):"); |
$display("------------------------------"); |
i=0; |
while(i<8) begin |
$write("%d\t",read_tmp_1[i]); |
i=i+1; |
end |
$display("\n------------------------------"); |
|
$display("read from port 2 (read wrote regs will get its new value):"); |
$display("------------------------------"); |
i=0; |
while(i<8) begin |
$write("%d\t",read_tmp_2[i]); |
i=i+1; |
end |
$display("\n------------------------------"); |
end |
endtask |
endmodule |
|
/trunk/bench/hazard_detection_unit/hazard_detection_unit_tb_0.do
0,0 → 1,11
quit -sim |
vlib work |
vlog +incdir+../rtl ../rtl/hazard_detection_unit.v |
vlog +incdir+../rtl ../bench/hazard_detection_unit/hazard_detection_unit_tb_0.v |
|
vsim -t 1ps -novopt -lib work hazard_detection_unit_tb_0_v |
view wave |
add wave * |
view structure |
view signals |
run -all |
/trunk/bench/hazard_detection_unit/hazard_detection_unit_tb_0.v
0,0 → 1,126
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 15:54:44 02/09/2012 |
// Design Name: hazard_detection_unit |
// Module Name: F:/Projects/My_MIPS/mips_16/bench/hazard_detection_unit/hazard_detection_unit_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: hazard_detection_unit |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module hazard_detection_unit_tb_0_v; |
|
// Inputs |
reg [2:0] decoding_op_src1; |
reg [2:0] decoding_op_src2; |
reg [2:0] ex_op_dest; |
reg [2:0] mem_op_dest; |
reg [2:0] wb_op_dest; |
|
// Outputs |
wire pipeline_stall_n; |
|
// Instantiate the Unit Under Test (UUT) |
hazard_detection_unit uut ( |
.decoding_op_src1(decoding_op_src1), |
.decoding_op_src2(decoding_op_src2), |
.ex_op_dest(ex_op_dest), |
.mem_op_dest(mem_op_dest), |
.wb_op_dest(wb_op_dest), |
.pipeline_stall_n(pipeline_stall_n) |
); |
|
initial begin |
// Initialize Inputs |
decoding_op_src1 = 0; |
decoding_op_src2 = 0; |
ex_op_dest = 0; |
mem_op_dest = 0; |
wb_op_dest = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
#10 |
decoding_op_src1 = 0; |
decoding_op_src2 = 0; |
ex_op_dest = 1; |
mem_op_dest = 2; |
wb_op_dest = 3; |
#10 |
if(pipeline_stall_n == 1) |
$display("ok1"); |
else |
$display("error1"); |
|
#10 |
decoding_op_src1 = 5; |
decoding_op_src2 = 0; |
ex_op_dest = 5; |
mem_op_dest = 5; |
wb_op_dest = 3; |
#10 |
if(pipeline_stall_n == 0) |
$display("ok2"); |
else |
$display("error2"); |
|
|
#10 |
decoding_op_src1 = 5; |
decoding_op_src2 = 5; |
ex_op_dest = 5; |
mem_op_dest = 5; |
wb_op_dest = 0; |
#10 |
if(pipeline_stall_n == 0) |
$display("ok3"); |
else |
$display("error3"); |
|
#10 |
decoding_op_src1 = 5; |
decoding_op_src2 = 5; |
ex_op_dest = 7; |
mem_op_dest = 5; |
wb_op_dest = 0; |
#10 |
if(pipeline_stall_n == 0) |
$display("ok4"); |
else |
$display("error4"); |
|
#10 |
decoding_op_src1 = 5; |
decoding_op_src2 = 5; |
ex_op_dest = 0; |
mem_op_dest = 0; |
wb_op_dest = 0; |
#10 |
if(pipeline_stall_n == 1) |
$display("ok5"); |
else |
$display("error5"); |
|
|
#100 |
$stop; |
end |
|
endmodule |
|
/trunk/bench/mips_16_core_top/test1.asm
0,0 → 1,9
L1: ADDI R1,R0,8 |
ADDI R2,R1,8 |
ADDI R3,R2,8 |
ADD R4,R2,R3 |
ST R4,R1,2 |
LD R5,R1,2 |
SUB R6,R4,R5 |
BZ R6,L1 |
ADDI R7,R7,1 |
/trunk/bench/mips_16_core_top/mips_16_core_top_tb_0.v
0,0 → 1,172
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 19:38:28 02/09/2012 |
// Design Name: mips_16_core_top |
// Module Name: F:/Projects/My_MIPS/mips_16/bench/mips_16_core_top/mips_16_core_top_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: mips_16_core_top |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns/1ps |
`include "mips_16_defs.v" |
module mips_16_core_top_tb_0_v; |
|
// Inputs |
reg clk; |
reg rst; |
|
// Outputs |
wire [`PC_WIDTH-1:0] pc; |
|
parameter CLK_PERIOD = 10; |
always #(CLK_PERIOD /2) |
clk =~clk; |
integer i; |
integer test; |
|
// Instantiate the Unit Under Test (UUT) |
mips_16_core_top uut ( |
.clk(clk), |
.rst(rst), |
.pc(pc) |
); |
|
initial begin |
// Initialize Inputs |
clk = 0; |
rst = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
#(CLK_PERIOD/2) |
#1 |
display_debug_message; |
//test1; |
test2; |
$stop; |
end |
|
task display_debug_message; |
begin |
$display("\n***************************"); |
$display("mips_16 core test"); |
$display("***************************\n"); |
end |
endtask |
|
task sys_reset; |
begin |
rst = 0; |
#(CLK_PERIOD*1) rst = 1; |
#(CLK_PERIOD*1) rst = 0; |
end |
endtask |
|
|
task test1; |
begin |
$readmemb("../bench/mips_16_core_top/test1.prog",uut.IF_stage_inst.imem.rom); |
$display("rom load successfully\n"); |
$display("running test1\n"); |
sys_reset; |
#1 |
|
//#(CLK_PERIOD) test = 1; |
|
$monitor("current pc: %d ,instruction: %x", pc, uut.instruction); |
|
#(CLK_PERIOD*100) |
$monitoroff; |
display_all_regs; |
$display("ram[10] = %d", uut.MEM_stage_inst.dmem.ram[10]); |
//#(CLK_PERIOD*100) test = 0; |
sys_reset; |
|
end |
endtask |
|
task test2; |
begin |
$readmemb("../bench/mips_16_core_top/test2.prog",uut.IF_stage_inst.imem.rom); |
$display("rom load successfully\n"); |
$display("running test2\n"); |
$display("multiply R3=R1*R2\n"); |
sys_reset; |
display_all_regs; |
#1 |
test = 2; |
|
//#(CLK_PERIOD) test = 1; |
|
$monitor("current pc: %d ,instruction: %x", pc, uut.instruction); |
|
#(CLK_PERIOD*400) |
$monitoroff; |
display_all_regs; |
|
test = 0; |
sys_reset; |
|
end |
endtask |
|
task display_all_regs; |
begin |
$display("display_all_regs:"); |
$display("------------------------------"); |
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7"); |
for(i=0; i<8; i=i+1) |
$write("%d\t",uut.register_file_inst.reg_array[i]); |
$display("\n------------------------------"); |
end |
endtask |
|
|
always @ (test) begin |
case(test) |
// 1: begin |
// $display("running test1\n"); |
// while(test == 1) begin |
// @(uut.pc) |
// $display("current pc : %d",uut.pc); |
// if(uut.pc == 40) begin |
// #1 |
// branch_taken = 1; |
// branch_offset_imm = -30; |
// #(CLK_PERIOD*1) |
// branch_taken =0; |
// branch_offset_imm = 0; |
// end |
// end |
// end |
|
2: begin |
$display("running test2\n"); |
while(test == 2) begin |
@(pc) |
if(pc==6) begin |
$display("current pc : %d",uut.pc); |
display_all_regs(); |
end |
|
end |
end |
|
endcase |
end |
endmodule |
|
/trunk/bench/mips_16_core_top/test2.asm
0,0 → 1,29
;multiply R3=R1*R2 using add and shift instructions |
; R1: number 1 |
; R2: number 2 |
; R3: ACC |
; R4: masked R2 |
; R5: 16 |
; R6: mask, {15'b0,1'b1} |
; R7: conuter |
|
ADDI R1,R0,28 |
ADDI R2,R0,17 |
ADDI R6,R0,1 |
ADDI R7,R0,0 |
ADDI R5,R0,16 ;R5=16 |
L1: ADDI R7,R7,1 ;R7++ |
AND R4,R6,R2 |
BZ R4,L2 ;dont need add, skip |
NOP |
ADD R3,R3,R1 ;accumulate |
L2: SL R1,R1,R6 ;R1=R1<<1 |
SRU R2,R2,R6 ;R2=R2>>1 |
SUB R4,R5,R7 ;R4=R5-R7 |
BZ R4,L3 ;shift over, go to stop |
NOP |
BZ R0,L1 ;continue |
NOP |
L3: BZ R0,L3 ;stop here |
NOP |
|
/trunk/bench/mips_16_core_top/test1.prog
0,0 → 1,17
1001001000001000 |
1001010001001000 |
1001011010001000 |
0001100010011000 |
1011100001000010 |
1010101001000010 |
0010110100101000 |
1100000110111000 |
1001111111000001 |
|
|
|
|
|
|
|
|
/trunk/bench/mips_16_core_top/test2.prog
0,0 → 1,19
1001001000011100 |
1001010000010001 |
1001110000000001 |
1001111000000000 |
1001101000010000 |
1001111111000001 |
0011100110010000 |
1100000100000010 |
0000000000000000 |
0001011011001000 |
0110001001110000 |
1000010010110000 |
0010100101111000 |
1100000100000011 |
0000000000000000 |
1100000000110101 |
0000000000000000 |
1100000000111111 |
0000000000000000 |
/trunk/bench/mips_16_core_top/mips_16_core_top_tb_0.do
0,0 → 1,18
quit -sim |
vlib work |
vlog +incdir+../rtl ../rtl/*.v |
vlog +incdir+../rtl ../bench/mips_16_core_top/mips_16_core_top_tb_0.v |
|
vsim -t 1ps -novopt -lib work mips_16_core_top_tb_0_v |
view wave |
#add wave * |
add wave /mips_16_core_top_tb_0_v/uut/* |
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_op_code |
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_dest |
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_src1 |
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_src2 |
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_imm |
|
view structure |
view signals |
run -all |
/trunk/bench/WB_stage/WB_stage_tb_0.do
0,0 → 1,11
quit -sim |
vlib work |
vlog +incdir+../rtl ../rtl/WB_stage.v |
vlog +incdir+../rtl ../bench/WB_stage/WB_stage_tb_0.v |
|
vsim -t 1ps -novopt -lib work WB_stage_tb_0_v |
view wave |
add wave * |
view structure |
view signals |
run -all |
/trunk/bench/WB_stage/WB_stage_tb_0.v
0,0 → 1,81
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 15:21:32 02/09/2012 |
// Design Name: WB_stage |
// Module Name: F:/Projects/My_MIPS/mips_16/bench/WB_stage/WB_stage_tb_0.v |
// Project Name: mips_16 |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: WB_stage |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module WB_stage_tb_0_v; |
|
// Inputs |
reg [36:0] pipeline_reg_in; |
|
// Outputs |
wire reg_write_en; |
wire [2:0] reg_write_dest; |
wire [15:0] reg_write_data; |
wire [2:0] wb_op_dest; |
|
// Instantiate the Unit Under Test (UUT) |
WB_stage uut ( |
.pipeline_reg_in(pipeline_reg_in), |
.reg_write_en(reg_write_en), |
.reg_write_dest(reg_write_dest), |
.reg_write_data(reg_write_data), |
.wb_op_dest(wb_op_dest) |
); |
|
initial begin |
// Initialize Inputs |
pipeline_reg_in = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
pipeline_reg_in = {16'hf421, 16'h69fe, 5'b10101}; |
#10 |
if( |
reg_write_en == 1 && |
reg_write_dest == 3'b010 && |
wb_op_dest == 3'b010 && |
reg_write_data == 16'h69fe |
) |
$display("ok1"); |
else |
$display("error1"); |
|
pipeline_reg_in = {16'hf421, 16'h69fe, 5'b11100}; |
#10 |
if( |
reg_write_en == 1 && |
reg_write_dest == 3'b110 && |
wb_op_dest == 3'b110 && |
reg_write_data == 16'hf421 |
) |
$display("ok1"); |
else |
$display("error1"); |
#100 |
$stop; |
end |
|
endmodule |
|