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/source/RAMB16_S9_0.vhd
0,0 → 1,163
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Lazaridis Dimitris |
-- |
-- Create Date: 22:46:06 06/13/2012 |
-- Design Name: |
-- Module Name: RAMB16_S9_0 - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
--use IEEE.STD_LOGIC_UNSIGNED.ALL; |
Library UNISIM; |
use UNISIM.vcomponents.all; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--use IEEE.NUMERIC_STD.ALL; |
|
-- Uncomment the following library declaration if instantiating |
-- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity RAMB16_S9_0 is |
port ( |
clk : in std_logic; |
we : in std_logic; |
en : in std_logic; |
ssr : in std_logic; |
addr : in std_logic_vector(10 downto 0); |
di : in std_logic_vector (7 downto 0); |
do : out std_logic_vector(7 downto 0) |
); |
end RAMB16_S9_0; |
|
architecture Behavioral of RAMB16_S9_0 is |
signal clk_inv : std_logic; |
begin |
process(clk) |
variable invert : std_logic; |
begin |
invert := not clk; |
clk_inv <= invert; |
end process; |
|
RAMB16_S9_inst : RAMB16_S9 |
generic map ( |
INIT => X"000", -- Value of output RAM registers at startup |
SRVAL => X"000", -- Ouput value upon SSR assertion |
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE |
-- The following INIT_xx declarations specify the initial contents of the RAM |
-- Address 0 to 511 |
INIT_00 => X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0DDDDDDDDDDDDDDDDD", |
INIT_01 => X"DD0000D0DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD", |
INIT_02 => X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD", |
INIT_03 => X"DFDDDDDFDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDFDDDDDF", |
INIT_04 => X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD", |
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", |
-- Address 512 to 1023 |
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", |
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", |
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", |
-- Address 1024 to 1535 |
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", |
-- Address 1536 to 2047 |
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", |
-- The next set of INITP_xx are for the parity bits |
-- Address 0 to 511 |
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", |
-- Address 512 to 1023 |
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", |
-- Address 1024 to 1535 |
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", |
-- Address 1536 to 2047 |
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", |
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") |
port map ( |
DO => DO, -- 8-bit Data Output |
DOP => open, -- 1-bit parity Output |
ADDR => ADDR, -- 11-bit Address Input |
CLK => clk_inv, --CLK, -- Clock |
DI => DI, -- 8-bit Data Input |
DIP => "1", -- 1-bit parity Input |
EN => EN, -- RAM Enable Input |
SSR => SSR, -- Synchronous Set/Reset Input |
WE => WE -- Write Enable Input |
); |
|
-- End of RAMB16_S9_inst instantiation |
|
|
|
|
end Behavioral; |
|